1/* 2 * Enhanced Host Controller Interface (EHCI) driver for USB. 3 * 4 * Maintainer: Alan Stern <stern@rowland.harvard.edu> 5 * 6 * Copyright (c) 2000-2004 by David Brownell 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 16 * for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software Foundation, 20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 */ 22 23#include <linux/module.h> 24#include <linux/pci.h> 25#include <linux/dmapool.h> 26#include <linux/kernel.h> 27#include <linux/delay.h> 28#include <linux/ioport.h> 29#include <linux/sched.h> 30#include <linux/vmalloc.h> 31#include <linux/errno.h> 32#include <linux/init.h> 33#include <linux/hrtimer.h> 34#include <linux/list.h> 35#include <linux/interrupt.h> 36#include <linux/usb.h> 37#include <linux/usb/hcd.h> 38#include <linux/moduleparam.h> 39#include <linux/dma-mapping.h> 40#include <linux/debugfs.h> 41#include <linux/slab.h> 42 43#include <asm/byteorder.h> 44#include <asm/io.h> 45#include <asm/irq.h> 46#include <asm/unaligned.h> 47 48#if defined(CONFIG_PPC_PS3) 49#include <asm/firmware.h> 50#endif 51 52/*-------------------------------------------------------------------------*/ 53 54/* 55 * EHCI hc_driver implementation ... experimental, incomplete. 56 * Based on the final 1.0 register interface specification. 57 * 58 * USB 2.0 shows up in upcoming www.pcmcia.org technology. 59 * First was PCMCIA, like ISA; then CardBus, which is PCI. 60 * Next comes "CardBay", using USB 2.0 signals. 61 * 62 * Contains additional contributions by Brad Hards, Rory Bolt, and others. 63 * Special thanks to Intel and VIA for providing host controllers to 64 * test this driver on, and Cypress (including In-System Design) for 65 * providing early devices for those host controllers to talk to! 66 */ 67 68#define DRIVER_AUTHOR "David Brownell" 69#define DRIVER_DESC "USB 2.0 'Enhanced' Host Controller (EHCI) Driver" 70 71static const char hcd_name [] = "ehci_hcd"; 72 73 74#undef EHCI_URB_TRACE 75 76/* magic numbers that can affect system performance */ 77#define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */ 78#define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */ 79#define EHCI_TUNE_RL_TT 0 80#define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */ 81#define EHCI_TUNE_MULT_TT 1 82/* 83 * Some drivers think it's safe to schedule isochronous transfers more than 84 * 256 ms into the future (partly as a result of an old bug in the scheduling 85 * code). In an attempt to avoid trouble, we will use a minimum scheduling 86 * length of 512 frames instead of 256. 87 */ 88#define EHCI_TUNE_FLS 1 /* (medium) 512-frame schedule */ 89 90/* Initial IRQ latency: faster than hw default */ 91static int log2_irq_thresh = 0; // 0 to 6 92module_param (log2_irq_thresh, int, S_IRUGO); 93MODULE_PARM_DESC (log2_irq_thresh, "log2 IRQ latency, 1-64 microframes"); 94 95/* initial park setting: slower than hw default */ 96static unsigned park = 0; 97module_param (park, uint, S_IRUGO); 98MODULE_PARM_DESC (park, "park setting; 1-3 back-to-back async packets"); 99 100/* for flakey hardware, ignore overcurrent indicators */ 101static bool ignore_oc = 0; 102module_param (ignore_oc, bool, S_IRUGO); 103MODULE_PARM_DESC (ignore_oc, "ignore bogus hardware overcurrent indications"); 104 105#define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT) 106 107/*-------------------------------------------------------------------------*/ 108 109#include "ehci.h" 110#include "pci-quirks.h" 111 112static void compute_tt_budget(u8 budget_table[EHCI_BANDWIDTH_SIZE], 113 struct ehci_tt *tt); 114 115/* 116 * The MosChip MCS9990 controller updates its microframe counter 117 * a little before the frame counter, and occasionally we will read 118 * the invalid intermediate value. Avoid problems by checking the 119 * microframe number (the low-order 3 bits); if they are 0 then 120 * re-read the register to get the correct value. 121 */ 122static unsigned ehci_moschip_read_frame_index(struct ehci_hcd *ehci) 123{ 124 unsigned uf; 125 126 uf = ehci_readl(ehci, &ehci->regs->frame_index); 127 if (unlikely((uf & 7) == 0)) 128 uf = ehci_readl(ehci, &ehci->regs->frame_index); 129 return uf; 130} 131 132static inline unsigned ehci_read_frame_index(struct ehci_hcd *ehci) 133{ 134 if (ehci->frame_index_bug) 135 return ehci_moschip_read_frame_index(ehci); 136 return ehci_readl(ehci, &ehci->regs->frame_index); 137} 138 139#include "ehci-dbg.c" 140 141/*-------------------------------------------------------------------------*/ 142 143/* 144 * ehci_handshake - spin reading hc until handshake completes or fails 145 * @ptr: address of hc register to be read 146 * @mask: bits to look at in result of read 147 * @done: value of those bits when handshake succeeds 148 * @usec: timeout in microseconds 149 * 150 * Returns negative errno, or zero on success 151 * 152 * Success happens when the "mask" bits have the specified value (hardware 153 * handshake done). There are two failure modes: "usec" have passed (major 154 * hardware flakeout), or the register reads as all-ones (hardware removed). 155 * 156 * That last failure should_only happen in cases like physical cardbus eject 157 * before driver shutdown. But it also seems to be caused by bugs in cardbus 158 * bridge shutdown: shutting down the bridge before the devices using it. 159 */ 160int ehci_handshake(struct ehci_hcd *ehci, void __iomem *ptr, 161 u32 mask, u32 done, int usec) 162{ 163 u32 result; 164 165 do { 166 result = ehci_readl(ehci, ptr); 167 if (result == ~(u32)0) /* card removed */ 168 return -ENODEV; 169 result &= mask; 170 if (result == done) 171 return 0; 172 udelay (1); 173 usec--; 174 } while (usec > 0); 175 return -ETIMEDOUT; 176} 177EXPORT_SYMBOL_GPL(ehci_handshake); 178 179/* check TDI/ARC silicon is in host mode */ 180static int tdi_in_host_mode (struct ehci_hcd *ehci) 181{ 182 u32 tmp; 183 184 tmp = ehci_readl(ehci, &ehci->regs->usbmode); 185 return (tmp & 3) == USBMODE_CM_HC; 186} 187 188/* 189 * Force HC to halt state from unknown (EHCI spec section 2.3). 190 * Must be called with interrupts enabled and the lock not held. 191 */ 192static int ehci_halt (struct ehci_hcd *ehci) 193{ 194 u32 temp; 195 196 spin_lock_irq(&ehci->lock); 197 198 /* disable any irqs left enabled by previous code */ 199 ehci_writel(ehci, 0, &ehci->regs->intr_enable); 200 201 if (ehci_is_TDI(ehci) && !tdi_in_host_mode(ehci)) { 202 spin_unlock_irq(&ehci->lock); 203 return 0; 204 } 205 206 /* 207 * This routine gets called during probe before ehci->command 208 * has been initialized, so we can't rely on its value. 209 */ 210 ehci->command &= ~CMD_RUN; 211 temp = ehci_readl(ehci, &ehci->regs->command); 212 temp &= ~(CMD_RUN | CMD_IAAD); 213 ehci_writel(ehci, temp, &ehci->regs->command); 214 215 spin_unlock_irq(&ehci->lock); 216 synchronize_irq(ehci_to_hcd(ehci)->irq); 217 218 return ehci_handshake(ehci, &ehci->regs->status, 219 STS_HALT, STS_HALT, 16 * 125); 220} 221 222/* put TDI/ARC silicon into EHCI mode */ 223static void tdi_reset (struct ehci_hcd *ehci) 224{ 225 u32 tmp; 226 227 tmp = ehci_readl(ehci, &ehci->regs->usbmode); 228 tmp |= USBMODE_CM_HC; 229 /* The default byte access to MMR space is LE after 230 * controller reset. Set the required endian mode 231 * for transfer buffers to match the host microprocessor 232 */ 233 if (ehci_big_endian_mmio(ehci)) 234 tmp |= USBMODE_BE; 235 ehci_writel(ehci, tmp, &ehci->regs->usbmode); 236} 237 238/* 239 * Reset a non-running (STS_HALT == 1) controller. 240 * Must be called with interrupts enabled and the lock not held. 241 */ 242static int ehci_reset (struct ehci_hcd *ehci) 243{ 244 int retval; 245 u32 command = ehci_readl(ehci, &ehci->regs->command); 246 247 /* If the EHCI debug controller is active, special care must be 248 * taken before and after a host controller reset */ 249 if (ehci->debug && !dbgp_reset_prep(ehci_to_hcd(ehci))) 250 ehci->debug = NULL; 251 252 command |= CMD_RESET; 253 dbg_cmd (ehci, "reset", command); 254 ehci_writel(ehci, command, &ehci->regs->command); 255 ehci->rh_state = EHCI_RH_HALTED; 256 ehci->next_statechange = jiffies; 257 retval = ehci_handshake(ehci, &ehci->regs->command, 258 CMD_RESET, 0, 250 * 1000); 259 260 if (ehci->has_hostpc) { 261 ehci_writel(ehci, USBMODE_EX_HC | USBMODE_EX_VBPS, 262 &ehci->regs->usbmode_ex); 263 ehci_writel(ehci, TXFIFO_DEFAULT, &ehci->regs->txfill_tuning); 264 } 265 if (retval) 266 return retval; 267 268 if (ehci_is_TDI(ehci)) 269 tdi_reset (ehci); 270 271 if (ehci->debug) 272 dbgp_external_startup(ehci_to_hcd(ehci)); 273 274 ehci->port_c_suspend = ehci->suspended_ports = 275 ehci->resuming_ports = 0; 276 return retval; 277} 278 279/* 280 * Idle the controller (turn off the schedules). 281 * Must be called with interrupts enabled and the lock not held. 282 */ 283static void ehci_quiesce (struct ehci_hcd *ehci) 284{ 285 u32 temp; 286 287 if (ehci->rh_state != EHCI_RH_RUNNING) 288 return; 289 290 /* wait for any schedule enables/disables to take effect */ 291 temp = (ehci->command << 10) & (STS_ASS | STS_PSS); 292 ehci_handshake(ehci, &ehci->regs->status, STS_ASS | STS_PSS, temp, 293 16 * 125); 294 295 /* then disable anything that's still active */ 296 spin_lock_irq(&ehci->lock); 297 ehci->command &= ~(CMD_ASE | CMD_PSE); 298 ehci_writel(ehci, ehci->command, &ehci->regs->command); 299 spin_unlock_irq(&ehci->lock); 300 301 /* hardware can take 16 microframes to turn off ... */ 302 ehci_handshake(ehci, &ehci->regs->status, STS_ASS | STS_PSS, 0, 303 16 * 125); 304} 305 306/*-------------------------------------------------------------------------*/ 307 308static void end_unlink_async(struct ehci_hcd *ehci); 309static void unlink_empty_async(struct ehci_hcd *ehci); 310static void unlink_empty_async_suspended(struct ehci_hcd *ehci); 311static void ehci_work(struct ehci_hcd *ehci); 312static void start_unlink_intr(struct ehci_hcd *ehci, struct ehci_qh *qh); 313static void end_unlink_intr(struct ehci_hcd *ehci, struct ehci_qh *qh); 314static int ehci_port_power(struct ehci_hcd *ehci, int portnum, bool enable); 315 316#include "ehci-timer.c" 317#include "ehci-hub.c" 318#include "ehci-mem.c" 319#include "ehci-q.c" 320#include "ehci-sched.c" 321#include "ehci-sysfs.c" 322 323/*-------------------------------------------------------------------------*/ 324 325/* On some systems, leaving remote wakeup enabled prevents system shutdown. 326 * The firmware seems to think that powering off is a wakeup event! 327 * This routine turns off remote wakeup and everything else, on all ports. 328 */ 329static void ehci_turn_off_all_ports(struct ehci_hcd *ehci) 330{ 331 int port = HCS_N_PORTS(ehci->hcs_params); 332 333 while (port--) { 334 ehci_writel(ehci, PORT_RWC_BITS, 335 &ehci->regs->port_status[port]); 336 spin_unlock_irq(&ehci->lock); 337 ehci_port_power(ehci, port, false); 338 spin_lock_irq(&ehci->lock); 339 } 340} 341 342/* 343 * Halt HC, turn off all ports, and let the BIOS use the companion controllers. 344 * Must be called with interrupts enabled and the lock not held. 345 */ 346static void ehci_silence_controller(struct ehci_hcd *ehci) 347{ 348 ehci_halt(ehci); 349 350 spin_lock_irq(&ehci->lock); 351 ehci->rh_state = EHCI_RH_HALTED; 352 ehci_turn_off_all_ports(ehci); 353 354 /* make BIOS/etc use companion controller during reboot */ 355 ehci_writel(ehci, 0, &ehci->regs->configured_flag); 356 357 /* unblock posted writes */ 358 ehci_readl(ehci, &ehci->regs->configured_flag); 359 spin_unlock_irq(&ehci->lock); 360} 361 362/* ehci_shutdown kick in for silicon on any bus (not just pci, etc). 363 * This forcibly disables dma and IRQs, helping kexec and other cases 364 * where the next system software may expect clean state. 365 */ 366static void ehci_shutdown(struct usb_hcd *hcd) 367{ 368 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 369 370 spin_lock_irq(&ehci->lock); 371 ehci->shutdown = true; 372 ehci->rh_state = EHCI_RH_STOPPING; 373 ehci->enabled_hrtimer_events = 0; 374 spin_unlock_irq(&ehci->lock); 375 376 ehci_silence_controller(ehci); 377 378 hrtimer_cancel(&ehci->hrtimer); 379} 380 381/*-------------------------------------------------------------------------*/ 382 383/* 384 * ehci_work is called from some interrupts, timers, and so on. 385 * it calls driver completion functions, after dropping ehci->lock. 386 */ 387static void ehci_work (struct ehci_hcd *ehci) 388{ 389 /* another CPU may drop ehci->lock during a schedule scan while 390 * it reports urb completions. this flag guards against bogus 391 * attempts at re-entrant schedule scanning. 392 */ 393 if (ehci->scanning) { 394 ehci->need_rescan = true; 395 return; 396 } 397 ehci->scanning = true; 398 399 rescan: 400 ehci->need_rescan = false; 401 if (ehci->async_count) 402 scan_async(ehci); 403 if (ehci->intr_count > 0) 404 scan_intr(ehci); 405 if (ehci->isoc_count > 0) 406 scan_isoc(ehci); 407 if (ehci->need_rescan) 408 goto rescan; 409 ehci->scanning = false; 410 411 /* the IO watchdog guards against hardware or driver bugs that 412 * misplace IRQs, and should let us run completely without IRQs. 413 * such lossage has been observed on both VT6202 and VT8235. 414 */ 415 turn_on_io_watchdog(ehci); 416} 417 418/* 419 * Called when the ehci_hcd module is removed. 420 */ 421static void ehci_stop (struct usb_hcd *hcd) 422{ 423 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 424 425 ehci_dbg (ehci, "stop\n"); 426 427 /* no more interrupts ... */ 428 429 spin_lock_irq(&ehci->lock); 430 ehci->enabled_hrtimer_events = 0; 431 spin_unlock_irq(&ehci->lock); 432 433 ehci_quiesce(ehci); 434 ehci_silence_controller(ehci); 435 ehci_reset (ehci); 436 437 hrtimer_cancel(&ehci->hrtimer); 438 remove_sysfs_files(ehci); 439 remove_debug_files (ehci); 440 441 /* root hub is shut down separately (first, when possible) */ 442 spin_lock_irq (&ehci->lock); 443 end_free_itds(ehci); 444 spin_unlock_irq (&ehci->lock); 445 ehci_mem_cleanup (ehci); 446 447 if (ehci->amd_pll_fix == 1) 448 usb_amd_dev_put(); 449 450 dbg_status (ehci, "ehci_stop completed", 451 ehci_readl(ehci, &ehci->regs->status)); 452} 453 454/* one-time init, only for memory state */ 455static int ehci_init(struct usb_hcd *hcd) 456{ 457 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 458 u32 temp; 459 int retval; 460 u32 hcc_params; 461 struct ehci_qh_hw *hw; 462 463 spin_lock_init(&ehci->lock); 464 465 /* 466 * keep io watchdog by default, those good HCDs could turn off it later 467 */ 468 ehci->need_io_watchdog = 1; 469 470 hrtimer_init(&ehci->hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS); 471 ehci->hrtimer.function = ehci_hrtimer_func; 472 ehci->next_hrtimer_event = EHCI_HRTIMER_NO_EVENT; 473 474 hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params); 475 476 /* 477 * by default set standard 80% (== 100 usec/uframe) max periodic 478 * bandwidth as required by USB 2.0 479 */ 480 ehci->uframe_periodic_max = 100; 481 482 /* 483 * hw default: 1K periodic list heads, one per frame. 484 * periodic_size can shrink by USBCMD update if hcc_params allows. 485 */ 486 ehci->periodic_size = DEFAULT_I_TDPS; 487 INIT_LIST_HEAD(&ehci->async_unlink); 488 INIT_LIST_HEAD(&ehci->async_idle); 489 INIT_LIST_HEAD(&ehci->intr_unlink_wait); 490 INIT_LIST_HEAD(&ehci->intr_unlink); 491 INIT_LIST_HEAD(&ehci->intr_qh_list); 492 INIT_LIST_HEAD(&ehci->cached_itd_list); 493 INIT_LIST_HEAD(&ehci->cached_sitd_list); 494 INIT_LIST_HEAD(&ehci->tt_list); 495 496 if (HCC_PGM_FRAMELISTLEN(hcc_params)) { 497 /* periodic schedule size can be smaller than default */ 498 switch (EHCI_TUNE_FLS) { 499 case 0: ehci->periodic_size = 1024; break; 500 case 1: ehci->periodic_size = 512; break; 501 case 2: ehci->periodic_size = 256; break; 502 default: BUG(); 503 } 504 } 505 if ((retval = ehci_mem_init(ehci, GFP_KERNEL)) < 0) 506 return retval; 507 508 /* controllers may cache some of the periodic schedule ... */ 509 if (HCC_ISOC_CACHE(hcc_params)) // full frame cache 510 ehci->i_thresh = 0; 511 else // N microframes cached 512 ehci->i_thresh = 2 + HCC_ISOC_THRES(hcc_params); 513 514 /* 515 * dedicate a qh for the async ring head, since we couldn't unlink 516 * a 'real' qh without stopping the async schedule [4.8]. use it 517 * as the 'reclamation list head' too. 518 * its dummy is used in hw_alt_next of many tds, to prevent the qh 519 * from automatically advancing to the next td after short reads. 520 */ 521 ehci->async->qh_next.qh = NULL; 522 hw = ehci->async->hw; 523 hw->hw_next = QH_NEXT(ehci, ehci->async->qh_dma); 524 hw->hw_info1 = cpu_to_hc32(ehci, QH_HEAD); 525#if defined(CONFIG_PPC_PS3) 526 hw->hw_info1 |= cpu_to_hc32(ehci, QH_INACTIVATE); 527#endif 528 hw->hw_token = cpu_to_hc32(ehci, QTD_STS_HALT); 529 hw->hw_qtd_next = EHCI_LIST_END(ehci); 530 ehci->async->qh_state = QH_STATE_LINKED; 531 hw->hw_alt_next = QTD_NEXT(ehci, ehci->async->dummy->qtd_dma); 532 533 /* clear interrupt enables, set irq latency */ 534 if (log2_irq_thresh < 0 || log2_irq_thresh > 6) 535 log2_irq_thresh = 0; 536 temp = 1 << (16 + log2_irq_thresh); 537 if (HCC_PER_PORT_CHANGE_EVENT(hcc_params)) { 538 ehci->has_ppcd = 1; 539 ehci_dbg(ehci, "enable per-port change event\n"); 540 temp |= CMD_PPCEE; 541 } 542 if (HCC_CANPARK(hcc_params)) { 543 /* HW default park == 3, on hardware that supports it (like 544 * NVidia and ALI silicon), maximizes throughput on the async 545 * schedule by avoiding QH fetches between transfers. 546 * 547 * With fast usb storage devices and NForce2, "park" seems to 548 * make problems: throughput reduction (!), data errors... 549 */ 550 if (park) { 551 park = min(park, (unsigned) 3); 552 temp |= CMD_PARK; 553 temp |= park << 8; 554 } 555 ehci_dbg(ehci, "park %d\n", park); 556 } 557 if (HCC_PGM_FRAMELISTLEN(hcc_params)) { 558 /* periodic schedule size can be smaller than default */ 559 temp &= ~(3 << 2); 560 temp |= (EHCI_TUNE_FLS << 2); 561 } 562 ehci->command = temp; 563 564 /* Accept arbitrarily long scatter-gather lists */ 565 if (!(hcd->driver->flags & HCD_LOCAL_MEM)) 566 hcd->self.sg_tablesize = ~0; 567 return 0; 568} 569 570/* start HC running; it's halted, ehci_init() has been run (once) */ 571static int ehci_run (struct usb_hcd *hcd) 572{ 573 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 574 u32 temp; 575 u32 hcc_params; 576 577 hcd->uses_new_polling = 1; 578 579 /* EHCI spec section 4.1 */ 580 581 ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list); 582 ehci_writel(ehci, (u32)ehci->async->qh_dma, &ehci->regs->async_next); 583 584 /* 585 * hcc_params controls whether ehci->regs->segment must (!!!) 586 * be used; it constrains QH/ITD/SITD and QTD locations. 587 * pci_pool consistent memory always uses segment zero. 588 * streaming mappings for I/O buffers, like pci_map_single(), 589 * can return segments above 4GB, if the device allows. 590 * 591 * NOTE: the dma mask is visible through dma_supported(), so 592 * drivers can pass this info along ... like NETIF_F_HIGHDMA, 593 * Scsi_Host.highmem_io, and so forth. It's readonly to all 594 * host side drivers though. 595 */ 596 hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params); 597 if (HCC_64BIT_ADDR(hcc_params)) { 598 ehci_writel(ehci, 0, &ehci->regs->segment); 599#if 0 600// this is deeply broken on almost all architectures 601 if (!dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64))) 602 ehci_info(ehci, "enabled 64bit DMA\n"); 603#endif 604 } 605 606 607 // Philips, Intel, and maybe others need CMD_RUN before the 608 // root hub will detect new devices (why?); NEC doesn't 609 ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET); 610 ehci->command |= CMD_RUN; 611 ehci_writel(ehci, ehci->command, &ehci->regs->command); 612 dbg_cmd (ehci, "init", ehci->command); 613 614 /* 615 * Start, enabling full USB 2.0 functionality ... usb 1.1 devices 616 * are explicitly handed to companion controller(s), so no TT is 617 * involved with the root hub. (Except where one is integrated, 618 * and there's no companion controller unless maybe for USB OTG.) 619 * 620 * Turning on the CF flag will transfer ownership of all ports 621 * from the companions to the EHCI controller. If any of the 622 * companions are in the middle of a port reset at the time, it 623 * could cause trouble. Write-locking ehci_cf_port_reset_rwsem 624 * guarantees that no resets are in progress. After we set CF, 625 * a short delay lets the hardware catch up; new resets shouldn't 626 * be started before the port switching actions could complete. 627 */ 628 down_write(&ehci_cf_port_reset_rwsem); 629 ehci->rh_state = EHCI_RH_RUNNING; 630 ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag); 631 ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */ 632 msleep(5); 633 up_write(&ehci_cf_port_reset_rwsem); 634 ehci->last_periodic_enable = ktime_get_real(); 635 636 temp = HC_VERSION(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase)); 637 ehci_info (ehci, 638 "USB %x.%x started, EHCI %x.%02x%s\n", 639 ((ehci->sbrn & 0xf0)>>4), (ehci->sbrn & 0x0f), 640 temp >> 8, temp & 0xff, 641 ignore_oc ? ", overcurrent ignored" : ""); 642 643 ehci_writel(ehci, INTR_MASK, 644 &ehci->regs->intr_enable); /* Turn On Interrupts */ 645 646 /* GRR this is run-once init(), being done every time the HC starts. 647 * So long as they're part of class devices, we can't do it init() 648 * since the class device isn't created that early. 649 */ 650 create_debug_files(ehci); 651 create_sysfs_files(ehci); 652 653 return 0; 654} 655 656int ehci_setup(struct usb_hcd *hcd) 657{ 658 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 659 int retval; 660 661 ehci->regs = (void __iomem *)ehci->caps + 662 HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase)); 663 dbg_hcs_params(ehci, "reset"); 664 dbg_hcc_params(ehci, "reset"); 665 666 /* cache this readonly data; minimize chip reads */ 667 ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); 668 669 ehci->sbrn = HCD_USB2; 670 671 /* data structure init */ 672 retval = ehci_init(hcd); 673 if (retval) 674 return retval; 675 676 retval = ehci_halt(ehci); 677 if (retval) 678 return retval; 679 680 ehci_reset(ehci); 681 682 return 0; 683} 684EXPORT_SYMBOL_GPL(ehci_setup); 685 686/*-------------------------------------------------------------------------*/ 687 688static irqreturn_t ehci_irq (struct usb_hcd *hcd) 689{ 690 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 691 u32 status, masked_status, pcd_status = 0, cmd; 692 int bh; 693 unsigned long flags; 694 695 /* 696 * For threadirqs option we use spin_lock_irqsave() variant to prevent 697 * deadlock with ehci hrtimer callback, because hrtimer callbacks run 698 * in interrupt context even when threadirqs is specified. We can go 699 * back to spin_lock() variant when hrtimer callbacks become threaded. 700 */ 701 spin_lock_irqsave(&ehci->lock, flags); 702 703 status = ehci_readl(ehci, &ehci->regs->status); 704 705 /* e.g. cardbus physical eject */ 706 if (status == ~(u32) 0) { 707 ehci_dbg (ehci, "device removed\n"); 708 goto dead; 709 } 710 711 /* 712 * We don't use STS_FLR, but some controllers don't like it to 713 * remain on, so mask it out along with the other status bits. 714 */ 715 masked_status = status & (INTR_MASK | STS_FLR); 716 717 /* Shared IRQ? */ 718 if (!masked_status || unlikely(ehci->rh_state == EHCI_RH_HALTED)) { 719 spin_unlock_irqrestore(&ehci->lock, flags); 720 return IRQ_NONE; 721 } 722 723 /* clear (just) interrupts */ 724 ehci_writel(ehci, masked_status, &ehci->regs->status); 725 cmd = ehci_readl(ehci, &ehci->regs->command); 726 bh = 0; 727 728 /* normal [4.15.1.2] or error [4.15.1.1] completion */ 729 if (likely ((status & (STS_INT|STS_ERR)) != 0)) { 730 if (likely ((status & STS_ERR) == 0)) 731 COUNT (ehci->stats.normal); 732 else 733 COUNT (ehci->stats.error); 734 bh = 1; 735 } 736 737 /* complete the unlinking of some qh [4.15.2.3] */ 738 if (status & STS_IAA) { 739 740 /* Turn off the IAA watchdog */ 741 ehci->enabled_hrtimer_events &= ~BIT(EHCI_HRTIMER_IAA_WATCHDOG); 742 743 /* 744 * Mild optimization: Allow another IAAD to reset the 745 * hrtimer, if one occurs before the next expiration. 746 * In theory we could always cancel the hrtimer, but 747 * tests show that about half the time it will be reset 748 * for some other event anyway. 749 */ 750 if (ehci->next_hrtimer_event == EHCI_HRTIMER_IAA_WATCHDOG) 751 ++ehci->next_hrtimer_event; 752 753 /* guard against (alleged) silicon errata */ 754 if (cmd & CMD_IAAD) 755 ehci_dbg(ehci, "IAA with IAAD still set?\n"); 756 if (ehci->iaa_in_progress) 757 COUNT(ehci->stats.iaa); 758 end_unlink_async(ehci); 759 } 760 761 /* remote wakeup [4.3.1] */ 762 if (status & STS_PCD) { 763 unsigned i = HCS_N_PORTS (ehci->hcs_params); 764 u32 ppcd = ~0; 765 766 /* kick root hub later */ 767 pcd_status = status; 768 769 /* resume root hub? */ 770 if (ehci->rh_state == EHCI_RH_SUSPENDED) 771 usb_hcd_resume_root_hub(hcd); 772 773 /* get per-port change detect bits */ 774 if (ehci->has_ppcd) 775 ppcd = status >> 16; 776 777 while (i--) { 778 int pstatus; 779 780 /* leverage per-port change bits feature */ 781 if (!(ppcd & (1 << i))) 782 continue; 783 pstatus = ehci_readl(ehci, 784 &ehci->regs->port_status[i]); 785 786 if (pstatus & PORT_OWNER) 787 continue; 788 if (!(test_bit(i, &ehci->suspended_ports) && 789 ((pstatus & PORT_RESUME) || 790 !(pstatus & PORT_SUSPEND)) && 791 (pstatus & PORT_PE) && 792 ehci->reset_done[i] == 0)) 793 continue; 794 795 /* start USB_RESUME_TIMEOUT msec resume signaling from 796 * this port, and make hub_wq collect 797 * PORT_STAT_C_SUSPEND to stop that signaling. 798 */ 799 ehci->reset_done[i] = jiffies + 800 msecs_to_jiffies(USB_RESUME_TIMEOUT); 801 set_bit(i, &ehci->resuming_ports); 802 ehci_dbg (ehci, "port %d remote wakeup\n", i + 1); 803 usb_hcd_start_port_resume(&hcd->self, i); 804 mod_timer(&hcd->rh_timer, ehci->reset_done[i]); 805 } 806 } 807 808 /* PCI errors [4.15.2.4] */ 809 if (unlikely ((status & STS_FATAL) != 0)) { 810 ehci_err(ehci, "fatal error\n"); 811 dbg_cmd(ehci, "fatal", cmd); 812 dbg_status(ehci, "fatal", status); 813dead: 814 usb_hc_died(hcd); 815 816 /* Don't let the controller do anything more */ 817 ehci->shutdown = true; 818 ehci->rh_state = EHCI_RH_STOPPING; 819 ehci->command &= ~(CMD_RUN | CMD_ASE | CMD_PSE); 820 ehci_writel(ehci, ehci->command, &ehci->regs->command); 821 ehci_writel(ehci, 0, &ehci->regs->intr_enable); 822 ehci_handle_controller_death(ehci); 823 824 /* Handle completions when the controller stops */ 825 bh = 0; 826 } 827 828 if (bh) 829 ehci_work (ehci); 830 spin_unlock_irqrestore(&ehci->lock, flags); 831 if (pcd_status) 832 usb_hcd_poll_rh_status(hcd); 833 return IRQ_HANDLED; 834} 835 836/*-------------------------------------------------------------------------*/ 837 838/* 839 * non-error returns are a promise to giveback() the urb later 840 * we drop ownership so next owner (or urb unlink) can get it 841 * 842 * urb + dev is in hcd.self.controller.urb_list 843 * we're queueing TDs onto software and hardware lists 844 * 845 * hcd-specific init for hcpriv hasn't been done yet 846 * 847 * NOTE: control, bulk, and interrupt share the same code to append TDs 848 * to a (possibly active) QH, and the same QH scanning code. 849 */ 850static int ehci_urb_enqueue ( 851 struct usb_hcd *hcd, 852 struct urb *urb, 853 gfp_t mem_flags 854) { 855 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 856 struct list_head qtd_list; 857 858 INIT_LIST_HEAD (&qtd_list); 859 860 switch (usb_pipetype (urb->pipe)) { 861 case PIPE_CONTROL: 862 /* qh_completions() code doesn't handle all the fault cases 863 * in multi-TD control transfers. Even 1KB is rare anyway. 864 */ 865 if (urb->transfer_buffer_length > (16 * 1024)) 866 return -EMSGSIZE; 867 /* FALLTHROUGH */ 868 /* case PIPE_BULK: */ 869 default: 870 if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags)) 871 return -ENOMEM; 872 return submit_async(ehci, urb, &qtd_list, mem_flags); 873 874 case PIPE_INTERRUPT: 875 if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags)) 876 return -ENOMEM; 877 return intr_submit(ehci, urb, &qtd_list, mem_flags); 878 879 case PIPE_ISOCHRONOUS: 880 if (urb->dev->speed == USB_SPEED_HIGH) 881 return itd_submit (ehci, urb, mem_flags); 882 else 883 return sitd_submit (ehci, urb, mem_flags); 884 } 885} 886 887/* remove from hardware lists 888 * completions normally happen asynchronously 889 */ 890 891static int ehci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) 892{ 893 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 894 struct ehci_qh *qh; 895 unsigned long flags; 896 int rc; 897 898 spin_lock_irqsave (&ehci->lock, flags); 899 rc = usb_hcd_check_unlink_urb(hcd, urb, status); 900 if (rc) 901 goto done; 902 903 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { 904 /* 905 * We don't expedite dequeue for isochronous URBs. 906 * Just wait until they complete normally or their 907 * time slot expires. 908 */ 909 } else { 910 qh = (struct ehci_qh *) urb->hcpriv; 911 qh->exception = 1; 912 switch (qh->qh_state) { 913 case QH_STATE_LINKED: 914 if (usb_pipetype(urb->pipe) == PIPE_INTERRUPT) 915 start_unlink_intr(ehci, qh); 916 else 917 start_unlink_async(ehci, qh); 918 break; 919 case QH_STATE_COMPLETING: 920 qh->dequeue_during_giveback = 1; 921 break; 922 case QH_STATE_UNLINK: 923 case QH_STATE_UNLINK_WAIT: 924 /* already started */ 925 break; 926 case QH_STATE_IDLE: 927 /* QH might be waiting for a Clear-TT-Buffer */ 928 qh_completions(ehci, qh); 929 break; 930 } 931 } 932done: 933 spin_unlock_irqrestore (&ehci->lock, flags); 934 return rc; 935} 936 937/*-------------------------------------------------------------------------*/ 938 939// bulk qh holds the data toggle 940 941static void 942ehci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep) 943{ 944 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 945 unsigned long flags; 946 struct ehci_qh *qh; 947 948 /* ASSERT: any requests/urbs are being unlinked */ 949 /* ASSERT: nobody can be submitting urbs for this any more */ 950 951rescan: 952 spin_lock_irqsave (&ehci->lock, flags); 953 qh = ep->hcpriv; 954 if (!qh) 955 goto done; 956 957 /* endpoints can be iso streams. for now, we don't 958 * accelerate iso completions ... so spin a while. 959 */ 960 if (qh->hw == NULL) { 961 struct ehci_iso_stream *stream = ep->hcpriv; 962 963 if (!list_empty(&stream->td_list)) 964 goto idle_timeout; 965 966 /* BUG_ON(!list_empty(&stream->free_list)); */ 967 reserve_release_iso_bandwidth(ehci, stream, -1); 968 kfree(stream); 969 goto done; 970 } 971 972 qh->exception = 1; 973 switch (qh->qh_state) { 974 case QH_STATE_LINKED: 975 WARN_ON(!list_empty(&qh->qtd_list)); 976 if (usb_endpoint_type(&ep->desc) != USB_ENDPOINT_XFER_INT) 977 start_unlink_async(ehci, qh); 978 else 979 start_unlink_intr(ehci, qh); 980 /* FALL THROUGH */ 981 case QH_STATE_COMPLETING: /* already in unlinking */ 982 case QH_STATE_UNLINK: /* wait for hw to finish? */ 983 case QH_STATE_UNLINK_WAIT: 984idle_timeout: 985 spin_unlock_irqrestore (&ehci->lock, flags); 986 schedule_timeout_uninterruptible(1); 987 goto rescan; 988 case QH_STATE_IDLE: /* fully unlinked */ 989 if (qh->clearing_tt) 990 goto idle_timeout; 991 if (list_empty (&qh->qtd_list)) { 992 if (qh->ps.bw_uperiod) 993 reserve_release_intr_bandwidth(ehci, qh, -1); 994 qh_destroy(ehci, qh); 995 break; 996 } 997 /* else FALL THROUGH */ 998 default: 999 /* caller was supposed to have unlinked any requests; 1000 * that's not our job. just leak this memory. 1001 */ 1002 ehci_err (ehci, "qh %p (#%02x) state %d%s\n", 1003 qh, ep->desc.bEndpointAddress, qh->qh_state, 1004 list_empty (&qh->qtd_list) ? "" : "(has tds)"); 1005 break; 1006 } 1007 done: 1008 ep->hcpriv = NULL; 1009 spin_unlock_irqrestore (&ehci->lock, flags); 1010} 1011 1012static void 1013ehci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep) 1014{ 1015 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 1016 struct ehci_qh *qh; 1017 int eptype = usb_endpoint_type(&ep->desc); 1018 int epnum = usb_endpoint_num(&ep->desc); 1019 int is_out = usb_endpoint_dir_out(&ep->desc); 1020 unsigned long flags; 1021 1022 if (eptype != USB_ENDPOINT_XFER_BULK && eptype != USB_ENDPOINT_XFER_INT) 1023 return; 1024 1025 spin_lock_irqsave(&ehci->lock, flags); 1026 qh = ep->hcpriv; 1027 1028 /* For Bulk and Interrupt endpoints we maintain the toggle state 1029 * in the hardware; the toggle bits in udev aren't used at all. 1030 * When an endpoint is reset by usb_clear_halt() we must reset 1031 * the toggle bit in the QH. 1032 */ 1033 if (qh) { 1034 if (!list_empty(&qh->qtd_list)) { 1035 WARN_ONCE(1, "clear_halt for a busy endpoint\n"); 1036 } else { 1037 /* The toggle value in the QH can't be updated 1038 * while the QH is active. Unlink it now; 1039 * re-linking will call qh_refresh(). 1040 */ 1041 usb_settoggle(qh->ps.udev, epnum, is_out, 0); 1042 qh->exception = 1; 1043 if (eptype == USB_ENDPOINT_XFER_BULK) 1044 start_unlink_async(ehci, qh); 1045 else 1046 start_unlink_intr(ehci, qh); 1047 } 1048 } 1049 spin_unlock_irqrestore(&ehci->lock, flags); 1050} 1051 1052static int ehci_get_frame (struct usb_hcd *hcd) 1053{ 1054 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 1055 return (ehci_read_frame_index(ehci) >> 3) % ehci->periodic_size; 1056} 1057 1058/*-------------------------------------------------------------------------*/ 1059 1060/* Device addition and removal */ 1061 1062static void ehci_remove_device(struct usb_hcd *hcd, struct usb_device *udev) 1063{ 1064 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 1065 1066 spin_lock_irq(&ehci->lock); 1067 drop_tt(udev); 1068 spin_unlock_irq(&ehci->lock); 1069} 1070 1071/*-------------------------------------------------------------------------*/ 1072 1073#ifdef CONFIG_PM 1074 1075/* suspend/resume, section 4.3 */ 1076 1077/* These routines handle the generic parts of controller suspend/resume */ 1078 1079int ehci_suspend(struct usb_hcd *hcd, bool do_wakeup) 1080{ 1081 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 1082 1083 if (time_before(jiffies, ehci->next_statechange)) 1084 msleep(10); 1085 1086 /* 1087 * Root hub was already suspended. Disable IRQ emission and 1088 * mark HW unaccessible. The PM and USB cores make sure that 1089 * the root hub is either suspended or stopped. 1090 */ 1091 ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup); 1092 1093 spin_lock_irq(&ehci->lock); 1094 ehci_writel(ehci, 0, &ehci->regs->intr_enable); 1095 (void) ehci_readl(ehci, &ehci->regs->intr_enable); 1096 1097 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 1098 spin_unlock_irq(&ehci->lock); 1099 1100 synchronize_irq(hcd->irq); 1101 1102 /* Check for race with a wakeup request */ 1103 if (do_wakeup && HCD_WAKEUP_PENDING(hcd)) { 1104 ehci_resume(hcd, false); 1105 return -EBUSY; 1106 } 1107 1108 return 0; 1109} 1110EXPORT_SYMBOL_GPL(ehci_suspend); 1111 1112/* Returns 0 if power was preserved, 1 if power was lost */ 1113int ehci_resume(struct usb_hcd *hcd, bool force_reset) 1114{ 1115 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 1116 1117 if (time_before(jiffies, ehci->next_statechange)) 1118 msleep(100); 1119 1120 /* Mark hardware accessible again as we are back to full power by now */ 1121 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 1122 1123 if (ehci->shutdown) 1124 return 0; /* Controller is dead */ 1125 1126 /* 1127 * If CF is still set and reset isn't forced 1128 * then we maintained suspend power. 1129 * Just undo the effect of ehci_suspend(). 1130 */ 1131 if (ehci_readl(ehci, &ehci->regs->configured_flag) == FLAG_CF && 1132 !force_reset) { 1133 int mask = INTR_MASK; 1134 1135 ehci_prepare_ports_for_controller_resume(ehci); 1136 1137 spin_lock_irq(&ehci->lock); 1138 if (ehci->shutdown) 1139 goto skip; 1140 1141 if (!hcd->self.root_hub->do_remote_wakeup) 1142 mask &= ~STS_PCD; 1143 ehci_writel(ehci, mask, &ehci->regs->intr_enable); 1144 ehci_readl(ehci, &ehci->regs->intr_enable); 1145 skip: 1146 spin_unlock_irq(&ehci->lock); 1147 return 0; 1148 } 1149 1150 /* 1151 * Else reset, to cope with power loss or resume from hibernation 1152 * having let the firmware kick in during reboot. 1153 */ 1154 usb_root_hub_lost_power(hcd->self.root_hub); 1155 (void) ehci_halt(ehci); 1156 (void) ehci_reset(ehci); 1157 1158 spin_lock_irq(&ehci->lock); 1159 if (ehci->shutdown) 1160 goto skip; 1161 1162 ehci_writel(ehci, ehci->command, &ehci->regs->command); 1163 ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag); 1164 ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */ 1165 1166 ehci->rh_state = EHCI_RH_SUSPENDED; 1167 spin_unlock_irq(&ehci->lock); 1168 1169 return 1; 1170} 1171EXPORT_SYMBOL_GPL(ehci_resume); 1172 1173#endif 1174 1175/*-------------------------------------------------------------------------*/ 1176 1177/* 1178 * Generic structure: This gets copied for platform drivers so that 1179 * individual entries can be overridden as needed. 1180 */ 1181 1182static const struct hc_driver ehci_hc_driver = { 1183 .description = hcd_name, 1184 .product_desc = "EHCI Host Controller", 1185 .hcd_priv_size = sizeof(struct ehci_hcd), 1186 1187 /* 1188 * generic hardware linkage 1189 */ 1190 .irq = ehci_irq, 1191 .flags = HCD_MEMORY | HCD_USB2 | HCD_BH, 1192 1193 /* 1194 * basic lifecycle operations 1195 */ 1196 .reset = ehci_setup, 1197 .start = ehci_run, 1198 .stop = ehci_stop, 1199 .shutdown = ehci_shutdown, 1200 1201 /* 1202 * managing i/o requests and associated device resources 1203 */ 1204 .urb_enqueue = ehci_urb_enqueue, 1205 .urb_dequeue = ehci_urb_dequeue, 1206 .endpoint_disable = ehci_endpoint_disable, 1207 .endpoint_reset = ehci_endpoint_reset, 1208 .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, 1209 1210 /* 1211 * scheduling support 1212 */ 1213 .get_frame_number = ehci_get_frame, 1214 1215 /* 1216 * root hub support 1217 */ 1218 .hub_status_data = ehci_hub_status_data, 1219 .hub_control = ehci_hub_control, 1220 .bus_suspend = ehci_bus_suspend, 1221 .bus_resume = ehci_bus_resume, 1222 .relinquish_port = ehci_relinquish_port, 1223 .port_handed_over = ehci_port_handed_over, 1224 1225 /* 1226 * device support 1227 */ 1228 .free_dev = ehci_remove_device, 1229}; 1230 1231void ehci_init_driver(struct hc_driver *drv, 1232 const struct ehci_driver_overrides *over) 1233{ 1234 /* Copy the generic table to drv and then apply the overrides */ 1235 *drv = ehci_hc_driver; 1236 1237 if (over) { 1238 drv->hcd_priv_size += over->extra_priv_size; 1239 if (over->reset) 1240 drv->reset = over->reset; 1241 if (over->port_power) 1242 drv->port_power = over->port_power; 1243 } 1244} 1245EXPORT_SYMBOL_GPL(ehci_init_driver); 1246 1247/*-------------------------------------------------------------------------*/ 1248 1249MODULE_DESCRIPTION(DRIVER_DESC); 1250MODULE_AUTHOR (DRIVER_AUTHOR); 1251MODULE_LICENSE ("GPL"); 1252 1253#ifdef CONFIG_USB_EHCI_FSL 1254#include "ehci-fsl.c" 1255#define PLATFORM_DRIVER ehci_fsl_driver 1256#endif 1257 1258#ifdef CONFIG_USB_EHCI_SH 1259#include "ehci-sh.c" 1260#define PLATFORM_DRIVER ehci_hcd_sh_driver 1261#endif 1262 1263#ifdef CONFIG_PPC_PS3 1264#include "ehci-ps3.c" 1265#define PS3_SYSTEM_BUS_DRIVER ps3_ehci_driver 1266#endif 1267 1268#ifdef CONFIG_USB_EHCI_HCD_PPC_OF 1269#include "ehci-ppc-of.c" 1270#define OF_PLATFORM_DRIVER ehci_hcd_ppc_of_driver 1271#endif 1272 1273#ifdef CONFIG_XPS_USB_HCD_XILINX 1274#include "ehci-xilinx-of.c" 1275#define XILINX_OF_PLATFORM_DRIVER ehci_hcd_xilinx_of_driver 1276#endif 1277 1278#ifdef CONFIG_TILE_USB 1279#include "ehci-tilegx.c" 1280#define PLATFORM_DRIVER ehci_hcd_tilegx_driver 1281#endif 1282 1283#ifdef CONFIG_USB_EHCI_HCD_PMC_MSP 1284#include "ehci-pmcmsp.c" 1285#define PLATFORM_DRIVER ehci_hcd_msp_driver 1286#endif 1287 1288#ifdef CONFIG_SPARC_LEON 1289#include "ehci-grlib.c" 1290#define PLATFORM_DRIVER ehci_grlib_driver 1291#endif 1292 1293#ifdef CONFIG_USB_EHCI_MV 1294#include "ehci-mv.c" 1295#define PLATFORM_DRIVER ehci_mv_driver 1296#endif 1297 1298#ifdef CONFIG_MIPS_SEAD3 1299#include "ehci-sead3.c" 1300#define PLATFORM_DRIVER ehci_hcd_sead3_driver 1301#endif 1302 1303static int __init ehci_hcd_init(void) 1304{ 1305 int retval = 0; 1306 1307 if (usb_disabled()) 1308 return -ENODEV; 1309 1310 printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name); 1311 set_bit(USB_EHCI_LOADED, &usb_hcds_loaded); 1312 if (test_bit(USB_UHCI_LOADED, &usb_hcds_loaded) || 1313 test_bit(USB_OHCI_LOADED, &usb_hcds_loaded)) 1314 printk(KERN_WARNING "Warning! ehci_hcd should always be loaded" 1315 " before uhci_hcd and ohci_hcd, not after\n"); 1316 1317 pr_debug("%s: block sizes: qh %Zd qtd %Zd itd %Zd sitd %Zd\n", 1318 hcd_name, 1319 sizeof(struct ehci_qh), sizeof(struct ehci_qtd), 1320 sizeof(struct ehci_itd), sizeof(struct ehci_sitd)); 1321 1322#ifdef CONFIG_DYNAMIC_DEBUG 1323 ehci_debug_root = debugfs_create_dir("ehci", usb_debug_root); 1324 if (!ehci_debug_root) { 1325 retval = -ENOENT; 1326 goto err_debug; 1327 } 1328#endif 1329 1330#ifdef PLATFORM_DRIVER 1331 retval = platform_driver_register(&PLATFORM_DRIVER); 1332 if (retval < 0) 1333 goto clean0; 1334#endif 1335 1336#ifdef PS3_SYSTEM_BUS_DRIVER 1337 retval = ps3_ehci_driver_register(&PS3_SYSTEM_BUS_DRIVER); 1338 if (retval < 0) 1339 goto clean2; 1340#endif 1341 1342#ifdef OF_PLATFORM_DRIVER 1343 retval = platform_driver_register(&OF_PLATFORM_DRIVER); 1344 if (retval < 0) 1345 goto clean3; 1346#endif 1347 1348#ifdef XILINX_OF_PLATFORM_DRIVER 1349 retval = platform_driver_register(&XILINX_OF_PLATFORM_DRIVER); 1350 if (retval < 0) 1351 goto clean4; 1352#endif 1353 return retval; 1354 1355#ifdef XILINX_OF_PLATFORM_DRIVER 1356 /* platform_driver_unregister(&XILINX_OF_PLATFORM_DRIVER); */ 1357clean4: 1358#endif 1359#ifdef OF_PLATFORM_DRIVER 1360 platform_driver_unregister(&OF_PLATFORM_DRIVER); 1361clean3: 1362#endif 1363#ifdef PS3_SYSTEM_BUS_DRIVER 1364 ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER); 1365clean2: 1366#endif 1367#ifdef PLATFORM_DRIVER 1368 platform_driver_unregister(&PLATFORM_DRIVER); 1369clean0: 1370#endif 1371#ifdef CONFIG_DYNAMIC_DEBUG 1372 debugfs_remove(ehci_debug_root); 1373 ehci_debug_root = NULL; 1374err_debug: 1375#endif 1376 clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded); 1377 return retval; 1378} 1379module_init(ehci_hcd_init); 1380 1381static void __exit ehci_hcd_cleanup(void) 1382{ 1383#ifdef XILINX_OF_PLATFORM_DRIVER 1384 platform_driver_unregister(&XILINX_OF_PLATFORM_DRIVER); 1385#endif 1386#ifdef OF_PLATFORM_DRIVER 1387 platform_driver_unregister(&OF_PLATFORM_DRIVER); 1388#endif 1389#ifdef PLATFORM_DRIVER 1390 platform_driver_unregister(&PLATFORM_DRIVER); 1391#endif 1392#ifdef PS3_SYSTEM_BUS_DRIVER 1393 ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER); 1394#endif 1395#ifdef CONFIG_DYNAMIC_DEBUG 1396 debugfs_remove(ehci_debug_root); 1397#endif 1398 clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded); 1399} 1400module_exit(ehci_hcd_cleanup); 1401