1/** 2 * core.h - DesignWare USB3 DRD Core Header 3 * 4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com 5 * 6 * Authors: Felipe Balbi <balbi@ti.com>, 7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 8 * 9 * This program is free software: you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 of 11 * the License as published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19#ifndef __DRIVERS_USB_DWC3_CORE_H 20#define __DRIVERS_USB_DWC3_CORE_H 21 22#include <linux/device.h> 23#include <linux/spinlock.h> 24#include <linux/ioport.h> 25#include <linux/list.h> 26#include <linux/dma-mapping.h> 27#include <linux/mm.h> 28#include <linux/debugfs.h> 29 30#include <linux/usb/ch9.h> 31#include <linux/usb/gadget.h> 32#include <linux/usb/otg.h> 33 34#include <linux/phy/phy.h> 35 36#define DWC3_MSG_MAX 500 37 38/* Global constants */ 39#define DWC3_EP0_BOUNCE_SIZE 512 40#define DWC3_ENDPOINTS_NUM 32 41#define DWC3_XHCI_RESOURCES_NUM 2 42 43#define DWC3_SCRATCHBUF_SIZE 4096 /* each buffer is assumed to be 4KiB */ 44#define DWC3_EVENT_SIZE 4 /* bytes */ 45#define DWC3_EVENT_MAX_NUM 64 /* 2 events/endpoint */ 46#define DWC3_EVENT_BUFFERS_SIZE (DWC3_EVENT_SIZE * DWC3_EVENT_MAX_NUM) 47#define DWC3_EVENT_TYPE_MASK 0xfe 48 49#define DWC3_EVENT_TYPE_DEV 0 50#define DWC3_EVENT_TYPE_CARKIT 3 51#define DWC3_EVENT_TYPE_I2C 4 52 53#define DWC3_DEVICE_EVENT_DISCONNECT 0 54#define DWC3_DEVICE_EVENT_RESET 1 55#define DWC3_DEVICE_EVENT_CONNECT_DONE 2 56#define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3 57#define DWC3_DEVICE_EVENT_WAKEUP 4 58#define DWC3_DEVICE_EVENT_HIBER_REQ 5 59#define DWC3_DEVICE_EVENT_EOPF 6 60#define DWC3_DEVICE_EVENT_SOF 7 61#define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9 62#define DWC3_DEVICE_EVENT_CMD_CMPL 10 63#define DWC3_DEVICE_EVENT_OVERFLOW 11 64 65#define DWC3_GEVNTCOUNT_MASK 0xfffc 66#define DWC3_GSNPSID_MASK 0xffff0000 67#define DWC3_GSNPSREV_MASK 0xffff 68 69/* DWC3 registers memory space boundries */ 70#define DWC3_XHCI_REGS_START 0x0 71#define DWC3_XHCI_REGS_END 0x7fff 72#define DWC3_GLOBALS_REGS_START 0xc100 73#define DWC3_GLOBALS_REGS_END 0xc6ff 74#define DWC3_DEVICE_REGS_START 0xc700 75#define DWC3_DEVICE_REGS_END 0xcbff 76#define DWC3_OTG_REGS_START 0xcc00 77#define DWC3_OTG_REGS_END 0xccff 78 79/* Global Registers */ 80#define DWC3_GSBUSCFG0 0xc100 81#define DWC3_GSBUSCFG1 0xc104 82#define DWC3_GTXTHRCFG 0xc108 83#define DWC3_GRXTHRCFG 0xc10c 84#define DWC3_GCTL 0xc110 85#define DWC3_GEVTEN 0xc114 86#define DWC3_GSTS 0xc118 87#define DWC3_GSNPSID 0xc120 88#define DWC3_GGPIO 0xc124 89#define DWC3_GUID 0xc128 90#define DWC3_GUCTL 0xc12c 91#define DWC3_GBUSERRADDR0 0xc130 92#define DWC3_GBUSERRADDR1 0xc134 93#define DWC3_GPRTBIMAP0 0xc138 94#define DWC3_GPRTBIMAP1 0xc13c 95#define DWC3_GHWPARAMS0 0xc140 96#define DWC3_GHWPARAMS1 0xc144 97#define DWC3_GHWPARAMS2 0xc148 98#define DWC3_GHWPARAMS3 0xc14c 99#define DWC3_GHWPARAMS4 0xc150 100#define DWC3_GHWPARAMS5 0xc154 101#define DWC3_GHWPARAMS6 0xc158 102#define DWC3_GHWPARAMS7 0xc15c 103#define DWC3_GDBGFIFOSPACE 0xc160 104#define DWC3_GDBGLTSSM 0xc164 105#define DWC3_GPRTBIMAP_HS0 0xc180 106#define DWC3_GPRTBIMAP_HS1 0xc184 107#define DWC3_GPRTBIMAP_FS0 0xc188 108#define DWC3_GPRTBIMAP_FS1 0xc18c 109 110#define DWC3_VER_NUMBER 0xc1a0 111#define DWC3_VER_TYPE 0xc1a4 112 113#define DWC3_GUSB2PHYCFG(n) (0xc200 + (n * 0x04)) 114#define DWC3_GUSB2I2CCTL(n) (0xc240 + (n * 0x04)) 115 116#define DWC3_GUSB2PHYACC(n) (0xc280 + (n * 0x04)) 117 118#define DWC3_GUSB3PIPECTL(n) (0xc2c0 + (n * 0x04)) 119 120#define DWC3_GTXFIFOSIZ(n) (0xc300 + (n * 0x04)) 121#define DWC3_GRXFIFOSIZ(n) (0xc380 + (n * 0x04)) 122 123#define DWC3_GEVNTADRLO(n) (0xc400 + (n * 0x10)) 124#define DWC3_GEVNTADRHI(n) (0xc404 + (n * 0x10)) 125#define DWC3_GEVNTSIZ(n) (0xc408 + (n * 0x10)) 126#define DWC3_GEVNTCOUNT(n) (0xc40c + (n * 0x10)) 127 128#define DWC3_GHWPARAMS8 0xc600 129 130/* Device Registers */ 131#define DWC3_DCFG 0xc700 132#define DWC3_DCTL 0xc704 133#define DWC3_DEVTEN 0xc708 134#define DWC3_DSTS 0xc70c 135#define DWC3_DGCMDPAR 0xc710 136#define DWC3_DGCMD 0xc714 137#define DWC3_DALEPENA 0xc720 138#define DWC3_DEPCMDPAR2(n) (0xc800 + (n * 0x10)) 139#define DWC3_DEPCMDPAR1(n) (0xc804 + (n * 0x10)) 140#define DWC3_DEPCMDPAR0(n) (0xc808 + (n * 0x10)) 141#define DWC3_DEPCMD(n) (0xc80c + (n * 0x10)) 142 143/* OTG Registers */ 144#define DWC3_OCFG 0xcc00 145#define DWC3_OCTL 0xcc04 146#define DWC3_OEVT 0xcc08 147#define DWC3_OEVTEN 0xcc0C 148#define DWC3_OSTS 0xcc10 149 150/* Bit fields */ 151 152/* Global Configuration Register */ 153#define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19) 154#define DWC3_GCTL_U2RSTECN (1 << 16) 155#define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6) 156#define DWC3_GCTL_CLK_BUS (0) 157#define DWC3_GCTL_CLK_PIPE (1) 158#define DWC3_GCTL_CLK_PIPEHALF (2) 159#define DWC3_GCTL_CLK_MASK (3) 160 161#define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12) 162#define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12) 163#define DWC3_GCTL_PRTCAP_HOST 1 164#define DWC3_GCTL_PRTCAP_DEVICE 2 165#define DWC3_GCTL_PRTCAP_OTG 3 166 167#define DWC3_GCTL_CORESOFTRESET (1 << 11) 168#define DWC3_GCTL_SOFITPSYNC (1 << 10) 169#define DWC3_GCTL_SCALEDOWN(n) ((n) << 4) 170#define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3) 171#define DWC3_GCTL_DISSCRAMBLE (1 << 3) 172#define DWC3_GCTL_U2EXIT_LFPS (1 << 2) 173#define DWC3_GCTL_GBLHIBERNATIONEN (1 << 1) 174#define DWC3_GCTL_DSBLCLKGTNG (1 << 0) 175 176/* Global USB2 PHY Configuration Register */ 177#define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31) 178#define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6) 179 180/* Global USB3 PIPE Control Register */ 181#define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31) 182#define DWC3_GUSB3PIPECTL_U2SSINP3OK (1 << 29) 183#define DWC3_GUSB3PIPECTL_REQP1P2P3 (1 << 24) 184#define DWC3_GUSB3PIPECTL_DEP1P2P3(n) ((n) << 19) 185#define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK DWC3_GUSB3PIPECTL_DEP1P2P3(7) 186#define DWC3_GUSB3PIPECTL_DEP1P2P3_EN DWC3_GUSB3PIPECTL_DEP1P2P3(1) 187#define DWC3_GUSB3PIPECTL_DEPOCHANGE (1 << 18) 188#define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17) 189#define DWC3_GUSB3PIPECTL_LFPSFILT (1 << 9) 190#define DWC3_GUSB3PIPECTL_RX_DETOPOLL (1 << 8) 191#define DWC3_GUSB3PIPECTL_TX_DEEPH_MASK DWC3_GUSB3PIPECTL_TX_DEEPH(3) 192#define DWC3_GUSB3PIPECTL_TX_DEEPH(n) ((n) << 1) 193 194/* Global TX Fifo Size Register */ 195#define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff) 196#define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000) 197 198/* Global Event Size Registers */ 199#define DWC3_GEVNTSIZ_INTMASK (1 << 31) 200#define DWC3_GEVNTSIZ_SIZE(n) ((n) & 0xffff) 201 202/* Global HWPARAMS1 Register */ 203#define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24) 204#define DWC3_GHWPARAMS1_EN_PWROPT_NO 0 205#define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1 206#define DWC3_GHWPARAMS1_EN_PWROPT_HIB 2 207#define DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24) 208#define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3) 209 210/* Global HWPARAMS3 Register */ 211#define DWC3_GHWPARAMS3_SSPHY_IFC(n) ((n) & 3) 212#define DWC3_GHWPARAMS3_SSPHY_IFC_DIS 0 213#define DWC3_GHWPARAMS3_SSPHY_IFC_ENA 1 214#define DWC3_GHWPARAMS3_HSPHY_IFC(n) (((n) & (3 << 2)) >> 2) 215#define DWC3_GHWPARAMS3_HSPHY_IFC_DIS 0 216#define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI 1 217#define DWC3_GHWPARAMS3_HSPHY_IFC_ULPI 2 218#define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI 3 219#define DWC3_GHWPARAMS3_FSPHY_IFC(n) (((n) & (3 << 4)) >> 4) 220#define DWC3_GHWPARAMS3_FSPHY_IFC_DIS 0 221#define DWC3_GHWPARAMS3_FSPHY_IFC_ENA 1 222 223/* Global HWPARAMS4 Register */ 224#define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13) 225#define DWC3_MAX_HIBER_SCRATCHBUFS 15 226 227/* Global HWPARAMS6 Register */ 228#define DWC3_GHWPARAMS6_EN_FPGA (1 << 7) 229 230/* Device Configuration Register */ 231#define DWC3_DCFG_DEVADDR(addr) ((addr) << 3) 232#define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f) 233 234#define DWC3_DCFG_SPEED_MASK (7 << 0) 235#define DWC3_DCFG_SUPERSPEED (4 << 0) 236#define DWC3_DCFG_HIGHSPEED (0 << 0) 237#define DWC3_DCFG_FULLSPEED2 (1 << 0) 238#define DWC3_DCFG_LOWSPEED (2 << 0) 239#define DWC3_DCFG_FULLSPEED1 (3 << 0) 240 241#define DWC3_DCFG_LPM_CAP (1 << 22) 242 243/* Device Control Register */ 244#define DWC3_DCTL_RUN_STOP (1 << 31) 245#define DWC3_DCTL_CSFTRST (1 << 30) 246#define DWC3_DCTL_LSFTRST (1 << 29) 247 248#define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24) 249#define DWC3_DCTL_HIRD_THRES(n) ((n) << 24) 250 251#define DWC3_DCTL_APPL1RES (1 << 23) 252 253/* These apply for core versions 1.87a and earlier */ 254#define DWC3_DCTL_TRGTULST_MASK (0x0f << 17) 255#define DWC3_DCTL_TRGTULST(n) ((n) << 17) 256#define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2)) 257#define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3)) 258#define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4)) 259#define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5)) 260#define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6)) 261 262/* These apply for core versions 1.94a and later */ 263#define DWC3_DCTL_LPM_ERRATA_MASK DWC3_DCTL_LPM_ERRATA(0xf) 264#define DWC3_DCTL_LPM_ERRATA(n) ((n) << 20) 265 266#define DWC3_DCTL_KEEP_CONNECT (1 << 19) 267#define DWC3_DCTL_L1_HIBER_EN (1 << 18) 268#define DWC3_DCTL_CRS (1 << 17) 269#define DWC3_DCTL_CSS (1 << 16) 270 271#define DWC3_DCTL_INITU2ENA (1 << 12) 272#define DWC3_DCTL_ACCEPTU2ENA (1 << 11) 273#define DWC3_DCTL_INITU1ENA (1 << 10) 274#define DWC3_DCTL_ACCEPTU1ENA (1 << 9) 275#define DWC3_DCTL_TSTCTRL_MASK (0xf << 1) 276 277#define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5) 278#define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK) 279 280#define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0)) 281#define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4)) 282#define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5)) 283#define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6)) 284#define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8)) 285#define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10)) 286#define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11)) 287 288/* Device Event Enable Register */ 289#define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN (1 << 12) 290#define DWC3_DEVTEN_EVNTOVERFLOWEN (1 << 11) 291#define DWC3_DEVTEN_CMDCMPLTEN (1 << 10) 292#define DWC3_DEVTEN_ERRTICERREN (1 << 9) 293#define DWC3_DEVTEN_SOFEN (1 << 7) 294#define DWC3_DEVTEN_EOPFEN (1 << 6) 295#define DWC3_DEVTEN_HIBERNATIONREQEVTEN (1 << 5) 296#define DWC3_DEVTEN_WKUPEVTEN (1 << 4) 297#define DWC3_DEVTEN_ULSTCNGEN (1 << 3) 298#define DWC3_DEVTEN_CONNECTDONEEN (1 << 2) 299#define DWC3_DEVTEN_USBRSTEN (1 << 1) 300#define DWC3_DEVTEN_DISCONNEVTEN (1 << 0) 301 302/* Device Status Register */ 303#define DWC3_DSTS_DCNRD (1 << 29) 304 305/* This applies for core versions 1.87a and earlier */ 306#define DWC3_DSTS_PWRUPREQ (1 << 24) 307 308/* These apply for core versions 1.94a and later */ 309#define DWC3_DSTS_RSS (1 << 25) 310#define DWC3_DSTS_SSS (1 << 24) 311 312#define DWC3_DSTS_COREIDLE (1 << 23) 313#define DWC3_DSTS_DEVCTRLHLT (1 << 22) 314 315#define DWC3_DSTS_USBLNKST_MASK (0x0f << 18) 316#define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18) 317 318#define DWC3_DSTS_RXFIFOEMPTY (1 << 17) 319 320#define DWC3_DSTS_SOFFN_MASK (0x3fff << 3) 321#define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3) 322 323#define DWC3_DSTS_CONNECTSPD (7 << 0) 324 325#define DWC3_DSTS_SUPERSPEED (4 << 0) 326#define DWC3_DSTS_HIGHSPEED (0 << 0) 327#define DWC3_DSTS_FULLSPEED2 (1 << 0) 328#define DWC3_DSTS_LOWSPEED (2 << 0) 329#define DWC3_DSTS_FULLSPEED1 (3 << 0) 330 331/* Device Generic Command Register */ 332#define DWC3_DGCMD_SET_LMP 0x01 333#define DWC3_DGCMD_SET_PERIODIC_PAR 0x02 334#define DWC3_DGCMD_XMIT_FUNCTION 0x03 335 336/* These apply for core versions 1.94a and later */ 337#define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04 338#define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05 339 340#define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09 341#define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a 342#define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c 343#define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10 344 345#define DWC3_DGCMD_STATUS(n) (((n) >> 12) & 0x0F) 346#define DWC3_DGCMD_CMDACT (1 << 10) 347#define DWC3_DGCMD_CMDIOC (1 << 8) 348 349/* Device Generic Command Parameter Register */ 350#define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT (1 << 0) 351#define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0) 352#define DWC3_DGCMDPAR_RX_FIFO (0 << 5) 353#define DWC3_DGCMDPAR_TX_FIFO (1 << 5) 354#define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0) 355#define DWC3_DGCMDPAR_LOOPBACK_ENA (1 << 0) 356 357/* Device Endpoint Command Register */ 358#define DWC3_DEPCMD_PARAM_SHIFT 16 359#define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT) 360#define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f) 361#define DWC3_DEPCMD_STATUS(x) (((x) >> 12) & 0x0F) 362#define DWC3_DEPCMD_HIPRI_FORCERM (1 << 11) 363#define DWC3_DEPCMD_CMDACT (1 << 10) 364#define DWC3_DEPCMD_CMDIOC (1 << 8) 365 366#define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0) 367#define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0) 368#define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0) 369#define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0) 370#define DWC3_DEPCMD_CLEARSTALL (0x05 << 0) 371#define DWC3_DEPCMD_SETSTALL (0x04 << 0) 372/* This applies for core versions 1.90a and earlier */ 373#define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0) 374/* This applies for core versions 1.94a and later */ 375#define DWC3_DEPCMD_GETEPSTATE (0x03 << 0) 376#define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0) 377#define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0) 378 379/* The EP number goes 0..31 so ep0 is always out and ep1 is always in */ 380#define DWC3_DALEPENA_EP(n) (1 << n) 381 382#define DWC3_DEPCMD_TYPE_CONTROL 0 383#define DWC3_DEPCMD_TYPE_ISOC 1 384#define DWC3_DEPCMD_TYPE_BULK 2 385#define DWC3_DEPCMD_TYPE_INTR 3 386 387/* Structures */ 388 389struct dwc3_trb; 390 391/** 392 * struct dwc3_event_buffer - Software event buffer representation 393 * @buf: _THE_ buffer 394 * @length: size of this buffer 395 * @lpos: event offset 396 * @count: cache of last read event count register 397 * @flags: flags related to this event buffer 398 * @dma: dma_addr_t 399 * @dwc: pointer to DWC controller 400 */ 401struct dwc3_event_buffer { 402 void *buf; 403 unsigned length; 404 unsigned int lpos; 405 unsigned int count; 406 unsigned int flags; 407 408#define DWC3_EVENT_PENDING BIT(0) 409 410 dma_addr_t dma; 411 412 struct dwc3 *dwc; 413}; 414 415#define DWC3_EP_FLAG_STALLED (1 << 0) 416#define DWC3_EP_FLAG_WEDGED (1 << 1) 417 418#define DWC3_EP_DIRECTION_TX true 419#define DWC3_EP_DIRECTION_RX false 420 421#define DWC3_TRB_NUM 32 422#define DWC3_TRB_MASK (DWC3_TRB_NUM - 1) 423 424/** 425 * struct dwc3_ep - device side endpoint representation 426 * @endpoint: usb endpoint 427 * @request_list: list of requests for this endpoint 428 * @req_queued: list of requests on this ep which have TRBs setup 429 * @trb_pool: array of transaction buffers 430 * @trb_pool_dma: dma address of @trb_pool 431 * @free_slot: next slot which is going to be used 432 * @busy_slot: first slot which is owned by HW 433 * @desc: usb_endpoint_descriptor pointer 434 * @dwc: pointer to DWC controller 435 * @saved_state: ep state saved during hibernation 436 * @flags: endpoint flags (wedged, stalled, ...) 437 * @number: endpoint number (1 - 15) 438 * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK 439 * @resource_index: Resource transfer index 440 * @interval: the interval on which the ISOC transfer is started 441 * @name: a human readable name e.g. ep1out-bulk 442 * @direction: true for TX, false for RX 443 * @stream_capable: true when streams are enabled 444 */ 445struct dwc3_ep { 446 struct usb_ep endpoint; 447 struct list_head request_list; 448 struct list_head req_queued; 449 450 struct dwc3_trb *trb_pool; 451 dma_addr_t trb_pool_dma; 452 u32 free_slot; 453 u32 busy_slot; 454 const struct usb_ss_ep_comp_descriptor *comp_desc; 455 struct dwc3 *dwc; 456 457 u32 saved_state; 458 unsigned flags; 459#define DWC3_EP_ENABLED (1 << 0) 460#define DWC3_EP_STALL (1 << 1) 461#define DWC3_EP_WEDGE (1 << 2) 462#define DWC3_EP_BUSY (1 << 4) 463#define DWC3_EP_PENDING_REQUEST (1 << 5) 464#define DWC3_EP_MISSED_ISOC (1 << 6) 465 466 /* This last one is specific to EP0 */ 467#define DWC3_EP0_DIR_IN (1 << 31) 468 469 u8 number; 470 u8 type; 471 u8 resource_index; 472 u32 interval; 473 474 char name[20]; 475 476 unsigned direction:1; 477 unsigned stream_capable:1; 478}; 479 480enum dwc3_phy { 481 DWC3_PHY_UNKNOWN = 0, 482 DWC3_PHY_USB3, 483 DWC3_PHY_USB2, 484}; 485 486enum dwc3_ep0_next { 487 DWC3_EP0_UNKNOWN = 0, 488 DWC3_EP0_COMPLETE, 489 DWC3_EP0_NRDY_DATA, 490 DWC3_EP0_NRDY_STATUS, 491}; 492 493enum dwc3_ep0_state { 494 EP0_UNCONNECTED = 0, 495 EP0_SETUP_PHASE, 496 EP0_DATA_PHASE, 497 EP0_STATUS_PHASE, 498}; 499 500enum dwc3_link_state { 501 /* In SuperSpeed */ 502 DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */ 503 DWC3_LINK_STATE_U1 = 0x01, 504 DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */ 505 DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */ 506 DWC3_LINK_STATE_SS_DIS = 0x04, 507 DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */ 508 DWC3_LINK_STATE_SS_INACT = 0x06, 509 DWC3_LINK_STATE_POLL = 0x07, 510 DWC3_LINK_STATE_RECOV = 0x08, 511 DWC3_LINK_STATE_HRESET = 0x09, 512 DWC3_LINK_STATE_CMPLY = 0x0a, 513 DWC3_LINK_STATE_LPBK = 0x0b, 514 DWC3_LINK_STATE_RESET = 0x0e, 515 DWC3_LINK_STATE_RESUME = 0x0f, 516 DWC3_LINK_STATE_MASK = 0x0f, 517}; 518 519/* TRB Length, PCM and Status */ 520#define DWC3_TRB_SIZE_MASK (0x00ffffff) 521#define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK) 522#define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24) 523#define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28) 524 525#define DWC3_TRBSTS_OK 0 526#define DWC3_TRBSTS_MISSED_ISOC 1 527#define DWC3_TRBSTS_SETUP_PENDING 2 528#define DWC3_TRB_STS_XFER_IN_PROG 4 529 530/* TRB Control */ 531#define DWC3_TRB_CTRL_HWO (1 << 0) 532#define DWC3_TRB_CTRL_LST (1 << 1) 533#define DWC3_TRB_CTRL_CHN (1 << 2) 534#define DWC3_TRB_CTRL_CSP (1 << 3) 535#define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4) 536#define DWC3_TRB_CTRL_ISP_IMI (1 << 10) 537#define DWC3_TRB_CTRL_IOC (1 << 11) 538#define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14) 539 540#define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1) 541#define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2) 542#define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3) 543#define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4) 544#define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5) 545#define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6) 546#define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7) 547#define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8) 548 549/** 550 * struct dwc3_trb - transfer request block (hw format) 551 * @bpl: DW0-3 552 * @bph: DW4-7 553 * @size: DW8-B 554 * @trl: DWC-F 555 */ 556struct dwc3_trb { 557 u32 bpl; 558 u32 bph; 559 u32 size; 560 u32 ctrl; 561} __packed; 562 563/** 564 * dwc3_hwparams - copy of HWPARAMS registers 565 * @hwparams0 - GHWPARAMS0 566 * @hwparams1 - GHWPARAMS1 567 * @hwparams2 - GHWPARAMS2 568 * @hwparams3 - GHWPARAMS3 569 * @hwparams4 - GHWPARAMS4 570 * @hwparams5 - GHWPARAMS5 571 * @hwparams6 - GHWPARAMS6 572 * @hwparams7 - GHWPARAMS7 573 * @hwparams8 - GHWPARAMS8 574 */ 575struct dwc3_hwparams { 576 u32 hwparams0; 577 u32 hwparams1; 578 u32 hwparams2; 579 u32 hwparams3; 580 u32 hwparams4; 581 u32 hwparams5; 582 u32 hwparams6; 583 u32 hwparams7; 584 u32 hwparams8; 585}; 586 587/* HWPARAMS0 */ 588#define DWC3_MODE(n) ((n) & 0x7) 589 590#define DWC3_MDWIDTH(n) (((n) & 0xff00) >> 8) 591 592/* HWPARAMS1 */ 593#define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15) 594 595/* HWPARAMS3 */ 596#define DWC3_NUM_IN_EPS_MASK (0x1f << 18) 597#define DWC3_NUM_EPS_MASK (0x3f << 12) 598#define DWC3_NUM_EPS(p) (((p)->hwparams3 & \ 599 (DWC3_NUM_EPS_MASK)) >> 12) 600#define DWC3_NUM_IN_EPS(p) (((p)->hwparams3 & \ 601 (DWC3_NUM_IN_EPS_MASK)) >> 18) 602 603/* HWPARAMS7 */ 604#define DWC3_RAM1_DEPTH(n) ((n) & 0xffff) 605 606struct dwc3_request { 607 struct usb_request request; 608 struct list_head list; 609 struct dwc3_ep *dep; 610 u32 start_slot; 611 612 u8 epnum; 613 struct dwc3_trb *trb; 614 dma_addr_t trb_dma; 615 616 unsigned direction:1; 617 unsigned mapped:1; 618 unsigned queued:1; 619}; 620 621/* 622 * struct dwc3_scratchpad_array - hibernation scratchpad array 623 * (format defined by hw) 624 */ 625struct dwc3_scratchpad_array { 626 __le64 dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS]; 627}; 628 629/** 630 * struct dwc3 - representation of our controller 631 * @ctrl_req: usb control request which is used for ep0 632 * @ep0_trb: trb which is used for the ctrl_req 633 * @ep0_bounce: bounce buffer for ep0 634 * @setup_buf: used while precessing STD USB requests 635 * @ctrl_req_addr: dma address of ctrl_req 636 * @ep0_trb: dma address of ep0_trb 637 * @ep0_usb_req: dummy req used while handling STD USB requests 638 * @ep0_bounce_addr: dma address of ep0_bounce 639 * @scratch_addr: dma address of scratchbuf 640 * @lock: for synchronizing 641 * @dev: pointer to our struct device 642 * @xhci: pointer to our xHCI child 643 * @event_buffer_list: a list of event buffers 644 * @gadget: device side representation of the peripheral controller 645 * @gadget_driver: pointer to the gadget driver 646 * @regs: base address for our registers 647 * @regs_size: address space size 648 * @nr_scratch: number of scratch buffers 649 * @num_event_buffers: calculated number of event buffers 650 * @u1u2: only used on revisions <1.83a for workaround 651 * @maximum_speed: maximum speed requested (mainly for testing purposes) 652 * @revision: revision register contents 653 * @dr_mode: requested mode of operation 654 * @usb2_phy: pointer to USB2 PHY 655 * @usb3_phy: pointer to USB3 PHY 656 * @usb2_generic_phy: pointer to USB2 PHY 657 * @usb3_generic_phy: pointer to USB3 PHY 658 * @dcfg: saved contents of DCFG register 659 * @gctl: saved contents of GCTL register 660 * @isoch_delay: wValue from Set Isochronous Delay request; 661 * @u2sel: parameter from Set SEL request. 662 * @u2pel: parameter from Set SEL request. 663 * @u1sel: parameter from Set SEL request. 664 * @u1pel: parameter from Set SEL request. 665 * @num_out_eps: number of out endpoints 666 * @num_in_eps: number of in endpoints 667 * @ep0_next_event: hold the next expected event 668 * @ep0state: state of endpoint zero 669 * @link_state: link state 670 * @speed: device speed (super, high, full, low) 671 * @mem: points to start of memory which is used for this struct. 672 * @hwparams: copy of hwparams registers 673 * @root: debugfs root folder pointer 674 * @regset: debugfs pointer to regdump file 675 * @test_mode: true when we're entering a USB test mode 676 * @test_mode_nr: test feature selector 677 * @lpm_nyet_threshold: LPM NYET response threshold 678 * @hird_threshold: HIRD threshold 679 * @delayed_status: true when gadget driver asks for delayed status 680 * @ep0_bounced: true when we used bounce buffer 681 * @ep0_expect_in: true when we expect a DATA IN transfer 682 * @has_hibernation: true when dwc3 was configured with Hibernation 683 * @has_lpm_erratum: true when core was configured with LPM Erratum. Note that 684 * there's now way for software to detect this in runtime. 685 * @is_utmi_l1_suspend: the core asserts output signal 686 * 0 - utmi_sleep_n 687 * 1 - utmi_l1_suspend_n 688 * @is_fpga: true when we are using the FPGA board 689 * @needs_fifo_resize: not all users might want fifo resizing, flag it 690 * @pullups_connected: true when Run/Stop bit is set 691 * @resize_fifos: tells us it's ok to reconfigure our TxFIFO sizes. 692 * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround 693 * @start_config_issued: true when StartConfig command has been issued 694 * @three_stage_setup: set if we perform a three phase setup 695 * @usb3_lpm_capable: set if hadrware supports Link Power Management 696 * @disable_scramble_quirk: set if we enable the disable scramble quirk 697 * @u2exit_lfps_quirk: set if we enable u2exit lfps quirk 698 * @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk 699 * @req_p1p2p3_quirk: set if we enable request p1p2p3 quirk 700 * @del_p1p2p3_quirk: set if we enable delay p1p2p3 quirk 701 * @del_phy_power_chg_quirk: set if we enable delay phy power change quirk 702 * @lfps_filter_quirk: set if we enable LFPS filter quirk 703 * @rx_detect_poll_quirk: set if we enable rx_detect to polling lfps quirk 704 * @dis_u3_susphy_quirk: set if we disable usb3 suspend phy 705 * @dis_u2_susphy_quirk: set if we disable usb2 suspend phy 706 * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk 707 * @tx_de_emphasis: Tx de-emphasis value 708 * 0 - -6dB de-emphasis 709 * 1 - -3.5dB de-emphasis 710 * 2 - No de-emphasis 711 * 3 - Reserved 712 */ 713struct dwc3 { 714 struct usb_ctrlrequest *ctrl_req; 715 struct dwc3_trb *ep0_trb; 716 void *ep0_bounce; 717 void *scratchbuf; 718 u8 *setup_buf; 719 dma_addr_t ctrl_req_addr; 720 dma_addr_t ep0_trb_addr; 721 dma_addr_t ep0_bounce_addr; 722 dma_addr_t scratch_addr; 723 struct dwc3_request ep0_usb_req; 724 725 /* device lock */ 726 spinlock_t lock; 727 728 struct device *dev; 729 730 struct platform_device *xhci; 731 struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM]; 732 733 struct dwc3_event_buffer **ev_buffs; 734 struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM]; 735 736 struct usb_gadget gadget; 737 struct usb_gadget_driver *gadget_driver; 738 739 struct usb_phy *usb2_phy; 740 struct usb_phy *usb3_phy; 741 742 struct phy *usb2_generic_phy; 743 struct phy *usb3_generic_phy; 744 745 void __iomem *regs; 746 size_t regs_size; 747 748 enum usb_dr_mode dr_mode; 749 750 /* used for suspend/resume */ 751 u32 dcfg; 752 u32 gctl; 753 754 u32 nr_scratch; 755 u32 num_event_buffers; 756 u32 u1u2; 757 u32 maximum_speed; 758 759 /* 760 * All 3.1 IP version constants are greater than the 3.0 IP 761 * version constants. This works for most version checks in 762 * dwc3. However, in the future, this may not apply as 763 * features may be developed on newer versions of the 3.0 IP 764 * that are not in the 3.1 IP. 765 */ 766 u32 revision; 767 768#define DWC3_REVISION_173A 0x5533173a 769#define DWC3_REVISION_175A 0x5533175a 770#define DWC3_REVISION_180A 0x5533180a 771#define DWC3_REVISION_183A 0x5533183a 772#define DWC3_REVISION_185A 0x5533185a 773#define DWC3_REVISION_187A 0x5533187a 774#define DWC3_REVISION_188A 0x5533188a 775#define DWC3_REVISION_190A 0x5533190a 776#define DWC3_REVISION_194A 0x5533194a 777#define DWC3_REVISION_200A 0x5533200a 778#define DWC3_REVISION_202A 0x5533202a 779#define DWC3_REVISION_210A 0x5533210a 780#define DWC3_REVISION_220A 0x5533220a 781#define DWC3_REVISION_230A 0x5533230a 782#define DWC3_REVISION_240A 0x5533240a 783#define DWC3_REVISION_250A 0x5533250a 784#define DWC3_REVISION_260A 0x5533260a 785#define DWC3_REVISION_270A 0x5533270a 786#define DWC3_REVISION_280A 0x5533280a 787 788/* 789 * NOTICE: we're using bit 31 as a "is usb 3.1" flag. This is really 790 * just so dwc31 revisions are always larger than dwc3. 791 */ 792#define DWC3_REVISION_IS_DWC31 0x80000000 793#define DWC3_USB31_REVISION_110A (0x3131302a | DWC3_REVISION_IS_USB31) 794 795 enum dwc3_ep0_next ep0_next_event; 796 enum dwc3_ep0_state ep0state; 797 enum dwc3_link_state link_state; 798 799 u16 isoch_delay; 800 u16 u2sel; 801 u16 u2pel; 802 u8 u1sel; 803 u8 u1pel; 804 805 u8 speed; 806 807 u8 num_out_eps; 808 u8 num_in_eps; 809 810 void *mem; 811 812 struct dwc3_hwparams hwparams; 813 struct dentry *root; 814 struct debugfs_regset32 *regset; 815 816 u8 test_mode; 817 u8 test_mode_nr; 818 u8 lpm_nyet_threshold; 819 u8 hird_threshold; 820 821 unsigned delayed_status:1; 822 unsigned ep0_bounced:1; 823 unsigned ep0_expect_in:1; 824 unsigned has_hibernation:1; 825 unsigned has_lpm_erratum:1; 826 unsigned is_utmi_l1_suspend:1; 827 unsigned is_fpga:1; 828 unsigned needs_fifo_resize:1; 829 unsigned pullups_connected:1; 830 unsigned resize_fifos:1; 831 unsigned setup_packet_pending:1; 832 unsigned three_stage_setup:1; 833 unsigned usb3_lpm_capable:1; 834 835 unsigned disable_scramble_quirk:1; 836 unsigned u2exit_lfps_quirk:1; 837 unsigned u2ss_inp3_quirk:1; 838 unsigned req_p1p2p3_quirk:1; 839 unsigned del_p1p2p3_quirk:1; 840 unsigned del_phy_power_chg_quirk:1; 841 unsigned lfps_filter_quirk:1; 842 unsigned rx_detect_poll_quirk:1; 843 unsigned dis_u3_susphy_quirk:1; 844 unsigned dis_u2_susphy_quirk:1; 845 846 unsigned tx_de_emphasis_quirk:1; 847 unsigned tx_de_emphasis:2; 848}; 849 850/* -------------------------------------------------------------------------- */ 851 852/* -------------------------------------------------------------------------- */ 853 854struct dwc3_event_type { 855 u32 is_devspec:1; 856 u32 type:7; 857 u32 reserved8_31:24; 858} __packed; 859 860#define DWC3_DEPEVT_XFERCOMPLETE 0x01 861#define DWC3_DEPEVT_XFERINPROGRESS 0x02 862#define DWC3_DEPEVT_XFERNOTREADY 0x03 863#define DWC3_DEPEVT_RXTXFIFOEVT 0x04 864#define DWC3_DEPEVT_STREAMEVT 0x06 865#define DWC3_DEPEVT_EPCMDCMPLT 0x07 866 867/** 868 * struct dwc3_event_depvt - Device Endpoint Events 869 * @one_bit: indicates this is an endpoint event (not used) 870 * @endpoint_number: number of the endpoint 871 * @endpoint_event: The event we have: 872 * 0x00 - Reserved 873 * 0x01 - XferComplete 874 * 0x02 - XferInProgress 875 * 0x03 - XferNotReady 876 * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun) 877 * 0x05 - Reserved 878 * 0x06 - StreamEvt 879 * 0x07 - EPCmdCmplt 880 * @reserved11_10: Reserved, don't use. 881 * @status: Indicates the status of the event. Refer to databook for 882 * more information. 883 * @parameters: Parameters of the current event. Refer to databook for 884 * more information. 885 */ 886struct dwc3_event_depevt { 887 u32 one_bit:1; 888 u32 endpoint_number:5; 889 u32 endpoint_event:4; 890 u32 reserved11_10:2; 891 u32 status:4; 892 893/* Within XferNotReady */ 894#define DEPEVT_STATUS_TRANSFER_ACTIVE (1 << 3) 895 896/* Within XferComplete */ 897#define DEPEVT_STATUS_BUSERR (1 << 0) 898#define DEPEVT_STATUS_SHORT (1 << 1) 899#define DEPEVT_STATUS_IOC (1 << 2) 900#define DEPEVT_STATUS_LST (1 << 3) 901 902/* Stream event only */ 903#define DEPEVT_STREAMEVT_FOUND 1 904#define DEPEVT_STREAMEVT_NOTFOUND 2 905 906/* Control-only Status */ 907#define DEPEVT_STATUS_CONTROL_DATA 1 908#define DEPEVT_STATUS_CONTROL_STATUS 2 909 910 u32 parameters:16; 911} __packed; 912 913/** 914 * struct dwc3_event_devt - Device Events 915 * @one_bit: indicates this is a non-endpoint event (not used) 916 * @device_event: indicates it's a device event. Should read as 0x00 917 * @type: indicates the type of device event. 918 * 0 - DisconnEvt 919 * 1 - USBRst 920 * 2 - ConnectDone 921 * 3 - ULStChng 922 * 4 - WkUpEvt 923 * 5 - Reserved 924 * 6 - EOPF 925 * 7 - SOF 926 * 8 - Reserved 927 * 9 - ErrticErr 928 * 10 - CmdCmplt 929 * 11 - EvntOverflow 930 * 12 - VndrDevTstRcved 931 * @reserved15_12: Reserved, not used 932 * @event_info: Information about this event 933 * @reserved31_25: Reserved, not used 934 */ 935struct dwc3_event_devt { 936 u32 one_bit:1; 937 u32 device_event:7; 938 u32 type:4; 939 u32 reserved15_12:4; 940 u32 event_info:9; 941 u32 reserved31_25:7; 942} __packed; 943 944/** 945 * struct dwc3_event_gevt - Other Core Events 946 * @one_bit: indicates this is a non-endpoint event (not used) 947 * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event. 948 * @phy_port_number: self-explanatory 949 * @reserved31_12: Reserved, not used. 950 */ 951struct dwc3_event_gevt { 952 u32 one_bit:1; 953 u32 device_event:7; 954 u32 phy_port_number:4; 955 u32 reserved31_12:20; 956} __packed; 957 958/** 959 * union dwc3_event - representation of Event Buffer contents 960 * @raw: raw 32-bit event 961 * @type: the type of the event 962 * @depevt: Device Endpoint Event 963 * @devt: Device Event 964 * @gevt: Global Event 965 */ 966union dwc3_event { 967 u32 raw; 968 struct dwc3_event_type type; 969 struct dwc3_event_depevt depevt; 970 struct dwc3_event_devt devt; 971 struct dwc3_event_gevt gevt; 972}; 973 974/** 975 * struct dwc3_gadget_ep_cmd_params - representation of endpoint command 976 * parameters 977 * @param2: third parameter 978 * @param1: second parameter 979 * @param0: first parameter 980 */ 981struct dwc3_gadget_ep_cmd_params { 982 u32 param2; 983 u32 param1; 984 u32 param0; 985}; 986 987/* 988 * DWC3 Features to be used as Driver Data 989 */ 990 991#define DWC3_HAS_PERIPHERAL BIT(0) 992#define DWC3_HAS_XHCI BIT(1) 993#define DWC3_HAS_OTG BIT(3) 994 995/* prototypes */ 996void dwc3_set_mode(struct dwc3 *dwc, u32 mode); 997int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc); 998 999#if IS_ENABLED(CONFIG_USB_DWC3_HOST) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) 1000int dwc3_host_init(struct dwc3 *dwc); 1001void dwc3_host_exit(struct dwc3 *dwc); 1002#else 1003static inline int dwc3_host_init(struct dwc3 *dwc) 1004{ return 0; } 1005static inline void dwc3_host_exit(struct dwc3 *dwc) 1006{ } 1007#endif 1008 1009#if IS_ENABLED(CONFIG_USB_DWC3_GADGET) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) 1010int dwc3_gadget_init(struct dwc3 *dwc); 1011void dwc3_gadget_exit(struct dwc3 *dwc); 1012int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode); 1013int dwc3_gadget_get_link_state(struct dwc3 *dwc); 1014int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state); 1015int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep, 1016 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params); 1017int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param); 1018#else 1019static inline int dwc3_gadget_init(struct dwc3 *dwc) 1020{ return 0; } 1021static inline void dwc3_gadget_exit(struct dwc3 *dwc) 1022{ } 1023static inline int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) 1024{ return 0; } 1025static inline int dwc3_gadget_get_link_state(struct dwc3 *dwc) 1026{ return 0; } 1027static inline int dwc3_gadget_set_link_state(struct dwc3 *dwc, 1028 enum dwc3_link_state state) 1029{ return 0; } 1030 1031static inline int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep, 1032 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params) 1033{ return 0; } 1034static inline int dwc3_send_gadget_generic_command(struct dwc3 *dwc, 1035 int cmd, u32 param) 1036{ return 0; } 1037#endif 1038 1039/* power management interface */ 1040#if !IS_ENABLED(CONFIG_USB_DWC3_HOST) 1041int dwc3_gadget_suspend(struct dwc3 *dwc); 1042int dwc3_gadget_resume(struct dwc3 *dwc); 1043#else 1044static inline int dwc3_gadget_suspend(struct dwc3 *dwc) 1045{ 1046 return 0; 1047} 1048 1049static inline int dwc3_gadget_resume(struct dwc3 *dwc) 1050{ 1051 return 0; 1052} 1053#endif /* !IS_ENABLED(CONFIG_USB_DWC3_HOST) */ 1054 1055#endif /* __DRIVERS_USB_DWC3_CORE_H */ 1056