1/* 2 * core.c - ChipIdea USB IP core family device controller 3 * 4 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved. 5 * 6 * Author: David Lopo 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13/* 14 * Description: ChipIdea USB IP core family device controller 15 * 16 * This driver is composed of several blocks: 17 * - HW: hardware interface 18 * - DBG: debug facilities (optional) 19 * - UTIL: utilities 20 * - ISR: interrupts handling 21 * - ENDPT: endpoint operations (Gadget API) 22 * - GADGET: gadget operations (Gadget API) 23 * - BUS: bus glue code, bus abstraction layer 24 * 25 * Compile Options 26 * - CONFIG_USB_CHIPIDEA_DEBUG: enable debug facilities 27 * - STALL_IN: non-empty bulk-in pipes cannot be halted 28 * if defined mass storage compliance succeeds but with warnings 29 * => case 4: Hi > Dn 30 * => case 5: Hi > Di 31 * => case 8: Hi <> Do 32 * if undefined usbtest 13 fails 33 * - TRACE: enable function tracing (depends on DEBUG) 34 * 35 * Main Features 36 * - Chapter 9 & Mass Storage Compliance with Gadget File Storage 37 * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined) 38 * - Normal & LPM support 39 * 40 * USBTEST Report 41 * - OK: 0-12, 13 (STALL_IN defined) & 14 42 * - Not Supported: 15 & 16 (ISO) 43 * 44 * TODO List 45 * - Suspend & Remote Wakeup 46 */ 47#include <linux/delay.h> 48#include <linux/device.h> 49#include <linux/dma-mapping.h> 50#include <linux/phy/phy.h> 51#include <linux/platform_device.h> 52#include <linux/module.h> 53#include <linux/idr.h> 54#include <linux/interrupt.h> 55#include <linux/io.h> 56#include <linux/kernel.h> 57#include <linux/slab.h> 58#include <linux/pm_runtime.h> 59#include <linux/usb/ch9.h> 60#include <linux/usb/gadget.h> 61#include <linux/usb/otg.h> 62#include <linux/usb/chipidea.h> 63#include <linux/usb/of.h> 64#include <linux/of.h> 65#include <linux/phy.h> 66#include <linux/regulator/consumer.h> 67 68#include "ci.h" 69#include "udc.h" 70#include "bits.h" 71#include "host.h" 72#include "debug.h" 73#include "otg.h" 74#include "otg_fsm.h" 75 76/* Controller register map */ 77static const u8 ci_regs_nolpm[] = { 78 [CAP_CAPLENGTH] = 0x00U, 79 [CAP_HCCPARAMS] = 0x08U, 80 [CAP_DCCPARAMS] = 0x24U, 81 [CAP_TESTMODE] = 0x38U, 82 [OP_USBCMD] = 0x00U, 83 [OP_USBSTS] = 0x04U, 84 [OP_USBINTR] = 0x08U, 85 [OP_DEVICEADDR] = 0x14U, 86 [OP_ENDPTLISTADDR] = 0x18U, 87 [OP_PORTSC] = 0x44U, 88 [OP_DEVLC] = 0x84U, 89 [OP_OTGSC] = 0x64U, 90 [OP_USBMODE] = 0x68U, 91 [OP_ENDPTSETUPSTAT] = 0x6CU, 92 [OP_ENDPTPRIME] = 0x70U, 93 [OP_ENDPTFLUSH] = 0x74U, 94 [OP_ENDPTSTAT] = 0x78U, 95 [OP_ENDPTCOMPLETE] = 0x7CU, 96 [OP_ENDPTCTRL] = 0x80U, 97}; 98 99static const u8 ci_regs_lpm[] = { 100 [CAP_CAPLENGTH] = 0x00U, 101 [CAP_HCCPARAMS] = 0x08U, 102 [CAP_DCCPARAMS] = 0x24U, 103 [CAP_TESTMODE] = 0xFCU, 104 [OP_USBCMD] = 0x00U, 105 [OP_USBSTS] = 0x04U, 106 [OP_USBINTR] = 0x08U, 107 [OP_DEVICEADDR] = 0x14U, 108 [OP_ENDPTLISTADDR] = 0x18U, 109 [OP_PORTSC] = 0x44U, 110 [OP_DEVLC] = 0x84U, 111 [OP_OTGSC] = 0xC4U, 112 [OP_USBMODE] = 0xC8U, 113 [OP_ENDPTSETUPSTAT] = 0xD8U, 114 [OP_ENDPTPRIME] = 0xDCU, 115 [OP_ENDPTFLUSH] = 0xE0U, 116 [OP_ENDPTSTAT] = 0xE4U, 117 [OP_ENDPTCOMPLETE] = 0xE8U, 118 [OP_ENDPTCTRL] = 0xECU, 119}; 120 121static int hw_alloc_regmap(struct ci_hdrc *ci, bool is_lpm) 122{ 123 int i; 124 125 for (i = 0; i < OP_ENDPTCTRL; i++) 126 ci->hw_bank.regmap[i] = 127 (i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) + 128 (is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]); 129 130 for (; i <= OP_LAST; i++) 131 ci->hw_bank.regmap[i] = ci->hw_bank.op + 132 4 * (i - OP_ENDPTCTRL) + 133 (is_lpm 134 ? ci_regs_lpm[OP_ENDPTCTRL] 135 : ci_regs_nolpm[OP_ENDPTCTRL]); 136 137 return 0; 138} 139 140static enum ci_revision ci_get_revision(struct ci_hdrc *ci) 141{ 142 int ver = hw_read_id_reg(ci, ID_ID, VERSION) >> __ffs(VERSION); 143 enum ci_revision rev = CI_REVISION_UNKNOWN; 144 145 if (ver == 0x2) { 146 rev = hw_read_id_reg(ci, ID_ID, REVISION) 147 >> __ffs(REVISION); 148 rev += CI_REVISION_20; 149 } else if (ver == 0x0) { 150 rev = CI_REVISION_1X; 151 } 152 153 return rev; 154} 155 156/** 157 * hw_read_intr_enable: returns interrupt enable register 158 * 159 * @ci: the controller 160 * 161 * This function returns register data 162 */ 163u32 hw_read_intr_enable(struct ci_hdrc *ci) 164{ 165 return hw_read(ci, OP_USBINTR, ~0); 166} 167 168/** 169 * hw_read_intr_status: returns interrupt status register 170 * 171 * @ci: the controller 172 * 173 * This function returns register data 174 */ 175u32 hw_read_intr_status(struct ci_hdrc *ci) 176{ 177 return hw_read(ci, OP_USBSTS, ~0); 178} 179 180/** 181 * hw_port_test_set: writes port test mode (execute without interruption) 182 * @mode: new value 183 * 184 * This function returns an error code 185 */ 186int hw_port_test_set(struct ci_hdrc *ci, u8 mode) 187{ 188 const u8 TEST_MODE_MAX = 7; 189 190 if (mode > TEST_MODE_MAX) 191 return -EINVAL; 192 193 hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << __ffs(PORTSC_PTC)); 194 return 0; 195} 196 197/** 198 * hw_port_test_get: reads port test mode value 199 * 200 * @ci: the controller 201 * 202 * This function returns port test mode value 203 */ 204u8 hw_port_test_get(struct ci_hdrc *ci) 205{ 206 return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> __ffs(PORTSC_PTC); 207} 208 209static void hw_wait_phy_stable(void) 210{ 211 /* 212 * The phy needs some delay to output the stable status from low 213 * power mode. And for OTGSC, the status inputs are debounced 214 * using a 1 ms time constant, so, delay 2ms for controller to get 215 * the stable status, like vbus and id when the phy leaves low power. 216 */ 217 usleep_range(2000, 2500); 218} 219 220/* The PHY enters/leaves low power mode */ 221static void ci_hdrc_enter_lpm(struct ci_hdrc *ci, bool enable) 222{ 223 enum ci_hw_regs reg = ci->hw_bank.lpm ? OP_DEVLC : OP_PORTSC; 224 bool lpm = !!(hw_read(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm))); 225 226 if (enable && !lpm) 227 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm), 228 PORTSC_PHCD(ci->hw_bank.lpm)); 229 else if (!enable && lpm) 230 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm), 231 0); 232} 233 234static int hw_device_init(struct ci_hdrc *ci, void __iomem *base) 235{ 236 u32 reg; 237 238 /* bank is a module variable */ 239 ci->hw_bank.abs = base; 240 241 ci->hw_bank.cap = ci->hw_bank.abs; 242 ci->hw_bank.cap += ci->platdata->capoffset; 243 ci->hw_bank.op = ci->hw_bank.cap + (ioread32(ci->hw_bank.cap) & 0xff); 244 245 hw_alloc_regmap(ci, false); 246 reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >> 247 __ffs(HCCPARAMS_LEN); 248 ci->hw_bank.lpm = reg; 249 if (reg) 250 hw_alloc_regmap(ci, !!reg); 251 ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs; 252 ci->hw_bank.size += OP_LAST; 253 ci->hw_bank.size /= sizeof(u32); 254 255 reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >> 256 __ffs(DCCPARAMS_DEN); 257 ci->hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */ 258 259 if (ci->hw_ep_max > ENDPT_MAX) 260 return -ENODEV; 261 262 ci_hdrc_enter_lpm(ci, false); 263 264 /* Disable all interrupts bits */ 265 hw_write(ci, OP_USBINTR, 0xffffffff, 0); 266 267 /* Clear all interrupts status bits*/ 268 hw_write(ci, OP_USBSTS, 0xffffffff, 0xffffffff); 269 270 ci->rev = ci_get_revision(ci); 271 272 dev_dbg(ci->dev, 273 "ChipIdea HDRC found, revision: %d, lpm: %d; cap: %p op: %p\n", 274 ci->rev, ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op); 275 276 /* setup lock mode ? */ 277 278 /* ENDPTSETUPSTAT is '0' by default */ 279 280 /* HCSPARAMS.bf.ppc SHOULD BE zero for device */ 281 282 return 0; 283} 284 285static void hw_phymode_configure(struct ci_hdrc *ci) 286{ 287 u32 portsc, lpm, sts = 0; 288 289 switch (ci->platdata->phy_mode) { 290 case USBPHY_INTERFACE_MODE_UTMI: 291 portsc = PORTSC_PTS(PTS_UTMI); 292 lpm = DEVLC_PTS(PTS_UTMI); 293 break; 294 case USBPHY_INTERFACE_MODE_UTMIW: 295 portsc = PORTSC_PTS(PTS_UTMI) | PORTSC_PTW; 296 lpm = DEVLC_PTS(PTS_UTMI) | DEVLC_PTW; 297 break; 298 case USBPHY_INTERFACE_MODE_ULPI: 299 portsc = PORTSC_PTS(PTS_ULPI); 300 lpm = DEVLC_PTS(PTS_ULPI); 301 break; 302 case USBPHY_INTERFACE_MODE_SERIAL: 303 portsc = PORTSC_PTS(PTS_SERIAL); 304 lpm = DEVLC_PTS(PTS_SERIAL); 305 sts = 1; 306 break; 307 case USBPHY_INTERFACE_MODE_HSIC: 308 portsc = PORTSC_PTS(PTS_HSIC); 309 lpm = DEVLC_PTS(PTS_HSIC); 310 break; 311 default: 312 return; 313 } 314 315 if (ci->hw_bank.lpm) { 316 hw_write(ci, OP_DEVLC, DEVLC_PTS(7) | DEVLC_PTW, lpm); 317 if (sts) 318 hw_write(ci, OP_DEVLC, DEVLC_STS, DEVLC_STS); 319 } else { 320 hw_write(ci, OP_PORTSC, PORTSC_PTS(7) | PORTSC_PTW, portsc); 321 if (sts) 322 hw_write(ci, OP_PORTSC, PORTSC_STS, PORTSC_STS); 323 } 324} 325 326/** 327 * _ci_usb_phy_init: initialize phy taking in account both phy and usb_phy 328 * interfaces 329 * @ci: the controller 330 * 331 * This function returns an error code if the phy failed to init 332 */ 333static int _ci_usb_phy_init(struct ci_hdrc *ci) 334{ 335 int ret; 336 337 if (ci->phy) { 338 ret = phy_init(ci->phy); 339 if (ret) 340 return ret; 341 342 ret = phy_power_on(ci->phy); 343 if (ret) { 344 phy_exit(ci->phy); 345 return ret; 346 } 347 } else { 348 ret = usb_phy_init(ci->usb_phy); 349 } 350 351 return ret; 352} 353 354/** 355 * _ci_usb_phy_exit: deinitialize phy taking in account both phy and usb_phy 356 * interfaces 357 * @ci: the controller 358 */ 359static void ci_usb_phy_exit(struct ci_hdrc *ci) 360{ 361 if (ci->phy) { 362 phy_power_off(ci->phy); 363 phy_exit(ci->phy); 364 } else { 365 usb_phy_shutdown(ci->usb_phy); 366 } 367} 368 369/** 370 * ci_usb_phy_init: initialize phy according to different phy type 371 * @ci: the controller 372 * 373 * This function returns an error code if usb_phy_init has failed 374 */ 375static int ci_usb_phy_init(struct ci_hdrc *ci) 376{ 377 int ret; 378 379 switch (ci->platdata->phy_mode) { 380 case USBPHY_INTERFACE_MODE_UTMI: 381 case USBPHY_INTERFACE_MODE_UTMIW: 382 case USBPHY_INTERFACE_MODE_HSIC: 383 ret = _ci_usb_phy_init(ci); 384 if (!ret) 385 hw_wait_phy_stable(); 386 else 387 return ret; 388 hw_phymode_configure(ci); 389 break; 390 case USBPHY_INTERFACE_MODE_ULPI: 391 case USBPHY_INTERFACE_MODE_SERIAL: 392 hw_phymode_configure(ci); 393 ret = _ci_usb_phy_init(ci); 394 if (ret) 395 return ret; 396 break; 397 default: 398 ret = _ci_usb_phy_init(ci); 399 if (!ret) 400 hw_wait_phy_stable(); 401 } 402 403 return ret; 404} 405 406/** 407 * hw_controller_reset: do controller reset 408 * @ci: the controller 409 * 410 * This function returns an error code 411 */ 412static int hw_controller_reset(struct ci_hdrc *ci) 413{ 414 int count = 0; 415 416 hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST); 417 while (hw_read(ci, OP_USBCMD, USBCMD_RST)) { 418 udelay(10); 419 if (count++ > 1000) 420 return -ETIMEDOUT; 421 } 422 423 return 0; 424} 425 426/** 427 * hw_device_reset: resets chip (execute without interruption) 428 * @ci: the controller 429 * 430 * This function returns an error code 431 */ 432int hw_device_reset(struct ci_hdrc *ci) 433{ 434 int ret; 435 436 /* should flush & stop before reset */ 437 hw_write(ci, OP_ENDPTFLUSH, ~0, ~0); 438 hw_write(ci, OP_USBCMD, USBCMD_RS, 0); 439 440 ret = hw_controller_reset(ci); 441 if (ret) { 442 dev_err(ci->dev, "error resetting controller, ret=%d\n", ret); 443 return ret; 444 } 445 446 if (ci->platdata->notify_event) 447 ci->platdata->notify_event(ci, 448 CI_HDRC_CONTROLLER_RESET_EVENT); 449 450 if (ci->platdata->flags & CI_HDRC_DISABLE_STREAMING) 451 hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, USBMODE_CI_SDIS); 452 453 if (ci->platdata->flags & CI_HDRC_FORCE_FULLSPEED) { 454 if (ci->hw_bank.lpm) 455 hw_write(ci, OP_DEVLC, DEVLC_PFSC, DEVLC_PFSC); 456 else 457 hw_write(ci, OP_PORTSC, PORTSC_PFSC, PORTSC_PFSC); 458 } 459 460 /* USBMODE should be configured step by step */ 461 hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE); 462 hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_DC); 463 /* HW >= 2.3 */ 464 hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM); 465 466 if (hw_read(ci, OP_USBMODE, USBMODE_CM) != USBMODE_CM_DC) { 467 pr_err("cannot enter in %s device mode", ci_role(ci)->name); 468 pr_err("lpm = %i", ci->hw_bank.lpm); 469 return -ENODEV; 470 } 471 472 return 0; 473} 474 475/** 476 * hw_wait_reg: wait the register value 477 * 478 * Sometimes, it needs to wait register value before going on. 479 * Eg, when switch to device mode, the vbus value should be lower 480 * than OTGSC_BSV before connects to host. 481 * 482 * @ci: the controller 483 * @reg: register index 484 * @mask: mast bit 485 * @value: the bit value to wait 486 * @timeout_ms: timeout in millisecond 487 * 488 * This function returns an error code if timeout 489 */ 490int hw_wait_reg(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask, 491 u32 value, unsigned int timeout_ms) 492{ 493 unsigned long elapse = jiffies + msecs_to_jiffies(timeout_ms); 494 495 while (hw_read(ci, reg, mask) != value) { 496 if (time_after(jiffies, elapse)) { 497 dev_err(ci->dev, "timeout waiting for %08x in %d\n", 498 mask, reg); 499 return -ETIMEDOUT; 500 } 501 msleep(20); 502 } 503 504 return 0; 505} 506 507static irqreturn_t ci_irq(int irq, void *data) 508{ 509 struct ci_hdrc *ci = data; 510 irqreturn_t ret = IRQ_NONE; 511 u32 otgsc = 0; 512 513 if (ci->in_lpm) { 514 disable_irq_nosync(irq); 515 ci->wakeup_int = true; 516 pm_runtime_get(ci->dev); 517 return IRQ_HANDLED; 518 } 519 520 if (ci->is_otg) { 521 otgsc = hw_read_otgsc(ci, ~0); 522 if (ci_otg_is_fsm_mode(ci)) { 523 ret = ci_otg_fsm_irq(ci); 524 if (ret == IRQ_HANDLED) 525 return ret; 526 } 527 } 528 529 /* 530 * Handle id change interrupt, it indicates device/host function 531 * switch. 532 */ 533 if (ci->is_otg && (otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS)) { 534 ci->id_event = true; 535 /* Clear ID change irq status */ 536 hw_write_otgsc(ci, OTGSC_IDIS, OTGSC_IDIS); 537 ci_otg_queue_work(ci); 538 return IRQ_HANDLED; 539 } 540 541 /* 542 * Handle vbus change interrupt, it indicates device connection 543 * and disconnection events. 544 */ 545 if (ci->is_otg && (otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS)) { 546 ci->b_sess_valid_event = true; 547 /* Clear BSV irq */ 548 hw_write_otgsc(ci, OTGSC_BSVIS, OTGSC_BSVIS); 549 ci_otg_queue_work(ci); 550 return IRQ_HANDLED; 551 } 552 553 /* Handle device/host interrupt */ 554 if (ci->role != CI_ROLE_END) 555 ret = ci_role(ci)->irq(ci); 556 557 return ret; 558} 559 560static int ci_get_platdata(struct device *dev, 561 struct ci_hdrc_platform_data *platdata) 562{ 563 if (!platdata->phy_mode) 564 platdata->phy_mode = of_usb_get_phy_mode(dev->of_node); 565 566 if (!platdata->dr_mode) 567 platdata->dr_mode = of_usb_get_dr_mode(dev->of_node); 568 569 if (platdata->dr_mode == USB_DR_MODE_UNKNOWN) 570 platdata->dr_mode = USB_DR_MODE_OTG; 571 572 if (platdata->dr_mode != USB_DR_MODE_PERIPHERAL) { 573 /* Get the vbus regulator */ 574 platdata->reg_vbus = devm_regulator_get(dev, "vbus"); 575 if (PTR_ERR(platdata->reg_vbus) == -EPROBE_DEFER) { 576 return -EPROBE_DEFER; 577 } else if (PTR_ERR(platdata->reg_vbus) == -ENODEV) { 578 /* no vbus regulator is needed */ 579 platdata->reg_vbus = NULL; 580 } else if (IS_ERR(platdata->reg_vbus)) { 581 dev_err(dev, "Getting regulator error: %ld\n", 582 PTR_ERR(platdata->reg_vbus)); 583 return PTR_ERR(platdata->reg_vbus); 584 } 585 /* Get TPL support */ 586 if (!platdata->tpl_support) 587 platdata->tpl_support = 588 of_usb_host_tpl_support(dev->of_node); 589 } 590 591 if (of_usb_get_maximum_speed(dev->of_node) == USB_SPEED_FULL) 592 platdata->flags |= CI_HDRC_FORCE_FULLSPEED; 593 594 return 0; 595} 596 597static DEFINE_IDA(ci_ida); 598 599struct platform_device *ci_hdrc_add_device(struct device *dev, 600 struct resource *res, int nres, 601 struct ci_hdrc_platform_data *platdata) 602{ 603 struct platform_device *pdev; 604 int id, ret; 605 606 ret = ci_get_platdata(dev, platdata); 607 if (ret) 608 return ERR_PTR(ret); 609 610 id = ida_simple_get(&ci_ida, 0, 0, GFP_KERNEL); 611 if (id < 0) 612 return ERR_PTR(id); 613 614 pdev = platform_device_alloc("ci_hdrc", id); 615 if (!pdev) { 616 ret = -ENOMEM; 617 goto put_id; 618 } 619 620 pdev->dev.parent = dev; 621 pdev->dev.dma_mask = dev->dma_mask; 622 pdev->dev.dma_parms = dev->dma_parms; 623 dma_set_coherent_mask(&pdev->dev, dev->coherent_dma_mask); 624 625 ret = platform_device_add_resources(pdev, res, nres); 626 if (ret) 627 goto err; 628 629 ret = platform_device_add_data(pdev, platdata, sizeof(*platdata)); 630 if (ret) 631 goto err; 632 633 ret = platform_device_add(pdev); 634 if (ret) 635 goto err; 636 637 return pdev; 638 639err: 640 platform_device_put(pdev); 641put_id: 642 ida_simple_remove(&ci_ida, id); 643 return ERR_PTR(ret); 644} 645EXPORT_SYMBOL_GPL(ci_hdrc_add_device); 646 647void ci_hdrc_remove_device(struct platform_device *pdev) 648{ 649 int id = pdev->id; 650 platform_device_unregister(pdev); 651 ida_simple_remove(&ci_ida, id); 652} 653EXPORT_SYMBOL_GPL(ci_hdrc_remove_device); 654 655static inline void ci_role_destroy(struct ci_hdrc *ci) 656{ 657 ci_hdrc_gadget_destroy(ci); 658 ci_hdrc_host_destroy(ci); 659 if (ci->is_otg) 660 ci_hdrc_otg_destroy(ci); 661} 662 663static void ci_get_otg_capable(struct ci_hdrc *ci) 664{ 665 if (ci->platdata->flags & CI_HDRC_DUAL_ROLE_NOT_OTG) 666 ci->is_otg = false; 667 else 668 ci->is_otg = (hw_read(ci, CAP_DCCPARAMS, 669 DCCPARAMS_DC | DCCPARAMS_HC) 670 == (DCCPARAMS_DC | DCCPARAMS_HC)); 671 if (ci->is_otg) { 672 dev_dbg(ci->dev, "It is OTG capable controller\n"); 673 /* Disable and clear all OTG irq */ 674 hw_write_otgsc(ci, OTGSC_INT_EN_BITS | OTGSC_INT_STATUS_BITS, 675 OTGSC_INT_STATUS_BITS); 676 } 677} 678 679static int ci_hdrc_probe(struct platform_device *pdev) 680{ 681 struct device *dev = &pdev->dev; 682 struct ci_hdrc *ci; 683 struct resource *res; 684 void __iomem *base; 685 int ret; 686 enum usb_dr_mode dr_mode; 687 688 if (!dev_get_platdata(dev)) { 689 dev_err(dev, "platform data missing\n"); 690 return -ENODEV; 691 } 692 693 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 694 base = devm_ioremap_resource(dev, res); 695 if (IS_ERR(base)) 696 return PTR_ERR(base); 697 698 ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL); 699 if (!ci) 700 return -ENOMEM; 701 702 ci->dev = dev; 703 ci->platdata = dev_get_platdata(dev); 704 ci->imx28_write_fix = !!(ci->platdata->flags & 705 CI_HDRC_IMX28_WRITE_FIX); 706 ci->supports_runtime_pm = !!(ci->platdata->flags & 707 CI_HDRC_SUPPORTS_RUNTIME_PM); 708 709 ret = hw_device_init(ci, base); 710 if (ret < 0) { 711 dev_err(dev, "can't initialize hardware\n"); 712 return -ENODEV; 713 } 714 715 if (ci->platdata->phy) { 716 ci->phy = ci->platdata->phy; 717 } else if (ci->platdata->usb_phy) { 718 ci->usb_phy = ci->platdata->usb_phy; 719 } else { 720 ci->phy = devm_phy_get(dev->parent, "usb-phy"); 721 ci->usb_phy = devm_usb_get_phy(dev->parent, USB_PHY_TYPE_USB2); 722 723 /* if both generic PHY and USB PHY layers aren't enabled */ 724 if (PTR_ERR(ci->phy) == -ENOSYS && 725 PTR_ERR(ci->usb_phy) == -ENXIO) 726 return -ENXIO; 727 728 if (IS_ERR(ci->phy) && IS_ERR(ci->usb_phy)) 729 return -EPROBE_DEFER; 730 731 if (IS_ERR(ci->phy)) 732 ci->phy = NULL; 733 else if (IS_ERR(ci->usb_phy)) 734 ci->usb_phy = NULL; 735 } 736 737 ret = ci_usb_phy_init(ci); 738 if (ret) { 739 dev_err(dev, "unable to init phy: %d\n", ret); 740 return ret; 741 } 742 743 ci->hw_bank.phys = res->start; 744 745 ci->irq = platform_get_irq(pdev, 0); 746 if (ci->irq < 0) { 747 dev_err(dev, "missing IRQ\n"); 748 ret = ci->irq; 749 goto deinit_phy; 750 } 751 752 ci_get_otg_capable(ci); 753 754 dr_mode = ci->platdata->dr_mode; 755 /* initialize role(s) before the interrupt is requested */ 756 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) { 757 ret = ci_hdrc_host_init(ci); 758 if (ret) 759 dev_info(dev, "doesn't support host\n"); 760 } 761 762 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_PERIPHERAL) { 763 ret = ci_hdrc_gadget_init(ci); 764 if (ret) 765 dev_info(dev, "doesn't support gadget\n"); 766 } 767 768 if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) { 769 dev_err(dev, "no supported roles\n"); 770 ret = -ENODEV; 771 goto deinit_phy; 772 } 773 774 if (ci->is_otg && ci->roles[CI_ROLE_GADGET]) { 775 ret = ci_hdrc_otg_init(ci); 776 if (ret) { 777 dev_err(dev, "init otg fails, ret = %d\n", ret); 778 goto stop; 779 } 780 } 781 782 if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) { 783 if (ci->is_otg) { 784 ci->role = ci_otg_role(ci); 785 /* Enable ID change irq */ 786 hw_write_otgsc(ci, OTGSC_IDIE, OTGSC_IDIE); 787 } else { 788 /* 789 * If the controller is not OTG capable, but support 790 * role switch, the defalt role is gadget, and the 791 * user can switch it through debugfs. 792 */ 793 ci->role = CI_ROLE_GADGET; 794 } 795 } else { 796 ci->role = ci->roles[CI_ROLE_HOST] 797 ? CI_ROLE_HOST 798 : CI_ROLE_GADGET; 799 } 800 801 if (!ci_otg_is_fsm_mode(ci)) { 802 /* only update vbus status for peripheral */ 803 if (ci->role == CI_ROLE_GADGET) 804 ci_handle_vbus_change(ci); 805 806 ret = ci_role_start(ci, ci->role); 807 if (ret) { 808 dev_err(dev, "can't start %s role\n", 809 ci_role(ci)->name); 810 goto stop; 811 } 812 } 813 814 platform_set_drvdata(pdev, ci); 815 ret = devm_request_irq(dev, ci->irq, ci_irq, IRQF_SHARED, 816 ci->platdata->name, ci); 817 if (ret) 818 goto stop; 819 820 if (ci->supports_runtime_pm) { 821 pm_runtime_set_active(&pdev->dev); 822 pm_runtime_enable(&pdev->dev); 823 pm_runtime_set_autosuspend_delay(&pdev->dev, 2000); 824 pm_runtime_mark_last_busy(ci->dev); 825 pm_runtime_use_autosuspend(&pdev->dev); 826 } 827 828 if (ci_otg_is_fsm_mode(ci)) 829 ci_hdrc_otg_fsm_start(ci); 830 831 device_set_wakeup_capable(&pdev->dev, true); 832 833 ret = dbg_create_files(ci); 834 if (!ret) 835 return 0; 836 837stop: 838 ci_role_destroy(ci); 839deinit_phy: 840 ci_usb_phy_exit(ci); 841 842 return ret; 843} 844 845static int ci_hdrc_remove(struct platform_device *pdev) 846{ 847 struct ci_hdrc *ci = platform_get_drvdata(pdev); 848 849 if (ci->supports_runtime_pm) { 850 pm_runtime_get_sync(&pdev->dev); 851 pm_runtime_disable(&pdev->dev); 852 pm_runtime_put_noidle(&pdev->dev); 853 } 854 855 dbg_remove_files(ci); 856 ci_role_destroy(ci); 857 ci_hdrc_enter_lpm(ci, true); 858 ci_usb_phy_exit(ci); 859 860 return 0; 861} 862 863#ifdef CONFIG_PM 864/* Prepare wakeup by SRP before suspend */ 865static void ci_otg_fsm_suspend_for_srp(struct ci_hdrc *ci) 866{ 867 if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) && 868 !hw_read_otgsc(ci, OTGSC_ID)) { 869 hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_PP, 870 PORTSC_PP); 871 hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_WKCN, 872 PORTSC_WKCN); 873 } 874} 875 876/* Handle SRP when wakeup by data pulse */ 877static void ci_otg_fsm_wakeup_by_srp(struct ci_hdrc *ci) 878{ 879 if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) && 880 (ci->fsm.a_bus_drop == 1) && (ci->fsm.a_bus_req == 0)) { 881 if (!hw_read_otgsc(ci, OTGSC_ID)) { 882 ci->fsm.a_srp_det = 1; 883 ci->fsm.a_bus_drop = 0; 884 } else { 885 ci->fsm.id = 1; 886 } 887 ci_otg_queue_work(ci); 888 } 889} 890 891static void ci_controller_suspend(struct ci_hdrc *ci) 892{ 893 disable_irq(ci->irq); 894 ci_hdrc_enter_lpm(ci, true); 895 usb_phy_set_suspend(ci->usb_phy, 1); 896 ci->in_lpm = true; 897 enable_irq(ci->irq); 898} 899 900static int ci_controller_resume(struct device *dev) 901{ 902 struct ci_hdrc *ci = dev_get_drvdata(dev); 903 904 dev_dbg(dev, "at %s\n", __func__); 905 906 if (!ci->in_lpm) { 907 WARN_ON(1); 908 return 0; 909 } 910 911 ci_hdrc_enter_lpm(ci, false); 912 if (ci->usb_phy) { 913 usb_phy_set_suspend(ci->usb_phy, 0); 914 usb_phy_set_wakeup(ci->usb_phy, false); 915 hw_wait_phy_stable(); 916 } 917 918 ci->in_lpm = false; 919 if (ci->wakeup_int) { 920 ci->wakeup_int = false; 921 pm_runtime_mark_last_busy(ci->dev); 922 pm_runtime_put_autosuspend(ci->dev); 923 enable_irq(ci->irq); 924 if (ci_otg_is_fsm_mode(ci)) 925 ci_otg_fsm_wakeup_by_srp(ci); 926 } 927 928 return 0; 929} 930 931#ifdef CONFIG_PM_SLEEP 932static int ci_suspend(struct device *dev) 933{ 934 struct ci_hdrc *ci = dev_get_drvdata(dev); 935 936 if (ci->wq) 937 flush_workqueue(ci->wq); 938 /* 939 * Controller needs to be active during suspend, otherwise the core 940 * may run resume when the parent is at suspend if other driver's 941 * suspend fails, it occurs before parent's suspend has not started, 942 * but the core suspend has finished. 943 */ 944 if (ci->in_lpm) 945 pm_runtime_resume(dev); 946 947 if (ci->in_lpm) { 948 WARN_ON(1); 949 return 0; 950 } 951 952 if (device_may_wakeup(dev)) { 953 if (ci_otg_is_fsm_mode(ci)) 954 ci_otg_fsm_suspend_for_srp(ci); 955 956 usb_phy_set_wakeup(ci->usb_phy, true); 957 enable_irq_wake(ci->irq); 958 } 959 960 ci_controller_suspend(ci); 961 962 return 0; 963} 964 965static int ci_resume(struct device *dev) 966{ 967 struct ci_hdrc *ci = dev_get_drvdata(dev); 968 int ret; 969 970 if (device_may_wakeup(dev)) 971 disable_irq_wake(ci->irq); 972 973 ret = ci_controller_resume(dev); 974 if (ret) 975 return ret; 976 977 if (ci->supports_runtime_pm) { 978 pm_runtime_disable(dev); 979 pm_runtime_set_active(dev); 980 pm_runtime_enable(dev); 981 } 982 983 return ret; 984} 985#endif /* CONFIG_PM_SLEEP */ 986 987static int ci_runtime_suspend(struct device *dev) 988{ 989 struct ci_hdrc *ci = dev_get_drvdata(dev); 990 991 dev_dbg(dev, "at %s\n", __func__); 992 993 if (ci->in_lpm) { 994 WARN_ON(1); 995 return 0; 996 } 997 998 if (ci_otg_is_fsm_mode(ci)) 999 ci_otg_fsm_suspend_for_srp(ci); 1000 1001 usb_phy_set_wakeup(ci->usb_phy, true); 1002 ci_controller_suspend(ci); 1003 1004 return 0; 1005} 1006 1007static int ci_runtime_resume(struct device *dev) 1008{ 1009 return ci_controller_resume(dev); 1010} 1011 1012#endif /* CONFIG_PM */ 1013static const struct dev_pm_ops ci_pm_ops = { 1014 SET_SYSTEM_SLEEP_PM_OPS(ci_suspend, ci_resume) 1015 SET_RUNTIME_PM_OPS(ci_runtime_suspend, ci_runtime_resume, NULL) 1016}; 1017 1018static struct platform_driver ci_hdrc_driver = { 1019 .probe = ci_hdrc_probe, 1020 .remove = ci_hdrc_remove, 1021 .driver = { 1022 .name = "ci_hdrc", 1023 .pm = &ci_pm_ops, 1024 }, 1025}; 1026 1027static int __init ci_hdrc_platform_register(void) 1028{ 1029 ci_hdrc_host_driver_init(); 1030 return platform_driver_register(&ci_hdrc_driver); 1031} 1032module_init(ci_hdrc_platform_register); 1033 1034static void __exit ci_hdrc_platform_unregister(void) 1035{ 1036 platform_driver_unregister(&ci_hdrc_driver); 1037} 1038module_exit(ci_hdrc_platform_unregister); 1039 1040MODULE_ALIAS("platform:ci_hdrc"); 1041MODULE_LICENSE("GPL v2"); 1042MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>"); 1043MODULE_DESCRIPTION("ChipIdea HDRC Driver"); 1044