1#ifndef DDK750_REG_H__
2#define DDK750_REG_H__
3
4/* New register for SM750LE */
5#define DE_STATE1                                        0x100054
6#define DE_STATE1_DE_ABORT                               0:0
7#define DE_STATE1_DE_ABORT_OFF                           0
8#define DE_STATE1_DE_ABORT_ON                            1
9
10#define DE_STATE2                                        0x100058
11#define DE_STATE2_DE_FIFO                                3:3
12#define DE_STATE2_DE_FIFO_NOTEMPTY                       0
13#define DE_STATE2_DE_FIFO_EMPTY                          1
14#define DE_STATE2_DE_STATUS                              2:2
15#define DE_STATE2_DE_STATUS_IDLE                         0
16#define DE_STATE2_DE_STATUS_BUSY                         1
17#define DE_STATE2_DE_MEM_FIFO                            1:1
18#define DE_STATE2_DE_MEM_FIFO_NOTEMPTY                   0
19#define DE_STATE2_DE_MEM_FIFO_EMPTY                      1
20#define DE_STATE2_DE_RESERVED                            0:0
21
22
23
24#define SYSTEM_CTRL                                   0x000000
25#define SYSTEM_CTRL_DPMS                              31:30
26#define SYSTEM_CTRL_DPMS_VPHP                         0
27#define SYSTEM_CTRL_DPMS_VPHN                         1
28#define SYSTEM_CTRL_DPMS_VNHP                         2
29#define SYSTEM_CTRL_DPMS_VNHN                         3
30#define SYSTEM_CTRL_PCI_BURST                         29:29
31#define SYSTEM_CTRL_PCI_BURST_OFF                     0
32#define SYSTEM_CTRL_PCI_BURST_ON                      1
33#define SYSTEM_CTRL_PCI_MASTER                        25:25
34#define SYSTEM_CTRL_PCI_MASTER_OFF                    0
35#define SYSTEM_CTRL_PCI_MASTER_ON                     1
36#define SYSTEM_CTRL_LATENCY_TIMER                     24:24
37#define SYSTEM_CTRL_LATENCY_TIMER_ON                  0
38#define SYSTEM_CTRL_LATENCY_TIMER_OFF                 1
39#define SYSTEM_CTRL_DE_FIFO                           23:23
40#define SYSTEM_CTRL_DE_FIFO_NOTEMPTY                  0
41#define SYSTEM_CTRL_DE_FIFO_EMPTY                     1
42#define SYSTEM_CTRL_DE_STATUS                         22:22
43#define SYSTEM_CTRL_DE_STATUS_IDLE                    0
44#define SYSTEM_CTRL_DE_STATUS_BUSY                    1
45#define SYSTEM_CTRL_DE_MEM_FIFO                       21:21
46#define SYSTEM_CTRL_DE_MEM_FIFO_NOTEMPTY              0
47#define SYSTEM_CTRL_DE_MEM_FIFO_EMPTY                 1
48#define SYSTEM_CTRL_CSC_STATUS                        20:20
49#define SYSTEM_CTRL_CSC_STATUS_IDLE                   0
50#define SYSTEM_CTRL_CSC_STATUS_BUSY                   1
51#define SYSTEM_CTRL_CRT_VSYNC                         19:19
52#define SYSTEM_CTRL_CRT_VSYNC_INACTIVE                0
53#define SYSTEM_CTRL_CRT_VSYNC_ACTIVE                  1
54#define SYSTEM_CTRL_PANEL_VSYNC                       18:18
55#define SYSTEM_CTRL_PANEL_VSYNC_INACTIVE              0
56#define SYSTEM_CTRL_PANEL_VSYNC_ACTIVE                1
57#define SYSTEM_CTRL_CURRENT_BUFFER                    17:17
58#define SYSTEM_CTRL_CURRENT_BUFFER_NORMAL             0
59#define SYSTEM_CTRL_CURRENT_BUFFER_FLIP_PENDING       1
60#define SYSTEM_CTRL_DMA_STATUS                        16:16
61#define SYSTEM_CTRL_DMA_STATUS_IDLE                   0
62#define SYSTEM_CTRL_DMA_STATUS_BUSY                   1
63#define SYSTEM_CTRL_PCI_BURST_READ                    15:15
64#define SYSTEM_CTRL_PCI_BURST_READ_OFF                0
65#define SYSTEM_CTRL_PCI_BURST_READ_ON                 1
66#define SYSTEM_CTRL_DE_ABORT                          13:13
67#define SYSTEM_CTRL_DE_ABORT_OFF                      0
68#define SYSTEM_CTRL_DE_ABORT_ON                       1
69#define SYSTEM_CTRL_PCI_SUBSYS_ID_LOCK                11:11
70#define SYSTEM_CTRL_PCI_SUBSYS_ID_LOCK_OFF            0
71#define SYSTEM_CTRL_PCI_SUBSYS_ID_LOCK_ON             1
72#define SYSTEM_CTRL_PCI_RETRY                         7:7
73#define SYSTEM_CTRL_PCI_RETRY_ON                      0
74#define SYSTEM_CTRL_PCI_RETRY_OFF                     1
75#define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE         5:4
76#define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_1       0
77#define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_2       1
78#define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_4       2
79#define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_8       3
80#define SYSTEM_CTRL_CRT_TRISTATE                      3:3
81#define SYSTEM_CTRL_CRT_TRISTATE_OFF                  0
82#define SYSTEM_CTRL_CRT_TRISTATE_ON                   1
83#define SYSTEM_CTRL_PCIMEM_TRISTATE                   2:2
84#define SYSTEM_CTRL_PCIMEM_TRISTATE_OFF               0
85#define SYSTEM_CTRL_PCIMEM_TRISTATE_ON                1
86#define SYSTEM_CTRL_LOCALMEM_TRISTATE                 1:1
87#define SYSTEM_CTRL_LOCALMEM_TRISTATE_OFF             0
88#define SYSTEM_CTRL_LOCALMEM_TRISTATE_ON              1
89#define SYSTEM_CTRL_PANEL_TRISTATE                    0:0
90#define SYSTEM_CTRL_PANEL_TRISTATE_OFF                0
91#define SYSTEM_CTRL_PANEL_TRISTATE_ON                 1
92
93#define MISC_CTRL                                     0x000004
94#define MISC_CTRL_DRAM_RERESH_COUNT                   27:27
95#define MISC_CTRL_DRAM_RERESH_COUNT_1ROW              0
96#define MISC_CTRL_DRAM_RERESH_COUNT_3ROW              1
97#define MISC_CTRL_DRAM_REFRESH_TIME                   26:25
98#define MISC_CTRL_DRAM_REFRESH_TIME_8                 0
99#define MISC_CTRL_DRAM_REFRESH_TIME_16                1
100#define MISC_CTRL_DRAM_REFRESH_TIME_32                2
101#define MISC_CTRL_DRAM_REFRESH_TIME_64                3
102#define MISC_CTRL_INT_OUTPUT                          24:24
103#define MISC_CTRL_INT_OUTPUT_NORMAL                   0
104#define MISC_CTRL_INT_OUTPUT_INVERT                   1
105#define MISC_CTRL_PLL_CLK_COUNT                       23:23
106#define MISC_CTRL_PLL_CLK_COUNT_OFF                   0
107#define MISC_CTRL_PLL_CLK_COUNT_ON                    1
108#define MISC_CTRL_DAC_POWER                           20:20
109#define MISC_CTRL_DAC_POWER_ON                        0
110#define MISC_CTRL_DAC_POWER_OFF                       1
111#define MISC_CTRL_CLK_SELECT                          16:16
112#define MISC_CTRL_CLK_SELECT_OSC                      0
113#define MISC_CTRL_CLK_SELECT_TESTCLK                  1
114#define MISC_CTRL_DRAM_COLUMN_SIZE                    15:14
115#define MISC_CTRL_DRAM_COLUMN_SIZE_256                0
116#define MISC_CTRL_DRAM_COLUMN_SIZE_512                1
117#define MISC_CTRL_DRAM_COLUMN_SIZE_1024               2
118#define MISC_CTRL_LOCALMEM_SIZE                       13:12
119#define MISC_CTRL_LOCALMEM_SIZE_8M                    3
120#define MISC_CTRL_LOCALMEM_SIZE_16M                   0
121#define MISC_CTRL_LOCALMEM_SIZE_32M                   1
122#define MISC_CTRL_LOCALMEM_SIZE_64M                   2
123#define MISC_CTRL_DRAM_TWTR                           11:11
124#define MISC_CTRL_DRAM_TWTR_2CLK                      0
125#define MISC_CTRL_DRAM_TWTR_1CLK                      1
126#define MISC_CTRL_DRAM_TWR                            10:10
127#define MISC_CTRL_DRAM_TWR_3CLK                       0
128#define MISC_CTRL_DRAM_TWR_2CLK                       1
129#define MISC_CTRL_DRAM_TRP                            9:9
130#define MISC_CTRL_DRAM_TRP_3CLK                       0
131#define MISC_CTRL_DRAM_TRP_4CLK                       1
132#define MISC_CTRL_DRAM_TRFC                           8:8
133#define MISC_CTRL_DRAM_TRFC_12CLK                     0
134#define MISC_CTRL_DRAM_TRFC_14CLK                     1
135#define MISC_CTRL_DRAM_TRAS                           7:7
136#define MISC_CTRL_DRAM_TRAS_7CLK                      0
137#define MISC_CTRL_DRAM_TRAS_8CLK                      1
138#define MISC_CTRL_LOCALMEM_RESET                      6:6
139#define MISC_CTRL_LOCALMEM_RESET_RESET                0
140#define MISC_CTRL_LOCALMEM_RESET_NORMAL               1
141#define MISC_CTRL_LOCALMEM_STATE                      5:5
142#define MISC_CTRL_LOCALMEM_STATE_ACTIVE               0
143#define MISC_CTRL_LOCALMEM_STATE_INACTIVE             1
144#define MISC_CTRL_CPU_CAS_LATENCY                     4:4
145#define MISC_CTRL_CPU_CAS_LATENCY_2CLK                0
146#define MISC_CTRL_CPU_CAS_LATENCY_3CLK                1
147#define MISC_CTRL_DLL                                 3:3
148#define MISC_CTRL_DLL_ON                              0
149#define MISC_CTRL_DLL_OFF                             1
150#define MISC_CTRL_DRAM_OUTPUT                         2:2
151#define MISC_CTRL_DRAM_OUTPUT_LOW                     0
152#define MISC_CTRL_DRAM_OUTPUT_HIGH                    1
153#define MISC_CTRL_LOCALMEM_BUS_SIZE                   1:1
154#define MISC_CTRL_LOCALMEM_BUS_SIZE_32                0
155#define MISC_CTRL_LOCALMEM_BUS_SIZE_64                1
156#define MISC_CTRL_EMBEDDED_LOCALMEM                   0:0
157#define MISC_CTRL_EMBEDDED_LOCALMEM_ON                0
158#define MISC_CTRL_EMBEDDED_LOCALMEM_OFF               1
159
160#define GPIO_MUX                                      0x000008
161#define GPIO_MUX_31                                   31:31
162#define GPIO_MUX_31_GPIO                              0
163#define GPIO_MUX_31_I2C                               1
164#define GPIO_MUX_30                                   30:30
165#define GPIO_MUX_30_GPIO                              0
166#define GPIO_MUX_30_I2C                               1
167#define GPIO_MUX_29                                   29:29
168#define GPIO_MUX_29_GPIO                              0
169#define GPIO_MUX_29_SSP1                              1
170#define GPIO_MUX_28                                   28:28
171#define GPIO_MUX_28_GPIO                              0
172#define GPIO_MUX_28_SSP1                              1
173#define GPIO_MUX_27                                   27:27
174#define GPIO_MUX_27_GPIO                              0
175#define GPIO_MUX_27_SSP1                              1
176#define GPIO_MUX_26                                   26:26
177#define GPIO_MUX_26_GPIO                              0
178#define GPIO_MUX_26_SSP1                              1
179#define GPIO_MUX_25                                   25:25
180#define GPIO_MUX_25_GPIO                              0
181#define GPIO_MUX_25_SSP1                              1
182#define GPIO_MUX_24                                   24:24
183#define GPIO_MUX_24_GPIO                              0
184#define GPIO_MUX_24_SSP0                              1
185#define GPIO_MUX_23                                   23:23
186#define GPIO_MUX_23_GPIO                              0
187#define GPIO_MUX_23_SSP0                              1
188#define GPIO_MUX_22                                   22:22
189#define GPIO_MUX_22_GPIO                              0
190#define GPIO_MUX_22_SSP0                              1
191#define GPIO_MUX_21                                   21:21
192#define GPIO_MUX_21_GPIO                              0
193#define GPIO_MUX_21_SSP0                              1
194#define GPIO_MUX_20                                   20:20
195#define GPIO_MUX_20_GPIO                              0
196#define GPIO_MUX_20_SSP0                              1
197#define GPIO_MUX_19                                   19:19
198#define GPIO_MUX_19_GPIO                              0
199#define GPIO_MUX_19_PWM                               1
200#define GPIO_MUX_18                                   18:18
201#define GPIO_MUX_18_GPIO                              0
202#define GPIO_MUX_18_PWM                               1
203#define GPIO_MUX_17                                   17:17
204#define GPIO_MUX_17_GPIO                              0
205#define GPIO_MUX_17_PWM                               1
206#define GPIO_MUX_16                                   16:16
207#define GPIO_MUX_16_GPIO_ZVPORT                       0
208#define GPIO_MUX_16_TEST_DATA                         1
209#define GPIO_MUX_15                                   15:15
210#define GPIO_MUX_15_GPIO_ZVPORT                       0
211#define GPIO_MUX_15_TEST_DATA                         1
212#define GPIO_MUX_14                                   14:14
213#define GPIO_MUX_14_GPIO_ZVPORT                       0
214#define GPIO_MUX_14_TEST_DATA                         1
215#define GPIO_MUX_13                                   13:13
216#define GPIO_MUX_13_GPIO_ZVPORT                       0
217#define GPIO_MUX_13_TEST_DATA                         1
218#define GPIO_MUX_12                                   12:12
219#define GPIO_MUX_12_GPIO_ZVPORT                       0
220#define GPIO_MUX_12_TEST_DATA                         1
221#define GPIO_MUX_11                                   11:11
222#define GPIO_MUX_11_GPIO_ZVPORT                       0
223#define GPIO_MUX_11_TEST_DATA                         1
224#define GPIO_MUX_10                                   10:10
225#define GPIO_MUX_10_GPIO_ZVPORT                       0
226#define GPIO_MUX_10_TEST_DATA                         1
227#define GPIO_MUX_9                                    9:9
228#define GPIO_MUX_9_GPIO_ZVPORT                        0
229#define GPIO_MUX_9_TEST_DATA                          1
230#define GPIO_MUX_8                                    8:8
231#define GPIO_MUX_8_GPIO_ZVPORT                        0
232#define GPIO_MUX_8_TEST_DATA                          1
233#define GPIO_MUX_7                                    7:7
234#define GPIO_MUX_7_GPIO_ZVPORT                        0
235#define GPIO_MUX_7_TEST_DATA                          1
236#define GPIO_MUX_6                                    6:6
237#define GPIO_MUX_6_GPIO_ZVPORT                        0
238#define GPIO_MUX_6_TEST_DATA                          1
239#define GPIO_MUX_5                                    5:5
240#define GPIO_MUX_5_GPIO_ZVPORT                        0
241#define GPIO_MUX_5_TEST_DATA                          1
242#define GPIO_MUX_4                                    4:4
243#define GPIO_MUX_4_GPIO_ZVPORT                        0
244#define GPIO_MUX_4_TEST_DATA                          1
245#define GPIO_MUX_3                                    3:3
246#define GPIO_MUX_3_GPIO_ZVPORT                        0
247#define GPIO_MUX_3_TEST_DATA                          1
248#define GPIO_MUX_2                                    2:2
249#define GPIO_MUX_2_GPIO_ZVPORT                        0
250#define GPIO_MUX_2_TEST_DATA                          1
251#define GPIO_MUX_1                                    1:1
252#define GPIO_MUX_1_GPIO_ZVPORT                        0
253#define GPIO_MUX_1_TEST_DATA                          1
254#define GPIO_MUX_0                                    0:0
255#define GPIO_MUX_0_GPIO_ZVPORT                        0
256#define GPIO_MUX_0_TEST_DATA                          1
257
258#define LOCALMEM_ARBITRATION                          0x00000C
259#define LOCALMEM_ARBITRATION_ROTATE                   28:28
260#define LOCALMEM_ARBITRATION_ROTATE_OFF               0
261#define LOCALMEM_ARBITRATION_ROTATE_ON                1
262#define LOCALMEM_ARBITRATION_VGA                      26:24
263#define LOCALMEM_ARBITRATION_VGA_OFF                  0
264#define LOCALMEM_ARBITRATION_VGA_PRIORITY_1           1
265#define LOCALMEM_ARBITRATION_VGA_PRIORITY_2           2
266#define LOCALMEM_ARBITRATION_VGA_PRIORITY_3           3
267#define LOCALMEM_ARBITRATION_VGA_PRIORITY_4           4
268#define LOCALMEM_ARBITRATION_VGA_PRIORITY_5           5
269#define LOCALMEM_ARBITRATION_VGA_PRIORITY_6           6
270#define LOCALMEM_ARBITRATION_VGA_PRIORITY_7           7
271#define LOCALMEM_ARBITRATION_DMA                      22:20
272#define LOCALMEM_ARBITRATION_DMA_OFF                  0
273#define LOCALMEM_ARBITRATION_DMA_PRIORITY_1           1
274#define LOCALMEM_ARBITRATION_DMA_PRIORITY_2           2
275#define LOCALMEM_ARBITRATION_DMA_PRIORITY_3           3
276#define LOCALMEM_ARBITRATION_DMA_PRIORITY_4           4
277#define LOCALMEM_ARBITRATION_DMA_PRIORITY_5           5
278#define LOCALMEM_ARBITRATION_DMA_PRIORITY_6           6
279#define LOCALMEM_ARBITRATION_DMA_PRIORITY_7           7
280#define LOCALMEM_ARBITRATION_ZVPORT1                  18:16
281#define LOCALMEM_ARBITRATION_ZVPORT1_OFF              0
282#define LOCALMEM_ARBITRATION_ZVPORT1_PRIORITY_1       1
283#define LOCALMEM_ARBITRATION_ZVPORT1_PRIORITY_2       2
284#define LOCALMEM_ARBITRATION_ZVPORT1_PRIORITY_3       3
285#define LOCALMEM_ARBITRATION_ZVPORT1_PRIORITY_4       4
286#define LOCALMEM_ARBITRATION_ZVPORT1_PRIORITY_5       5
287#define LOCALMEM_ARBITRATION_ZVPORT1_PRIORITY_6       6
288#define LOCALMEM_ARBITRATION_ZVPORT1_PRIORITY_7       7
289#define LOCALMEM_ARBITRATION_ZVPORT0                  14:12
290#define LOCALMEM_ARBITRATION_ZVPORT0_OFF              0
291#define LOCALMEM_ARBITRATION_ZVPORT0_PRIORITY_1       1
292#define LOCALMEM_ARBITRATION_ZVPORT0_PRIORITY_2       2
293#define LOCALMEM_ARBITRATION_ZVPORT0_PRIORITY_3       3
294#define LOCALMEM_ARBITRATION_ZVPORT0_PRIORITY_4       4
295#define LOCALMEM_ARBITRATION_ZVPORT0_PRIORITY_5       5
296#define LOCALMEM_ARBITRATION_ZVPORT0_PRIORITY_6       6
297#define LOCALMEM_ARBITRATION_ZVPORT0_PRIORITY_7       7
298#define LOCALMEM_ARBITRATION_VIDEO                    10:8
299#define LOCALMEM_ARBITRATION_VIDEO_OFF                0
300#define LOCALMEM_ARBITRATION_VIDEO_PRIORITY_1         1
301#define LOCALMEM_ARBITRATION_VIDEO_PRIORITY_2         2
302#define LOCALMEM_ARBITRATION_VIDEO_PRIORITY_3         3
303#define LOCALMEM_ARBITRATION_VIDEO_PRIORITY_4         4
304#define LOCALMEM_ARBITRATION_VIDEO_PRIORITY_5         5
305#define LOCALMEM_ARBITRATION_VIDEO_PRIORITY_6         6
306#define LOCALMEM_ARBITRATION_VIDEO_PRIORITY_7         7
307#define LOCALMEM_ARBITRATION_PANEL                    6:4
308#define LOCALMEM_ARBITRATION_PANEL_OFF                0
309#define LOCALMEM_ARBITRATION_PANEL_PRIORITY_1         1
310#define LOCALMEM_ARBITRATION_PANEL_PRIORITY_2         2
311#define LOCALMEM_ARBITRATION_PANEL_PRIORITY_3         3
312#define LOCALMEM_ARBITRATION_PANEL_PRIORITY_4         4
313#define LOCALMEM_ARBITRATION_PANEL_PRIORITY_5         5
314#define LOCALMEM_ARBITRATION_PANEL_PRIORITY_6         6
315#define LOCALMEM_ARBITRATION_PANEL_PRIORITY_7         7
316#define LOCALMEM_ARBITRATION_CRT                      2:0
317#define LOCALMEM_ARBITRATION_CRT_OFF                  0
318#define LOCALMEM_ARBITRATION_CRT_PRIORITY_1           1
319#define LOCALMEM_ARBITRATION_CRT_PRIORITY_2           2
320#define LOCALMEM_ARBITRATION_CRT_PRIORITY_3           3
321#define LOCALMEM_ARBITRATION_CRT_PRIORITY_4           4
322#define LOCALMEM_ARBITRATION_CRT_PRIORITY_5           5
323#define LOCALMEM_ARBITRATION_CRT_PRIORITY_6           6
324#define LOCALMEM_ARBITRATION_CRT_PRIORITY_7           7
325
326#define PCIMEM_ARBITRATION                            0x000010
327#define PCIMEM_ARBITRATION_ROTATE                     28:28
328#define PCIMEM_ARBITRATION_ROTATE_OFF                 0
329#define PCIMEM_ARBITRATION_ROTATE_ON                  1
330#define PCIMEM_ARBITRATION_VGA                        26:24
331#define PCIMEM_ARBITRATION_VGA_OFF                    0
332#define PCIMEM_ARBITRATION_VGA_PRIORITY_1             1
333#define PCIMEM_ARBITRATION_VGA_PRIORITY_2             2
334#define PCIMEM_ARBITRATION_VGA_PRIORITY_3             3
335#define PCIMEM_ARBITRATION_VGA_PRIORITY_4             4
336#define PCIMEM_ARBITRATION_VGA_PRIORITY_5             5
337#define PCIMEM_ARBITRATION_VGA_PRIORITY_6             6
338#define PCIMEM_ARBITRATION_VGA_PRIORITY_7             7
339#define PCIMEM_ARBITRATION_DMA                        22:20
340#define PCIMEM_ARBITRATION_DMA_OFF                    0
341#define PCIMEM_ARBITRATION_DMA_PRIORITY_1             1
342#define PCIMEM_ARBITRATION_DMA_PRIORITY_2             2
343#define PCIMEM_ARBITRATION_DMA_PRIORITY_3             3
344#define PCIMEM_ARBITRATION_DMA_PRIORITY_4             4
345#define PCIMEM_ARBITRATION_DMA_PRIORITY_5             5
346#define PCIMEM_ARBITRATION_DMA_PRIORITY_6             6
347#define PCIMEM_ARBITRATION_DMA_PRIORITY_7             7
348#define PCIMEM_ARBITRATION_ZVPORT1                    18:16
349#define PCIMEM_ARBITRATION_ZVPORT1_OFF                0
350#define PCIMEM_ARBITRATION_ZVPORT1_PRIORITY_1         1
351#define PCIMEM_ARBITRATION_ZVPORT1_PRIORITY_2         2
352#define PCIMEM_ARBITRATION_ZVPORT1_PRIORITY_3         3
353#define PCIMEM_ARBITRATION_ZVPORT1_PRIORITY_4         4
354#define PCIMEM_ARBITRATION_ZVPORT1_PRIORITY_5         5
355#define PCIMEM_ARBITRATION_ZVPORT1_PRIORITY_6         6
356#define PCIMEM_ARBITRATION_ZVPORT1_PRIORITY_7         7
357#define PCIMEM_ARBITRATION_ZVPORT0                    14:12
358#define PCIMEM_ARBITRATION_ZVPORT0_OFF                0
359#define PCIMEM_ARBITRATION_ZVPORT0_PRIORITY_1         1
360#define PCIMEM_ARBITRATION_ZVPORT0_PRIORITY_2         2
361#define PCIMEM_ARBITRATION_ZVPORT0_PRIORITY_3         3
362#define PCIMEM_ARBITRATION_ZVPORT0_PRIORITY_4         4
363#define PCIMEM_ARBITRATION_ZVPORT0_PRIORITY_5         5
364#define PCIMEM_ARBITRATION_ZVPORT0_PRIORITY_6         6
365#define PCIMEM_ARBITRATION_ZVPORT0_PRIORITY_7         7
366#define PCIMEM_ARBITRATION_VIDEO                      10:8
367#define PCIMEM_ARBITRATION_VIDEO_OFF                  0
368#define PCIMEM_ARBITRATION_VIDEO_PRIORITY_1           1
369#define PCIMEM_ARBITRATION_VIDEO_PRIORITY_2           2
370#define PCIMEM_ARBITRATION_VIDEO_PRIORITY_3           3
371#define PCIMEM_ARBITRATION_VIDEO_PRIORITY_4           4
372#define PCIMEM_ARBITRATION_VIDEO_PRIORITY_5           5
373#define PCIMEM_ARBITRATION_VIDEO_PRIORITY_6           6
374#define PCIMEM_ARBITRATION_VIDEO_PRIORITY_7           7
375#define PCIMEM_ARBITRATION_PANEL                      6:4
376#define PCIMEM_ARBITRATION_PANEL_OFF                  0
377#define PCIMEM_ARBITRATION_PANEL_PRIORITY_1           1
378#define PCIMEM_ARBITRATION_PANEL_PRIORITY_2           2
379#define PCIMEM_ARBITRATION_PANEL_PRIORITY_3           3
380#define PCIMEM_ARBITRATION_PANEL_PRIORITY_4           4
381#define PCIMEM_ARBITRATION_PANEL_PRIORITY_5           5
382#define PCIMEM_ARBITRATION_PANEL_PRIORITY_6           6
383#define PCIMEM_ARBITRATION_PANEL_PRIORITY_7           7
384#define PCIMEM_ARBITRATION_CRT                        2:0
385#define PCIMEM_ARBITRATION_CRT_OFF                    0
386#define PCIMEM_ARBITRATION_CRT_PRIORITY_1             1
387#define PCIMEM_ARBITRATION_CRT_PRIORITY_2             2
388#define PCIMEM_ARBITRATION_CRT_PRIORITY_3             3
389#define PCIMEM_ARBITRATION_CRT_PRIORITY_4             4
390#define PCIMEM_ARBITRATION_CRT_PRIORITY_5             5
391#define PCIMEM_ARBITRATION_CRT_PRIORITY_6             6
392#define PCIMEM_ARBITRATION_CRT_PRIORITY_7             7
393
394#define RAW_INT                                       0x000020
395#define RAW_INT_ZVPORT1_VSYNC                         4:4
396#define RAW_INT_ZVPORT1_VSYNC_INACTIVE                0
397#define RAW_INT_ZVPORT1_VSYNC_ACTIVE                  1
398#define RAW_INT_ZVPORT1_VSYNC_CLEAR                   1
399#define RAW_INT_ZVPORT0_VSYNC                         3:3
400#define RAW_INT_ZVPORT0_VSYNC_INACTIVE                0
401#define RAW_INT_ZVPORT0_VSYNC_ACTIVE                  1
402#define RAW_INT_ZVPORT0_VSYNC_CLEAR                   1
403#define RAW_INT_CRT_VSYNC                             2:2
404#define RAW_INT_CRT_VSYNC_INACTIVE                    0
405#define RAW_INT_CRT_VSYNC_ACTIVE                      1
406#define RAW_INT_CRT_VSYNC_CLEAR                       1
407#define RAW_INT_PANEL_VSYNC                           1:1
408#define RAW_INT_PANEL_VSYNC_INACTIVE                  0
409#define RAW_INT_PANEL_VSYNC_ACTIVE                    1
410#define RAW_INT_PANEL_VSYNC_CLEAR                     1
411#define RAW_INT_VGA_VSYNC                             0:0
412#define RAW_INT_VGA_VSYNC_INACTIVE                    0
413#define RAW_INT_VGA_VSYNC_ACTIVE                      1
414#define RAW_INT_VGA_VSYNC_CLEAR                       1
415
416#define INT_STATUS                                    0x000024
417#define INT_STATUS_GPIO31                             31:31
418#define INT_STATUS_GPIO31_INACTIVE                    0
419#define INT_STATUS_GPIO31_ACTIVE                      1
420#define INT_STATUS_GPIO30                             30:30
421#define INT_STATUS_GPIO30_INACTIVE                    0
422#define INT_STATUS_GPIO30_ACTIVE                      1
423#define INT_STATUS_GPIO29                             29:29
424#define INT_STATUS_GPIO29_INACTIVE                    0
425#define INT_STATUS_GPIO29_ACTIVE                      1
426#define INT_STATUS_GPIO28                             28:28
427#define INT_STATUS_GPIO28_INACTIVE                    0
428#define INT_STATUS_GPIO28_ACTIVE                      1
429#define INT_STATUS_GPIO27                             27:27
430#define INT_STATUS_GPIO27_INACTIVE                    0
431#define INT_STATUS_GPIO27_ACTIVE                      1
432#define INT_STATUS_GPIO26                             26:26
433#define INT_STATUS_GPIO26_INACTIVE                    0
434#define INT_STATUS_GPIO26_ACTIVE                      1
435#define INT_STATUS_GPIO25                             25:25
436#define INT_STATUS_GPIO25_INACTIVE                    0
437#define INT_STATUS_GPIO25_ACTIVE                      1
438#define INT_STATUS_I2C                                12:12
439#define INT_STATUS_I2C_INACTIVE                       0
440#define INT_STATUS_I2C_ACTIVE                         1
441#define INT_STATUS_PWM                                11:11
442#define INT_STATUS_PWM_INACTIVE                       0
443#define INT_STATUS_PWM_ACTIVE                         1
444#define INT_STATUS_DMA1                               10:10
445#define INT_STATUS_DMA1_INACTIVE                      0
446#define INT_STATUS_DMA1_ACTIVE                        1
447#define INT_STATUS_DMA0                               9:9
448#define INT_STATUS_DMA0_INACTIVE                      0
449#define INT_STATUS_DMA0_ACTIVE                        1
450#define INT_STATUS_PCI                                8:8
451#define INT_STATUS_PCI_INACTIVE                       0
452#define INT_STATUS_PCI_ACTIVE                         1
453#define INT_STATUS_SSP1                               7:7
454#define INT_STATUS_SSP1_INACTIVE                      0
455#define INT_STATUS_SSP1_ACTIVE                        1
456#define INT_STATUS_SSP0                               6:6
457#define INT_STATUS_SSP0_INACTIVE                      0
458#define INT_STATUS_SSP0_ACTIVE                        1
459#define INT_STATUS_DE                                 5:5
460#define INT_STATUS_DE_INACTIVE                        0
461#define INT_STATUS_DE_ACTIVE                          1
462#define INT_STATUS_ZVPORT1_VSYNC                      4:4
463#define INT_STATUS_ZVPORT1_VSYNC_INACTIVE             0
464#define INT_STATUS_ZVPORT1_VSYNC_ACTIVE               1
465#define INT_STATUS_ZVPORT0_VSYNC                      3:3
466#define INT_STATUS_ZVPORT0_VSYNC_INACTIVE             0
467#define INT_STATUS_ZVPORT0_VSYNC_ACTIVE               1
468#define INT_STATUS_CRT_VSYNC                          2:2
469#define INT_STATUS_CRT_VSYNC_INACTIVE                 0
470#define INT_STATUS_CRT_VSYNC_ACTIVE                   1
471#define INT_STATUS_PANEL_VSYNC                        1:1
472#define INT_STATUS_PANEL_VSYNC_INACTIVE               0
473#define INT_STATUS_PANEL_VSYNC_ACTIVE                 1
474#define INT_STATUS_VGA_VSYNC                          0:0
475#define INT_STATUS_VGA_VSYNC_INACTIVE                 0
476#define INT_STATUS_VGA_VSYNC_ACTIVE                   1
477
478#define INT_MASK                                      0x000028
479#define INT_MASK_GPIO31                               31:31
480#define INT_MASK_GPIO31_DISABLE                       0
481#define INT_MASK_GPIO31_ENABLE                        1
482#define INT_MASK_GPIO30                               30:30
483#define INT_MASK_GPIO30_DISABLE                       0
484#define INT_MASK_GPIO30_ENABLE                        1
485#define INT_MASK_GPIO29                               29:29
486#define INT_MASK_GPIO29_DISABLE                       0
487#define INT_MASK_GPIO29_ENABLE                        1
488#define INT_MASK_GPIO28                               28:28
489#define INT_MASK_GPIO28_DISABLE                       0
490#define INT_MASK_GPIO28_ENABLE                        1
491#define INT_MASK_GPIO27                               27:27
492#define INT_MASK_GPIO27_DISABLE                       0
493#define INT_MASK_GPIO27_ENABLE                        1
494#define INT_MASK_GPIO26                               26:26
495#define INT_MASK_GPIO26_DISABLE                       0
496#define INT_MASK_GPIO26_ENABLE                        1
497#define INT_MASK_GPIO25                               25:25
498#define INT_MASK_GPIO25_DISABLE                       0
499#define INT_MASK_GPIO25_ENABLE                        1
500#define INT_MASK_I2C                                  12:12
501#define INT_MASK_I2C_DISABLE                          0
502#define INT_MASK_I2C_ENABLE                           1
503#define INT_MASK_PWM                                  11:11
504#define INT_MASK_PWM_DISABLE                          0
505#define INT_MASK_PWM_ENABLE                           1
506#define INT_MASK_DMA1                                 10:10
507#define INT_MASK_DMA1_DISABLE                         0
508#define INT_MASK_DMA1_ENABLE                          1
509#define INT_MASK_DMA                                  9:9
510#define INT_MASK_DMA_DISABLE                          0
511#define INT_MASK_DMA_ENABLE                           1
512#define INT_MASK_PCI                                  8:8
513#define INT_MASK_PCI_DISABLE                          0
514#define INT_MASK_PCI_ENABLE                           1
515#define INT_MASK_SSP1                                 7:7
516#define INT_MASK_SSP1_DISABLE                         0
517#define INT_MASK_SSP1_ENABLE                          1
518#define INT_MASK_SSP0                                 6:6
519#define INT_MASK_SSP0_DISABLE                         0
520#define INT_MASK_SSP0_ENABLE                          1
521#define INT_MASK_DE                                   5:5
522#define INT_MASK_DE_DISABLE                           0
523#define INT_MASK_DE_ENABLE                            1
524#define INT_MASK_ZVPORT1_VSYNC                        4:4
525#define INT_MASK_ZVPORT1_VSYNC_DISABLE                0
526#define INT_MASK_ZVPORT1_VSYNC_ENABLE                 1
527#define INT_MASK_ZVPORT0_VSYNC                        3:3
528#define INT_MASK_ZVPORT0_VSYNC_DISABLE                0
529#define INT_MASK_ZVPORT0_VSYNC_ENABLE                 1
530#define INT_MASK_CRT_VSYNC                            2:2
531#define INT_MASK_CRT_VSYNC_DISABLE                    0
532#define INT_MASK_CRT_VSYNC_ENABLE                     1
533#define INT_MASK_PANEL_VSYNC                          1:1
534#define INT_MASK_PANEL_VSYNC_DISABLE                  0
535#define INT_MASK_PANEL_VSYNC_ENABLE                   1
536#define INT_MASK_VGA_VSYNC                            0:0
537#define INT_MASK_VGA_VSYNC_DISABLE                    0
538#define INT_MASK_VGA_VSYNC_ENABLE                     1
539
540#define CURRENT_GATE                                  0x000040
541#define CURRENT_GATE_MCLK                             15:14
542#ifdef VALIDATION_CHIP
543    #define CURRENT_GATE_MCLK_112MHZ                      0
544    #define CURRENT_GATE_MCLK_84MHZ                       1
545    #define CURRENT_GATE_MCLK_56MHZ                       2
546    #define CURRENT_GATE_MCLK_42MHZ                       3
547#else
548    #define CURRENT_GATE_MCLK_DIV_3                       0
549    #define CURRENT_GATE_MCLK_DIV_4                       1
550    #define CURRENT_GATE_MCLK_DIV_6                       2
551    #define CURRENT_GATE_MCLK_DIV_8                       3
552#endif
553#define CURRENT_GATE_M2XCLK                           13:12
554#ifdef VALIDATION_CHIP
555    #define CURRENT_GATE_M2XCLK_336MHZ                    0
556    #define CURRENT_GATE_M2XCLK_168MHZ                    1
557    #define CURRENT_GATE_M2XCLK_112MHZ                    2
558    #define CURRENT_GATE_M2XCLK_84MHZ                     3
559#else
560    #define CURRENT_GATE_M2XCLK_DIV_1                     0
561    #define CURRENT_GATE_M2XCLK_DIV_2                     1
562    #define CURRENT_GATE_M2XCLK_DIV_3                     2
563    #define CURRENT_GATE_M2XCLK_DIV_4                     3
564#endif
565#define CURRENT_GATE_VGA                              10:10
566#define CURRENT_GATE_VGA_OFF                          0
567#define CURRENT_GATE_VGA_ON                           1
568#define CURRENT_GATE_PWM                              9:9
569#define CURRENT_GATE_PWM_OFF                          0
570#define CURRENT_GATE_PWM_ON                           1
571#define CURRENT_GATE_I2C                              8:8
572#define CURRENT_GATE_I2C_OFF                          0
573#define CURRENT_GATE_I2C_ON                           1
574#define CURRENT_GATE_SSP                              7:7
575#define CURRENT_GATE_SSP_OFF                          0
576#define CURRENT_GATE_SSP_ON                           1
577#define CURRENT_GATE_GPIO                             6:6
578#define CURRENT_GATE_GPIO_OFF                         0
579#define CURRENT_GATE_GPIO_ON                          1
580#define CURRENT_GATE_ZVPORT                           5:5
581#define CURRENT_GATE_ZVPORT_OFF                       0
582#define CURRENT_GATE_ZVPORT_ON                        1
583#define CURRENT_GATE_CSC                              4:4
584#define CURRENT_GATE_CSC_OFF                          0
585#define CURRENT_GATE_CSC_ON                           1
586#define CURRENT_GATE_DE                               3:3
587#define CURRENT_GATE_DE_OFF                           0
588#define CURRENT_GATE_DE_ON                            1
589#define CURRENT_GATE_DISPLAY                          2:2
590#define CURRENT_GATE_DISPLAY_OFF                      0
591#define CURRENT_GATE_DISPLAY_ON                       1
592#define CURRENT_GATE_LOCALMEM                         1:1
593#define CURRENT_GATE_LOCALMEM_OFF                     0
594#define CURRENT_GATE_LOCALMEM_ON                      1
595#define CURRENT_GATE_DMA                              0:0
596#define CURRENT_GATE_DMA_OFF                          0
597#define CURRENT_GATE_DMA_ON                           1
598
599#define MODE0_GATE                                    0x000044
600#define MODE0_GATE_MCLK                               15:14
601#define MODE0_GATE_MCLK_112MHZ                        0
602#define MODE0_GATE_MCLK_84MHZ                         1
603#define MODE0_GATE_MCLK_56MHZ                         2
604#define MODE0_GATE_MCLK_42MHZ                         3
605#define MODE0_GATE_M2XCLK                             13:12
606#define MODE0_GATE_M2XCLK_336MHZ                      0
607#define MODE0_GATE_M2XCLK_168MHZ                      1
608#define MODE0_GATE_M2XCLK_112MHZ                      2
609#define MODE0_GATE_M2XCLK_84MHZ                       3
610#define MODE0_GATE_VGA                                10:10
611#define MODE0_GATE_VGA_OFF                            0
612#define MODE0_GATE_VGA_ON                             1
613#define MODE0_GATE_PWM                                9:9
614#define MODE0_GATE_PWM_OFF                            0
615#define MODE0_GATE_PWM_ON                             1
616#define MODE0_GATE_I2C                                8:8
617#define MODE0_GATE_I2C_OFF                            0
618#define MODE0_GATE_I2C_ON                             1
619#define MODE0_GATE_SSP                                7:7
620#define MODE0_GATE_SSP_OFF                            0
621#define MODE0_GATE_SSP_ON                             1
622#define MODE0_GATE_GPIO                               6:6
623#define MODE0_GATE_GPIO_OFF                           0
624#define MODE0_GATE_GPIO_ON                            1
625#define MODE0_GATE_ZVPORT                             5:5
626#define MODE0_GATE_ZVPORT_OFF                         0
627#define MODE0_GATE_ZVPORT_ON                          1
628#define MODE0_GATE_CSC                                4:4
629#define MODE0_GATE_CSC_OFF                            0
630#define MODE0_GATE_CSC_ON                             1
631#define MODE0_GATE_DE                                 3:3
632#define MODE0_GATE_DE_OFF                             0
633#define MODE0_GATE_DE_ON                              1
634#define MODE0_GATE_DISPLAY                            2:2
635#define MODE0_GATE_DISPLAY_OFF                        0
636#define MODE0_GATE_DISPLAY_ON                         1
637#define MODE0_GATE_LOCALMEM                           1:1
638#define MODE0_GATE_LOCALMEM_OFF                       0
639#define MODE0_GATE_LOCALMEM_ON                        1
640#define MODE0_GATE_DMA                                0:0
641#define MODE0_GATE_DMA_OFF                            0
642#define MODE0_GATE_DMA_ON                             1
643
644#define MODE1_GATE                                    0x000048
645#define MODE1_GATE_MCLK                               15:14
646#define MODE1_GATE_MCLK_112MHZ                        0
647#define MODE1_GATE_MCLK_84MHZ                         1
648#define MODE1_GATE_MCLK_56MHZ                         2
649#define MODE1_GATE_MCLK_42MHZ                         3
650#define MODE1_GATE_M2XCLK                             13:12
651#define MODE1_GATE_M2XCLK_336MHZ                      0
652#define MODE1_GATE_M2XCLK_168MHZ                      1
653#define MODE1_GATE_M2XCLK_112MHZ                      2
654#define MODE1_GATE_M2XCLK_84MHZ                       3
655#define MODE1_GATE_VGA                                10:10
656#define MODE1_GATE_VGA_OFF                            0
657#define MODE1_GATE_VGA_ON                             1
658#define MODE1_GATE_PWM                                9:9
659#define MODE1_GATE_PWM_OFF                            0
660#define MODE1_GATE_PWM_ON                             1
661#define MODE1_GATE_I2C                                8:8
662#define MODE1_GATE_I2C_OFF                            0
663#define MODE1_GATE_I2C_ON                             1
664#define MODE1_GATE_SSP                                7:7
665#define MODE1_GATE_SSP_OFF                            0
666#define MODE1_GATE_SSP_ON                             1
667#define MODE1_GATE_GPIO                               6:6
668#define MODE1_GATE_GPIO_OFF                           0
669#define MODE1_GATE_GPIO_ON                            1
670#define MODE1_GATE_ZVPORT                             5:5
671#define MODE1_GATE_ZVPORT_OFF                         0
672#define MODE1_GATE_ZVPORT_ON                          1
673#define MODE1_GATE_CSC                                4:4
674#define MODE1_GATE_CSC_OFF                            0
675#define MODE1_GATE_CSC_ON                             1
676#define MODE1_GATE_DE                                 3:3
677#define MODE1_GATE_DE_OFF                             0
678#define MODE1_GATE_DE_ON                              1
679#define MODE1_GATE_DISPLAY                            2:2
680#define MODE1_GATE_DISPLAY_OFF                        0
681#define MODE1_GATE_DISPLAY_ON                         1
682#define MODE1_GATE_LOCALMEM                           1:1
683#define MODE1_GATE_LOCALMEM_OFF                       0
684#define MODE1_GATE_LOCALMEM_ON                        1
685#define MODE1_GATE_DMA                                0:0
686#define MODE1_GATE_DMA_OFF                            0
687#define MODE1_GATE_DMA_ON                             1
688
689#define POWER_MODE_CTRL                               0x00004C
690#ifdef VALIDATION_CHIP
691    #define POWER_MODE_CTRL_336CLK                    4:4
692    #define POWER_MODE_CTRL_336CLK_OFF                0
693    #define POWER_MODE_CTRL_336CLK_ON                 1
694#endif
695#define POWER_MODE_CTRL_OSC_INPUT                     3:3
696#define POWER_MODE_CTRL_OSC_INPUT_OFF                 0
697#define POWER_MODE_CTRL_OSC_INPUT_ON                  1
698#define POWER_MODE_CTRL_ACPI                          2:2
699#define POWER_MODE_CTRL_ACPI_OFF                      0
700#define POWER_MODE_CTRL_ACPI_ON                       1
701#define POWER_MODE_CTRL_MODE                          1:0
702#define POWER_MODE_CTRL_MODE_MODE0                    0
703#define POWER_MODE_CTRL_MODE_MODE1                    1
704#define POWER_MODE_CTRL_MODE_SLEEP                    2
705
706#define PCI_MASTER_BASE                               0x000050
707#define PCI_MASTER_BASE_ADDRESS                       7:0
708
709#define DEVICE_ID                                     0x000054
710#define DEVICE_ID_DEVICE_ID                           31:16
711#define DEVICE_ID_REVISION_ID                         7:0
712
713#define PLL_CLK_COUNT                                 0x000058
714#define PLL_CLK_COUNT_COUNTER                         15:0
715
716#define PANEL_PLL_CTRL                                0x00005C
717#define PANEL_PLL_CTRL_BYPASS                         18:18
718#define PANEL_PLL_CTRL_BYPASS_OFF                     0
719#define PANEL_PLL_CTRL_BYPASS_ON                      1
720#define PANEL_PLL_CTRL_POWER                          17:17
721#define PANEL_PLL_CTRL_POWER_OFF                      0
722#define PANEL_PLL_CTRL_POWER_ON                       1
723#define PANEL_PLL_CTRL_INPUT                          16:16
724#define PANEL_PLL_CTRL_INPUT_OSC                      0
725#define PANEL_PLL_CTRL_INPUT_TESTCLK                  1
726#ifdef VALIDATION_CHIP
727    #define PANEL_PLL_CTRL_OD                         15:14
728#else
729    #define PANEL_PLL_CTRL_POD                        15:14
730    #define PANEL_PLL_CTRL_OD                         13:12
731#endif
732#define PANEL_PLL_CTRL_N                              11:8
733#define PANEL_PLL_CTRL_M                              7:0
734
735#define CRT_PLL_CTRL                                  0x000060
736#define CRT_PLL_CTRL_BYPASS                           18:18
737#define CRT_PLL_CTRL_BYPASS_OFF                       0
738#define CRT_PLL_CTRL_BYPASS_ON                        1
739#define CRT_PLL_CTRL_POWER                            17:17
740#define CRT_PLL_CTRL_POWER_OFF                        0
741#define CRT_PLL_CTRL_POWER_ON                         1
742#define CRT_PLL_CTRL_INPUT                            16:16
743#define CRT_PLL_CTRL_INPUT_OSC                        0
744#define CRT_PLL_CTRL_INPUT_TESTCLK                    1
745#ifdef VALIDATION_CHIP
746    #define CRT_PLL_CTRL_OD                           15:14
747#else
748    #define CRT_PLL_CTRL_POD                          15:14
749    #define CRT_PLL_CTRL_OD                           13:12
750#endif
751#define CRT_PLL_CTRL_N                                11:8
752#define CRT_PLL_CTRL_M                                7:0
753
754#define VGA_PLL0_CTRL                                 0x000064
755#define VGA_PLL0_CTRL_BYPASS                          18:18
756#define VGA_PLL0_CTRL_BYPASS_OFF                      0
757#define VGA_PLL0_CTRL_BYPASS_ON                       1
758#define VGA_PLL0_CTRL_POWER                           17:17
759#define VGA_PLL0_CTRL_POWER_OFF                       0
760#define VGA_PLL0_CTRL_POWER_ON                        1
761#define VGA_PLL0_CTRL_INPUT                           16:16
762#define VGA_PLL0_CTRL_INPUT_OSC                       0
763#define VGA_PLL0_CTRL_INPUT_TESTCLK                   1
764#ifdef VALIDATION_CHIP
765    #define VGA_PLL0_CTRL_OD                          15:14
766#else
767    #define VGA_PLL0_CTRL_POD                         15:14
768    #define VGA_PLL0_CTRL_OD                          13:12
769#endif
770#define VGA_PLL0_CTRL_N                               11:8
771#define VGA_PLL0_CTRL_M                               7:0
772
773#define VGA_PLL1_CTRL                                 0x000068
774#define VGA_PLL1_CTRL_BYPASS                          18:18
775#define VGA_PLL1_CTRL_BYPASS_OFF                      0
776#define VGA_PLL1_CTRL_BYPASS_ON                       1
777#define VGA_PLL1_CTRL_POWER                           17:17
778#define VGA_PLL1_CTRL_POWER_OFF                       0
779#define VGA_PLL1_CTRL_POWER_ON                        1
780#define VGA_PLL1_CTRL_INPUT                           16:16
781#define VGA_PLL1_CTRL_INPUT_OSC                       0
782#define VGA_PLL1_CTRL_INPUT_TESTCLK                   1
783#ifdef VALIDATION_CHIP
784    #define VGA_PLL1_CTRL_OD                          15:14
785#else
786    #define VGA_PLL1_CTRL_POD                         15:14
787    #define VGA_PLL1_CTRL_OD                          13:12
788#endif
789#define VGA_PLL1_CTRL_N                               11:8
790#define VGA_PLL1_CTRL_M                               7:0
791
792#define SCRATCH_DATA                                  0x00006c
793
794#ifndef VALIDATION_CHIP
795
796#define MXCLK_PLL_CTRL                                0x000070
797#define MXCLK_PLL_CTRL_BYPASS                         18:18
798#define MXCLK_PLL_CTRL_BYPASS_OFF                     0
799#define MXCLK_PLL_CTRL_BYPASS_ON                      1
800#define MXCLK_PLL_CTRL_POWER                          17:17
801#define MXCLK_PLL_CTRL_POWER_OFF                      0
802#define MXCLK_PLL_CTRL_POWER_ON                       1
803#define MXCLK_PLL_CTRL_INPUT                          16:16
804#define MXCLK_PLL_CTRL_INPUT_OSC                      0
805#define MXCLK_PLL_CTRL_INPUT_TESTCLK                  1
806#define MXCLK_PLL_CTRL_POD                            15:14
807#define MXCLK_PLL_CTRL_OD                             13:12
808#define MXCLK_PLL_CTRL_N                              11:8
809#define MXCLK_PLL_CTRL_M                              7:0
810
811#define VGA_CONFIGURATION                             0x000088
812#define VGA_CONFIGURATION_USER_DEFINE                 5:4
813#define VGA_CONFIGURATION_PLL                         2:2
814#define VGA_CONFIGURATION_PLL_VGA                     0
815#define VGA_CONFIGURATION_PLL_PANEL                   1
816#define VGA_CONFIGURATION_MODE                        1:1
817#define VGA_CONFIGURATION_MODE_TEXT                   0
818#define VGA_CONFIGURATION_MODE_GRAPHIC                1
819
820#endif
821
822#define GPIO_DATA                                       0x010000
823#define GPIO_DATA_31                                    31:31
824#define GPIO_DATA_30                                    30:30
825#define GPIO_DATA_29                                    29:29
826#define GPIO_DATA_28                                    28:28
827#define GPIO_DATA_27                                    27:27
828#define GPIO_DATA_26                                    26:26
829#define GPIO_DATA_25                                    25:25
830#define GPIO_DATA_24                                    24:24
831#define GPIO_DATA_23                                    23:23
832#define GPIO_DATA_22                                    22:22
833#define GPIO_DATA_21                                    21:21
834#define GPIO_DATA_20                                    20:20
835#define GPIO_DATA_19                                    19:19
836#define GPIO_DATA_18                                    18:18
837#define GPIO_DATA_17                                    17:17
838#define GPIO_DATA_16                                    16:16
839#define GPIO_DATA_15                                    15:15
840#define GPIO_DATA_14                                    14:14
841#define GPIO_DATA_13                                    13:13
842#define GPIO_DATA_12                                    12:12
843#define GPIO_DATA_11                                    11:11
844#define GPIO_DATA_10                                    10:10
845#define GPIO_DATA_9                                     9:9
846#define GPIO_DATA_8                                     8:8
847#define GPIO_DATA_7                                     7:7
848#define GPIO_DATA_6                                     6:6
849#define GPIO_DATA_5                                     5:5
850#define GPIO_DATA_4                                     4:4
851#define GPIO_DATA_3                                     3:3
852#define GPIO_DATA_2                                     2:2
853#define GPIO_DATA_1                                     1:1
854#define GPIO_DATA_0                                     0:0
855
856#define GPIO_DATA_DIRECTION                             0x010004
857#define GPIO_DATA_DIRECTION_31                          31:31
858#define GPIO_DATA_DIRECTION_31_INPUT                    0
859#define GPIO_DATA_DIRECTION_31_OUTPUT                   1
860#define GPIO_DATA_DIRECTION_30                          30:30
861#define GPIO_DATA_DIRECTION_30_INPUT                    0
862#define GPIO_DATA_DIRECTION_30_OUTPUT                   1
863#define GPIO_DATA_DIRECTION_29                          29:29
864#define GPIO_DATA_DIRECTION_29_INPUT                    0
865#define GPIO_DATA_DIRECTION_29_OUTPUT                   1
866#define GPIO_DATA_DIRECTION_28                          28:28
867#define GPIO_DATA_DIRECTION_28_INPUT                    0
868#define GPIO_DATA_DIRECTION_28_OUTPUT                   1
869#define GPIO_DATA_DIRECTION_27                          27:27
870#define GPIO_DATA_DIRECTION_27_INPUT                    0
871#define GPIO_DATA_DIRECTION_27_OUTPUT                   1
872#define GPIO_DATA_DIRECTION_26                          26:26
873#define GPIO_DATA_DIRECTION_26_INPUT                    0
874#define GPIO_DATA_DIRECTION_26_OUTPUT                   1
875#define GPIO_DATA_DIRECTION_25                          25:25
876#define GPIO_DATA_DIRECTION_25_INPUT                    0
877#define GPIO_DATA_DIRECTION_25_OUTPUT                   1
878#define GPIO_DATA_DIRECTION_24                          24:24
879#define GPIO_DATA_DIRECTION_24_INPUT                    0
880#define GPIO_DATA_DIRECTION_24_OUTPUT                   1
881#define GPIO_DATA_DIRECTION_23                          23:23
882#define GPIO_DATA_DIRECTION_23_INPUT                    0
883#define GPIO_DATA_DIRECTION_23_OUTPUT                   1
884#define GPIO_DATA_DIRECTION_22                          22:22
885#define GPIO_DATA_DIRECTION_22_INPUT                    0
886#define GPIO_DATA_DIRECTION_22_OUTPUT                   1
887#define GPIO_DATA_DIRECTION_21                          21:21
888#define GPIO_DATA_DIRECTION_21_INPUT                    0
889#define GPIO_DATA_DIRECTION_21_OUTPUT                   1
890#define GPIO_DATA_DIRECTION_20                          20:20
891#define GPIO_DATA_DIRECTION_20_INPUT                    0
892#define GPIO_DATA_DIRECTION_20_OUTPUT                   1
893#define GPIO_DATA_DIRECTION_19                          19:19
894#define GPIO_DATA_DIRECTION_19_INPUT                    0
895#define GPIO_DATA_DIRECTION_19_OUTPUT                   1
896#define GPIO_DATA_DIRECTION_18                          18:18
897#define GPIO_DATA_DIRECTION_18_INPUT                    0
898#define GPIO_DATA_DIRECTION_18_OUTPUT                   1
899#define GPIO_DATA_DIRECTION_17                          17:17
900#define GPIO_DATA_DIRECTION_17_INPUT                    0
901#define GPIO_DATA_DIRECTION_17_OUTPUT                   1
902#define GPIO_DATA_DIRECTION_16                          16:16
903#define GPIO_DATA_DIRECTION_16_INPUT                    0
904#define GPIO_DATA_DIRECTION_16_OUTPUT                   1
905#define GPIO_DATA_DIRECTION_15                          15:15
906#define GPIO_DATA_DIRECTION_15_INPUT                    0
907#define GPIO_DATA_DIRECTION_15_OUTPUT                   1
908#define GPIO_DATA_DIRECTION_14                          14:14
909#define GPIO_DATA_DIRECTION_14_INPUT                    0
910#define GPIO_DATA_DIRECTION_14_OUTPUT                   1
911#define GPIO_DATA_DIRECTION_13                          13:13
912#define GPIO_DATA_DIRECTION_13_INPUT                    0
913#define GPIO_DATA_DIRECTION_13_OUTPUT                   1
914#define GPIO_DATA_DIRECTION_12                          12:12
915#define GPIO_DATA_DIRECTION_12_INPUT                    0
916#define GPIO_DATA_DIRECTION_12_OUTPUT                   1
917#define GPIO_DATA_DIRECTION_11                          11:11
918#define GPIO_DATA_DIRECTION_11_INPUT                    0
919#define GPIO_DATA_DIRECTION_11_OUTPUT                   1
920#define GPIO_DATA_DIRECTION_10                          10:10
921#define GPIO_DATA_DIRECTION_10_INPUT                    0
922#define GPIO_DATA_DIRECTION_10_OUTPUT                   1
923#define GPIO_DATA_DIRECTION_9                           9:9
924#define GPIO_DATA_DIRECTION_9_INPUT                     0
925#define GPIO_DATA_DIRECTION_9_OUTPUT                    1
926#define GPIO_DATA_DIRECTION_8                           8:8
927#define GPIO_DATA_DIRECTION_8_INPUT                     0
928#define GPIO_DATA_DIRECTION_8_OUTPUT                    1
929#define GPIO_DATA_DIRECTION_7                           7:7
930#define GPIO_DATA_DIRECTION_7_INPUT                     0
931#define GPIO_DATA_DIRECTION_7_OUTPUT                    1
932#define GPIO_DATA_DIRECTION_6                           6:6
933#define GPIO_DATA_DIRECTION_6_INPUT                     0
934#define GPIO_DATA_DIRECTION_6_OUTPUT                    1
935#define GPIO_DATA_DIRECTION_5                           5:5
936#define GPIO_DATA_DIRECTION_5_INPUT                     0
937#define GPIO_DATA_DIRECTION_5_OUTPUT                    1
938#define GPIO_DATA_DIRECTION_4                           4:4
939#define GPIO_DATA_DIRECTION_4_INPUT                     0
940#define GPIO_DATA_DIRECTION_4_OUTPUT                    1
941#define GPIO_DATA_DIRECTION_3                           3:3
942#define GPIO_DATA_DIRECTION_3_INPUT                     0
943#define GPIO_DATA_DIRECTION_3_OUTPUT                    1
944#define GPIO_DATA_DIRECTION_2                           2:2
945#define GPIO_DATA_DIRECTION_2_INPUT                     0
946#define GPIO_DATA_DIRECTION_2_OUTPUT                    1
947#define GPIO_DATA_DIRECTION_1                           131
948#define GPIO_DATA_DIRECTION_1_INPUT                     0
949#define GPIO_DATA_DIRECTION_1_OUTPUT                    1
950#define GPIO_DATA_DIRECTION_0                           0:0
951#define GPIO_DATA_DIRECTION_0_INPUT                     0
952#define GPIO_DATA_DIRECTION_0_OUTPUT                    1
953
954#define GPIO_INTERRUPT_SETUP                            0x010008
955#define GPIO_INTERRUPT_SETUP_TRIGGER_31                 22:22
956#define GPIO_INTERRUPT_SETUP_TRIGGER_31_EDGE            0
957#define GPIO_INTERRUPT_SETUP_TRIGGER_31_LEVEL           1
958#define GPIO_INTERRUPT_SETUP_TRIGGER_30                 21:21
959#define GPIO_INTERRUPT_SETUP_TRIGGER_30_EDGE            0
960#define GPIO_INTERRUPT_SETUP_TRIGGER_30_LEVEL           1
961#define GPIO_INTERRUPT_SETUP_TRIGGER_29                 20:20
962#define GPIO_INTERRUPT_SETUP_TRIGGER_29_EDGE            0
963#define GPIO_INTERRUPT_SETUP_TRIGGER_29_LEVEL           1
964#define GPIO_INTERRUPT_SETUP_TRIGGER_28                 19:19
965#define GPIO_INTERRUPT_SETUP_TRIGGER_28_EDGE            0
966#define GPIO_INTERRUPT_SETUP_TRIGGER_28_LEVEL           1
967#define GPIO_INTERRUPT_SETUP_TRIGGER_27                 18:18
968#define GPIO_INTERRUPT_SETUP_TRIGGER_27_EDGE            0
969#define GPIO_INTERRUPT_SETUP_TRIGGER_27_LEVEL           1
970#define GPIO_INTERRUPT_SETUP_TRIGGER_26                 17:17
971#define GPIO_INTERRUPT_SETUP_TRIGGER_26_EDGE            0
972#define GPIO_INTERRUPT_SETUP_TRIGGER_26_LEVEL           1
973#define GPIO_INTERRUPT_SETUP_TRIGGER_25                 16:16
974#define GPIO_INTERRUPT_SETUP_TRIGGER_25_EDGE            0
975#define GPIO_INTERRUPT_SETUP_TRIGGER_25_LEVEL           1
976#define GPIO_INTERRUPT_SETUP_ACTIVE_31                  14:14
977#define GPIO_INTERRUPT_SETUP_ACTIVE_31_LOW              0
978#define GPIO_INTERRUPT_SETUP_ACTIVE_31_HIGH             1
979#define GPIO_INTERRUPT_SETUP_ACTIVE_30                  13:13
980#define GPIO_INTERRUPT_SETUP_ACTIVE_30_LOW              0
981#define GPIO_INTERRUPT_SETUP_ACTIVE_30_HIGH             1
982#define GPIO_INTERRUPT_SETUP_ACTIVE_29                  12:12
983#define GPIO_INTERRUPT_SETUP_ACTIVE_29_LOW              0
984#define GPIO_INTERRUPT_SETUP_ACTIVE_29_HIGH             1
985#define GPIO_INTERRUPT_SETUP_ACTIVE_28                  11:11
986#define GPIO_INTERRUPT_SETUP_ACTIVE_28_LOW              0
987#define GPIO_INTERRUPT_SETUP_ACTIVE_28_HIGH             1
988#define GPIO_INTERRUPT_SETUP_ACTIVE_27                  10:10
989#define GPIO_INTERRUPT_SETUP_ACTIVE_27_LOW              0
990#define GPIO_INTERRUPT_SETUP_ACTIVE_27_HIGH             1
991#define GPIO_INTERRUPT_SETUP_ACTIVE_26                  9:9
992#define GPIO_INTERRUPT_SETUP_ACTIVE_26_LOW              0
993#define GPIO_INTERRUPT_SETUP_ACTIVE_26_HIGH             1
994#define GPIO_INTERRUPT_SETUP_ACTIVE_25                  8:8
995#define GPIO_INTERRUPT_SETUP_ACTIVE_25_LOW              0
996#define GPIO_INTERRUPT_SETUP_ACTIVE_25_HIGH             1
997#define GPIO_INTERRUPT_SETUP_ENABLE_31                  6:6
998#define GPIO_INTERRUPT_SETUP_ENABLE_31_GPIO             0
999#define GPIO_INTERRUPT_SETUP_ENABLE_31_INTERRUPT        1
1000#define GPIO_INTERRUPT_SETUP_ENABLE_30                  5:5
1001#define GPIO_INTERRUPT_SETUP_ENABLE_30_GPIO             0
1002#define GPIO_INTERRUPT_SETUP_ENABLE_30_INTERRUPT        1
1003#define GPIO_INTERRUPT_SETUP_ENABLE_29                  4:4
1004#define GPIO_INTERRUPT_SETUP_ENABLE_29_GPIO             0
1005#define GPIO_INTERRUPT_SETUP_ENABLE_29_INTERRUPT        1
1006#define GPIO_INTERRUPT_SETUP_ENABLE_28                  3:3
1007#define GPIO_INTERRUPT_SETUP_ENABLE_28_GPIO             0
1008#define GPIO_INTERRUPT_SETUP_ENABLE_28_INTERRUPT        1
1009#define GPIO_INTERRUPT_SETUP_ENABLE_27                  2:2
1010#define GPIO_INTERRUPT_SETUP_ENABLE_27_GPIO             0
1011#define GPIO_INTERRUPT_SETUP_ENABLE_27_INTERRUPT        1
1012#define GPIO_INTERRUPT_SETUP_ENABLE_26                  1:1
1013#define GPIO_INTERRUPT_SETUP_ENABLE_26_GPIO             0
1014#define GPIO_INTERRUPT_SETUP_ENABLE_26_INTERRUPT        1
1015#define GPIO_INTERRUPT_SETUP_ENABLE_25                  0:0
1016#define GPIO_INTERRUPT_SETUP_ENABLE_25_GPIO             0
1017#define GPIO_INTERRUPT_SETUP_ENABLE_25_INTERRUPT        1
1018
1019#define GPIO_INTERRUPT_STATUS                           0x01000C
1020#define GPIO_INTERRUPT_STATUS_31                        22:22
1021#define GPIO_INTERRUPT_STATUS_31_INACTIVE               0
1022#define GPIO_INTERRUPT_STATUS_31_ACTIVE                 1
1023#define GPIO_INTERRUPT_STATUS_31_RESET                  1
1024#define GPIO_INTERRUPT_STATUS_30                        21:21
1025#define GPIO_INTERRUPT_STATUS_30_INACTIVE               0
1026#define GPIO_INTERRUPT_STATUS_30_ACTIVE                 1
1027#define GPIO_INTERRUPT_STATUS_30_RESET                  1
1028#define GPIO_INTERRUPT_STATUS_29                        20:20
1029#define GPIO_INTERRUPT_STATUS_29_INACTIVE               0
1030#define GPIO_INTERRUPT_STATUS_29_ACTIVE                 1
1031#define GPIO_INTERRUPT_STATUS_29_RESET                  1
1032#define GPIO_INTERRUPT_STATUS_28                        19:19
1033#define GPIO_INTERRUPT_STATUS_28_INACTIVE               0
1034#define GPIO_INTERRUPT_STATUS_28_ACTIVE                 1
1035#define GPIO_INTERRUPT_STATUS_28_RESET                  1
1036#define GPIO_INTERRUPT_STATUS_27                        18:18
1037#define GPIO_INTERRUPT_STATUS_27_INACTIVE               0
1038#define GPIO_INTERRUPT_STATUS_27_ACTIVE                 1
1039#define GPIO_INTERRUPT_STATUS_27_RESET                  1
1040#define GPIO_INTERRUPT_STATUS_26                        17:17
1041#define GPIO_INTERRUPT_STATUS_26_INACTIVE               0
1042#define GPIO_INTERRUPT_STATUS_26_ACTIVE                 1
1043#define GPIO_INTERRUPT_STATUS_26_RESET                  1
1044#define GPIO_INTERRUPT_STATUS_25                        16:16
1045#define GPIO_INTERRUPT_STATUS_25_INACTIVE               0
1046#define GPIO_INTERRUPT_STATUS_25_ACTIVE                 1
1047#define GPIO_INTERRUPT_STATUS_25_RESET                  1
1048
1049
1050#define PANEL_DISPLAY_CTRL                            0x080000
1051#define PANEL_DISPLAY_CTRL_RESERVED_1_MASK            31:30
1052#define PANEL_DISPLAY_CTRL_RESERVED_1_MASK_DISABLE    0
1053#define PANEL_DISPLAY_CTRL_RESERVED_1_MASK_ENABLE     3
1054#define PANEL_DISPLAY_CTRL_SELECT                     29:28
1055#define PANEL_DISPLAY_CTRL_SELECT_PANEL               0
1056#define PANEL_DISPLAY_CTRL_SELECT_VGA                 1
1057#define PANEL_DISPLAY_CTRL_SELECT_CRT                 2
1058#define PANEL_DISPLAY_CTRL_FPEN                       27:27
1059#define PANEL_DISPLAY_CTRL_FPEN_LOW                   0
1060#define PANEL_DISPLAY_CTRL_FPEN_HIGH                  1
1061#define PANEL_DISPLAY_CTRL_VBIASEN                    26:26
1062#define PANEL_DISPLAY_CTRL_VBIASEN_LOW                0
1063#define PANEL_DISPLAY_CTRL_VBIASEN_HIGH               1
1064#define PANEL_DISPLAY_CTRL_DATA                       25:25
1065#define PANEL_DISPLAY_CTRL_DATA_DISABLE               0
1066#define PANEL_DISPLAY_CTRL_DATA_ENABLE                1
1067#define PANEL_DISPLAY_CTRL_FPVDDEN                    24:24
1068#define PANEL_DISPLAY_CTRL_FPVDDEN_LOW                0
1069#define PANEL_DISPLAY_CTRL_FPVDDEN_HIGH               1
1070#define PANEL_DISPLAY_CTRL_RESERVED_2_MASK            23:20
1071#define PANEL_DISPLAY_CTRL_RESERVED_2_MASK_DISABLE    0
1072#define PANEL_DISPLAY_CTRL_RESERVED_2_MASK_ENABLE     15
1073
1074#define PANEL_DISPLAY_CTRL_TFT_DISP 19:18
1075#define PANEL_DISPLAY_CTRL_TFT_DISP_24 0
1076#define PANEL_DISPLAY_CTRL_TFT_DISP_36 1
1077#define PANEL_DISPLAY_CTRL_TFT_DISP_18 2
1078
1079
1080#define PANEL_DISPLAY_CTRL_DUAL_DISPLAY               19:19
1081#define PANEL_DISPLAY_CTRL_DUAL_DISPLAY_DISABLE       0
1082#define PANEL_DISPLAY_CTRL_DUAL_DISPLAY_ENABLE        1
1083#define PANEL_DISPLAY_CTRL_DOUBLE_PIXEL               18:18
1084#define PANEL_DISPLAY_CTRL_DOUBLE_PIXEL_DISABLE       0
1085#define PANEL_DISPLAY_CTRL_DOUBLE_PIXEL_ENABLE        1
1086#define PANEL_DISPLAY_CTRL_FIFO                       17:16
1087#define PANEL_DISPLAY_CTRL_FIFO_1                     0
1088#define PANEL_DISPLAY_CTRL_FIFO_3                     1
1089#define PANEL_DISPLAY_CTRL_FIFO_7                     2
1090#define PANEL_DISPLAY_CTRL_FIFO_11                    3
1091#define PANEL_DISPLAY_CTRL_RESERVED_3_MASK            15:15
1092#define PANEL_DISPLAY_CTRL_RESERVED_3_MASK_DISABLE    0
1093#define PANEL_DISPLAY_CTRL_RESERVED_3_MASK_ENABLE     1
1094#define PANEL_DISPLAY_CTRL_CLOCK_PHASE                14:14
1095#define PANEL_DISPLAY_CTRL_CLOCK_PHASE_ACTIVE_HIGH    0
1096#define PANEL_DISPLAY_CTRL_CLOCK_PHASE_ACTIVE_LOW     1
1097#define PANEL_DISPLAY_CTRL_VSYNC_PHASE                13:13
1098#define PANEL_DISPLAY_CTRL_VSYNC_PHASE_ACTIVE_HIGH    0
1099#define PANEL_DISPLAY_CTRL_VSYNC_PHASE_ACTIVE_LOW     1
1100#define PANEL_DISPLAY_CTRL_HSYNC_PHASE                12:12
1101#define PANEL_DISPLAY_CTRL_HSYNC_PHASE_ACTIVE_HIGH    0
1102#define PANEL_DISPLAY_CTRL_HSYNC_PHASE_ACTIVE_LOW     1
1103#define PANEL_DISPLAY_CTRL_VSYNC                      11:11
1104#define PANEL_DISPLAY_CTRL_VSYNC_ACTIVE_HIGH          0
1105#define PANEL_DISPLAY_CTRL_VSYNC_ACTIVE_LOW           1
1106#define PANEL_DISPLAY_CTRL_CAPTURE_TIMING             10:10
1107#define PANEL_DISPLAY_CTRL_CAPTURE_TIMING_DISABLE     0
1108#define PANEL_DISPLAY_CTRL_CAPTURE_TIMING_ENABLE      1
1109#define PANEL_DISPLAY_CTRL_COLOR_KEY                  9:9
1110#define PANEL_DISPLAY_CTRL_COLOR_KEY_DISABLE          0
1111#define PANEL_DISPLAY_CTRL_COLOR_KEY_ENABLE           1
1112#define PANEL_DISPLAY_CTRL_TIMING                     8:8
1113#define PANEL_DISPLAY_CTRL_TIMING_DISABLE             0
1114#define PANEL_DISPLAY_CTRL_TIMING_ENABLE              1
1115#define PANEL_DISPLAY_CTRL_VERTICAL_PAN_DIR           7:7
1116#define PANEL_DISPLAY_CTRL_VERTICAL_PAN_DIR_DOWN      0
1117#define PANEL_DISPLAY_CTRL_VERTICAL_PAN_DIR_UP        1
1118#define PANEL_DISPLAY_CTRL_VERTICAL_PAN               6:6
1119#define PANEL_DISPLAY_CTRL_VERTICAL_PAN_DISABLE       0
1120#define PANEL_DISPLAY_CTRL_VERTICAL_PAN_ENABLE        1
1121#define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN_DIR         5:5
1122#define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN_DIR_RIGHT   0
1123#define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN_DIR_LEFT    1
1124#define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN             4:4
1125#define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN_DISABLE     0
1126#define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN_ENABLE      1
1127#define PANEL_DISPLAY_CTRL_GAMMA                      3:3
1128#define PANEL_DISPLAY_CTRL_GAMMA_DISABLE              0
1129#define PANEL_DISPLAY_CTRL_GAMMA_ENABLE               1
1130#define PANEL_DISPLAY_CTRL_PLANE                      2:2
1131#define PANEL_DISPLAY_CTRL_PLANE_DISABLE              0
1132#define PANEL_DISPLAY_CTRL_PLANE_ENABLE               1
1133#define PANEL_DISPLAY_CTRL_FORMAT                     1:0
1134#define PANEL_DISPLAY_CTRL_FORMAT_8                   0
1135#define PANEL_DISPLAY_CTRL_FORMAT_16                  1
1136#define PANEL_DISPLAY_CTRL_FORMAT_32                  2
1137
1138#define PANEL_PAN_CTRL                                0x080004
1139#define PANEL_PAN_CTRL_VERTICAL_PAN                   31:24
1140#define PANEL_PAN_CTRL_VERTICAL_VSYNC                 21:16
1141#define PANEL_PAN_CTRL_HORIZONTAL_PAN                 15:8
1142#define PANEL_PAN_CTRL_HORIZONTAL_VSYNC               5:0
1143
1144#define PANEL_COLOR_KEY                               0x080008
1145#define PANEL_COLOR_KEY_MASK                          31:16
1146#define PANEL_COLOR_KEY_VALUE                         15:0
1147
1148#define PANEL_FB_ADDRESS                              0x08000C
1149#define PANEL_FB_ADDRESS_STATUS                       31:31
1150#define PANEL_FB_ADDRESS_STATUS_CURRENT               0
1151#define PANEL_FB_ADDRESS_STATUS_PENDING               1
1152#define PANEL_FB_ADDRESS_EXT                          27:27
1153#define PANEL_FB_ADDRESS_EXT_LOCAL                    0
1154#define PANEL_FB_ADDRESS_EXT_EXTERNAL                 1
1155#define PANEL_FB_ADDRESS_ADDRESS                      25:0
1156
1157#define PANEL_FB_WIDTH                                0x080010
1158#define PANEL_FB_WIDTH_WIDTH                          29:16
1159#define PANEL_FB_WIDTH_OFFSET                         13:0
1160
1161#define PANEL_WINDOW_WIDTH                            0x080014
1162#define PANEL_WINDOW_WIDTH_WIDTH                      27:16
1163#define PANEL_WINDOW_WIDTH_X                          11:0
1164
1165#define PANEL_WINDOW_HEIGHT                           0x080018
1166#define PANEL_WINDOW_HEIGHT_HEIGHT                    27:16
1167#define PANEL_WINDOW_HEIGHT_Y                         11:0
1168
1169#define PANEL_PLANE_TL                                0x08001C
1170#define PANEL_PLANE_TL_TOP                            26:16
1171#define PANEL_PLANE_TL_LEFT                           10:0
1172
1173#define PANEL_PLANE_BR                                0x080020
1174#define PANEL_PLANE_BR_BOTTOM                         26:16
1175#define PANEL_PLANE_BR_RIGHT                          10:0
1176
1177#define PANEL_HORIZONTAL_TOTAL                        0x080024
1178#define PANEL_HORIZONTAL_TOTAL_TOTAL                  27:16
1179#define PANEL_HORIZONTAL_TOTAL_DISPLAY_END            11:0
1180
1181#define PANEL_HORIZONTAL_SYNC                         0x080028
1182#define PANEL_HORIZONTAL_SYNC_WIDTH                   23:16
1183#define PANEL_HORIZONTAL_SYNC_START                   11:0
1184
1185#define PANEL_VERTICAL_TOTAL                          0x08002C
1186#define PANEL_VERTICAL_TOTAL_TOTAL                    26:16
1187#define PANEL_VERTICAL_TOTAL_DISPLAY_END              10:0
1188
1189#define PANEL_VERTICAL_SYNC                           0x080030
1190#define PANEL_VERTICAL_SYNC_HEIGHT                    21:16
1191#define PANEL_VERTICAL_SYNC_START                     10:0
1192
1193#define PANEL_CURRENT_LINE                            0x080034
1194#define PANEL_CURRENT_LINE_LINE                       10:0
1195
1196/* Video Control */
1197
1198#define VIDEO_DISPLAY_CTRL                              0x080040
1199#define VIDEO_DISPLAY_CTRL_LINE_BUFFER                  18:18
1200#define VIDEO_DISPLAY_CTRL_LINE_BUFFER_DISABLE          0
1201#define VIDEO_DISPLAY_CTRL_LINE_BUFFER_ENABLE           1
1202#define VIDEO_DISPLAY_CTRL_FIFO                         17:16
1203#define VIDEO_DISPLAY_CTRL_FIFO_1                       0
1204#define VIDEO_DISPLAY_CTRL_FIFO_3                       1
1205#define VIDEO_DISPLAY_CTRL_FIFO_7                       2
1206#define VIDEO_DISPLAY_CTRL_FIFO_11                      3
1207#define VIDEO_DISPLAY_CTRL_BUFFER                       15:15
1208#define VIDEO_DISPLAY_CTRL_BUFFER_0                     0
1209#define VIDEO_DISPLAY_CTRL_BUFFER_1                     1
1210#define VIDEO_DISPLAY_CTRL_CAPTURE                      14:14
1211#define VIDEO_DISPLAY_CTRL_CAPTURE_DISABLE              0
1212#define VIDEO_DISPLAY_CTRL_CAPTURE_ENABLE               1
1213#define VIDEO_DISPLAY_CTRL_DOUBLE_BUFFER                13:13
1214#define VIDEO_DISPLAY_CTRL_DOUBLE_BUFFER_DISABLE        0
1215#define VIDEO_DISPLAY_CTRL_DOUBLE_BUFFER_ENABLE         1
1216#define VIDEO_DISPLAY_CTRL_BYTE_SWAP                    12:12
1217#define VIDEO_DISPLAY_CTRL_BYTE_SWAP_DISABLE            0
1218#define VIDEO_DISPLAY_CTRL_BYTE_SWAP_ENABLE             1
1219#define VIDEO_DISPLAY_CTRL_VERTICAL_SCALE               11:11
1220#define VIDEO_DISPLAY_CTRL_VERTICAL_SCALE_NORMAL        0
1221#define VIDEO_DISPLAY_CTRL_VERTICAL_SCALE_HALF          1
1222#define VIDEO_DISPLAY_CTRL_HORIZONTAL_SCALE             10:10
1223#define VIDEO_DISPLAY_CTRL_HORIZONTAL_SCALE_NORMAL      0
1224#define VIDEO_DISPLAY_CTRL_HORIZONTAL_SCALE_HALF        1
1225#define VIDEO_DISPLAY_CTRL_VERTICAL_MODE                9:9
1226#define VIDEO_DISPLAY_CTRL_VERTICAL_MODE_REPLICATE      0
1227#define VIDEO_DISPLAY_CTRL_VERTICAL_MODE_INTERPOLATE    1
1228#define VIDEO_DISPLAY_CTRL_HORIZONTAL_MODE              8:8
1229#define VIDEO_DISPLAY_CTRL_HORIZONTAL_MODE_REPLICATE    0
1230#define VIDEO_DISPLAY_CTRL_HORIZONTAL_MODE_INTERPOLATE  1
1231#define VIDEO_DISPLAY_CTRL_PIXEL                        7:4
1232#define VIDEO_DISPLAY_CTRL_GAMMA                        3:3
1233#define VIDEO_DISPLAY_CTRL_GAMMA_DISABLE                0
1234#define VIDEO_DISPLAY_CTRL_GAMMA_ENABLE                 1
1235#define VIDEO_DISPLAY_CTRL_PLANE                        2:2
1236#define VIDEO_DISPLAY_CTRL_PLANE_DISABLE                0
1237#define VIDEO_DISPLAY_CTRL_PLANE_ENABLE                 1
1238#define VIDEO_DISPLAY_CTRL_FORMAT                       1:0
1239#define VIDEO_DISPLAY_CTRL_FORMAT_8                     0
1240#define VIDEO_DISPLAY_CTRL_FORMAT_16                    1
1241#define VIDEO_DISPLAY_CTRL_FORMAT_32                    2
1242#define VIDEO_DISPLAY_CTRL_FORMAT_YUV                   3
1243
1244#define VIDEO_FB_0_ADDRESS                            0x080044
1245#define VIDEO_FB_0_ADDRESS_STATUS                     31:31
1246#define VIDEO_FB_0_ADDRESS_STATUS_CURRENT             0
1247#define VIDEO_FB_0_ADDRESS_STATUS_PENDING             1
1248#define VIDEO_FB_0_ADDRESS_EXT                        27:27
1249#define VIDEO_FB_0_ADDRESS_EXT_LOCAL                  0
1250#define VIDEO_FB_0_ADDRESS_EXT_EXTERNAL               1
1251#define VIDEO_FB_0_ADDRESS_ADDRESS                    25:0
1252
1253#define VIDEO_FB_WIDTH                                0x080048
1254#define VIDEO_FB_WIDTH_WIDTH                          29:16
1255#define VIDEO_FB_WIDTH_OFFSET                         13:0
1256
1257#define VIDEO_FB_0_LAST_ADDRESS                       0x08004C
1258#define VIDEO_FB_0_LAST_ADDRESS_EXT                   27:27
1259#define VIDEO_FB_0_LAST_ADDRESS_EXT_LOCAL             0
1260#define VIDEO_FB_0_LAST_ADDRESS_EXT_EXTERNAL          1
1261#define VIDEO_FB_0_LAST_ADDRESS_ADDRESS               25:0
1262
1263#define VIDEO_PLANE_TL                                0x080050
1264#define VIDEO_PLANE_TL_TOP                            26:16
1265#define VIDEO_PLANE_TL_LEFT                           10:0
1266
1267#define VIDEO_PLANE_BR                                0x080054
1268#define VIDEO_PLANE_BR_BOTTOM                         26:16
1269#define VIDEO_PLANE_BR_RIGHT                          10:0
1270
1271#define VIDEO_SCALE                                   0x080058
1272#define VIDEO_SCALE_VERTICAL_MODE                     31:31
1273#define VIDEO_SCALE_VERTICAL_MODE_EXPAND              0
1274#define VIDEO_SCALE_VERTICAL_MODE_SHRINK              1
1275#define VIDEO_SCALE_VERTICAL_SCALE                    27:16
1276#define VIDEO_SCALE_HORIZONTAL_MODE                   15:15
1277#define VIDEO_SCALE_HORIZONTAL_MODE_EXPAND            0
1278#define VIDEO_SCALE_HORIZONTAL_MODE_SHRINK            1
1279#define VIDEO_SCALE_HORIZONTAL_SCALE                  11:0
1280
1281#define VIDEO_INITIAL_SCALE                           0x08005C
1282#define VIDEO_INITIAL_SCALE_FB_1                      27:16
1283#define VIDEO_INITIAL_SCALE_FB_0                      11:0
1284
1285#define VIDEO_YUV_CONSTANTS                           0x080060
1286#define VIDEO_YUV_CONSTANTS_Y                         31:24
1287#define VIDEO_YUV_CONSTANTS_R                         23:16
1288#define VIDEO_YUV_CONSTANTS_G                         15:8
1289#define VIDEO_YUV_CONSTANTS_B                         7:0
1290
1291#define VIDEO_FB_1_ADDRESS                            0x080064
1292#define VIDEO_FB_1_ADDRESS_STATUS                     31:31
1293#define VIDEO_FB_1_ADDRESS_STATUS_CURRENT             0
1294#define VIDEO_FB_1_ADDRESS_STATUS_PENDING             1
1295#define VIDEO_FB_1_ADDRESS_EXT                        27:27
1296#define VIDEO_FB_1_ADDRESS_EXT_LOCAL                  0
1297#define VIDEO_FB_1_ADDRESS_EXT_EXTERNAL               1
1298#define VIDEO_FB_1_ADDRESS_ADDRESS                    25:0
1299
1300#define VIDEO_FB_1_LAST_ADDRESS                       0x080068
1301#define VIDEO_FB_1_LAST_ADDRESS_EXT                   27:27
1302#define VIDEO_FB_1_LAST_ADDRESS_EXT_LOCAL             0
1303#define VIDEO_FB_1_LAST_ADDRESS_EXT_EXTERNAL          1
1304#define VIDEO_FB_1_LAST_ADDRESS_ADDRESS               25:0
1305
1306/* Video Alpha Control */
1307
1308#define VIDEO_ALPHA_DISPLAY_CTRL                        0x080080
1309#define VIDEO_ALPHA_DISPLAY_CTRL_SELECT                 28:28
1310#define VIDEO_ALPHA_DISPLAY_CTRL_SELECT_PER_PIXEL       0
1311#define VIDEO_ALPHA_DISPLAY_CTRL_SELECT_ALPHA           1
1312#define VIDEO_ALPHA_DISPLAY_CTRL_ALPHA                  27:24
1313#define VIDEO_ALPHA_DISPLAY_CTRL_FIFO                   17:16
1314#define VIDEO_ALPHA_DISPLAY_CTRL_FIFO_1                 0
1315#define VIDEO_ALPHA_DISPLAY_CTRL_FIFO_3                 1
1316#define VIDEO_ALPHA_DISPLAY_CTRL_FIFO_7                 2
1317#define VIDEO_ALPHA_DISPLAY_CTRL_FIFO_11                3
1318#define VIDEO_ALPHA_DISPLAY_CTRL_VERT_SCALE             11:11
1319#define VIDEO_ALPHA_DISPLAY_CTRL_VERT_SCALE_NORMAL      0
1320#define VIDEO_ALPHA_DISPLAY_CTRL_VERT_SCALE_HALF        1
1321#define VIDEO_ALPHA_DISPLAY_CTRL_HORZ_SCALE             10:10
1322#define VIDEO_ALPHA_DISPLAY_CTRL_HORZ_SCALE_NORMAL      0
1323#define VIDEO_ALPHA_DISPLAY_CTRL_HORZ_SCALE_HALF        1
1324#define VIDEO_ALPHA_DISPLAY_CTRL_VERT_MODE              9:9
1325#define VIDEO_ALPHA_DISPLAY_CTRL_VERT_MODE_REPLICATE    0
1326#define VIDEO_ALPHA_DISPLAY_CTRL_VERT_MODE_INTERPOLATE  1
1327#define VIDEO_ALPHA_DISPLAY_CTRL_HORZ_MODE              8:8
1328#define VIDEO_ALPHA_DISPLAY_CTRL_HORZ_MODE_REPLICATE    0
1329#define VIDEO_ALPHA_DISPLAY_CTRL_HORZ_MODE_INTERPOLATE  1
1330#define VIDEO_ALPHA_DISPLAY_CTRL_PIXEL                  7:4
1331#define VIDEO_ALPHA_DISPLAY_CTRL_CHROMA_KEY             3:3
1332#define VIDEO_ALPHA_DISPLAY_CTRL_CHROMA_KEY_DISABLE     0
1333#define VIDEO_ALPHA_DISPLAY_CTRL_CHROMA_KEY_ENABLE      1
1334#define VIDEO_ALPHA_DISPLAY_CTRL_PLANE                  2:2
1335#define VIDEO_ALPHA_DISPLAY_CTRL_PLANE_DISABLE          0
1336#define VIDEO_ALPHA_DISPLAY_CTRL_PLANE_ENABLE           1
1337#define VIDEO_ALPHA_DISPLAY_CTRL_FORMAT                 1:0
1338#define VIDEO_ALPHA_DISPLAY_CTRL_FORMAT_8               0
1339#define VIDEO_ALPHA_DISPLAY_CTRL_FORMAT_16              1
1340#define VIDEO_ALPHA_DISPLAY_CTRL_FORMAT_ALPHA_4_4       2
1341#define VIDEO_ALPHA_DISPLAY_CTRL_FORMAT_ALPHA_4_4_4_4   3
1342
1343#define VIDEO_ALPHA_FB_ADDRESS                        0x080084
1344#define VIDEO_ALPHA_FB_ADDRESS_STATUS                 31:31
1345#define VIDEO_ALPHA_FB_ADDRESS_STATUS_CURRENT         0
1346#define VIDEO_ALPHA_FB_ADDRESS_STATUS_PENDING         1
1347#define VIDEO_ALPHA_FB_ADDRESS_EXT                    27:27
1348#define VIDEO_ALPHA_FB_ADDRESS_EXT_LOCAL              0
1349#define VIDEO_ALPHA_FB_ADDRESS_EXT_EXTERNAL           1
1350#define VIDEO_ALPHA_FB_ADDRESS_ADDRESS                25:0
1351
1352#define VIDEO_ALPHA_FB_WIDTH                          0x080088
1353#define VIDEO_ALPHA_FB_WIDTH_WIDTH                    29:16
1354#define VIDEO_ALPHA_FB_WIDTH_OFFSET                   13:0
1355
1356#define VIDEO_ALPHA_FB_LAST_ADDRESS                   0x08008C
1357#define VIDEO_ALPHA_FB_LAST_ADDRESS_EXT               27:27
1358#define VIDEO_ALPHA_FB_LAST_ADDRESS_EXT_LOCAL         0
1359#define VIDEO_ALPHA_FB_LAST_ADDRESS_EXT_EXTERNAL      1
1360#define VIDEO_ALPHA_FB_LAST_ADDRESS_ADDRESS           25:0
1361
1362#define VIDEO_ALPHA_PLANE_TL                          0x080090
1363#define VIDEO_ALPHA_PLANE_TL_TOP                      26:16
1364#define VIDEO_ALPHA_PLANE_TL_LEFT                     10:0
1365
1366#define VIDEO_ALPHA_PLANE_BR                          0x080094
1367#define VIDEO_ALPHA_PLANE_BR_BOTTOM                   26:16
1368#define VIDEO_ALPHA_PLANE_BR_RIGHT                    10:0
1369
1370#define VIDEO_ALPHA_SCALE                             0x080098
1371#define VIDEO_ALPHA_SCALE_VERTICAL_MODE               31:31
1372#define VIDEO_ALPHA_SCALE_VERTICAL_MODE_EXPAND        0
1373#define VIDEO_ALPHA_SCALE_VERTICAL_MODE_SHRINK        1
1374#define VIDEO_ALPHA_SCALE_VERTICAL_SCALE              27:16
1375#define VIDEO_ALPHA_SCALE_HORIZONTAL_MODE             15:15
1376#define VIDEO_ALPHA_SCALE_HORIZONTAL_MODE_EXPAND      0
1377#define VIDEO_ALPHA_SCALE_HORIZONTAL_MODE_SHRINK      1
1378#define VIDEO_ALPHA_SCALE_HORIZONTAL_SCALE            11:0
1379
1380#define VIDEO_ALPHA_INITIAL_SCALE                     0x08009C
1381#define VIDEO_ALPHA_INITIAL_SCALE_VERTICAL            27:16
1382#define VIDEO_ALPHA_INITIAL_SCALE_HORIZONTAL          11:0
1383
1384#define VIDEO_ALPHA_CHROMA_KEY                        0x0800A0
1385#define VIDEO_ALPHA_CHROMA_KEY_MASK                   31:16
1386#define VIDEO_ALPHA_CHROMA_KEY_VALUE                  15:0
1387
1388#define VIDEO_ALPHA_COLOR_LOOKUP_01                   0x0800A4
1389#define VIDEO_ALPHA_COLOR_LOOKUP_01_1                 31:16
1390#define VIDEO_ALPHA_COLOR_LOOKUP_01_1_RED             31:27
1391#define VIDEO_ALPHA_COLOR_LOOKUP_01_1_GREEN           26:21
1392#define VIDEO_ALPHA_COLOR_LOOKUP_01_1_BLUE            20:16
1393#define VIDEO_ALPHA_COLOR_LOOKUP_01_0                 15:0
1394#define VIDEO_ALPHA_COLOR_LOOKUP_01_0_RED             15:11
1395#define VIDEO_ALPHA_COLOR_LOOKUP_01_0_GREEN           10:5
1396#define VIDEO_ALPHA_COLOR_LOOKUP_01_0_BLUE            4:0
1397
1398#define VIDEO_ALPHA_COLOR_LOOKUP_23                   0x0800A8
1399#define VIDEO_ALPHA_COLOR_LOOKUP_23_3                 31:16
1400#define VIDEO_ALPHA_COLOR_LOOKUP_23_3_RED             31:27
1401#define VIDEO_ALPHA_COLOR_LOOKUP_23_3_GREEN           26:21
1402#define VIDEO_ALPHA_COLOR_LOOKUP_23_3_BLUE            20:16
1403#define VIDEO_ALPHA_COLOR_LOOKUP_23_2                 15:0
1404#define VIDEO_ALPHA_COLOR_LOOKUP_23_2_RED             15:11
1405#define VIDEO_ALPHA_COLOR_LOOKUP_23_2_GREEN           10:5
1406#define VIDEO_ALPHA_COLOR_LOOKUP_23_2_BLUE            4:0
1407
1408#define VIDEO_ALPHA_COLOR_LOOKUP_45                   0x0800AC
1409#define VIDEO_ALPHA_COLOR_LOOKUP_45_5                 31:16
1410#define VIDEO_ALPHA_COLOR_LOOKUP_45_5_RED             31:27
1411#define VIDEO_ALPHA_COLOR_LOOKUP_45_5_GREEN           26:21
1412#define VIDEO_ALPHA_COLOR_LOOKUP_45_5_BLUE            20:16
1413#define VIDEO_ALPHA_COLOR_LOOKUP_45_4                 15:0
1414#define VIDEO_ALPHA_COLOR_LOOKUP_45_4_RED             15:11
1415#define VIDEO_ALPHA_COLOR_LOOKUP_45_4_GREEN           10:5
1416#define VIDEO_ALPHA_COLOR_LOOKUP_45_4_BLUE            4:0
1417
1418#define VIDEO_ALPHA_COLOR_LOOKUP_67                   0x0800B0
1419#define VIDEO_ALPHA_COLOR_LOOKUP_67_7                 31:16
1420#define VIDEO_ALPHA_COLOR_LOOKUP_67_7_RED             31:27
1421#define VIDEO_ALPHA_COLOR_LOOKUP_67_7_GREEN           26:21
1422#define VIDEO_ALPHA_COLOR_LOOKUP_67_7_BLUE            20:16
1423#define VIDEO_ALPHA_COLOR_LOOKUP_67_6                 15:0
1424#define VIDEO_ALPHA_COLOR_LOOKUP_67_6_RED             15:11
1425#define VIDEO_ALPHA_COLOR_LOOKUP_67_6_GREEN           10:5
1426#define VIDEO_ALPHA_COLOR_LOOKUP_67_6_BLUE            4:0
1427
1428#define VIDEO_ALPHA_COLOR_LOOKUP_89                   0x0800B4
1429#define VIDEO_ALPHA_COLOR_LOOKUP_89_9                 31:16
1430#define VIDEO_ALPHA_COLOR_LOOKUP_89_9_RED             31:27
1431#define VIDEO_ALPHA_COLOR_LOOKUP_89_9_GREEN           26:21
1432#define VIDEO_ALPHA_COLOR_LOOKUP_89_9_BLUE            20:16
1433#define VIDEO_ALPHA_COLOR_LOOKUP_89_8                 15:0
1434#define VIDEO_ALPHA_COLOR_LOOKUP_89_8_RED             15:11
1435#define VIDEO_ALPHA_COLOR_LOOKUP_89_8_GREEN           10:5
1436#define VIDEO_ALPHA_COLOR_LOOKUP_89_8_BLUE            4:0
1437
1438#define VIDEO_ALPHA_COLOR_LOOKUP_AB                   0x0800B8
1439#define VIDEO_ALPHA_COLOR_LOOKUP_AB_B                 31:16
1440#define VIDEO_ALPHA_COLOR_LOOKUP_AB_B_RED             31:27
1441#define VIDEO_ALPHA_COLOR_LOOKUP_AB_B_GREEN           26:21
1442#define VIDEO_ALPHA_COLOR_LOOKUP_AB_B_BLUE            20:16
1443#define VIDEO_ALPHA_COLOR_LOOKUP_AB_A                 15:0
1444#define VIDEO_ALPHA_COLOR_LOOKUP_AB_A_RED             15:11
1445#define VIDEO_ALPHA_COLOR_LOOKUP_AB_A_GREEN           10:5
1446#define VIDEO_ALPHA_COLOR_LOOKUP_AB_A_BLUE            4:0
1447
1448#define VIDEO_ALPHA_COLOR_LOOKUP_CD                   0x0800BC
1449#define VIDEO_ALPHA_COLOR_LOOKUP_CD_D                 31:16
1450#define VIDEO_ALPHA_COLOR_LOOKUP_CD_D_RED             31:27
1451#define VIDEO_ALPHA_COLOR_LOOKUP_CD_D_GREEN           26:21
1452#define VIDEO_ALPHA_COLOR_LOOKUP_CD_D_BLUE            20:16
1453#define VIDEO_ALPHA_COLOR_LOOKUP_CD_C                 15:0
1454#define VIDEO_ALPHA_COLOR_LOOKUP_CD_C_RED             15:11
1455#define VIDEO_ALPHA_COLOR_LOOKUP_CD_C_GREEN           10:5
1456#define VIDEO_ALPHA_COLOR_LOOKUP_CD_C_BLUE            4:0
1457
1458#define VIDEO_ALPHA_COLOR_LOOKUP_EF                   0x0800C0
1459#define VIDEO_ALPHA_COLOR_LOOKUP_EF_F                 31:16
1460#define VIDEO_ALPHA_COLOR_LOOKUP_EF_F_RED             31:27
1461#define VIDEO_ALPHA_COLOR_LOOKUP_EF_F_GREEN           26:21
1462#define VIDEO_ALPHA_COLOR_LOOKUP_EF_F_BLUE            20:16
1463#define VIDEO_ALPHA_COLOR_LOOKUP_EF_E                 15:0
1464#define VIDEO_ALPHA_COLOR_LOOKUP_EF_E_RED             15:11
1465#define VIDEO_ALPHA_COLOR_LOOKUP_EF_E_GREEN           10:5
1466#define VIDEO_ALPHA_COLOR_LOOKUP_EF_E_BLUE            4:0
1467
1468/* Panel Cursor Control */
1469
1470#define PANEL_HWC_ADDRESS                             0x0800F0
1471#define PANEL_HWC_ADDRESS_ENABLE                      31:31
1472#define PANEL_HWC_ADDRESS_ENABLE_DISABLE              0
1473#define PANEL_HWC_ADDRESS_ENABLE_ENABLE               1
1474#define PANEL_HWC_ADDRESS_EXT                         27:27
1475#define PANEL_HWC_ADDRESS_EXT_LOCAL                   0
1476#define PANEL_HWC_ADDRESS_EXT_EXTERNAL                1
1477#define PANEL_HWC_ADDRESS_ADDRESS                     25:0
1478
1479#define PANEL_HWC_LOCATION                            0x0800F4
1480#define PANEL_HWC_LOCATION_TOP                        27:27
1481#define PANEL_HWC_LOCATION_TOP_INSIDE                 0
1482#define PANEL_HWC_LOCATION_TOP_OUTSIDE                1
1483#define PANEL_HWC_LOCATION_Y                          26:16
1484#define PANEL_HWC_LOCATION_LEFT                       11:11
1485#define PANEL_HWC_LOCATION_LEFT_INSIDE                0
1486#define PANEL_HWC_LOCATION_LEFT_OUTSIDE               1
1487#define PANEL_HWC_LOCATION_X                          10:0
1488
1489#define PANEL_HWC_COLOR_12                            0x0800F8
1490#define PANEL_HWC_COLOR_12_2_RGB565                   31:16
1491#define PANEL_HWC_COLOR_12_1_RGB565                   15:0
1492
1493#define PANEL_HWC_COLOR_3                             0x0800FC
1494#define PANEL_HWC_COLOR_3_RGB565                      15:0
1495
1496/* Old Definitions +++ */
1497#define PANEL_HWC_COLOR_01                            0x0800F8
1498#define PANEL_HWC_COLOR_01_1_RED                      31:27
1499#define PANEL_HWC_COLOR_01_1_GREEN                    26:21
1500#define PANEL_HWC_COLOR_01_1_BLUE                     20:16
1501#define PANEL_HWC_COLOR_01_0_RED                      15:11
1502#define PANEL_HWC_COLOR_01_0_GREEN                    10:5
1503#define PANEL_HWC_COLOR_01_0_BLUE                     4:0
1504
1505#define PANEL_HWC_COLOR_2                             0x0800FC
1506#define PANEL_HWC_COLOR_2_RED                         15:11
1507#define PANEL_HWC_COLOR_2_GREEN                       10:5
1508#define PANEL_HWC_COLOR_2_BLUE                        4:0
1509/* Old Definitions --- */
1510
1511/* Alpha Control */
1512
1513#define ALPHA_DISPLAY_CTRL                            0x080100
1514#define ALPHA_DISPLAY_CTRL_SELECT                     28:28
1515#define ALPHA_DISPLAY_CTRL_SELECT_PER_PIXEL           0
1516#define ALPHA_DISPLAY_CTRL_SELECT_ALPHA               1
1517#define ALPHA_DISPLAY_CTRL_ALPHA                      27:24
1518#define ALPHA_DISPLAY_CTRL_FIFO                       17:16
1519#define ALPHA_DISPLAY_CTRL_FIFO_1                     0
1520#define ALPHA_DISPLAY_CTRL_FIFO_3                     1
1521#define ALPHA_DISPLAY_CTRL_FIFO_7                     2
1522#define ALPHA_DISPLAY_CTRL_FIFO_11                    3
1523#define ALPHA_DISPLAY_CTRL_PIXEL                      7:4
1524#define ALPHA_DISPLAY_CTRL_CHROMA_KEY                 3:3
1525#define ALPHA_DISPLAY_CTRL_CHROMA_KEY_DISABLE         0
1526#define ALPHA_DISPLAY_CTRL_CHROMA_KEY_ENABLE          1
1527#define ALPHA_DISPLAY_CTRL_PLANE                      2:2
1528#define ALPHA_DISPLAY_CTRL_PLANE_DISABLE              0
1529#define ALPHA_DISPLAY_CTRL_PLANE_ENABLE               1
1530#define ALPHA_DISPLAY_CTRL_FORMAT                     1:0
1531#define ALPHA_DISPLAY_CTRL_FORMAT_16                  1
1532#define ALPHA_DISPLAY_CTRL_FORMAT_ALPHA_4_4           2
1533#define ALPHA_DISPLAY_CTRL_FORMAT_ALPHA_4_4_4_4       3
1534
1535#define ALPHA_FB_ADDRESS                              0x080104
1536#define ALPHA_FB_ADDRESS_STATUS                       31:31
1537#define ALPHA_FB_ADDRESS_STATUS_CURRENT               0
1538#define ALPHA_FB_ADDRESS_STATUS_PENDING               1
1539#define ALPHA_FB_ADDRESS_EXT                          27:27
1540#define ALPHA_FB_ADDRESS_EXT_LOCAL                    0
1541#define ALPHA_FB_ADDRESS_EXT_EXTERNAL                 1
1542#define ALPHA_FB_ADDRESS_ADDRESS                      25:0
1543
1544#define ALPHA_FB_WIDTH                                0x080108
1545#define ALPHA_FB_WIDTH_WIDTH                          29:16
1546#define ALPHA_FB_WIDTH_OFFSET                         13:0
1547
1548#define ALPHA_PLANE_TL                                0x08010C
1549#define ALPHA_PLANE_TL_TOP                            26:16
1550#define ALPHA_PLANE_TL_LEFT                           10:0
1551
1552#define ALPHA_PLANE_BR                                0x080110
1553#define ALPHA_PLANE_BR_BOTTOM                         26:16
1554#define ALPHA_PLANE_BR_RIGHT                          10:0
1555
1556#define ALPHA_CHROMA_KEY                              0x080114
1557#define ALPHA_CHROMA_KEY_MASK                         31:16
1558#define ALPHA_CHROMA_KEY_VALUE                        15:0
1559
1560#define ALPHA_COLOR_LOOKUP_01                         0x080118
1561#define ALPHA_COLOR_LOOKUP_01_1                       31:16
1562#define ALPHA_COLOR_LOOKUP_01_1_RED                   31:27
1563#define ALPHA_COLOR_LOOKUP_01_1_GREEN                 26:21
1564#define ALPHA_COLOR_LOOKUP_01_1_BLUE                  20:16
1565#define ALPHA_COLOR_LOOKUP_01_0                       15:0
1566#define ALPHA_COLOR_LOOKUP_01_0_RED                   15:11
1567#define ALPHA_COLOR_LOOKUP_01_0_GREEN                 10:5
1568#define ALPHA_COLOR_LOOKUP_01_0_BLUE                  4:0
1569
1570#define ALPHA_COLOR_LOOKUP_23                         0x08011C
1571#define ALPHA_COLOR_LOOKUP_23_3                       31:16
1572#define ALPHA_COLOR_LOOKUP_23_3_RED                   31:27
1573#define ALPHA_COLOR_LOOKUP_23_3_GREEN                 26:21
1574#define ALPHA_COLOR_LOOKUP_23_3_BLUE                  20:16
1575#define ALPHA_COLOR_LOOKUP_23_2                       15:0
1576#define ALPHA_COLOR_LOOKUP_23_2_RED                   15:11
1577#define ALPHA_COLOR_LOOKUP_23_2_GREEN                 10:5
1578#define ALPHA_COLOR_LOOKUP_23_2_BLUE                  4:0
1579
1580#define ALPHA_COLOR_LOOKUP_45                         0x080120
1581#define ALPHA_COLOR_LOOKUP_45_5                       31:16
1582#define ALPHA_COLOR_LOOKUP_45_5_RED                   31:27
1583#define ALPHA_COLOR_LOOKUP_45_5_GREEN                 26:21
1584#define ALPHA_COLOR_LOOKUP_45_5_BLUE                  20:16
1585#define ALPHA_COLOR_LOOKUP_45_4                       15:0
1586#define ALPHA_COLOR_LOOKUP_45_4_RED                   15:11
1587#define ALPHA_COLOR_LOOKUP_45_4_GREEN                 10:5
1588#define ALPHA_COLOR_LOOKUP_45_4_BLUE                  4:0
1589
1590#define ALPHA_COLOR_LOOKUP_67                         0x080124
1591#define ALPHA_COLOR_LOOKUP_67_7                       31:16
1592#define ALPHA_COLOR_LOOKUP_67_7_RED                   31:27
1593#define ALPHA_COLOR_LOOKUP_67_7_GREEN                 26:21
1594#define ALPHA_COLOR_LOOKUP_67_7_BLUE                  20:16
1595#define ALPHA_COLOR_LOOKUP_67_6                       15:0
1596#define ALPHA_COLOR_LOOKUP_67_6_RED                   15:11
1597#define ALPHA_COLOR_LOOKUP_67_6_GREEN                 10:5
1598#define ALPHA_COLOR_LOOKUP_67_6_BLUE                  4:0
1599
1600#define ALPHA_COLOR_LOOKUP_89                         0x080128
1601#define ALPHA_COLOR_LOOKUP_89_9                       31:16
1602#define ALPHA_COLOR_LOOKUP_89_9_RED                   31:27
1603#define ALPHA_COLOR_LOOKUP_89_9_GREEN                 26:21
1604#define ALPHA_COLOR_LOOKUP_89_9_BLUE                  20:16
1605#define ALPHA_COLOR_LOOKUP_89_8                       15:0
1606#define ALPHA_COLOR_LOOKUP_89_8_RED                   15:11
1607#define ALPHA_COLOR_LOOKUP_89_8_GREEN                 10:5
1608#define ALPHA_COLOR_LOOKUP_89_8_BLUE                  4:0
1609
1610#define ALPHA_COLOR_LOOKUP_AB                         0x08012C
1611#define ALPHA_COLOR_LOOKUP_AB_B                       31:16
1612#define ALPHA_COLOR_LOOKUP_AB_B_RED                   31:27
1613#define ALPHA_COLOR_LOOKUP_AB_B_GREEN                 26:21
1614#define ALPHA_COLOR_LOOKUP_AB_B_BLUE                  20:16
1615#define ALPHA_COLOR_LOOKUP_AB_A                       15:0
1616#define ALPHA_COLOR_LOOKUP_AB_A_RED                   15:11
1617#define ALPHA_COLOR_LOOKUP_AB_A_GREEN                 10:5
1618#define ALPHA_COLOR_LOOKUP_AB_A_BLUE                  4:0
1619
1620#define ALPHA_COLOR_LOOKUP_CD                         0x080130
1621#define ALPHA_COLOR_LOOKUP_CD_D                       31:16
1622#define ALPHA_COLOR_LOOKUP_CD_D_RED                   31:27
1623#define ALPHA_COLOR_LOOKUP_CD_D_GREEN                 26:21
1624#define ALPHA_COLOR_LOOKUP_CD_D_BLUE                  20:16
1625#define ALPHA_COLOR_LOOKUP_CD_C                       15:0
1626#define ALPHA_COLOR_LOOKUP_CD_C_RED                   15:11
1627#define ALPHA_COLOR_LOOKUP_CD_C_GREEN                 10:5
1628#define ALPHA_COLOR_LOOKUP_CD_C_BLUE                  4:0
1629
1630#define ALPHA_COLOR_LOOKUP_EF                         0x080134
1631#define ALPHA_COLOR_LOOKUP_EF_F                       31:16
1632#define ALPHA_COLOR_LOOKUP_EF_F_RED                   31:27
1633#define ALPHA_COLOR_LOOKUP_EF_F_GREEN                 26:21
1634#define ALPHA_COLOR_LOOKUP_EF_F_BLUE                  20:16
1635#define ALPHA_COLOR_LOOKUP_EF_E                       15:0
1636#define ALPHA_COLOR_LOOKUP_EF_E_RED                   15:11
1637#define ALPHA_COLOR_LOOKUP_EF_E_GREEN                 10:5
1638#define ALPHA_COLOR_LOOKUP_EF_E_BLUE                  4:0
1639
1640/* CRT Graphics Control */
1641
1642#define CRT_DISPLAY_CTRL                              0x080200
1643#define CRT_DISPLAY_CTRL_RESERVED_1_MASK  			  31:27
1644#define CRT_DISPLAY_CTRL_RESERVED_1_MASK_DISABLE  			  0
1645#define CRT_DISPLAY_CTRL_RESERVED_1_MASK_ENABLE 			  0x1F
1646
1647/* SM750LE definition */
1648#define CRT_DISPLAY_CTRL_DPMS                         31:30
1649#define CRT_DISPLAY_CTRL_DPMS_0                       0
1650#define CRT_DISPLAY_CTRL_DPMS_1                       1
1651#define CRT_DISPLAY_CTRL_DPMS_2                       2
1652#define CRT_DISPLAY_CTRL_DPMS_3                       3
1653#define CRT_DISPLAY_CTRL_CLK                          29:27
1654#define CRT_DISPLAY_CTRL_CLK_PLL25                    0
1655#define CRT_DISPLAY_CTRL_CLK_PLL41                    1
1656#define CRT_DISPLAY_CTRL_CLK_PLL62                    2
1657#define CRT_DISPLAY_CTRL_CLK_PLL65                    3
1658#define CRT_DISPLAY_CTRL_CLK_PLL74                    4
1659#define CRT_DISPLAY_CTRL_CLK_PLL80                    5
1660#define CRT_DISPLAY_CTRL_CLK_PLL108                   6
1661#define CRT_DISPLAY_CTRL_CLK_RESERVED                 7
1662#define CRT_DISPLAY_CTRL_SHIFT_VGA_DAC                26:26
1663#define CRT_DISPLAY_CTRL_SHIFT_VGA_DAC_DISABLE        1
1664#define CRT_DISPLAY_CTRL_SHIFT_VGA_DAC_ENABLE         0
1665
1666
1667#define CRT_DISPLAY_CTRL_RESERVED_2_MASK 			  25:24
1668#define CRT_DISPLAY_CTRL_RESERVED_2_MASK_ENABLE 			  3
1669#define CRT_DISPLAY_CTRL_RESERVED_2_MASK_DISABLE 			  0
1670
1671/* SM750LE definition */
1672#define CRT_DISPLAY_CTRL_CRTSELECT                    25:25
1673#define CRT_DISPLAY_CTRL_CRTSELECT_VGA                0
1674#define CRT_DISPLAY_CTRL_CRTSELECT_CRT                1
1675#define CRT_DISPLAY_CTRL_RGBBIT                       24:24
1676#define CRT_DISPLAY_CTRL_RGBBIT_24BIT                 0
1677#define CRT_DISPLAY_CTRL_RGBBIT_12BIT                 1
1678
1679
1680#define CRT_DISPLAY_CTRL_RESERVED_3_MASK 			  15:15
1681#define CRT_DISPLAY_CTRL_RESERVED_3_MASK_DISABLE      0
1682#define CRT_DISPLAY_CTRL_RESERVED_3_MASK_ENABLE       1
1683
1684#define CRT_DISPLAY_CTRL_RESERVED_4_MASK 			  9:9
1685#define CRT_DISPLAY_CTRL_RESERVED_4_MASK_DISABLE      0
1686#define CRT_DISPLAY_CTRL_RESERVED_4_MASK_ENABLE       1
1687
1688#ifndef VALIDATION_CHIP
1689    #define CRT_DISPLAY_CTRL_SHIFT_VGA_DAC            26:26
1690    #define CRT_DISPLAY_CTRL_SHIFT_VGA_DAC_DISABLE    1
1691    #define CRT_DISPLAY_CTRL_SHIFT_VGA_DAC_ENABLE     0
1692    #define CRT_DISPLAY_CTRL_CENTERING                24:24
1693    #define CRT_DISPLAY_CTRL_CENTERING_DISABLE        0
1694    #define CRT_DISPLAY_CTRL_CENTERING_ENABLE         1
1695#endif
1696#define CRT_DISPLAY_CTRL_LOCK_TIMING                  23:23
1697#define CRT_DISPLAY_CTRL_LOCK_TIMING_DISABLE          0
1698#define CRT_DISPLAY_CTRL_LOCK_TIMING_ENABLE           1
1699#define CRT_DISPLAY_CTRL_EXPANSION                    22:22
1700#define CRT_DISPLAY_CTRL_EXPANSION_DISABLE            0
1701#define CRT_DISPLAY_CTRL_EXPANSION_ENABLE             1
1702#define CRT_DISPLAY_CTRL_VERTICAL_MODE                21:21
1703#define CRT_DISPLAY_CTRL_VERTICAL_MODE_REPLICATE      0
1704#define CRT_DISPLAY_CTRL_VERTICAL_MODE_INTERPOLATE    1
1705#define CRT_DISPLAY_CTRL_HORIZONTAL_MODE              20:20
1706#define CRT_DISPLAY_CTRL_HORIZONTAL_MODE_REPLICATE    0
1707#define CRT_DISPLAY_CTRL_HORIZONTAL_MODE_INTERPOLATE  1
1708#define CRT_DISPLAY_CTRL_SELECT                       19:18
1709#define CRT_DISPLAY_CTRL_SELECT_PANEL                 0
1710#define CRT_DISPLAY_CTRL_SELECT_VGA                   1
1711#define CRT_DISPLAY_CTRL_SELECT_CRT                   2
1712#define CRT_DISPLAY_CTRL_FIFO                         17:16
1713#define CRT_DISPLAY_CTRL_FIFO_1                       0
1714#define CRT_DISPLAY_CTRL_FIFO_3                       1
1715#define CRT_DISPLAY_CTRL_FIFO_7                       2
1716#define CRT_DISPLAY_CTRL_FIFO_11                      3
1717#define CRT_DISPLAY_CTRL_CLOCK_PHASE                  14:14
1718#define CRT_DISPLAY_CTRL_CLOCK_PHASE_ACTIVE_HIGH      0
1719#define CRT_DISPLAY_CTRL_CLOCK_PHASE_ACTIVE_LOW       1
1720#define CRT_DISPLAY_CTRL_VSYNC_PHASE                  13:13
1721#define CRT_DISPLAY_CTRL_VSYNC_PHASE_ACTIVE_HIGH      0
1722#define CRT_DISPLAY_CTRL_VSYNC_PHASE_ACTIVE_LOW       1
1723#define CRT_DISPLAY_CTRL_HSYNC_PHASE                  12:12
1724#define CRT_DISPLAY_CTRL_HSYNC_PHASE_ACTIVE_HIGH      0
1725#define CRT_DISPLAY_CTRL_HSYNC_PHASE_ACTIVE_LOW       1
1726#define CRT_DISPLAY_CTRL_BLANK                        10:10
1727#define CRT_DISPLAY_CTRL_BLANK_OFF                    0
1728#define CRT_DISPLAY_CTRL_BLANK_ON                     1
1729#define CRT_DISPLAY_CTRL_TIMING                       8:8
1730#define CRT_DISPLAY_CTRL_TIMING_DISABLE               0
1731#define CRT_DISPLAY_CTRL_TIMING_ENABLE                1
1732#define CRT_DISPLAY_CTRL_PIXEL                        7:4
1733#define CRT_DISPLAY_CTRL_GAMMA                        3:3
1734#define CRT_DISPLAY_CTRL_GAMMA_DISABLE                0
1735#define CRT_DISPLAY_CTRL_GAMMA_ENABLE                 1
1736#define CRT_DISPLAY_CTRL_PLANE                        2:2
1737#define CRT_DISPLAY_CTRL_PLANE_DISABLE                0
1738#define CRT_DISPLAY_CTRL_PLANE_ENABLE                 1
1739#define CRT_DISPLAY_CTRL_FORMAT                       1:0
1740#define CRT_DISPLAY_CTRL_FORMAT_8                     0
1741#define CRT_DISPLAY_CTRL_FORMAT_16                    1
1742#define CRT_DISPLAY_CTRL_FORMAT_32                    2
1743#define CRT_DISPLAY_CTRL_RESERVED_BITS_MASK           0xFF000200
1744
1745#define CRT_FB_ADDRESS                                0x080204
1746#define CRT_FB_ADDRESS_STATUS                         31:31
1747#define CRT_FB_ADDRESS_STATUS_CURRENT                 0
1748#define CRT_FB_ADDRESS_STATUS_PENDING                 1
1749#define CRT_FB_ADDRESS_EXT                            27:27
1750#define CRT_FB_ADDRESS_EXT_LOCAL                      0
1751#define CRT_FB_ADDRESS_EXT_EXTERNAL                   1
1752#define CRT_FB_ADDRESS_ADDRESS                        25:0
1753
1754#define CRT_FB_WIDTH                                  0x080208
1755#define CRT_FB_WIDTH_WIDTH                            29:16
1756#define CRT_FB_WIDTH_OFFSET                           13:0
1757
1758#define CRT_HORIZONTAL_TOTAL                          0x08020C
1759#define CRT_HORIZONTAL_TOTAL_TOTAL                    27:16
1760#define CRT_HORIZONTAL_TOTAL_DISPLAY_END              11:0
1761
1762#define CRT_HORIZONTAL_SYNC                           0x080210
1763#define CRT_HORIZONTAL_SYNC_WIDTH                     23:16
1764#define CRT_HORIZONTAL_SYNC_START                     11:0
1765
1766#define CRT_VERTICAL_TOTAL                            0x080214
1767#define CRT_VERTICAL_TOTAL_TOTAL                      26:16
1768#define CRT_VERTICAL_TOTAL_DISPLAY_END                10:0
1769
1770#define CRT_VERTICAL_SYNC                             0x080218
1771#define CRT_VERTICAL_SYNC_HEIGHT                      21:16
1772#define CRT_VERTICAL_SYNC_START                       10:0
1773
1774#define CRT_SIGNATURE_ANALYZER                        0x08021C
1775#define CRT_SIGNATURE_ANALYZER_STATUS                 31:16
1776#define CRT_SIGNATURE_ANALYZER_ENABLE                 3:3
1777#define CRT_SIGNATURE_ANALYZER_ENABLE_DISABLE         0
1778#define CRT_SIGNATURE_ANALYZER_ENABLE_ENABLE          1
1779#define CRT_SIGNATURE_ANALYZER_RESET                  2:2
1780#define CRT_SIGNATURE_ANALYZER_RESET_NORMAL           0
1781#define CRT_SIGNATURE_ANALYZER_RESET_RESET            1
1782#define CRT_SIGNATURE_ANALYZER_SOURCE                 1:0
1783#define CRT_SIGNATURE_ANALYZER_SOURCE_RED             0
1784#define CRT_SIGNATURE_ANALYZER_SOURCE_GREEN           1
1785#define CRT_SIGNATURE_ANALYZER_SOURCE_BLUE            2
1786
1787#define CRT_CURRENT_LINE                              0x080220
1788#define CRT_CURRENT_LINE_LINE                         10:0
1789
1790#define CRT_MONITOR_DETECT                            0x080224
1791#define CRT_MONITOR_DETECT_VALUE                      25:25
1792#define CRT_MONITOR_DETECT_VALUE_DISABLE              0
1793#define CRT_MONITOR_DETECT_VALUE_ENABLE               1
1794#define CRT_MONITOR_DETECT_ENABLE                     24:24
1795#define CRT_MONITOR_DETECT_ENABLE_DISABLE             0
1796#define CRT_MONITOR_DETECT_ENABLE_ENABLE              1
1797#define CRT_MONITOR_DETECT_RED                        23:16
1798#define CRT_MONITOR_DETECT_GREEN                      15:8
1799#define CRT_MONITOR_DETECT_BLUE                       7:0
1800
1801#define CRT_SCALE                                     0x080228
1802#define CRT_SCALE_VERTICAL_MODE                       31:31
1803#define CRT_SCALE_VERTICAL_MODE_EXPAND                0
1804#define CRT_SCALE_VERTICAL_MODE_SHRINK                1
1805#define CRT_SCALE_VERTICAL_SCALE                      27:16
1806#define CRT_SCALE_HORIZONTAL_MODE                     15:15
1807#define CRT_SCALE_HORIZONTAL_MODE_EXPAND              0
1808#define CRT_SCALE_HORIZONTAL_MODE_SHRINK              1
1809#define CRT_SCALE_HORIZONTAL_SCALE                    11:0
1810
1811/* CRT Cursor Control */
1812
1813#define CRT_HWC_ADDRESS                               0x080230
1814#define CRT_HWC_ADDRESS_ENABLE                        31:31
1815#define CRT_HWC_ADDRESS_ENABLE_DISABLE                0
1816#define CRT_HWC_ADDRESS_ENABLE_ENABLE                 1
1817#define CRT_HWC_ADDRESS_EXT                           27:27
1818#define CRT_HWC_ADDRESS_EXT_LOCAL                     0
1819#define CRT_HWC_ADDRESS_EXT_EXTERNAL                  1
1820#define CRT_HWC_ADDRESS_ADDRESS                       25:0
1821
1822#define CRT_HWC_LOCATION                              0x080234
1823#define CRT_HWC_LOCATION_TOP                          27:27
1824#define CRT_HWC_LOCATION_TOP_INSIDE                   0
1825#define CRT_HWC_LOCATION_TOP_OUTSIDE                  1
1826#define CRT_HWC_LOCATION_Y                            26:16
1827#define CRT_HWC_LOCATION_LEFT                         11:11
1828#define CRT_HWC_LOCATION_LEFT_INSIDE                  0
1829#define CRT_HWC_LOCATION_LEFT_OUTSIDE                 1
1830#define CRT_HWC_LOCATION_X                            10:0
1831
1832#define CRT_HWC_COLOR_12                              0x080238
1833#define CRT_HWC_COLOR_12_2_RGB565                     31:16
1834#define CRT_HWC_COLOR_12_1_RGB565                     15:0
1835
1836#define CRT_HWC_COLOR_3                               0x08023C
1837#define CRT_HWC_COLOR_3_RGB565                        15:0
1838
1839/* Old Definitions +++. Need to be removed if no application use it. */
1840#if 0
1841    #define CRT_HWC_COLOR_01                          0x080238
1842    #define CRT_HWC_COLOR_01_1_RED                    31:27
1843    #define CRT_HWC_COLOR_01_1_GREEN                  26:21
1844    #define CRT_HWC_COLOR_01_1_BLUE                   20:16
1845    #define CRT_HWC_COLOR_01_0_RED                    15:11
1846    #define CRT_HWC_COLOR_01_0_GREEN                  10:5
1847    #define CRT_HWC_COLOR_01_0_BLUE                   4:0
1848
1849    #define CRT_HWC_COLOR_2                           0x08023C
1850    #define CRT_HWC_COLOR_2_RED                       15:11
1851    #define CRT_HWC_COLOR_2_GREEN                     10:5
1852    #define CRT_HWC_COLOR_2_BLUE                      4:0
1853#endif
1854/* Old Definitions --- */
1855
1856/* This vertical expansion below start at 0x080240 ~ 0x080264 */
1857#define CRT_VERTICAL_EXPANSION                        0x080240
1858#ifndef VALIDATION_CHIP
1859    #define CRT_VERTICAL_CENTERING_VALUE              31:24
1860#endif
1861#define CRT_VERTICAL_EXPANSION_COMPARE_VALUE          23:16
1862#define CRT_VERTICAL_EXPANSION_LINE_BUFFER            15:12
1863#define CRT_VERTICAL_EXPANSION_SCALE_FACTOR           11:0
1864
1865/* This horizontal expansion below start at 0x080268 ~ 0x08027C */
1866#define CRT_HORIZONTAL_EXPANSION                      0x080268
1867#ifndef VALIDATION_CHIP
1868    #define CRT_HORIZONTAL_CENTERING_VALUE            31:24
1869#endif
1870#define CRT_HORIZONTAL_EXPANSION_COMPARE_VALUE        23:16
1871#define CRT_HORIZONTAL_EXPANSION_SCALE_FACTOR         11:0
1872
1873#ifndef VALIDATION_CHIP
1874    /* Auto Centering */
1875    #define CRT_AUTO_CENTERING_TL                     0x080280
1876    #define CRT_AUTO_CENTERING_TL_TOP                 26:16
1877    #define CRT_AUTO_CENTERING_TL_LEFT                10:0
1878
1879    #define CRT_AUTO_CENTERING_BR                     0x080284
1880    #define CRT_AUTO_CENTERING_BR_BOTTOM              26:16
1881    #define CRT_AUTO_CENTERING_BR_RIGHT               10:0
1882#endif
1883
1884/* sm750le new register to control panel output */
1885#define DISPLAY_CONTROL_750LE 	0x80288
1886/* Palette RAM */
1887
1888/* Panel Pallete register starts at 0x080400 ~ 0x0807FC */
1889#define PANEL_PALETTE_RAM                             0x080400
1890
1891/* Panel Pallete register starts at 0x080C00 ~ 0x080FFC */
1892#define CRT_PALETTE_RAM                               0x080C00
1893
1894/* 2D registers
1895 * move their defination into general lynx_accel.h file
1896 * because all smi graphic chip share the same drawing engine
1897 * register format */
1898#if 0
1899#define DE_SOURCE                                       0x100000
1900#define DE_SOURCE_WRAP                                  31:31
1901#define DE_SOURCE_WRAP_DISABLE                          0
1902#define DE_SOURCE_WRAP_ENABLE                           1
1903
1904/*
1905 * The following definitions are used in different setting
1906 */
1907
1908/* Use these definitions in XY addressing mode or linear addressing mode. */
1909#define DE_SOURCE_X_K1                                  27:16
1910#define DE_SOURCE_Y_K2                                  11:0
1911
1912/* Use this definition in host write mode for mono. The Y_K2 is not used
1913   in host write mode. */
1914#define DE_SOURCE_X_K1_MONO                             20:16
1915
1916/* Use these definitions in Bresenham line drawing mode. */
1917#define DE_SOURCE_X_K1_LINE                             29:16
1918#define DE_SOURCE_Y_K2_LINE                             13:0
1919
1920#define DE_DESTINATION                                  0x100004
1921#define DE_DESTINATION_WRAP                             31:31
1922#define DE_DESTINATION_WRAP_DISABLE                     0
1923#define DE_DESTINATION_WRAP_ENABLE                      1
1924#if 1
1925    #define DE_DESTINATION_X                            27:16
1926    #define DE_DESTINATION_Y                            11:0
1927#else
1928    #define DE_DESTINATION_X                            28:16
1929    #define DE_DESTINATION_Y                            15:0
1930#endif
1931
1932#define DE_DIMENSION                                    0x100008
1933#define DE_DIMENSION_X                                  28:16
1934#define DE_DIMENSION_Y_ET                               15:0
1935
1936#define DE_CONTROL                                      0x10000C
1937#define DE_CONTROL_STATUS                               31:31
1938#define DE_CONTROL_STATUS_STOP                          0
1939#define DE_CONTROL_STATUS_START                         1
1940#define DE_CONTROL_PATTERN                              30:30
1941#define DE_CONTROL_PATTERN_MONO                         0
1942#define DE_CONTROL_PATTERN_COLOR                        1
1943#define DE_CONTROL_UPDATE_DESTINATION_X                 29:29
1944#define DE_CONTROL_UPDATE_DESTINATION_X_DISABLE         0
1945#define DE_CONTROL_UPDATE_DESTINATION_X_ENABLE          1
1946#define DE_CONTROL_QUICK_START                          28:28
1947#define DE_CONTROL_QUICK_START_DISABLE                  0
1948#define DE_CONTROL_QUICK_START_ENABLE                   1
1949#define DE_CONTROL_DIRECTION                            27:27
1950#define DE_CONTROL_DIRECTION_LEFT_TO_RIGHT              0
1951#define DE_CONTROL_DIRECTION_RIGHT_TO_LEFT              1
1952#define DE_CONTROL_MAJOR                                26:26
1953#define DE_CONTROL_MAJOR_X                              0
1954#define DE_CONTROL_MAJOR_Y                              1
1955#define DE_CONTROL_STEP_X                               25:25
1956#define DE_CONTROL_STEP_X_POSITIVE                      0
1957#define DE_CONTROL_STEP_X_NEGATIVE                      1
1958#define DE_CONTROL_STEP_Y                               24:24
1959#define DE_CONTROL_STEP_Y_POSITIVE                      0
1960#define DE_CONTROL_STEP_Y_NEGATIVE                      1
1961#define DE_CONTROL_STRETCH                              23:23
1962#define DE_CONTROL_STRETCH_DISABLE                      0
1963#define DE_CONTROL_STRETCH_ENABLE                       1
1964#define DE_CONTROL_HOST                                 22:22
1965#define DE_CONTROL_HOST_COLOR                           0
1966#define DE_CONTROL_HOST_MONO                            1
1967#define DE_CONTROL_LAST_PIXEL                           21:21
1968#define DE_CONTROL_LAST_PIXEL_OFF                       0
1969#define DE_CONTROL_LAST_PIXEL_ON                        1
1970#define DE_CONTROL_COMMAND                              20:16
1971#define DE_CONTROL_COMMAND_BITBLT                       0
1972#define DE_CONTROL_COMMAND_RECTANGLE_FILL               1
1973#define DE_CONTROL_COMMAND_DE_TILE                      2
1974#define DE_CONTROL_COMMAND_TRAPEZOID_FILL               3
1975#define DE_CONTROL_COMMAND_ALPHA_BLEND                  4
1976#define DE_CONTROL_COMMAND_RLE_STRIP                    5
1977#define DE_CONTROL_COMMAND_SHORT_STROKE                 6
1978#define DE_CONTROL_COMMAND_LINE_DRAW                    7
1979#define DE_CONTROL_COMMAND_HOST_WRITE                   8
1980#define DE_CONTROL_COMMAND_HOST_READ                    9
1981#define DE_CONTROL_COMMAND_HOST_WRITE_BOTTOM_UP         10
1982#define DE_CONTROL_COMMAND_ROTATE                       11
1983#define DE_CONTROL_COMMAND_FONT                         12
1984#define DE_CONTROL_COMMAND_TEXTURE_LOAD                 15
1985#define DE_CONTROL_ROP_SELECT                           15:15
1986#define DE_CONTROL_ROP_SELECT_ROP3                      0
1987#define DE_CONTROL_ROP_SELECT_ROP2                      1
1988#define DE_CONTROL_ROP2_SOURCE                          14:14
1989#define DE_CONTROL_ROP2_SOURCE_BITMAP                   0
1990#define DE_CONTROL_ROP2_SOURCE_PATTERN                  1
1991#define DE_CONTROL_MONO_DATA                            13:12
1992#define DE_CONTROL_MONO_DATA_NOT_PACKED                 0
1993#define DE_CONTROL_MONO_DATA_8_PACKED                   1
1994#define DE_CONTROL_MONO_DATA_16_PACKED                  2
1995#define DE_CONTROL_MONO_DATA_32_PACKED                  3
1996#define DE_CONTROL_REPEAT_ROTATE                        11:11
1997#define DE_CONTROL_REPEAT_ROTATE_DISABLE                0
1998#define DE_CONTROL_REPEAT_ROTATE_ENABLE                 1
1999#define DE_CONTROL_TRANSPARENCY_MATCH                   10:10
2000#define DE_CONTROL_TRANSPARENCY_MATCH_OPAQUE            0
2001#define DE_CONTROL_TRANSPARENCY_MATCH_TRANSPARENT       1
2002#define DE_CONTROL_TRANSPARENCY_SELECT                  9:9
2003#define DE_CONTROL_TRANSPARENCY_SELECT_SOURCE           0
2004#define DE_CONTROL_TRANSPARENCY_SELECT_DESTINATION      1
2005#define DE_CONTROL_TRANSPARENCY                         8:8
2006#define DE_CONTROL_TRANSPARENCY_DISABLE                 0
2007#define DE_CONTROL_TRANSPARENCY_ENABLE                  1
2008#define DE_CONTROL_ROP                                  7:0
2009
2010/* Pseudo fields. */
2011
2012#define DE_CONTROL_SHORT_STROKE_DIR                     27:24
2013#define DE_CONTROL_SHORT_STROKE_DIR_225                 0
2014#define DE_CONTROL_SHORT_STROKE_DIR_135                 1
2015#define DE_CONTROL_SHORT_STROKE_DIR_315                 2
2016#define DE_CONTROL_SHORT_STROKE_DIR_45                  3
2017#define DE_CONTROL_SHORT_STROKE_DIR_270                 4
2018#define DE_CONTROL_SHORT_STROKE_DIR_90                  5
2019#define DE_CONTROL_SHORT_STROKE_DIR_180                 8
2020#define DE_CONTROL_SHORT_STROKE_DIR_0                   10
2021#define DE_CONTROL_ROTATION                             25:24
2022#define DE_CONTROL_ROTATION_0                           0
2023#define DE_CONTROL_ROTATION_270                         1
2024#define DE_CONTROL_ROTATION_90                          2
2025#define DE_CONTROL_ROTATION_180                         3
2026
2027#define DE_PITCH                                        0x100010
2028#define DE_PITCH_DESTINATION                            28:16
2029#define DE_PITCH_SOURCE                                 12:0
2030
2031#define DE_FOREGROUND                                   0x100014
2032#define DE_FOREGROUND_COLOR                             31:0
2033
2034#define DE_BACKGROUND                                   0x100018
2035#define DE_BACKGROUND_COLOR                             31:0
2036
2037#define DE_STRETCH_FORMAT                               0x10001C
2038#define DE_STRETCH_FORMAT_PATTERN_XY                    30:30
2039#define DE_STRETCH_FORMAT_PATTERN_XY_NORMAL             0
2040#define DE_STRETCH_FORMAT_PATTERN_XY_OVERWRITE          1
2041#define DE_STRETCH_FORMAT_PATTERN_Y                     29:27
2042#define DE_STRETCH_FORMAT_PATTERN_X                     25:23
2043#define DE_STRETCH_FORMAT_PIXEL_FORMAT                  21:20
2044#define DE_STRETCH_FORMAT_PIXEL_FORMAT_8                0
2045#define DE_STRETCH_FORMAT_PIXEL_FORMAT_16               1
2046#define DE_STRETCH_FORMAT_PIXEL_FORMAT_32               2
2047#define DE_STRETCH_FORMAT_ADDRESSING                    19:16
2048#define DE_STRETCH_FORMAT_ADDRESSING_XY                 0
2049#define DE_STRETCH_FORMAT_ADDRESSING_LINEAR             15
2050#define DE_STRETCH_FORMAT_SOURCE_HEIGHT                 11:0
2051
2052#define DE_COLOR_COMPARE                                0x100020
2053#define DE_COLOR_COMPARE_COLOR                          23:0
2054
2055#define DE_COLOR_COMPARE_MASK                           0x100024
2056#define DE_COLOR_COMPARE_MASK_MASKS                     23:0
2057
2058#define DE_MASKS                                        0x100028
2059#define DE_MASKS_BYTE_MASK                              31:16
2060#define DE_MASKS_BIT_MASK                               15:0
2061
2062#define DE_CLIP_TL                                      0x10002C
2063#define DE_CLIP_TL_TOP                                  31:16
2064#define DE_CLIP_TL_STATUS                               13:13
2065#define DE_CLIP_TL_STATUS_DISABLE                       0
2066#define DE_CLIP_TL_STATUS_ENABLE                        1
2067#define DE_CLIP_TL_INHIBIT                              12:12
2068#define DE_CLIP_TL_INHIBIT_OUTSIDE                      0
2069#define DE_CLIP_TL_INHIBIT_INSIDE                       1
2070#define DE_CLIP_TL_LEFT                                 11:0
2071
2072#define DE_CLIP_BR                                      0x100030
2073#define DE_CLIP_BR_BOTTOM                               31:16
2074#define DE_CLIP_BR_RIGHT                                12:0
2075
2076#define DE_MONO_PATTERN_LOW                             0x100034
2077#define DE_MONO_PATTERN_LOW_PATTERN                     31:0
2078
2079#define DE_MONO_PATTERN_HIGH                            0x100038
2080#define DE_MONO_PATTERN_HIGH_PATTERN                    31:0
2081
2082#define DE_WINDOW_WIDTH                                 0x10003C
2083#define DE_WINDOW_WIDTH_DESTINATION                     28:16
2084#define DE_WINDOW_WIDTH_SOURCE                          12:0
2085
2086#define DE_WINDOW_SOURCE_BASE                           0x100040
2087#define DE_WINDOW_SOURCE_BASE_EXT                       27:27
2088#define DE_WINDOW_SOURCE_BASE_EXT_LOCAL                 0
2089#define DE_WINDOW_SOURCE_BASE_EXT_EXTERNAL              1
2090#define DE_WINDOW_SOURCE_BASE_CS                        26:26
2091#define DE_WINDOW_SOURCE_BASE_CS_0                      0
2092#define DE_WINDOW_SOURCE_BASE_CS_1                      1
2093#define DE_WINDOW_SOURCE_BASE_ADDRESS                   25:0
2094
2095#define DE_WINDOW_DESTINATION_BASE                      0x100044
2096#define DE_WINDOW_DESTINATION_BASE_EXT                  27:27
2097#define DE_WINDOW_DESTINATION_BASE_EXT_LOCAL            0
2098#define DE_WINDOW_DESTINATION_BASE_EXT_EXTERNAL         1
2099#define DE_WINDOW_DESTINATION_BASE_CS                   26:26
2100#define DE_WINDOW_DESTINATION_BASE_CS_0                 0
2101#define DE_WINDOW_DESTINATION_BASE_CS_1                 1
2102#define DE_WINDOW_DESTINATION_BASE_ADDRESS              25:0
2103
2104#define DE_ALPHA                                        0x100048
2105#define DE_ALPHA_VALUE                                  7:0
2106
2107#define DE_WRAP                                         0x10004C
2108#define DE_WRAP_X                                       31:16
2109#define DE_WRAP_Y                                       15:0
2110
2111#define DE_STATUS                                       0x100050
2112#define DE_STATUS_CSC                                   1:1
2113#define DE_STATUS_CSC_CLEAR                             0
2114#define DE_STATUS_CSC_NOT_ACTIVE                        0
2115#define DE_STATUS_CSC_ACTIVE                            1
2116#define DE_STATUS_2D                                    0:0
2117#define DE_STATUS_2D_CLEAR                              0
2118#define DE_STATUS_2D_NOT_ACTIVE                         0
2119#define DE_STATUS_2D_ACTIVE                             1
2120#endif
2121/* Color Space Conversion registers. */
2122
2123#define CSC_Y_SOURCE_BASE                               0x1000C8
2124#define CSC_Y_SOURCE_BASE_EXT                           27:27
2125#define CSC_Y_SOURCE_BASE_EXT_LOCAL                     0
2126#define CSC_Y_SOURCE_BASE_EXT_EXTERNAL                  1
2127#define CSC_Y_SOURCE_BASE_CS                            26:26
2128#define CSC_Y_SOURCE_BASE_CS_0                          0
2129#define CSC_Y_SOURCE_BASE_CS_1                          1
2130#define CSC_Y_SOURCE_BASE_ADDRESS                       25:0
2131
2132#define CSC_CONSTANTS                                   0x1000CC
2133#define CSC_CONSTANTS_Y                                 31:24
2134#define CSC_CONSTANTS_R                                 23:16
2135#define CSC_CONSTANTS_G                                 15:8
2136#define CSC_CONSTANTS_B                                 7:0
2137
2138#define CSC_Y_SOURCE_X                                  0x1000D0
2139#define CSC_Y_SOURCE_X_INTEGER                          26:16
2140#define CSC_Y_SOURCE_X_FRACTION                         15:3
2141
2142#define CSC_Y_SOURCE_Y                                  0x1000D4
2143#define CSC_Y_SOURCE_Y_INTEGER                          27:16
2144#define CSC_Y_SOURCE_Y_FRACTION                         15:3
2145
2146#define CSC_U_SOURCE_BASE                               0x1000D8
2147#define CSC_U_SOURCE_BASE_EXT                           27:27
2148#define CSC_U_SOURCE_BASE_EXT_LOCAL                     0
2149#define CSC_U_SOURCE_BASE_EXT_EXTERNAL                  1
2150#define CSC_U_SOURCE_BASE_CS                            26:26
2151#define CSC_U_SOURCE_BASE_CS_0                          0
2152#define CSC_U_SOURCE_BASE_CS_1                          1
2153#define CSC_U_SOURCE_BASE_ADDRESS                       25:0
2154
2155#define CSC_V_SOURCE_BASE                               0x1000DC
2156#define CSC_V_SOURCE_BASE_EXT                           27:27
2157#define CSC_V_SOURCE_BASE_EXT_LOCAL                     0
2158#define CSC_V_SOURCE_BASE_EXT_EXTERNAL                  1
2159#define CSC_V_SOURCE_BASE_CS                            26:26
2160#define CSC_V_SOURCE_BASE_CS_0                          0
2161#define CSC_V_SOURCE_BASE_CS_1                          1
2162#define CSC_V_SOURCE_BASE_ADDRESS                       25:0
2163
2164#define CSC_SOURCE_DIMENSION                            0x1000E0
2165#define CSC_SOURCE_DIMENSION_X                          31:16
2166#define CSC_SOURCE_DIMENSION_Y                          15:0
2167
2168#define CSC_SOURCE_PITCH                                0x1000E4
2169#define CSC_SOURCE_PITCH_Y                              31:16
2170#define CSC_SOURCE_PITCH_UV                             15:0
2171
2172#define CSC_DESTINATION                                 0x1000E8
2173#define CSC_DESTINATION_WRAP                            31:31
2174#define CSC_DESTINATION_WRAP_DISABLE                    0
2175#define CSC_DESTINATION_WRAP_ENABLE                     1
2176#define CSC_DESTINATION_X                               27:16
2177#define CSC_DESTINATION_Y                               11:0
2178
2179#define CSC_DESTINATION_DIMENSION                       0x1000EC
2180#define CSC_DESTINATION_DIMENSION_X                     31:16
2181#define CSC_DESTINATION_DIMENSION_Y                     15:0
2182
2183#define CSC_DESTINATION_PITCH                           0x1000F0
2184#define CSC_DESTINATION_PITCH_X                         31:16
2185#define CSC_DESTINATION_PITCH_Y                         15:0
2186
2187#define CSC_SCALE_FACTOR                                0x1000F4
2188#define CSC_SCALE_FACTOR_HORIZONTAL                     31:16
2189#define CSC_SCALE_FACTOR_VERTICAL                       15:0
2190
2191#define CSC_DESTINATION_BASE                            0x1000F8
2192#define CSC_DESTINATION_BASE_EXT                        27:27
2193#define CSC_DESTINATION_BASE_EXT_LOCAL                  0
2194#define CSC_DESTINATION_BASE_EXT_EXTERNAL               1
2195#define CSC_DESTINATION_BASE_CS                         26:26
2196#define CSC_DESTINATION_BASE_CS_0                       0
2197#define CSC_DESTINATION_BASE_CS_1                       1
2198#define CSC_DESTINATION_BASE_ADDRESS                    25:0
2199
2200#define CSC_CONTROL                                     0x1000FC
2201#define CSC_CONTROL_STATUS                              31:31
2202#define CSC_CONTROL_STATUS_STOP                         0
2203#define CSC_CONTROL_STATUS_START                        1
2204#define CSC_CONTROL_SOURCE_FORMAT                       30:28
2205#define CSC_CONTROL_SOURCE_FORMAT_YUV422                0
2206#define CSC_CONTROL_SOURCE_FORMAT_YUV420I               1
2207#define CSC_CONTROL_SOURCE_FORMAT_YUV420                2
2208#define CSC_CONTROL_SOURCE_FORMAT_YVU9                  3
2209#define CSC_CONTROL_SOURCE_FORMAT_IYU1                  4
2210#define CSC_CONTROL_SOURCE_FORMAT_IYU2                  5
2211#define CSC_CONTROL_SOURCE_FORMAT_RGB565                6
2212#define CSC_CONTROL_SOURCE_FORMAT_RGB8888               7
2213#define CSC_CONTROL_DESTINATION_FORMAT                  27:26
2214#define CSC_CONTROL_DESTINATION_FORMAT_RGB565           0
2215#define CSC_CONTROL_DESTINATION_FORMAT_RGB8888          1
2216#define CSC_CONTROL_HORIZONTAL_FILTER                   25:25
2217#define CSC_CONTROL_HORIZONTAL_FILTER_DISABLE           0
2218#define CSC_CONTROL_HORIZONTAL_FILTER_ENABLE            1
2219#define CSC_CONTROL_VERTICAL_FILTER                     24:24
2220#define CSC_CONTROL_VERTICAL_FILTER_DISABLE             0
2221#define CSC_CONTROL_VERTICAL_FILTER_ENABLE              1
2222#define CSC_CONTROL_BYTE_ORDER                          23:23
2223#define CSC_CONTROL_BYTE_ORDER_YUYV                     0
2224#define CSC_CONTROL_BYTE_ORDER_UYVY                     1
2225
2226#define DE_DATA_PORT                                    0x110000
2227
2228#define I2C_BYTE_COUNT                                  0x010040
2229#define I2C_BYTE_COUNT_COUNT                            3:0
2230
2231#define I2C_CTRL                                        0x010041
2232#define I2C_CTRL_INT                                    4:4
2233#define I2C_CTRL_INT_DISABLE                            0
2234#define I2C_CTRL_INT_ENABLE                             1
2235#define I2C_CTRL_DIR                                    3:3
2236#define I2C_CTRL_DIR_WR                                 0
2237#define I2C_CTRL_DIR_RD                                 1
2238#define I2C_CTRL_CTRL                                   2:2
2239#define I2C_CTRL_CTRL_STOP                              0
2240#define I2C_CTRL_CTRL_START                             1
2241#define I2C_CTRL_MODE                                   1:1
2242#define I2C_CTRL_MODE_STANDARD                          0
2243#define I2C_CTRL_MODE_FAST                              1
2244#define I2C_CTRL_EN                                     0:0
2245#define I2C_CTRL_EN_DISABLE                             0
2246#define I2C_CTRL_EN_ENABLE                              1
2247
2248#define I2C_STATUS                                      0x010042
2249#define I2C_STATUS_TX                                   3:3
2250#define I2C_STATUS_TX_PROGRESS                          0
2251#define I2C_STATUS_TX_COMPLETED                         1
2252#define I2C_TX_DONE                                     0x08
2253#define I2C_STATUS_ERR                                  2:2
2254#define I2C_STATUS_ERR_NORMAL                           0
2255#define I2C_STATUS_ERR_ERROR                            1
2256#define I2C_STATUS_ERR_CLEAR                            0
2257#define I2C_STATUS_ACK                                  1:1
2258#define I2C_STATUS_ACK_RECEIVED                         0
2259#define I2C_STATUS_ACK_NOT                              1
2260#define I2C_STATUS_BSY                                  0:0
2261#define I2C_STATUS_BSY_IDLE                             0
2262#define I2C_STATUS_BSY_BUSY                             1
2263
2264#define I2C_RESET                                       0x010042
2265#define I2C_RESET_BUS_ERROR                             2:2
2266#define I2C_RESET_BUS_ERROR_CLEAR                       0
2267
2268#define I2C_SLAVE_ADDRESS                               0x010043
2269#define I2C_SLAVE_ADDRESS_ADDRESS                       7:1
2270#define I2C_SLAVE_ADDRESS_RW                            0:0
2271#define I2C_SLAVE_ADDRESS_RW_W                          0
2272#define I2C_SLAVE_ADDRESS_RW_R                          1
2273
2274#define I2C_DATA0                                       0x010044
2275#define I2C_DATA1                                       0x010045
2276#define I2C_DATA2                                       0x010046
2277#define I2C_DATA3                                       0x010047
2278#define I2C_DATA4                                       0x010048
2279#define I2C_DATA5                                       0x010049
2280#define I2C_DATA6                                       0x01004A
2281#define I2C_DATA7                                       0x01004B
2282#define I2C_DATA8                                       0x01004C
2283#define I2C_DATA9                                       0x01004D
2284#define I2C_DATA10                                      0x01004E
2285#define I2C_DATA11                                      0x01004F
2286#define I2C_DATA12                                      0x010050
2287#define I2C_DATA13                                      0x010051
2288#define I2C_DATA14                                      0x010052
2289#define I2C_DATA15                                      0x010053
2290
2291
2292#define ZV0_CAPTURE_CTRL                                0x090000
2293#define ZV0_CAPTURE_CTRL_FIELD_INPUT                    27:27
2294#define ZV0_CAPTURE_CTRL_FIELD_INPUT_EVEN_FIELD         0
2295#define ZV0_CAPTURE_CTRL_FIELD_INPUT_ODD_FIELD          1
2296#define ZV0_CAPTURE_CTRL_SCAN                           26:26
2297#define ZV0_CAPTURE_CTRL_SCAN_PROGRESSIVE               0
2298#define ZV0_CAPTURE_CTRL_SCAN_INTERLACE                 1
2299#define ZV0_CAPTURE_CTRL_CURRENT_BUFFER                 25:25
2300#define ZV0_CAPTURE_CTRL_CURRENT_BUFFER_0               0
2301#define ZV0_CAPTURE_CTRL_CURRENT_BUFFER_1               1
2302#define ZV0_CAPTURE_CTRL_VERTICAL_SYNC                  24:24
2303#define ZV0_CAPTURE_CTRL_VERTICAL_SYNC_INACTIVE         0
2304#define ZV0_CAPTURE_CTRL_VERTICAL_SYNC_ACTIVE           1
2305#define ZV0_CAPTURE_CTRL_ADJ                            19:19
2306#define ZV0_CAPTURE_CTRL_ADJ_NORMAL                     0
2307#define ZV0_CAPTURE_CTRL_ADJ_DELAY                      1
2308#define ZV0_CAPTURE_CTRL_HA                             18:18
2309#define ZV0_CAPTURE_CTRL_HA_DISABLE                     0
2310#define ZV0_CAPTURE_CTRL_HA_ENABLE                      1
2311#define ZV0_CAPTURE_CTRL_VSK                            17:17
2312#define ZV0_CAPTURE_CTRL_VSK_DISABLE                    0
2313#define ZV0_CAPTURE_CTRL_VSK_ENABLE                     1
2314#define ZV0_CAPTURE_CTRL_HSK                            16:16
2315#define ZV0_CAPTURE_CTRL_HSK_DISABLE                    0
2316#define ZV0_CAPTURE_CTRL_HSK_ENABLE                     1
2317#define ZV0_CAPTURE_CTRL_FD                             15:15
2318#define ZV0_CAPTURE_CTRL_FD_RISING                      0
2319#define ZV0_CAPTURE_CTRL_FD_FALLING                     1
2320#define ZV0_CAPTURE_CTRL_VP                             14:14
2321#define ZV0_CAPTURE_CTRL_VP_HIGH                        0
2322#define ZV0_CAPTURE_CTRL_VP_LOW                         1
2323#define ZV0_CAPTURE_CTRL_HP                             13:13
2324#define ZV0_CAPTURE_CTRL_HP_HIGH                        0
2325#define ZV0_CAPTURE_CTRL_HP_LOW                         1
2326#define ZV0_CAPTURE_CTRL_CP                             12:12
2327#define ZV0_CAPTURE_CTRL_CP_HIGH                        0
2328#define ZV0_CAPTURE_CTRL_CP_LOW                         1
2329#define ZV0_CAPTURE_CTRL_UVS                            11:11
2330#define ZV0_CAPTURE_CTRL_UVS_DISABLE                    0
2331#define ZV0_CAPTURE_CTRL_UVS_ENABLE                     1
2332#define ZV0_CAPTURE_CTRL_BS                             10:10
2333#define ZV0_CAPTURE_CTRL_BS_DISABLE                     0
2334#define ZV0_CAPTURE_CTRL_BS_ENABLE                      1
2335#define ZV0_CAPTURE_CTRL_CS                             9:9
2336#define ZV0_CAPTURE_CTRL_CS_16                          0
2337#define ZV0_CAPTURE_CTRL_CS_8                           1
2338#define ZV0_CAPTURE_CTRL_CF                             8:8
2339#define ZV0_CAPTURE_CTRL_CF_YUV                         0
2340#define ZV0_CAPTURE_CTRL_CF_RGB                         1
2341#define ZV0_CAPTURE_CTRL_FS                             7:7
2342#define ZV0_CAPTURE_CTRL_FS_DISABLE                     0
2343#define ZV0_CAPTURE_CTRL_FS_ENABLE                      1
2344#define ZV0_CAPTURE_CTRL_WEAVE                          6:6
2345#define ZV0_CAPTURE_CTRL_WEAVE_DISABLE                  0
2346#define ZV0_CAPTURE_CTRL_WEAVE_ENABLE                   1
2347#define ZV0_CAPTURE_CTRL_BOB                            5:5
2348#define ZV0_CAPTURE_CTRL_BOB_DISABLE                    0
2349#define ZV0_CAPTURE_CTRL_BOB_ENABLE                     1
2350#define ZV0_CAPTURE_CTRL_DB                             4:4
2351#define ZV0_CAPTURE_CTRL_DB_DISABLE                     0
2352#define ZV0_CAPTURE_CTRL_DB_ENABLE                      1
2353#define ZV0_CAPTURE_CTRL_CC                             3:3
2354#define ZV0_CAPTURE_CTRL_CC_CONTINUE                    0
2355#define ZV0_CAPTURE_CTRL_CC_CONDITION                   1
2356#define ZV0_CAPTURE_CTRL_RGB                            2:2
2357#define ZV0_CAPTURE_CTRL_RGB_DISABLE                    0
2358#define ZV0_CAPTURE_CTRL_RGB_ENABLE                     1
2359#define ZV0_CAPTURE_CTRL_656                            1:1
2360#define ZV0_CAPTURE_CTRL_656_DISABLE                    0
2361#define ZV0_CAPTURE_CTRL_656_ENABLE                     1
2362#define ZV0_CAPTURE_CTRL_CAP                            0:0
2363#define ZV0_CAPTURE_CTRL_CAP_DISABLE                    0
2364#define ZV0_CAPTURE_CTRL_CAP_ENABLE                     1
2365
2366#define ZV0_CAPTURE_CLIP                                0x090004
2367#define ZV0_CAPTURE_CLIP_YCLIP_EVEN_FIELD                25:16
2368#define ZV0_CAPTURE_CLIP_YCLIP                          25:16
2369#define ZV0_CAPTURE_CLIP_XCLIP                          9:0
2370
2371#define ZV0_CAPTURE_SIZE                                0x090008
2372#define ZV0_CAPTURE_SIZE_HEIGHT                         26:16
2373#define ZV0_CAPTURE_SIZE_WIDTH                          10:0
2374
2375#define ZV0_CAPTURE_BUF0_ADDRESS                        0x09000C
2376#define ZV0_CAPTURE_BUF0_ADDRESS_STATUS                 31:31
2377#define ZV0_CAPTURE_BUF0_ADDRESS_STATUS_CURRENT         0
2378#define ZV0_CAPTURE_BUF0_ADDRESS_STATUS_PENDING         1
2379#define ZV0_CAPTURE_BUF0_ADDRESS_EXT                    27:27
2380#define ZV0_CAPTURE_BUF0_ADDRESS_EXT_LOCAL              0
2381#define ZV0_CAPTURE_BUF0_ADDRESS_EXT_EXTERNAL           1
2382#define ZV0_CAPTURE_BUF0_ADDRESS_CS                     26:26
2383#define ZV0_CAPTURE_BUF0_ADDRESS_CS_0                   0
2384#define ZV0_CAPTURE_BUF0_ADDRESS_CS_1                   1
2385#define ZV0_CAPTURE_BUF0_ADDRESS_ADDRESS                25:0
2386
2387#define ZV0_CAPTURE_BUF1_ADDRESS                        0x090010
2388#define ZV0_CAPTURE_BUF1_ADDRESS_STATUS                 31:31
2389#define ZV0_CAPTURE_BUF1_ADDRESS_STATUS_CURRENT         0
2390#define ZV0_CAPTURE_BUF1_ADDRESS_STATUS_PENDING         1
2391#define ZV0_CAPTURE_BUF1_ADDRESS_EXT                    27:27
2392#define ZV0_CAPTURE_BUF1_ADDRESS_EXT_LOCAL              0
2393#define ZV0_CAPTURE_BUF1_ADDRESS_EXT_EXTERNAL           1
2394#define ZV0_CAPTURE_BUF1_ADDRESS_CS                     26:26
2395#define ZV0_CAPTURE_BUF1_ADDRESS_CS_0                   0
2396#define ZV0_CAPTURE_BUF1_ADDRESS_CS_1                   1
2397#define ZV0_CAPTURE_BUF1_ADDRESS_ADDRESS                25:0
2398
2399#define ZV0_CAPTURE_BUF_OFFSET                          0x090014
2400#ifndef VALIDATION_CHIP
2401    #define ZV0_CAPTURE_BUF_OFFSET_YCLIP_ODD_FIELD      25:16
2402#endif
2403#define ZV0_CAPTURE_BUF_OFFSET_OFFSET                   15:0
2404
2405#define ZV0_CAPTURE_FIFO_CTRL                           0x090018
2406#define ZV0_CAPTURE_FIFO_CTRL_FIFO                      2:0
2407#define ZV0_CAPTURE_FIFO_CTRL_FIFO_0                    0
2408#define ZV0_CAPTURE_FIFO_CTRL_FIFO_1                    1
2409#define ZV0_CAPTURE_FIFO_CTRL_FIFO_2                    2
2410#define ZV0_CAPTURE_FIFO_CTRL_FIFO_3                    3
2411#define ZV0_CAPTURE_FIFO_CTRL_FIFO_4                    4
2412#define ZV0_CAPTURE_FIFO_CTRL_FIFO_5                    5
2413#define ZV0_CAPTURE_FIFO_CTRL_FIFO_6                    6
2414#define ZV0_CAPTURE_FIFO_CTRL_FIFO_7                    7
2415
2416#define ZV0_CAPTURE_YRGB_CONST                          0x09001C
2417#define ZV0_CAPTURE_YRGB_CONST_Y                        31:24
2418#define ZV0_CAPTURE_YRGB_CONST_R                        23:16
2419#define ZV0_CAPTURE_YRGB_CONST_G                        15:8
2420#define ZV0_CAPTURE_YRGB_CONST_B                        7:0
2421
2422#define ZV0_CAPTURE_LINE_COMP                           0x090020
2423#define ZV0_CAPTURE_LINE_COMP_LC                        10:0
2424
2425/* ZV1 */
2426
2427#define ZV1_CAPTURE_CTRL                                0x098000
2428#define ZV1_CAPTURE_CTRL_FIELD_INPUT                    27:27
2429#define ZV1_CAPTURE_CTRL_FIELD_INPUT_EVEN_FIELD         0
2430#define ZV1_CAPTURE_CTRL_FIELD_INPUT_ODD_FIELD          0
2431#define ZV1_CAPTURE_CTRL_SCAN                           26:26
2432#define ZV1_CAPTURE_CTRL_SCAN_PROGRESSIVE               0
2433#define ZV1_CAPTURE_CTRL_SCAN_INTERLACE                 1
2434#define ZV1_CAPTURE_CTRL_CURRENT_BUFFER                 25:25
2435#define ZV1_CAPTURE_CTRL_CURRENT_BUFFER_0               0
2436#define ZV1_CAPTURE_CTRL_CURRENT_BUFFER_1               1
2437#define ZV1_CAPTURE_CTRL_VERTICAL_SYNC                  24:24
2438#define ZV1_CAPTURE_CTRL_VERTICAL_SYNC_INACTIVE         0
2439#define ZV1_CAPTURE_CTRL_VERTICAL_SYNC_ACTIVE           1
2440#define ZV1_CAPTURE_CTRL_PANEL                          20:20
2441#define ZV1_CAPTURE_CTRL_PANEL_DISABLE                  0
2442#define ZV1_CAPTURE_CTRL_PANEL_ENABLE                   1
2443#define ZV1_CAPTURE_CTRL_ADJ                            19:19
2444#define ZV1_CAPTURE_CTRL_ADJ_NORMAL                     0
2445#define ZV1_CAPTURE_CTRL_ADJ_DELAY                      1
2446#define ZV1_CAPTURE_CTRL_HA                             18:18
2447#define ZV1_CAPTURE_CTRL_HA_DISABLE                     0
2448#define ZV1_CAPTURE_CTRL_HA_ENABLE                      1
2449#define ZV1_CAPTURE_CTRL_VSK                            17:17
2450#define ZV1_CAPTURE_CTRL_VSK_DISABLE                    0
2451#define ZV1_CAPTURE_CTRL_VSK_ENABLE                     1
2452#define ZV1_CAPTURE_CTRL_HSK                            16:16
2453#define ZV1_CAPTURE_CTRL_HSK_DISABLE                    0
2454#define ZV1_CAPTURE_CTRL_HSK_ENABLE                     1
2455#define ZV1_CAPTURE_CTRL_FD                             15:15
2456#define ZV1_CAPTURE_CTRL_FD_RISING                      0
2457#define ZV1_CAPTURE_CTRL_FD_FALLING                     1
2458#define ZV1_CAPTURE_CTRL_VP                             14:14
2459#define ZV1_CAPTURE_CTRL_VP_HIGH                        0
2460#define ZV1_CAPTURE_CTRL_VP_LOW                         1
2461#define ZV1_CAPTURE_CTRL_HP                             13:13
2462#define ZV1_CAPTURE_CTRL_HP_HIGH                        0
2463#define ZV1_CAPTURE_CTRL_HP_LOW                         1
2464#define ZV1_CAPTURE_CTRL_CP                             12:12
2465#define ZV1_CAPTURE_CTRL_CP_HIGH                        0
2466#define ZV1_CAPTURE_CTRL_CP_LOW                         1
2467#define ZV1_CAPTURE_CTRL_UVS                            11:11
2468#define ZV1_CAPTURE_CTRL_UVS_DISABLE                    0
2469#define ZV1_CAPTURE_CTRL_UVS_ENABLE                     1
2470#define ZV1_CAPTURE_CTRL_BS                             10:10
2471#define ZV1_CAPTURE_CTRL_BS_DISABLE                     0
2472#define ZV1_CAPTURE_CTRL_BS_ENABLE                      1
2473#define ZV1_CAPTURE_CTRL_CS                             9:9
2474#define ZV1_CAPTURE_CTRL_CS_16                          0
2475#define ZV1_CAPTURE_CTRL_CS_8                           1
2476#define ZV1_CAPTURE_CTRL_CF                             8:8
2477#define ZV1_CAPTURE_CTRL_CF_YUV                         0
2478#define ZV1_CAPTURE_CTRL_CF_RGB                         1
2479#define ZV1_CAPTURE_CTRL_FS                             7:7
2480#define ZV1_CAPTURE_CTRL_FS_DISABLE                     0
2481#define ZV1_CAPTURE_CTRL_FS_ENABLE                      1
2482#define ZV1_CAPTURE_CTRL_WEAVE                          6:6
2483#define ZV1_CAPTURE_CTRL_WEAVE_DISABLE                  0
2484#define ZV1_CAPTURE_CTRL_WEAVE_ENABLE                   1
2485#define ZV1_CAPTURE_CTRL_BOB                            5:5
2486#define ZV1_CAPTURE_CTRL_BOB_DISABLE                    0
2487#define ZV1_CAPTURE_CTRL_BOB_ENABLE                     1
2488#define ZV1_CAPTURE_CTRL_DB                             4:4
2489#define ZV1_CAPTURE_CTRL_DB_DISABLE                     0
2490#define ZV1_CAPTURE_CTRL_DB_ENABLE                      1
2491#define ZV1_CAPTURE_CTRL_CC                             3:3
2492#define ZV1_CAPTURE_CTRL_CC_CONTINUE                    0
2493#define ZV1_CAPTURE_CTRL_CC_CONDITION                   1
2494#define ZV1_CAPTURE_CTRL_RGB                            2:2
2495#define ZV1_CAPTURE_CTRL_RGB_DISABLE                    0
2496#define ZV1_CAPTURE_CTRL_RGB_ENABLE                     1
2497#define ZV1_CAPTURE_CTRL_656                            1:1
2498#define ZV1_CAPTURE_CTRL_656_DISABLE                    0
2499#define ZV1_CAPTURE_CTRL_656_ENABLE                     1
2500#define ZV1_CAPTURE_CTRL_CAP                            0:0
2501#define ZV1_CAPTURE_CTRL_CAP_DISABLE                    0
2502#define ZV1_CAPTURE_CTRL_CAP_ENABLE                     1
2503
2504#define ZV1_CAPTURE_CLIP                                0x098004
2505#define ZV1_CAPTURE_CLIP_YCLIP                          25:16
2506#define ZV1_CAPTURE_CLIP_XCLIP                          9:0
2507
2508#define ZV1_CAPTURE_SIZE                                0x098008
2509#define ZV1_CAPTURE_SIZE_HEIGHT                         26:16
2510#define ZV1_CAPTURE_SIZE_WIDTH                          10:0
2511
2512#define ZV1_CAPTURE_BUF0_ADDRESS                        0x09800C
2513#define ZV1_CAPTURE_BUF0_ADDRESS_STATUS                 31:31
2514#define ZV1_CAPTURE_BUF0_ADDRESS_STATUS_CURRENT         0
2515#define ZV1_CAPTURE_BUF0_ADDRESS_STATUS_PENDING         1
2516#define ZV1_CAPTURE_BUF0_ADDRESS_EXT                    27:27
2517#define ZV1_CAPTURE_BUF0_ADDRESS_EXT_LOCAL              0
2518#define ZV1_CAPTURE_BUF0_ADDRESS_EXT_EXTERNAL           1
2519#define ZV1_CAPTURE_BUF0_ADDRESS_CS                     26:26
2520#define ZV1_CAPTURE_BUF0_ADDRESS_CS_0                   0
2521#define ZV1_CAPTURE_BUF0_ADDRESS_CS_1                   1
2522#define ZV1_CAPTURE_BUF0_ADDRESS_ADDRESS                25:0
2523
2524#define ZV1_CAPTURE_BUF1_ADDRESS                        0x098010
2525#define ZV1_CAPTURE_BUF1_ADDRESS_STATUS                 31:31
2526#define ZV1_CAPTURE_BUF1_ADDRESS_STATUS_CURRENT         0
2527#define ZV1_CAPTURE_BUF1_ADDRESS_STATUS_PENDING         1
2528#define ZV1_CAPTURE_BUF1_ADDRESS_EXT                    27:27
2529#define ZV1_CAPTURE_BUF1_ADDRESS_EXT_LOCAL              0
2530#define ZV1_CAPTURE_BUF1_ADDRESS_EXT_EXTERNAL           1
2531#define ZV1_CAPTURE_BUF1_ADDRESS_CS                     26:26
2532#define ZV1_CAPTURE_BUF1_ADDRESS_CS_0                   0
2533#define ZV1_CAPTURE_BUF1_ADDRESS_CS_1                   1
2534#define ZV1_CAPTURE_BUF1_ADDRESS_ADDRESS                25:0
2535
2536#define ZV1_CAPTURE_BUF_OFFSET                          0x098014
2537#define ZV1_CAPTURE_BUF_OFFSET_OFFSET                   15:0
2538
2539#define ZV1_CAPTURE_FIFO_CTRL                           0x098018
2540#define ZV1_CAPTURE_FIFO_CTRL_FIFO                      2:0
2541#define ZV1_CAPTURE_FIFO_CTRL_FIFO_0                    0
2542#define ZV1_CAPTURE_FIFO_CTRL_FIFO_1                    1
2543#define ZV1_CAPTURE_FIFO_CTRL_FIFO_2                    2
2544#define ZV1_CAPTURE_FIFO_CTRL_FIFO_3                    3
2545#define ZV1_CAPTURE_FIFO_CTRL_FIFO_4                    4
2546#define ZV1_CAPTURE_FIFO_CTRL_FIFO_5                    5
2547#define ZV1_CAPTURE_FIFO_CTRL_FIFO_6                    6
2548#define ZV1_CAPTURE_FIFO_CTRL_FIFO_7                    7
2549
2550#define ZV1_CAPTURE_YRGB_CONST                          0x09801C
2551#define ZV1_CAPTURE_YRGB_CONST_Y                        31:24
2552#define ZV1_CAPTURE_YRGB_CONST_R                        23:16
2553#define ZV1_CAPTURE_YRGB_CONST_G                        15:8
2554#define ZV1_CAPTURE_YRGB_CONST_B                        7:0
2555
2556#define DMA_1_SOURCE                                    0x0D0010
2557#define DMA_1_SOURCE_ADDRESS_EXT                        27:27
2558#define DMA_1_SOURCE_ADDRESS_EXT_LOCAL                  0
2559#define DMA_1_SOURCE_ADDRESS_EXT_EXTERNAL               1
2560#define DMA_1_SOURCE_ADDRESS_CS                         26:26
2561#define DMA_1_SOURCE_ADDRESS_CS_0                       0
2562#define DMA_1_SOURCE_ADDRESS_CS_1                       1
2563#define DMA_1_SOURCE_ADDRESS                            25:0
2564
2565#define DMA_1_DESTINATION                               0x0D0014
2566#define DMA_1_DESTINATION_ADDRESS_EXT                   27:27
2567#define DMA_1_DESTINATION_ADDRESS_EXT_LOCAL             0
2568#define DMA_1_DESTINATION_ADDRESS_EXT_EXTERNAL          1
2569#define DMA_1_DESTINATION_ADDRESS_CS                    26:26
2570#define DMA_1_DESTINATION_ADDRESS_CS_0                  0
2571#define DMA_1_DESTINATION_ADDRESS_CS_1                  1
2572#define DMA_1_DESTINATION_ADDRESS                       25:0
2573
2574#define DMA_1_SIZE_CONTROL                              0x0D0018
2575#define DMA_1_SIZE_CONTROL_STATUS                       31:31
2576#define DMA_1_SIZE_CONTROL_STATUS_IDLE                  0
2577#define DMA_1_SIZE_CONTROL_STATUS_ACTIVE                1
2578#define DMA_1_SIZE_CONTROL_SIZE                         23:0
2579
2580#define DMA_ABORT_INTERRUPT                             0x0D0020
2581#define DMA_ABORT_INTERRUPT_ABORT_1                     5:5
2582#define DMA_ABORT_INTERRUPT_ABORT_1_ENABLE              0
2583#define DMA_ABORT_INTERRUPT_ABORT_1_ABORT               1
2584#define DMA_ABORT_INTERRUPT_ABORT_0                     4:4
2585#define DMA_ABORT_INTERRUPT_ABORT_0_ENABLE              0
2586#define DMA_ABORT_INTERRUPT_ABORT_0_ABORT               1
2587#define DMA_ABORT_INTERRUPT_INT_1                       1:1
2588#define DMA_ABORT_INTERRUPT_INT_1_CLEAR                 0
2589#define DMA_ABORT_INTERRUPT_INT_1_FINISHED              1
2590#define DMA_ABORT_INTERRUPT_INT_0                       0:0
2591#define DMA_ABORT_INTERRUPT_INT_0_CLEAR                 0
2592#define DMA_ABORT_INTERRUPT_INT_0_FINISHED              1
2593
2594
2595
2596
2597
2598/* Default i2c CLK and Data GPIO. These are the default i2c pins */
2599#define DEFAULT_I2C_SCL                     30
2600#define DEFAULT_I2C_SDA                     31
2601
2602
2603#define GPIO_DATA_SM750LE                               0x020018
2604#define GPIO_DATA_SM750LE_1                             1:1
2605#define GPIO_DATA_SM750LE_0                             0:0
2606
2607#define GPIO_DATA_DIRECTION_SM750LE                     0x02001C
2608#define GPIO_DATA_DIRECTION_SM750LE_1                   1:1
2609#define GPIO_DATA_DIRECTION_SM750LE_1_INPUT             0
2610#define GPIO_DATA_DIRECTION_SM750LE_1_OUTPUT            1
2611#define GPIO_DATA_DIRECTION_SM750LE_0                   0:0
2612#define GPIO_DATA_DIRECTION_SM750LE_0_INPUT             0
2613#define GPIO_DATA_DIRECTION_SM750LE_0_OUTPUT            1
2614
2615
2616#endif
2617