1#ifndef DDK750_DISPLAY_H__
2#define DDK750_DISPLAY_H__
3
4/* panel path select
5	80000[29:28]
6*/
7
8#define PNL_2_OFFSET 0
9#define PNL_2_MASK (3 << PNL_2_OFFSET)
10#define PNL_2_USAGE	(PNL_2_MASK << 16)
11#define PNL_2_PRI 	((0 << PNL_2_OFFSET)|PNL_2_USAGE)
12#define PNL_2_SEC	((2 << PNL_2_OFFSET)|PNL_2_USAGE)
13
14
15/* primary timing & plane enable bit
16	1: 80000[8] & 80000[2] on
17	0: both off
18*/
19#define PRI_TP_OFFSET 4
20#define PRI_TP_MASK (1 << PRI_TP_OFFSET)
21#define PRI_TP_USAGE (PRI_TP_MASK << 16)
22#define PRI_TP_ON ((0x1 << PRI_TP_OFFSET)|PRI_TP_USAGE)
23#define PRI_TP_OFF ((0x0 << PRI_TP_OFFSET)|PRI_TP_USAGE)
24
25
26/* panel sequency status
27	80000[27:24]
28*/
29#define PNL_SEQ_OFFSET 6
30#define PNL_SEQ_MASK (1 << PNL_SEQ_OFFSET)
31#define PNL_SEQ_USAGE (PNL_SEQ_MASK << 16)
32#define PNL_SEQ_ON ((1 << PNL_SEQ_OFFSET)|PNL_SEQ_USAGE)
33#define PNL_SEQ_OFF ((0 << PNL_SEQ_OFFSET)|PNL_SEQ_USAGE)
34
35/* dual digital output
36	80000[19]
37*/
38#define DUAL_TFT_OFFSET 8
39#define DUAL_TFT_MASK (1 << DUAL_TFT_OFFSET)
40#define DUAL_TFT_USAGE (DUAL_TFT_MASK << 16)
41#define DUAL_TFT_ON ((1 << DUAL_TFT_OFFSET)|DUAL_TFT_USAGE)
42#define DUAL_TFT_OFF ((0 << DUAL_TFT_OFFSET)|DUAL_TFT_USAGE)
43
44/* secondary timing & plane enable bit
45	1:80200[8] & 80200[2] on
46	0: both off
47*/
48#define SEC_TP_OFFSET 5
49#define SEC_TP_MASK (1<< SEC_TP_OFFSET)
50#define SEC_TP_USAGE (SEC_TP_MASK << 16)
51#define SEC_TP_ON  ((0x1 << SEC_TP_OFFSET)|SEC_TP_USAGE)
52#define SEC_TP_OFF ((0x0 << SEC_TP_OFFSET)|SEC_TP_USAGE)
53
54/* crt path select
55	80200[19:18]
56*/
57#define CRT_2_OFFSET 2
58#define CRT_2_MASK (3 << CRT_2_OFFSET)
59#define CRT_2_USAGE (CRT_2_MASK << 16)
60#define CRT_2_PRI ((0x0 << CRT_2_OFFSET)|CRT_2_USAGE)
61#define CRT_2_SEC ((0x2 << CRT_2_OFFSET)|CRT_2_USAGE)
62
63
64/* DAC affect both DVI and DSUB
65	4[20]
66*/
67#define DAC_OFFSET 7
68#define DAC_MASK (1 << DAC_OFFSET)
69#define DAC_USAGE (DAC_MASK << 16)
70#define DAC_ON ((0x0<< DAC_OFFSET)|DAC_USAGE)
71#define DAC_OFF ((0x1 << DAC_OFFSET)|DAC_USAGE)
72
73/* DPMS only affect D-SUB head
74	0[31:30]
75*/
76#define DPMS_OFFSET 9
77#define DPMS_MASK (3 << DPMS_OFFSET)
78#define DPMS_USAGE (DPMS_MASK << 16)
79#define DPMS_OFF ((3 << DPMS_OFFSET)|DPMS_USAGE)
80#define DPMS_ON ((0 << DPMS_OFFSET)|DPMS_USAGE)
81
82
83
84/*
85	LCD1 means panel path TFT1  & panel path DVI (so enable DAC)
86	CRT means crt path DSUB
87*/
88#if 0
89typedef enum _disp_output_t
90{
91	NO_DISPLAY = DPMS_OFF,
92
93	LCD1_PRI = PNL_2_PRI|PRI_TP_ON|PNL_SEQ_ON|DPMS_OFF|DAC_ON,
94	LCD1_SEC = PNL_2_SEC|SEC_TP_ON|PNL_SEQ_ON|DPMS_OFF|DAC_ON,
95
96	LCD2_PRI = CRT_2_PRI|PRI_TP_ON|DUAL_TFT_ON|DPMS_OFF,
97	LCD2_SEC = CRT_2_SEC|SEC_TP_ON|DUAL_TFT_ON|DPMS_OFF,
98
99	DSUB_PRI = CRT_2_PRI|PRI_TP_ON|DAC_ON,
100	DSUB_SEC = CRT_2_SEC|SEC_TP_ON|DAC_ON,
101
102	LCD1_DSUB_PRI = PNL_2_PRI|PRI_TP_ON|PNL_SEQ_ON|
103					CRT_2_PRI|SEC_TP_OFF|DAC_ON,
104
105	LCD1_DSUB_SEC = PNL_2_SEC|SEC_TP_ON|PNL_SEQ_ON|
106					CRT_2_SEC|PRI_TP_OFF|DAC_ON,
107
108	/* LCD1 show primary and DSUB show secondary */
109	LCD1_DSUB_DUAL = PNL_2_PRI|PRI_TP_ON|PNL_SEQ_ON|
110					 CRT_2_SEC|SEC_TP_ON|DAC_ON,
111
112	/* LCD1 show secondary and DSUB show primary */
113	LCD1_DSUB_DUAL_SWAP = PNL_2_SEC|SEC_TP_ON|PNL_SEQ_ON|
114							CRT_2_PRI|PRI_TP_ON|DAC_ON,
115
116	LCD1_LCD2_PRI = PNL_2_PRI|PRI_TP_ON|PNL_SEQ_ON|
117					CRT_2_PRI|SEC_TP_OFF|DPMS_OFF|DUAL_TFT_ON,
118
119	LCD1_LCD2_SEC = PNL_2_SEC|SEC_TP_ON|PNL_SEQ_ON|
120					CRT_2_SEC|PRI_TP_OFF|DPMS_OFF|DUAL_TFT_ON,
121
122	LCD1_LCD2_DSUB_PRI = PNL_2_PRI|PRI_TP_ON|PNL_SEQ_ON|DAC_ON|
123						CRT_2_PRI|SEC_TP_OFF|DPMS_ON|DUAL_TFT_ON,
124
125	LCD1_LCD2_DSUB_SEC = PNL_2_SEC|SEC_TP_ON|PNL_SEQ_ON|DAC_ON|
126						CRT_2_SEC|PRI_TP_OFF|DPMS_ON|DUAL_TFT_ON,
127
128
129}
130disp_output_t;
131#else
132typedef enum _disp_output_t{
133	do_LCD1_PRI = PNL_2_PRI|PRI_TP_ON|PNL_SEQ_ON|DAC_ON,
134	do_LCD1_SEC = PNL_2_SEC|SEC_TP_ON|PNL_SEQ_ON|DAC_ON,
135#if 0
136	do_LCD2_PRI = CRT_2_PRI|PRI_TP_ON,
137	do_LCD2_SEC = CRT_2_SEC|SEC_TP_ON,
138#else
139	do_LCD2_PRI = CRT_2_PRI|PRI_TP_ON|DUAL_TFT_ON,
140	do_LCD2_SEC = CRT_2_SEC|SEC_TP_ON|DUAL_TFT_ON,
141#endif
142	/*
143	do_DSUB_PRI = CRT_2_PRI|PRI_TP_ON|DPMS_ON|DAC_ON,
144	do_DSUB_SEC = CRT_2_SEC|SEC_TP_ON|DPMS_ON|DAC_ON,
145	*/
146#if 0
147	do_CRT_PRI = CRT_2_PRI|PRI_TP_ON,
148	do_CRT_SEC = CRT_2_SEC|SEC_TP_ON,
149#else
150	do_CRT_PRI = CRT_2_PRI|PRI_TP_ON|DPMS_ON|DAC_ON,
151	do_CRT_SEC = CRT_2_SEC|SEC_TP_ON|DPMS_ON|DAC_ON,
152#endif
153}
154disp_output_t;
155#endif
156
157void ddk750_setLogicalDispOut(disp_output_t);
158int ddk750_initDVIDisp(void);
159
160#endif
161