1/****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * 15 ******************************************************************************/ 16#ifndef __INC_HAL8723APHYREG_H__ 17#define __INC_HAL8723APHYREG_H__ 18 19/* 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF */ 20/* 1. Page1(0x100) */ 21#define rPMAC_Reset 0x100 22#define rPMAC_TxStart 0x104 23#define rPMAC_TxLegacySIG 0x108 24#define rPMAC_TxHTSIG1 0x10c 25#define rPMAC_TxHTSIG2 0x110 26#define rPMAC_PHYDebug 0x114 27#define rPMAC_TxPacketNum 0x118 28#define rPMAC_TxIdle 0x11c 29#define rPMAC_TxMACHeader0 0x120 30#define rPMAC_TxMACHeader1 0x124 31#define rPMAC_TxMACHeader2 0x128 32#define rPMAC_TxMACHeader3 0x12c 33#define rPMAC_TxMACHeader4 0x130 34#define rPMAC_TxMACHeader5 0x134 35#define rPMAC_TxDataType 0x138 36#define rPMAC_TxRandomSeed 0x13c 37#define rPMAC_CCKPLCPPreamble 0x140 38#define rPMAC_CCKPLCPHeader 0x144 39#define rPMAC_CCKCRC16 0x148 40#define rPMAC_OFDMRxCRC32OK 0x170 41#define rPMAC_OFDMRxCRC32Er 0x174 42#define rPMAC_OFDMRxParityEr 0x178 43#define rPMAC_OFDMRxCRC8Er 0x17c 44#define rPMAC_CCKCRxRC16Er 0x180 45#define rPMAC_CCKCRxRC32Er 0x184 46#define rPMAC_CCKCRxRC32OK 0x188 47#define rPMAC_TxStatus 0x18c 48 49/* 2. Page2(0x200) */ 50/* The following two definition are only used for USB interface. */ 51#define RF_BB_CMD_ADDR 0x02c0 /* RF/BB read/write command address. */ 52#define RF_BB_CMD_DATA 0x02c4 /* RF/BB read/write command data. */ 53 54/* 3. Page8(0x800) */ 55#define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC RF BW Setting?? */ 56 57#define rFPGA0_TxInfo 0x804 /* Status report?? */ 58#define rFPGA0_PSDFunction 0x808 59 60#define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */ 61 62#define rFPGA0_RFTiming1 0x810 /* Useless now */ 63#define rFPGA0_RFTiming2 0x814 64 65#define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */ 66#define rFPGA0_XA_HSSIParameter2 0x824 67#define rFPGA0_XB_HSSIParameter1 0x828 68#define rFPGA0_XB_HSSIParameter2 0x82c 69#define rTxAGC_B_Rate18_06 0x830 70#define rTxAGC_B_Rate54_24 0x834 71#define rTxAGC_B_CCK1_55_Mcs32 0x838 72#define rTxAGC_B_Mcs03_Mcs00 0x83c 73 74#define rTxAGC_B_Mcs07_Mcs04 0x848 75#define rTxAGC_B_Mcs11_Mcs08 0x84c 76 77#define rFPGA0_XA_LSSIParameter 0x840 78#define rFPGA0_XB_LSSIParameter 0x844 79 80#define rFPGA0_RFWakeUpParameter 0x850 /* Useless now */ 81#define rFPGA0_RFSleepUpParameter 0x854 82 83#define rFPGA0_XAB_SwitchControl 0x858 /* RF Channel switch */ 84#define rFPGA0_XCD_SwitchControl 0x85c 85 86#define rFPGA0_XA_RFInterfaceOE 0x860 /* RF Channel switch */ 87#define rFPGA0_XB_RFInterfaceOE 0x864 88 89#define rTxAGC_B_Mcs15_Mcs12 0x868 90#define rTxAGC_B_CCK11_A_CCK2_11 0x86c 91 92#define rFPGA0_XAB_RFInterfaceSW 0x870 /* RF Interface Software Control */ 93#define rFPGA0_XCD_RFInterfaceSW 0x874 94 95#define rFPGA0_XAB_RFParameter 0x878 /* RF Parameter */ 96#define rFPGA0_XCD_RFParameter 0x87c 97 98#define rFPGA0_AnalogParameter1 0x880 /* Crystal cap setting RF-R/W protection for parameter4?? */ 99#define rFPGA0_AnalogParameter2 0x884 100#define rFPGA0_AnalogParameter3 0x888 /* Useless now */ 101#define rFPGA0_AnalogParameter4 0x88c 102 103#define rFPGA0_XA_LSSIReadBack 0x8a0 /* Tranceiver LSSI Readback */ 104#define rFPGA0_XB_LSSIReadBack 0x8a4 105#define rFPGA0_XC_LSSIReadBack 0x8a8 106#define rFPGA0_XD_LSSIReadBack 0x8ac 107 108#define rFPGA0_PSDReport 0x8b4 /* Useless now */ 109#define TransceiverA_HSPI_Readback 0x8b8 /* Transceiver A HSPI Readback */ 110#define TransceiverB_HSPI_Readback 0x8bc /* Transceiver B HSPI Readback */ 111#define rFPGA0_XAB_RFInterfaceRB 0x8e0 /* Useless now RF Interface Readback Value */ 112#define rFPGA0_XCD_RFInterfaceRB 0x8e4 /* Useless now */ 113 114/* 4. Page9(0x900) */ 115#define rFPGA1_RFMOD 0x900 /* RF mode & OFDM TxSC RF BW Setting?? */ 116 117#define rFPGA1_TxBlock 0x904 /* Useless now */ 118#define rFPGA1_DebugSelect 0x908 /* Useless now */ 119#define rFPGA1_TxInfo 0x90c /* Useless now Status report?? */ 120 121/* 5. PageA(0xA00) */ 122/* Set Control channel to upper or lower. These settings are required only for 40MHz */ 123#define rCCK0_System 0xa00 124 125#define rCCK0_AFESetting 0xa04 /* Disable init gain now Select RX path by RSSI */ 126#define rCCK0_CCA 0xa08 /* Disable init gain now Init gain */ 127 128#define rCCK0_RxAGC1 0xa0c /* AGC default value, saturation level Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series */ 129#define rCCK0_RxAGC2 0xa10 /* AGC & DAGC */ 130 131#define rCCK0_RxHP 0xa14 132 133#define rCCK0_DSPParameter1 0xa18 /* Timing recovery & Channel estimation threshold */ 134#define rCCK0_DSPParameter2 0xa1c /* SQ threshold */ 135 136#define rCCK0_TxFilter1 0xa20 137#define rCCK0_TxFilter2 0xa24 138#define rCCK0_DebugPort 0xa28 /* debug port and Tx filter3 */ 139#define rCCK0_FalseAlarmReport 0xa2c /* 0xa2d useless now 0xa30-a4f channel report */ 140#define rCCK0_TRSSIReport 0xa50 141#define rCCK0_RxReport 0xa54 /* 0xa57 */ 142#define rCCK0_FACounterLower 0xa5c /* 0xa5b */ 143#define rCCK0_FACounterUpper 0xa58 /* 0xa5c */ 144/* PageB(0xB00) */ 145#define rPdp_AntA 0xb00 146#define rPdp_AntA_4 0xb04 147#define rConfig_Pmpd_AntA 0xb28 148#define rConfig_AntA 0xb68 149#define rConfig_AntB 0xb6c 150#define rPdp_AntB 0xb70 151#define rPdp_AntB_4 0xb74 152#define rConfig_Pmpd_AntB 0xb98 153#define rAPK 0xbd8 154 155/* 6. PageC(0xC00) */ 156#define rOFDM0_LSTF 0xc00 157 158#define rOFDM0_TRxPathEnable 0xc04 159#define rOFDM0_TRMuxPar 0xc08 160#define rOFDM0_TRSWIsolation 0xc0c 161 162#define rOFDM0_XARxAFE 0xc10 /* RxIQ DC offset, Rx digital filter, DC notch filter */ 163#define rOFDM0_XARxIQImbalance 0xc14 /* RxIQ imblance matrix */ 164#define rOFDM0_XBRxAFE 0xc18 165#define rOFDM0_XBRxIQImbalance 0xc1c 166#define rOFDM0_XCRxAFE 0xc20 167#define rOFDM0_XCRxIQImbalance 0xc24 168#define rOFDM0_XDRxAFE 0xc28 169#define rOFDM0_XDRxIQImbalance 0xc2c 170 171#define rOFDM0_RxDetector1 0xc30 /* PD,BW & SBD DM tune init gain */ 172#define rOFDM0_RxDetector2 0xc34 /* SBD & Fame Sync. */ 173#define rOFDM0_RxDetector3 0xc38 /* Frame Sync. */ 174#define rOFDM0_RxDetector4 0xc3c /* PD, SBD, Frame Sync & Short-GI */ 175 176#define rOFDM0_RxDSP 0xc40 /* Rx Sync Path */ 177#define rOFDM0_CFOandDAGC 0xc44 /* CFO & DAGC */ 178#define rOFDM0_CCADropThreshold 0xc48 /* CCA Drop threshold */ 179#define rOFDM0_ECCAThreshold 0xc4c /* energy CCA */ 180 181#define rOFDM0_XAAGCCore1 0xc50 /* DIG */ 182#define rOFDM0_XAAGCCore2 0xc54 183#define rOFDM0_XBAGCCore1 0xc58 184#define rOFDM0_XBAGCCore2 0xc5c 185#define rOFDM0_XCAGCCore1 0xc60 186#define rOFDM0_XCAGCCore2 0xc64 187#define rOFDM0_XDAGCCore1 0xc68 188#define rOFDM0_XDAGCCore2 0xc6c 189 190#define rOFDM0_AGCParameter1 0xc70 191#define rOFDM0_AGCParameter2 0xc74 192#define rOFDM0_AGCRSSITable 0xc78 193#define rOFDM0_HTSTFAGC 0xc7c 194 195#define rOFDM0_XATxIQImbalance 0xc80 /* TX PWR TRACK and DIG */ 196#define rOFDM0_XATxAFE 0xc84 197#define rOFDM0_XBTxIQImbalance 0xc88 198#define rOFDM0_XBTxAFE 0xc8c 199#define rOFDM0_XCTxIQImbalance 0xc90 200#define rOFDM0_XCTxAFE 0xc94 201#define rOFDM0_XDTxIQImbalance 0xc98 202#define rOFDM0_XDTxAFE 0xc9c 203 204#define rOFDM0_RxIQExtAnta 0xca0 205#define rOFDM0_TxCoeff1 0xca4 206#define rOFDM0_TxCoeff2 0xca8 207#define rOFDM0_TxCoeff3 0xcac 208#define rOFDM0_TxCoeff4 0xcb0 209#define rOFDM0_TxCoeff5 0xcb4 210#define rOFDM0_TxCoeff6 0xcb8 211#define rOFDM0_RxHPParameter 0xce0 212#define rOFDM0_TxPseudoNoiseWgt 0xce4 213#define rOFDM0_FrameSync 0xcf0 214#define rOFDM0_DFSReport 0xcf4 215 216/* 7. PageD(0xD00) */ 217#define rOFDM1_LSTF 0xd00 218#define rOFDM1_TRxPathEnable 0xd04 219 220#define rOFDM1_CFO 0xd08 /* No setting now */ 221#define rOFDM1_CSI1 0xd10 222#define rOFDM1_SBD 0xd14 223#define rOFDM1_CSI2 0xd18 224#define rOFDM1_CFOTracking 0xd2c 225#define rOFDM1_TRxMesaure1 0xd34 226#define rOFDM1_IntfDet 0xd3c 227#define rOFDM1_PseudoNoiseStateAB 0xd50 228#define rOFDM1_PseudoNoiseStateCD 0xd54 229#define rOFDM1_RxPseudoNoiseWgt 0xd58 230 231#define rOFDM_PHYCounter1 0xda0 /* cca, parity fail */ 232#define rOFDM_PHYCounter2 0xda4 /* rate illegal, crc8 fail */ 233#define rOFDM_PHYCounter3 0xda8 /* MCS not support */ 234 235#define rOFDM_ShortCFOAB 0xdac /* No setting now */ 236#define rOFDM_ShortCFOCD 0xdb0 237#define rOFDM_LongCFOAB 0xdb4 238#define rOFDM_LongCFOCD 0xdb8 239#define rOFDM_TailCFOAB 0xdbc 240#define rOFDM_TailCFOCD 0xdc0 241#define rOFDM_PWMeasure1 0xdc4 242#define rOFDM_PWMeasure2 0xdc8 243#define rOFDM_BWReport 0xdcc 244#define rOFDM_AGCReport 0xdd0 245#define rOFDM_RxSNR 0xdd4 246#define rOFDM_RxEVMCSI 0xdd8 247#define rOFDM_SIGReport 0xddc 248 249 250/* 8. PageE(0xE00) */ 251#define rTxAGC_A_Rate18_06 0xe00 252#define rTxAGC_A_Rate54_24 0xe04 253#define rTxAGC_A_CCK1_Mcs32 0xe08 254#define rTxAGC_A_Mcs03_Mcs00 0xe10 255#define rTxAGC_A_Mcs07_Mcs04 0xe14 256#define rTxAGC_A_Mcs11_Mcs08 0xe18 257#define rTxAGC_A_Mcs15_Mcs12 0xe1c 258 259#define rFPGA0_IQK 0xe28 260#define rTx_IQK_Tone_A 0xe30 261#define rRx_IQK_Tone_A 0xe34 262#define rTx_IQK_PI_A 0xe38 263#define rRx_IQK_PI_A 0xe3c 264 265#define rTx_IQK 0xe40 266#define rRx_IQK 0xe44 267#define rIQK_AGC_Pts 0xe48 268#define rIQK_AGC_Rsp 0xe4c 269#define rTx_IQK_Tone_B 0xe50 270#define rRx_IQK_Tone_B 0xe54 271#define rTx_IQK_PI_B 0xe58 272#define rRx_IQK_PI_B 0xe5c 273#define rIQK_AGC_Cont 0xe60 274 275#define rBlue_Tooth 0xe6c 276#define rRx_Wait_CCA 0xe70 277#define rTx_CCK_RFON 0xe74 278#define rTx_CCK_BBON 0xe78 279#define rTx_OFDM_RFON 0xe7c 280#define rTx_OFDM_BBON 0xe80 281#define rTx_To_Rx 0xe84 282#define rTx_To_Tx 0xe88 283#define rRx_CCK 0xe8c 284 285#define rTx_Power_Before_IQK_A 0xe94 286#define rTx_Power_After_IQK_A 0xe9c 287 288#define rRx_Power_Before_IQK_A 0xea0 289#define rRx_Power_Before_IQK_A_2 0xea4 290#define rRx_Power_After_IQK_A 0xea8 291#define rRx_Power_After_IQK_A_2 0xeac 292 293#define rTx_Power_Before_IQK_B 0xeb4 294#define rTx_Power_After_IQK_B 0xebc 295 296#define rRx_Power_Before_IQK_B 0xec0 297#define rRx_Power_Before_IQK_B_2 0xec4 298#define rRx_Power_After_IQK_B 0xec8 299#define rRx_Power_After_IQK_B_2 0xecc 300 301#define rRx_OFDM 0xed0 302#define rRx_Wait_RIFS 0xed4 303#define rRx_TO_Rx 0xed8 304#define rStandby 0xedc 305#define rSleep 0xee0 306#define rPMPD_ANAEN 0xeec 307 308/* 7. RF Register 0x00-0x2E (RF 8256) */ 309/* RF-0222D 0x00-3F */ 310/* Zebra1 */ 311#define rZebra1_HSSIEnable 0x0 /* Useless now */ 312#define rZebra1_TRxEnable1 0x1 313#define rZebra1_TRxEnable2 0x2 314#define rZebra1_AGC 0x4 315#define rZebra1_ChargePump 0x5 316#define rZebra1_Channel 0x7 /* RF channel switch */ 317 318#define rZebra1_TxGain 0x8 /* Useless now */ 319#define rZebra1_TxLPF 0x9 320#define rZebra1_RxLPF 0xb 321#define rZebra1_RxHPFCorner 0xc 322 323/* Zebra4 */ 324#define rGlobalCtrl 0 /* Useless now */ 325#define rRTL8256_TxLPF 19 326#define rRTL8256_RxLPF 11 327 328/* RTL8258 */ 329#define rRTL8258_TxLPF 0x11 /* Useless now */ 330#define rRTL8258_RxLPF 0x13 331#define rRTL8258_RSSILPF 0xa 332 333/* RL6052 Register definition */ 334#define RF_AC 0x00 335#define RF_IQADJ_G1 0x01 336#define RF_IQADJ_G2 0x02 337#define RF_BS_PA_APSET_G1_G4 0x03 338#define RF_BS_PA_APSET_G5_G8 0x04 339#define RF_POW_TRSW 0x05 340#define RF_GAIN_RX 0x06 341#define RF_GAIN_TX 0x07 342#define RF_TXM_IDAC 0x08 343#define RF_IPA_G 0x09 344#define RF_TXBIAS_G 0x0A 345#define RF_TXPA_AG 0x0B 346#define RF_IPA_A 0x0C 347#define RF_TXBIAS_A 0x0D 348#define RF_BS_PA_APSET_G9_G11 0x0E 349#define RF_BS_IQGEN 0x0F 350#define RF_MODE1 0x10 351#define RF_MODE2 0x11 352#define RF_RX_AGC_HP 0x12 353#define RF_TX_AGC 0x13 354#define RF_BIAS 0x14 355#define RF_IPA 0x15 356#define RF_TXBIAS 0x16 357#define RF_POW_ABILITY 0x17 358#define RF_MODE_AG 0x18 359#define rRfChannel 0x18 /* RF channel and BW switch */ 360#define RF_CHNLBW 0x18 /* RF channel and BW switch */ 361#define RF_TOP 0x19 362#define RF_RX_G1 0x1A 363#define RF_RX_G2 0x1B 364#define RF_RX_BB2 0x1C 365#define RF_RX_BB1 0x1D 366#define RF_RCK1 0x1E 367#define RF_RCK2 0x1F 368#define RF_TX_G1 0x20 369#define RF_TX_G2 0x21 370#define RF_TX_G3 0x22 371#define RF_TX_BB1 0x23 372#define RF_T_METER 0x24 373#define RF_SYN_G1 0x25 /* RF TX Power control */ 374#define RF_SYN_G2 0x26 /* RF TX Power control */ 375#define RF_SYN_G3 0x27 /* RF TX Power control */ 376#define RF_SYN_G4 0x28 /* RF TX Power control */ 377#define RF_SYN_G5 0x29 /* RF TX Power control */ 378#define RF_SYN_G6 0x2A /* RF TX Power control */ 379#define RF_SYN_G7 0x2B /* RF TX Power control */ 380#define RF_SYN_G8 0x2C /* RF TX Power control */ 381 382#define RF_RCK_OS 0x30 /* RF TX PA control */ 383 384#define RF_TXPA_G1 0x31 /* RF TX PA control */ 385#define RF_TXPA_G2 0x32 /* RF TX PA control */ 386#define RF_TXPA_G3 0x33 /* RF TX PA control */ 387 388/* Bit Mask */ 389/* 1. Page1(0x100) */ 390#define bBBResetB 0x100 /* Useless now? */ 391#define bGlobalResetB 0x200 392#define bOFDMTxStart 0x4 393#define bCCKTxStart 0x8 394#define bCRC32Debug 0x100 395#define bPMACLoopback 0x10 396#define bTxLSIG 0xffffff 397#define bOFDMTxRate 0xf 398#define bOFDMTxReserved 0x10 399#define bOFDMTxLength 0x1ffe0 400#define bOFDMTxParity 0x20000 401#define bTxHTSIG1 0xffffff 402#define bTxHTMCSRate 0x7f 403#define bTxHTBW 0x80 404#define bTxHTLength 0xffff00 405#define bTxHTSIG2 0xffffff 406#define bTxHTSmoothing 0x1 407#define bTxHTSounding 0x2 408#define bTxHTReserved 0x4 409#define bTxHTAggreation 0x8 410#define bTxHTSTBC 0x30 411#define bTxHTAdvanceCoding 0x40 412#define bTxHTShortGI 0x80 413#define bTxHTNumberHT_LTF 0x300 414#define bTxHTCRC8 0x3fc00 415#define bCounterReset 0x10000 416#define bNumOfOFDMTx 0xffff 417#define bNumOfCCKTx 0xffff0000 418#define bTxIdleInterval 0xffff 419#define bOFDMService 0xffff0000 420#define bTxMACHeader 0xffffffff 421#define bTxDataInit 0xff 422#define bTxHTMode 0x100 423#define bTxDataType 0x30000 424#define bTxRandomSeed 0xffffffff 425#define bCCKTxPreamble 0x1 426#define bCCKTxSFD 0xffff0000 427#define bCCKTxSIG 0xff 428#define bCCKTxService 0xff00 429#define bCCKLengthExt 0x8000 430#define bCCKTxLength 0xffff0000 431#define bCCKTxCRC16 0xffff 432#define bCCKTxStatus 0x1 433#define bOFDMTxStatus 0x2 434 435#define IS_BB_REG_OFFSET_92S(_Offset) \ 436 ((_Offset >= 0x800) && (_Offset <= 0xfff)) 437 438/* 2. Page8(0x800) */ 439#define bRFMOD 0x1 /* Reg 0x800 rFPGA0_RFMOD */ 440#define bJapanMode 0x2 441#define bCCKTxSC 0x30 442#define bCCKEn 0x1000000 443#define bOFDMEn 0x2000000 444 445#define bOFDMRxADCPhase 0x10000 /* Useless now */ 446#define bOFDMTxDACPhase 0x40000 447#define bXATxAGC 0x3f 448 449#define bAntennaSelect 0x0300 450 451#define bXBTxAGC 0xf00 /* Reg 80c rFPGA0_TxGainStage */ 452#define bXCTxAGC 0xf000 453#define bXDTxAGC 0xf0000 454 455#define bPAStart 0xf0000000 /* Useless now */ 456#define bTRStart 0x00f00000 457#define bRFStart 0x0000f000 458#define bBBStart 0x000000f0 459#define bBBCCKStart 0x0000000f 460#define bPAEnd 0xf /* Reg0x814 */ 461#define bTREnd 0x0f000000 462#define bRFEnd 0x000f0000 463#define bCCAMask 0x000000f0 /* T2R */ 464#define bR2RCCAMask 0x00000f00 465#define bHSSI_R2TDelay 0xf8000000 466#define bHSSI_T2RDelay 0xf80000 467#define bContTxHSSI 0x400 /* chane gain at continue Tx */ 468#define bIGFromCCK 0x200 469#define bAGCAddress 0x3f 470#define bRxHPTx 0x7000 471#define bRxHPT2R 0x38000 472#define bRxHPCCKIni 0xc0000 473#define bAGCTxCode 0xc00000 474#define bAGCRxCode 0x300000 475 476#define b3WireDataLength 0x800 /* Reg 0x820~84f rFPGA0_XA_HSSIParameter1 */ 477#define b3WireAddressLength 0x400 478 479#define b3WireRFPowerDown 0x1 /* Useless now */ 480/* define bHWSISelect 0x8 */ 481#define b5GPAPEPolarity 0x40000000 482#define b2GPAPEPolarity 0x80000000 483#define bRFSW_TxDefaultAnt 0x3 484#define bRFSW_TxOptionAnt 0x30 485#define bRFSW_RxDefaultAnt 0x300 486#define bRFSW_RxOptionAnt 0x3000 487#define bRFSI_3WireData 0x1 488#define bRFSI_3WireClock 0x2 489#define bRFSI_3WireLoad 0x4 490#define bRFSI_3WireRW 0x8 491#define bRFSI_3Wire 0xf 492 493#define bRFSI_RFENV 0x10 /* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */ 494 495#define bRFSI_TRSW 0x20 /* Useless now */ 496#define bRFSI_TRSWB 0x40 497#define bRFSI_ANTSW 0x100 498#define bRFSI_ANTSWB 0x200 499#define bRFSI_PAPE 0x400 500#define bRFSI_PAPE5G 0x800 501#define bBandSelect 0x1 502#define bHTSIG2_GI 0x80 503#define bHTSIG2_Smoothing 0x01 504#define bHTSIG2_Sounding 0x02 505#define bHTSIG2_Aggreaton 0x08 506#define bHTSIG2_STBC 0x30 507#define bHTSIG2_AdvCoding 0x40 508#define bHTSIG2_NumOfHTLTF 0x300 509#define bHTSIG2_CRC8 0x3fc 510#define bHTSIG1_MCS 0x7f 511#define bHTSIG1_BandWidth 0x80 512#define bHTSIG1_HTLength 0xffff 513#define bLSIG_Rate 0xf 514#define bLSIG_Reserved 0x10 515#define bLSIG_Length 0x1fffe 516#define bLSIG_Parity 0x20 517#define bCCKRxPhase 0x4 518 519#define bLSSIReadAddress 0x7f800000 /* T65 RF */ 520 521#define bLSSIReadEdge 0x80000000 /* LSSI "Read" edge signal */ 522 523#define bLSSIReadBackData 0xfffff /* T65 RF */ 524 525#define bLSSIReadOKFlag 0x1000 /* Useless now */ 526#define bCCKSampleRate 0x8 /* 0: 44MHz, 1:88MHz */ 527#define bRegulator0Standby 0x1 528#define bRegulatorPLLStandby 0x2 529#define bRegulator1Standby 0x4 530#define bPLLPowerUp 0x8 531#define bDPLLPowerUp 0x10 532#define bDA10PowerUp 0x20 533#define bAD7PowerUp 0x200 534#define bDA6PowerUp 0x2000 535#define bXtalPowerUp 0x4000 536#define b40MDClkPowerUP 0x8000 537#define bDA6DebugMode 0x20000 538#define bDA6Swing 0x380000 539 540#define bADClkPhase 0x4000000 /* Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */ 541 542#define b80MClkDelay 0x18000000 /* Useless */ 543#define bAFEWatchDogEnable 0x20000000 544 545#define bXtalCap01 0xc0000000 /* Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap */ 546#define bXtalCap23 0x3 547#define bXtalCap92x 0x0f000000 548#define bXtalCap 0x0f000000 549 550#define bIntDifClkEnable 0x400 /* Useless */ 551#define bExtSigClkEnable 0x800 552#define bBandgapMbiasPowerUp 0x10000 553#define bAD11SHGain 0xc0000 554#define bAD11InputRange 0x700000 555#define bAD11OPCurrent 0x3800000 556#define bIPathLoopback 0x4000000 557#define bQPathLoopback 0x8000000 558#define bAFELoopback 0x10000000 559#define bDA10Swing 0x7e0 560#define bDA10Reverse 0x800 561#define bDAClkSource 0x1000 562#define bAD7InputRange 0x6000 563#define bAD7Gain 0x38000 564#define bAD7OutputCMMode 0x40000 565#define bAD7InputCMMode 0x380000 566#define bAD7Current 0xc00000 567#define bRegulatorAdjust 0x7000000 568#define bAD11PowerUpAtTx 0x1 569#define bDA10PSAtTx 0x10 570#define bAD11PowerUpAtRx 0x100 571#define bDA10PSAtRx 0x1000 572#define bCCKRxAGCFormat 0x200 573#define bPSDFFTSamplepPoint 0xc000 574#define bPSDAverageNum 0x3000 575#define bIQPathControl 0xc00 576#define bPSDFreq 0x3ff 577#define bPSDAntennaPath 0x30 578#define bPSDIQSwitch 0x40 579#define bPSDRxTrigger 0x400000 580#define bPSDTxTrigger 0x80000000 581#define bPSDSineToneScale 0x7f000000 582#define bPSDReport 0xffff 583 584/* 3. Page9(0x900) */ 585#define bOFDMTxSC 0x30000000 /* Useless */ 586#define bCCKTxOn 0x1 587#define bOFDMTxOn 0x2 588#define bDebugPage 0xfff /* reset debug page and also HWord, LWord */ 589#define bDebugItem 0xff /* reset debug page and LWord */ 590#define bAntL 0x10 591#define bAntNonHT 0x100 592#define bAntHT1 0x1000 593#define bAntHT2 0x10000 594#define bAntHT1S1 0x100000 595#define bAntNonHTS1 0x1000000 596 597/* 4. PageA(0xA00) */ 598#define bCCKBBMode 0x3 /* Useless */ 599#define bCCKTxPowerSaving 0x80 600#define bCCKRxPowerSaving 0x40 601 602#define bCCKSideBand 0x10 /* Reg 0xa00 rCCK0_System 20/40 switch */ 603 604#define bCCKScramble 0x8 /* Useless */ 605#define bCCKAntDiversity 0x8000 606#define bCCKCarrierRecovery 0x4000 607#define bCCKTxRate 0x3000 608#define bCCKDCCancel 0x0800 609#define bCCKISICancel 0x0400 610#define bCCKMatchFilter 0x0200 611#define bCCKEqualizer 0x0100 612#define bCCKPreambleDetect 0x800000 613#define bCCKFastFalseCCA 0x400000 614#define bCCKChEstStart 0x300000 615#define bCCKCCACount 0x080000 616#define bCCKcs_lim 0x070000 617#define bCCKBistMode 0x80000000 618#define bCCKCCAMask 0x40000000 619#define bCCKTxDACPhase 0x4 620#define bCCKRxADCPhase 0x20000000 /* r_rx_clk */ 621#define bCCKr_cp_mode0 0x0100 622#define bCCKTxDCOffset 0xf0 623#define bCCKRxDCOffset 0xf 624#define bCCKCCAMode 0xc000 625#define bCCKFalseCS_lim 0x3f00 626#define bCCKCS_ratio 0xc00000 627#define bCCKCorgBit_sel 0x300000 628#define bCCKPD_lim 0x0f0000 629#define bCCKNewCCA 0x80000000 630#define bCCKRxHPofIG 0x8000 631#define bCCKRxIG 0x7f00 632#define bCCKLNAPolarity 0x800000 633#define bCCKRx1stGain 0x7f0000 634#define bCCKRFExtend 0x20000000 /* CCK Rx Iinital gain polarity */ 635#define bCCKRxAGCSatLevel 0x1f000000 636#define bCCKRxAGCSatCount 0xe0 637#define bCCKRxRFSettle 0x1f /* AGCsamp_dly */ 638#define bCCKFixedRxAGC 0x8000 639/* define bCCKRxAGCFormat 0x4000 remove to HSSI register 0x824 */ 640#define bCCKAntennaPolarity 0x2000 641#define bCCKTxFilterType 0x0c00 642#define bCCKRxAGCReportType 0x0300 643#define bCCKRxDAGCEn 0x80000000 644#define bCCKRxDAGCPeriod 0x20000000 645#define bCCKRxDAGCSatLevel 0x1f000000 646#define bCCKTimingRecovery 0x800000 647#define bCCKTxC0 0x3f0000 648#define bCCKTxC1 0x3f000000 649#define bCCKTxC2 0x3f 650#define bCCKTxC3 0x3f00 651#define bCCKTxC4 0x3f0000 652#define bCCKTxC5 0x3f000000 653#define bCCKTxC6 0x3f 654#define bCCKTxC7 0x3f00 655#define bCCKDebugPort 0xff0000 656#define bCCKDACDebug 0x0f000000 657#define bCCKFalseAlarmEnable 0x8000 658#define bCCKFalseAlarmRead 0x4000 659#define bCCKTRSSI 0x7f 660#define bCCKRxAGCReport 0xfe 661#define bCCKRxReport_AntSel 0x80000000 662#define bCCKRxReport_MFOff 0x40000000 663#define bCCKRxRxReport_SQLoss 0x20000000 664#define bCCKRxReport_Pktloss 0x10000000 665#define bCCKRxReport_Lockedbit 0x08000000 666#define bCCKRxReport_RateError 0x04000000 667#define bCCKRxReport_RxRate 0x03000000 668#define bCCKRxFACounterLower 0xff 669#define bCCKRxFACounterUpper 0xff000000 670#define bCCKRxHPAGCStart 0xe000 671#define bCCKRxHPAGCFinal 0x1c00 672#define bCCKRxFalseAlarmEnable 0x8000 673#define bCCKFACounterFreeze 0x4000 674#define bCCKTxPathSel 0x10000000 675#define bCCKDefaultRxPath 0xc000000 676#define bCCKOptionRxPath 0x3000000 677 678/* 5. PageC(0xC00) */ 679#define bNumOfSTF 0x3 /* Useless */ 680#define bShift_L 0xc0 681#define bGI_TH 0xc 682#define bRxPathA 0x1 683#define bRxPathB 0x2 684#define bRxPathC 0x4 685#define bRxPathD 0x8 686#define bTxPathA 0x1 687#define bTxPathB 0x2 688#define bTxPathC 0x4 689#define bTxPathD 0x8 690#define bTRSSIFreq 0x200 691#define bADCBackoff 0x3000 692#define bDFIRBackoff 0xc000 693#define bTRSSILatchPhase 0x10000 694#define bRxIDCOffset 0xff 695#define bRxQDCOffset 0xff00 696#define bRxDFIRMode 0x1800000 697#define bRxDCNFType 0xe000000 698#define bRXIQImb_A 0x3ff 699#define bRXIQImb_B 0xfc00 700#define bRXIQImb_C 0x3f0000 701#define bRXIQImb_D 0xffc00000 702#define bDC_dc_Notch 0x60000 703#define bRxNBINotch 0x1f000000 704#define bPD_TH 0xf 705#define bPD_TH_Opt2 0xc000 706#define bPWED_TH 0x700 707#define bIfMF_Win_L 0x800 708#define bPD_Option 0x1000 709#define bMF_Win_L 0xe000 710#define bBW_Search_L 0x30000 711#define bwin_enh_L 0xc0000 712#define bBW_TH 0x700000 713#define bED_TH2 0x3800000 714#define bBW_option 0x4000000 715#define bRatio_TH 0x18000000 716#define bWindow_L 0xe0000000 717#define bSBD_Option 0x1 718#define bFrame_TH 0x1c 719#define bFS_Option 0x60 720#define bDC_Slope_check 0x80 721#define bFGuard_Counter_DC_L 0xe00 722#define bFrame_Weight_Short 0x7000 723#define bSub_Tune 0xe00000 724#define bFrame_DC_Length 0xe000000 725#define bSBD_start_offset 0x30000000 726#define bFrame_TH_2 0x7 727#define bFrame_GI2_TH 0x38 728#define bGI2_Sync_en 0x40 729#define bSarch_Short_Early 0x300 730#define bSarch_Short_Late 0xc00 731#define bSarch_GI2_Late 0x70000 732#define bCFOAntSum 0x1 733#define bCFOAcc 0x2 734#define bCFOStartOffset 0xc 735#define bCFOLookBack 0x70 736#define bCFOSumWeight 0x80 737#define bDAGCEnable 0x10000 738#define bTXIQImb_A 0x3ff 739#define bTXIQImb_B 0xfc00 740#define bTXIQImb_C 0x3f0000 741#define bTXIQImb_D 0xffc00000 742#define bTxIDCOffset 0xff 743#define bTxQDCOffset 0xff00 744#define bTxDFIRMode 0x10000 745#define bTxPesudoNoiseOn 0x4000000 746#define bTxPesudoNoise_A 0xff 747#define bTxPesudoNoise_B 0xff00 748#define bTxPesudoNoise_C 0xff0000 749#define bTxPesudoNoise_D 0xff000000 750#define bCCADropOption 0x20000 751#define bCCADropThres 0xfff00000 752#define bEDCCA_H 0xf 753#define bEDCCA_L 0xf0 754#define bLambda_ED 0x300 755#define bRxInitialGain 0x7f 756#define bRxAntDivEn 0x80 757#define bRxAGCAddressForLNA 0x7f00 758#define bRxHighPowerFlow 0x8000 759#define bRxAGCFreezeThres 0xc0000 760#define bRxFreezeStep_AGC1 0x300000 761#define bRxFreezeStep_AGC2 0xc00000 762#define bRxFreezeStep_AGC3 0x3000000 763#define bRxFreezeStep_AGC0 0xc000000 764#define bRxRssi_Cmp_En 0x10000000 765#define bRxQuickAGCEn 0x20000000 766#define bRxAGCFreezeThresMode 0x40000000 767#define bRxOverFlowCheckType 0x80000000 768#define bRxAGCShift 0x7f 769#define bTRSW_Tri_Only 0x80 770#define bPowerThres 0x300 771#define bRxAGCEn 0x1 772#define bRxAGCTogetherEn 0x2 773#define bRxAGCMin 0x4 774#define bRxHP_Ini 0x7 775#define bRxHP_TRLNA 0x70 776#define bRxHP_RSSI 0x700 777#define bRxHP_BBP1 0x7000 778#define bRxHP_BBP2 0x70000 779#define bRxHP_BBP3 0x700000 780#define bRSSI_H 0x7f0000 /* the threshold for high power */ 781#define bRSSI_Gen 0x7f000000 /* the threshold for ant diversity */ 782#define bRxSettle_TRSW 0x7 783#define bRxSettle_LNA 0x38 784#define bRxSettle_RSSI 0x1c0 785#define bRxSettle_BBP 0xe00 786#define bRxSettle_RxHP 0x7000 787#define bRxSettle_AntSW_RSSI 0x38000 788#define bRxSettle_AntSW 0xc0000 789#define bRxProcessTime_DAGC 0x300000 790#define bRxSettle_HSSI 0x400000 791#define bRxProcessTime_BBPPW 0x800000 792#define bRxAntennaPowerShift 0x3000000 793#define bRSSITableSelect 0xc000000 794#define bRxHP_Final 0x7000000 795#define bRxHTSettle_BBP 0x7 796#define bRxHTSettle_HSSI 0x8 797#define bRxHTSettle_RxHP 0x70 798#define bRxHTSettle_BBPPW 0x80 799#define bRxHTSettle_Idle 0x300 800#define bRxHTSettle_Reserved 0x1c00 801#define bRxHTRxHPEn 0x8000 802#define bRxHTAGCFreezeThres 0x30000 803#define bRxHTAGCTogetherEn 0x40000 804#define bRxHTAGCMin 0x80000 805#define bRxHTAGCEn 0x100000 806#define bRxHTDAGCEn 0x200000 807#define bRxHTRxHP_BBP 0x1c00000 808#define bRxHTRxHP_Final 0xe0000000 809#define bRxPWRatioTH 0x3 810#define bRxPWRatioEn 0x4 811#define bRxMFHold 0x3800 812#define bRxPD_Delay_TH1 0x38 813#define bRxPD_Delay_TH2 0x1c0 814#define bRxPD_DC_COUNT_MAX 0x600 815/* define bRxMF_Hold 0x3800 */ 816#define bRxPD_Delay_TH 0x8000 817#define bRxProcess_Delay 0xf0000 818#define bRxSearchrange_GI2_Early 0x700000 819#define bRxFrame_Guard_Counter_L 0x3800000 820#define bRxSGI_Guard_L 0xc000000 821#define bRxSGI_Search_L 0x30000000 822#define bRxSGI_TH 0xc0000000 823#define bDFSCnt0 0xff 824#define bDFSCnt1 0xff00 825#define bDFSFlag 0xf0000 826#define bMFWeightSum 0x300000 827#define bMinIdxTH 0x7f000000 828#define bDAFormat 0x40000 829#define bTxChEmuEnable 0x01000000 830#define bTRSWIsolation_A 0x7f 831#define bTRSWIsolation_B 0x7f00 832#define bTRSWIsolation_C 0x7f0000 833#define bTRSWIsolation_D 0x7f000000 834#define bExtLNAGain 0x7c00 835 836/* 6. PageE(0xE00) */ 837#define bSTBCEn 0x4 /* Useless */ 838#define bAntennaMapping 0x10 839#define bNss 0x20 840#define bCFOAntSumD 0x200 841#define bPHYCounterReset 0x8000000 842#define bCFOReportGet 0x4000000 843#define bOFDMContinueTx 0x10000000 844#define bOFDMSingleCarrier 0x20000000 845#define bOFDMSingleTone 0x40000000 846/* define bRxPath1 0x01 */ 847/* define bRxPath2 0x02 */ 848/* define bRxPath3 0x04 */ 849/* define bRxPath4 0x08 */ 850/* define bTxPath1 0x10 */ 851/* define bTxPath2 0x20 */ 852#define bHTDetect 0x100 853#define bCFOEn 0x10000 854#define bCFOValue 0xfff00000 855#define bSigTone_Re 0x3f 856#define bSigTone_Im 0x7f00 857#define bCounter_CCA 0xffff 858#define bCounter_ParityFail 0xffff0000 859#define bCounter_RateIllegal 0xffff 860#define bCounter_CRC8Fail 0xffff0000 861#define bCounter_MCSNoSupport 0xffff 862#define bCounter_FastSync 0xffff 863#define bShortCFO 0xfff 864#define bShortCFOTLength 12 /* total */ 865#define bShortCFOFLength 11 /* fraction */ 866#define bLongCFO 0x7ff 867#define bLongCFOTLength 11 868#define bLongCFOFLength 11 869#define bTailCFO 0x1fff 870#define bTailCFOTLength 13 871#define bTailCFOFLength 12 872#define bmax_en_pwdB 0xffff 873#define bCC_power_dB 0xffff0000 874#define bnoise_pwdB 0xffff 875#define bPowerMeasTLength 10 876#define bPowerMeasFLength 3 877#define bRx_HT_BW 0x1 878#define bRxSC 0x6 879#define bRx_HT 0x8 880#define bNB_intf_det_on 0x1 881#define bIntf_win_len_cfg 0x30 882#define bNB_Intf_TH_cfg 0x1c0 883#define bRFGain 0x3f 884#define bTableSel 0x40 885#define bTRSW 0x80 886#define bRxSNR_A 0xff 887#define bRxSNR_B 0xff00 888#define bRxSNR_C 0xff0000 889#define bRxSNR_D 0xff000000 890#define bSNREVMTLength 8 891#define bSNREVMFLength 1 892#define bCSI1st 0xff 893#define bCSI2nd 0xff00 894#define bRxEVM1st 0xff0000 895#define bRxEVM2nd 0xff000000 896#define bSIGEVM 0xff 897#define bPWDB 0xff00 898#define bSGIEN 0x10000 899 900#define bSFactorQAM1 0xf /* Useless */ 901#define bSFactorQAM2 0xf0 902#define bSFactorQAM3 0xf00 903#define bSFactorQAM4 0xf000 904#define bSFactorQAM5 0xf0000 905#define bSFactorQAM6 0xf0000 906#define bSFactorQAM7 0xf00000 907#define bSFactorQAM8 0xf000000 908#define bSFactorQAM9 0xf0000000 909#define bCSIScheme 0x100000 910 911#define bNoiseLvlTopSet 0x3 /* Useless */ 912#define bChSmooth 0x4 913#define bChSmoothCfg1 0x38 914#define bChSmoothCfg2 0x1c0 915#define bChSmoothCfg3 0xe00 916#define bChSmoothCfg4 0x7000 917#define bMRCMode 0x800000 918#define bTHEVMCfg 0x7000000 919 920#define bLoopFitType 0x1 /* Useless */ 921#define bUpdCFO 0x40 922#define bUpdCFOOffData 0x80 923#define bAdvUpdCFO 0x100 924#define bAdvTimeCtrl 0x800 925#define bUpdClko 0x1000 926#define bFC 0x6000 927#define bTrackingMode 0x8000 928#define bPhCmpEnable 0x10000 929#define bUpdClkoLTF 0x20000 930#define bComChCFO 0x40000 931#define bCSIEstiMode 0x80000 932#define bAdvUpdEqz 0x100000 933#define bUChCfg 0x7000000 934#define bUpdEqz 0x8000000 935 936/* Rx Pseduo noise */ 937#define bRxPesudoNoiseOn 0x20000000 /* Useless */ 938#define bRxPesudoNoise_A 0xff 939#define bRxPesudoNoise_B 0xff00 940#define bRxPesudoNoise_C 0xff0000 941#define bRxPesudoNoise_D 0xff000000 942#define bPesudoNoiseState_A 0xffff 943#define bPesudoNoiseState_B 0xffff0000 944#define bPesudoNoiseState_C 0xffff 945#define bPesudoNoiseState_D 0xffff0000 946 947/* 7. RF Register */ 948/* Zebra1 */ 949#define bZebra1_HSSIEnable 0x8 /* Useless */ 950#define bZebra1_TRxControl 0xc00 951#define bZebra1_TRxGainSetting 0x07f 952#define bZebra1_RxCorner 0xc00 953#define bZebra1_TxChargePump 0x38 954#define bZebra1_RxChargePump 0x7 955#define bZebra1_ChannelNum 0xf80 956#define bZebra1_TxLPFBW 0x400 957#define bZebra1_RxLPFBW 0x600 958 959/* Zebra4 */ 960#define bRTL8256RegModeCtrl1 0x100 /* Useless */ 961#define bRTL8256RegModeCtrl0 0x40 962#define bRTL8256_TxLPFBW 0x18 963#define bRTL8256_RxLPFBW 0x600 964 965/* RTL8258 */ 966#define bRTL8258_TxLPFBW 0xc /* Useless */ 967#define bRTL8258_RxLPFBW 0xc00 968#define bRTL8258_RSSILPFBW 0xc0 969 970 971/* Other Definition */ 972 973/* byte endable for sb_write */ 974#define bByte0 0x1 /* Useless */ 975#define bByte1 0x2 976#define bByte2 0x4 977#define bByte3 0x8 978#define bWord0 0x3 979#define bWord1 0xc 980#define bDWord 0xf 981 982/* for PutRegsetting & GetRegSetting BitMask */ 983#define bMaskByte0 0xff /* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */ 984#define bMaskByte1 0xff00 985#define bMaskByte2 0xff0000 986#define bMaskByte3 0xff000000 987#define bMaskHWord 0xffff0000 988#define bMaskLWord 0x0000ffff 989#define bMaskDWord 0xffffffff 990#define bMask12Bits 0xfff 991#define bMaskH4Bits 0xf0000000 992#define bMaskOFDM_D 0xffc00000 993#define bMaskCCK 0x3f3f3f3f 994 995/* for PutRFRegsetting & GetRFRegSetting BitMask */ 996#define bRFRegOffsetMask 0xfffff 997 998#define bDisable 0x0 999 1000#define LeftAntenna 0x0 /* Useless */ 1001#define RightAntenna 0x1 1002 1003#define tCheckTxStatus 500 /* 500ms Useless */ 1004#define tUpdateRxCounter 100 /* 100ms */ 1005 1006#define rateCCK 0 /* Useless */ 1007#define rateOFDM 1 1008#define rateHT 2 1009 1010/* define Register-End */ 1011#define bPMAC_End 0x1ff /* Useless */ 1012#define bFPGAPHY0_End 0x8ff 1013#define bFPGAPHY1_End 0x9ff 1014#define bCCKPHY0_End 0xaff 1015#define bOFDMPHY0_End 0xcff 1016#define bOFDMPHY1_End 0xdff 1017 1018/* define max debug item in each debug page */ 1019/* define bMaxItem_FPGA_PHY0 0x9 */ 1020/* define bMaxItem_FPGA_PHY1 0x3 */ 1021/* define bMaxItem_PHY_11B 0x16 */ 1022/* define bMaxItem_OFDM_PHY0 0x29 */ 1023/* define bMaxItem_OFDM_PHY1 0x0 */ 1024 1025#define bPMACControl 0x0 /* Useless */ 1026#define bWMACControl 0x1 1027#define bWNICControl 0x2 1028 1029#define PathA 0x0 /* Useless */ 1030#define PathB 0x1 1031#define PathC 0x2 1032#define PathD 0x3 1033 1034/* PageB(0xB00) */ 1035#define rPdp_AntA 0xb00 1036#define rPdp_AntA_4 0xb04 1037#define rPdp_AntA_8 0xb08 1038#define rPdp_AntA_C 0xb0c 1039#define rPdp_AntA_18 0xb18 1040#define rPdp_AntA_1C 0xb1c 1041#define rPdp_AntA_20 0xb20 1042#define rPdp_AntA_24 0xb24 1043 1044#define rConfig_Pmpd_AntA 0xb28 1045#define rConfig_ram64x16 0xb2c 1046 1047#define rBndA 0xb30 1048#define rHssiPar 0xb34 1049 1050#define rConfig_AntA 0xb68 1051#define rConfig_AntB 0xb6c 1052 1053#define rPdp_AntB 0xb70 1054#define rPdp_AntB_4 0xb74 1055#define rPdp_AntB_8 0xb78 1056#define rPdp_AntB_C 0xb7c 1057#define rPdp_AntB_10 0xb80 1058#define rPdp_AntB_14 0xb84 1059#define rPdp_AntB_18 0xb88 1060#define rPdp_AntB_1C 0xb8c 1061#define rPdp_AntB_20 0xb90 1062#define rPdp_AntB_24 0xb94 1063 1064#define rConfig_Pmpd_AntB 0xb98 1065 1066#define rBndB 0xba0 1067 1068#define rAPK 0xbd8 1069#define rPm_Rx0_AntA 0xbdc 1070#define rPm_Rx1_AntA 0xbe0 1071#define rPm_Rx2_AntA 0xbe4 1072#define rPm_Rx3_AntA 0xbe8 1073#define rPm_Rx0_AntB 0xbec 1074#define rPm_Rx1_AntB 0xbf0 1075#define rPm_Rx2_AntB 0xbf4 1076#define rPm_Rx3_AntB 0xbf8 1077 1078#endif 1079