1/* 2 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs 3 * Copyright (C) 2013, Intel Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16#include <linux/init.h> 17#include <linux/module.h> 18#include <linux/device.h> 19#include <linux/ioport.h> 20#include <linux/errno.h> 21#include <linux/err.h> 22#include <linux/interrupt.h> 23#include <linux/kernel.h> 24#include <linux/platform_device.h> 25#include <linux/spi/pxa2xx_spi.h> 26#include <linux/spi/spi.h> 27#include <linux/delay.h> 28#include <linux/gpio.h> 29#include <linux/slab.h> 30#include <linux/clk.h> 31#include <linux/pm_runtime.h> 32#include <linux/acpi.h> 33 34#include "spi-pxa2xx.h" 35 36MODULE_AUTHOR("Stephen Street"); 37MODULE_DESCRIPTION("PXA2xx SSP SPI Controller"); 38MODULE_LICENSE("GPL"); 39MODULE_ALIAS("platform:pxa2xx-spi"); 40 41#define TIMOUT_DFLT 1000 42 43/* 44 * for testing SSCR1 changes that require SSP restart, basically 45 * everything except the service and interrupt enables, the pxa270 developer 46 * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this 47 * list, but the PXA255 dev man says all bits without really meaning the 48 * service and interrupt enables 49 */ 50#define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \ 51 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \ 52 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \ 53 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \ 54 | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \ 55 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) 56 57#define QUARK_X1000_SSCR1_CHANGE_MASK (QUARK_X1000_SSCR1_STRF \ 58 | QUARK_X1000_SSCR1_EFWR \ 59 | QUARK_X1000_SSCR1_RFT \ 60 | QUARK_X1000_SSCR1_TFT \ 61 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) 62 63#define LPSS_RX_THRESH_DFLT 64 64#define LPSS_TX_LOTHRESH_DFLT 160 65#define LPSS_TX_HITHRESH_DFLT 224 66 67/* Offset from drv_data->lpss_base */ 68#define GENERAL_REG 0x08 69#define GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24) 70#define SSP_REG 0x0c 71#define SPI_CS_CONTROL 0x18 72#define SPI_CS_CONTROL_SW_MODE BIT(0) 73#define SPI_CS_CONTROL_CS_HIGH BIT(1) 74 75static bool is_lpss_ssp(const struct driver_data *drv_data) 76{ 77 return drv_data->ssp_type == LPSS_SSP; 78} 79 80static bool is_quark_x1000_ssp(const struct driver_data *drv_data) 81{ 82 return drv_data->ssp_type == QUARK_X1000_SSP; 83} 84 85static u32 pxa2xx_spi_get_ssrc1_change_mask(const struct driver_data *drv_data) 86{ 87 switch (drv_data->ssp_type) { 88 case QUARK_X1000_SSP: 89 return QUARK_X1000_SSCR1_CHANGE_MASK; 90 default: 91 return SSCR1_CHANGE_MASK; 92 } 93} 94 95static u32 96pxa2xx_spi_get_rx_default_thre(const struct driver_data *drv_data) 97{ 98 switch (drv_data->ssp_type) { 99 case QUARK_X1000_SSP: 100 return RX_THRESH_QUARK_X1000_DFLT; 101 default: 102 return RX_THRESH_DFLT; 103 } 104} 105 106static bool pxa2xx_spi_txfifo_full(const struct driver_data *drv_data) 107{ 108 u32 mask; 109 110 switch (drv_data->ssp_type) { 111 case QUARK_X1000_SSP: 112 mask = QUARK_X1000_SSSR_TFL_MASK; 113 break; 114 default: 115 mask = SSSR_TFL_MASK; 116 break; 117 } 118 119 return (pxa2xx_spi_read(drv_data, SSSR) & mask) == mask; 120} 121 122static void pxa2xx_spi_clear_rx_thre(const struct driver_data *drv_data, 123 u32 *sccr1_reg) 124{ 125 u32 mask; 126 127 switch (drv_data->ssp_type) { 128 case QUARK_X1000_SSP: 129 mask = QUARK_X1000_SSCR1_RFT; 130 break; 131 default: 132 mask = SSCR1_RFT; 133 break; 134 } 135 *sccr1_reg &= ~mask; 136} 137 138static void pxa2xx_spi_set_rx_thre(const struct driver_data *drv_data, 139 u32 *sccr1_reg, u32 threshold) 140{ 141 switch (drv_data->ssp_type) { 142 case QUARK_X1000_SSP: 143 *sccr1_reg |= QUARK_X1000_SSCR1_RxTresh(threshold); 144 break; 145 default: 146 *sccr1_reg |= SSCR1_RxTresh(threshold); 147 break; 148 } 149} 150 151static u32 pxa2xx_configure_sscr0(const struct driver_data *drv_data, 152 u32 clk_div, u8 bits) 153{ 154 switch (drv_data->ssp_type) { 155 case QUARK_X1000_SSP: 156 return clk_div 157 | QUARK_X1000_SSCR0_Motorola 158 | QUARK_X1000_SSCR0_DataSize(bits > 32 ? 8 : bits) 159 | SSCR0_SSE; 160 default: 161 return clk_div 162 | SSCR0_Motorola 163 | SSCR0_DataSize(bits > 16 ? bits - 16 : bits) 164 | SSCR0_SSE 165 | (bits > 16 ? SSCR0_EDSS : 0); 166 } 167} 168 169/* 170 * Read and write LPSS SSP private registers. Caller must first check that 171 * is_lpss_ssp() returns true before these can be called. 172 */ 173static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset) 174{ 175 WARN_ON(!drv_data->lpss_base); 176 return readl(drv_data->lpss_base + offset); 177} 178 179static void __lpss_ssp_write_priv(struct driver_data *drv_data, 180 unsigned offset, u32 value) 181{ 182 WARN_ON(!drv_data->lpss_base); 183 writel(value, drv_data->lpss_base + offset); 184} 185 186/* 187 * lpss_ssp_setup - perform LPSS SSP specific setup 188 * @drv_data: pointer to the driver private data 189 * 190 * Perform LPSS SSP specific setup. This function must be called first if 191 * one is going to use LPSS SSP private registers. 192 */ 193static void lpss_ssp_setup(struct driver_data *drv_data) 194{ 195 unsigned offset = 0x400; 196 u32 value, orig; 197 198 /* 199 * Perform auto-detection of the LPSS SSP private registers. They 200 * can be either at 1k or 2k offset from the base address. 201 */ 202 orig = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL); 203 204 /* Test SPI_CS_CONTROL_SW_MODE bit enabling */ 205 value = orig | SPI_CS_CONTROL_SW_MODE; 206 writel(value, drv_data->ioaddr + offset + SPI_CS_CONTROL); 207 value = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL); 208 if (value != (orig | SPI_CS_CONTROL_SW_MODE)) { 209 offset = 0x800; 210 goto detection_done; 211 } 212 213 orig = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL); 214 215 /* Test SPI_CS_CONTROL_SW_MODE bit disabling */ 216 value = orig & ~SPI_CS_CONTROL_SW_MODE; 217 writel(value, drv_data->ioaddr + offset + SPI_CS_CONTROL); 218 value = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL); 219 if (value != (orig & ~SPI_CS_CONTROL_SW_MODE)) { 220 offset = 0x800; 221 goto detection_done; 222 } 223 224detection_done: 225 /* Now set the LPSS base */ 226 drv_data->lpss_base = drv_data->ioaddr + offset; 227 228 /* Enable software chip select control */ 229 value = SPI_CS_CONTROL_SW_MODE | SPI_CS_CONTROL_CS_HIGH; 230 __lpss_ssp_write_priv(drv_data, SPI_CS_CONTROL, value); 231 232 /* Enable multiblock DMA transfers */ 233 if (drv_data->master_info->enable_dma) { 234 __lpss_ssp_write_priv(drv_data, SSP_REG, 1); 235 236 value = __lpss_ssp_read_priv(drv_data, GENERAL_REG); 237 value |= GENERAL_REG_RXTO_HOLDOFF_DISABLE; 238 __lpss_ssp_write_priv(drv_data, GENERAL_REG, value); 239 } 240} 241 242static void lpss_ssp_cs_control(struct driver_data *drv_data, bool enable) 243{ 244 u32 value; 245 246 value = __lpss_ssp_read_priv(drv_data, SPI_CS_CONTROL); 247 if (enable) 248 value &= ~SPI_CS_CONTROL_CS_HIGH; 249 else 250 value |= SPI_CS_CONTROL_CS_HIGH; 251 __lpss_ssp_write_priv(drv_data, SPI_CS_CONTROL, value); 252} 253 254static void cs_assert(struct driver_data *drv_data) 255{ 256 struct chip_data *chip = drv_data->cur_chip; 257 258 if (drv_data->ssp_type == CE4100_SSP) { 259 pxa2xx_spi_write(drv_data, SSSR, drv_data->cur_chip->frm); 260 return; 261 } 262 263 if (chip->cs_control) { 264 chip->cs_control(PXA2XX_CS_ASSERT); 265 return; 266 } 267 268 if (gpio_is_valid(chip->gpio_cs)) { 269 gpio_set_value(chip->gpio_cs, chip->gpio_cs_inverted); 270 return; 271 } 272 273 if (is_lpss_ssp(drv_data)) 274 lpss_ssp_cs_control(drv_data, true); 275} 276 277static void cs_deassert(struct driver_data *drv_data) 278{ 279 struct chip_data *chip = drv_data->cur_chip; 280 281 if (drv_data->ssp_type == CE4100_SSP) 282 return; 283 284 if (chip->cs_control) { 285 chip->cs_control(PXA2XX_CS_DEASSERT); 286 return; 287 } 288 289 if (gpio_is_valid(chip->gpio_cs)) { 290 gpio_set_value(chip->gpio_cs, !chip->gpio_cs_inverted); 291 return; 292 } 293 294 if (is_lpss_ssp(drv_data)) 295 lpss_ssp_cs_control(drv_data, false); 296} 297 298int pxa2xx_spi_flush(struct driver_data *drv_data) 299{ 300 unsigned long limit = loops_per_jiffy << 1; 301 302 do { 303 while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) 304 pxa2xx_spi_read(drv_data, SSDR); 305 } while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit); 306 write_SSSR_CS(drv_data, SSSR_ROR); 307 308 return limit; 309} 310 311static int null_writer(struct driver_data *drv_data) 312{ 313 u8 n_bytes = drv_data->n_bytes; 314 315 if (pxa2xx_spi_txfifo_full(drv_data) 316 || (drv_data->tx == drv_data->tx_end)) 317 return 0; 318 319 pxa2xx_spi_write(drv_data, SSDR, 0); 320 drv_data->tx += n_bytes; 321 322 return 1; 323} 324 325static int null_reader(struct driver_data *drv_data) 326{ 327 u8 n_bytes = drv_data->n_bytes; 328 329 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) 330 && (drv_data->rx < drv_data->rx_end)) { 331 pxa2xx_spi_read(drv_data, SSDR); 332 drv_data->rx += n_bytes; 333 } 334 335 return drv_data->rx == drv_data->rx_end; 336} 337 338static int u8_writer(struct driver_data *drv_data) 339{ 340 if (pxa2xx_spi_txfifo_full(drv_data) 341 || (drv_data->tx == drv_data->tx_end)) 342 return 0; 343 344 pxa2xx_spi_write(drv_data, SSDR, *(u8 *)(drv_data->tx)); 345 ++drv_data->tx; 346 347 return 1; 348} 349 350static int u8_reader(struct driver_data *drv_data) 351{ 352 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) 353 && (drv_data->rx < drv_data->rx_end)) { 354 *(u8 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); 355 ++drv_data->rx; 356 } 357 358 return drv_data->rx == drv_data->rx_end; 359} 360 361static int u16_writer(struct driver_data *drv_data) 362{ 363 if (pxa2xx_spi_txfifo_full(drv_data) 364 || (drv_data->tx == drv_data->tx_end)) 365 return 0; 366 367 pxa2xx_spi_write(drv_data, SSDR, *(u16 *)(drv_data->tx)); 368 drv_data->tx += 2; 369 370 return 1; 371} 372 373static int u16_reader(struct driver_data *drv_data) 374{ 375 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) 376 && (drv_data->rx < drv_data->rx_end)) { 377 *(u16 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); 378 drv_data->rx += 2; 379 } 380 381 return drv_data->rx == drv_data->rx_end; 382} 383 384static int u32_writer(struct driver_data *drv_data) 385{ 386 if (pxa2xx_spi_txfifo_full(drv_data) 387 || (drv_data->tx == drv_data->tx_end)) 388 return 0; 389 390 pxa2xx_spi_write(drv_data, SSDR, *(u32 *)(drv_data->tx)); 391 drv_data->tx += 4; 392 393 return 1; 394} 395 396static int u32_reader(struct driver_data *drv_data) 397{ 398 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) 399 && (drv_data->rx < drv_data->rx_end)) { 400 *(u32 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); 401 drv_data->rx += 4; 402 } 403 404 return drv_data->rx == drv_data->rx_end; 405} 406 407void *pxa2xx_spi_next_transfer(struct driver_data *drv_data) 408{ 409 struct spi_message *msg = drv_data->cur_msg; 410 struct spi_transfer *trans = drv_data->cur_transfer; 411 412 /* Move to next transfer */ 413 if (trans->transfer_list.next != &msg->transfers) { 414 drv_data->cur_transfer = 415 list_entry(trans->transfer_list.next, 416 struct spi_transfer, 417 transfer_list); 418 return RUNNING_STATE; 419 } else 420 return DONE_STATE; 421} 422 423/* caller already set message->status; dma and pio irqs are blocked */ 424static void giveback(struct driver_data *drv_data) 425{ 426 struct spi_transfer* last_transfer; 427 struct spi_message *msg; 428 429 msg = drv_data->cur_msg; 430 drv_data->cur_msg = NULL; 431 drv_data->cur_transfer = NULL; 432 433 last_transfer = list_last_entry(&msg->transfers, struct spi_transfer, 434 transfer_list); 435 436 /* Delay if requested before any change in chip select */ 437 if (last_transfer->delay_usecs) 438 udelay(last_transfer->delay_usecs); 439 440 /* Drop chip select UNLESS cs_change is true or we are returning 441 * a message with an error, or next message is for another chip 442 */ 443 if (!last_transfer->cs_change) 444 cs_deassert(drv_data); 445 else { 446 struct spi_message *next_msg; 447 448 /* Holding of cs was hinted, but we need to make sure 449 * the next message is for the same chip. Don't waste 450 * time with the following tests unless this was hinted. 451 * 452 * We cannot postpone this until pump_messages, because 453 * after calling msg->complete (below) the driver that 454 * sent the current message could be unloaded, which 455 * could invalidate the cs_control() callback... 456 */ 457 458 /* get a pointer to the next message, if any */ 459 next_msg = spi_get_next_queued_message(drv_data->master); 460 461 /* see if the next and current messages point 462 * to the same chip 463 */ 464 if (next_msg && next_msg->spi != msg->spi) 465 next_msg = NULL; 466 if (!next_msg || msg->state == ERROR_STATE) 467 cs_deassert(drv_data); 468 } 469 470 drv_data->cur_chip = NULL; 471 spi_finalize_current_message(drv_data->master); 472} 473 474static void reset_sccr1(struct driver_data *drv_data) 475{ 476 struct chip_data *chip = drv_data->cur_chip; 477 u32 sccr1_reg; 478 479 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1; 480 sccr1_reg &= ~SSCR1_RFT; 481 sccr1_reg |= chip->threshold; 482 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg); 483} 484 485static void int_error_stop(struct driver_data *drv_data, const char* msg) 486{ 487 /* Stop and reset SSP */ 488 write_SSSR_CS(drv_data, drv_data->clear_sr); 489 reset_sccr1(drv_data); 490 if (!pxa25x_ssp_comp(drv_data)) 491 pxa2xx_spi_write(drv_data, SSTO, 0); 492 pxa2xx_spi_flush(drv_data); 493 pxa2xx_spi_write(drv_data, SSCR0, 494 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE); 495 496 dev_err(&drv_data->pdev->dev, "%s\n", msg); 497 498 drv_data->cur_msg->state = ERROR_STATE; 499 tasklet_schedule(&drv_data->pump_transfers); 500} 501 502static void int_transfer_complete(struct driver_data *drv_data) 503{ 504 /* Stop SSP */ 505 write_SSSR_CS(drv_data, drv_data->clear_sr); 506 reset_sccr1(drv_data); 507 if (!pxa25x_ssp_comp(drv_data)) 508 pxa2xx_spi_write(drv_data, SSTO, 0); 509 510 /* Update total byte transferred return count actual bytes read */ 511 drv_data->cur_msg->actual_length += drv_data->len - 512 (drv_data->rx_end - drv_data->rx); 513 514 /* Transfer delays and chip select release are 515 * handled in pump_transfers or giveback 516 */ 517 518 /* Move to next transfer */ 519 drv_data->cur_msg->state = pxa2xx_spi_next_transfer(drv_data); 520 521 /* Schedule transfer tasklet */ 522 tasklet_schedule(&drv_data->pump_transfers); 523} 524 525static irqreturn_t interrupt_transfer(struct driver_data *drv_data) 526{ 527 u32 irq_mask = (pxa2xx_spi_read(drv_data, SSCR1) & SSCR1_TIE) ? 528 drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS; 529 530 u32 irq_status = pxa2xx_spi_read(drv_data, SSSR) & irq_mask; 531 532 if (irq_status & SSSR_ROR) { 533 int_error_stop(drv_data, "interrupt_transfer: fifo overrun"); 534 return IRQ_HANDLED; 535 } 536 537 if (irq_status & SSSR_TINT) { 538 pxa2xx_spi_write(drv_data, SSSR, SSSR_TINT); 539 if (drv_data->read(drv_data)) { 540 int_transfer_complete(drv_data); 541 return IRQ_HANDLED; 542 } 543 } 544 545 /* Drain rx fifo, Fill tx fifo and prevent overruns */ 546 do { 547 if (drv_data->read(drv_data)) { 548 int_transfer_complete(drv_data); 549 return IRQ_HANDLED; 550 } 551 } while (drv_data->write(drv_data)); 552 553 if (drv_data->read(drv_data)) { 554 int_transfer_complete(drv_data); 555 return IRQ_HANDLED; 556 } 557 558 if (drv_data->tx == drv_data->tx_end) { 559 u32 bytes_left; 560 u32 sccr1_reg; 561 562 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1); 563 sccr1_reg &= ~SSCR1_TIE; 564 565 /* 566 * PXA25x_SSP has no timeout, set up rx threshould for the 567 * remaining RX bytes. 568 */ 569 if (pxa25x_ssp_comp(drv_data)) { 570 u32 rx_thre; 571 572 pxa2xx_spi_clear_rx_thre(drv_data, &sccr1_reg); 573 574 bytes_left = drv_data->rx_end - drv_data->rx; 575 switch (drv_data->n_bytes) { 576 case 4: 577 bytes_left >>= 1; 578 case 2: 579 bytes_left >>= 1; 580 } 581 582 rx_thre = pxa2xx_spi_get_rx_default_thre(drv_data); 583 if (rx_thre > bytes_left) 584 rx_thre = bytes_left; 585 586 pxa2xx_spi_set_rx_thre(drv_data, &sccr1_reg, rx_thre); 587 } 588 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg); 589 } 590 591 /* We did something */ 592 return IRQ_HANDLED; 593} 594 595static irqreturn_t ssp_int(int irq, void *dev_id) 596{ 597 struct driver_data *drv_data = dev_id; 598 u32 sccr1_reg; 599 u32 mask = drv_data->mask_sr; 600 u32 status; 601 602 /* 603 * The IRQ might be shared with other peripherals so we must first 604 * check that are we RPM suspended or not. If we are we assume that 605 * the IRQ was not for us (we shouldn't be RPM suspended when the 606 * interrupt is enabled). 607 */ 608 if (pm_runtime_suspended(&drv_data->pdev->dev)) 609 return IRQ_NONE; 610 611 /* 612 * If the device is not yet in RPM suspended state and we get an 613 * interrupt that is meant for another device, check if status bits 614 * are all set to one. That means that the device is already 615 * powered off. 616 */ 617 status = pxa2xx_spi_read(drv_data, SSSR); 618 if (status == ~0) 619 return IRQ_NONE; 620 621 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1); 622 623 /* Ignore possible writes if we don't need to write */ 624 if (!(sccr1_reg & SSCR1_TIE)) 625 mask &= ~SSSR_TFS; 626 627 /* Ignore RX timeout interrupt if it is disabled */ 628 if (!(sccr1_reg & SSCR1_TINTE)) 629 mask &= ~SSSR_TINT; 630 631 if (!(status & mask)) 632 return IRQ_NONE; 633 634 if (!drv_data->cur_msg) { 635 636 pxa2xx_spi_write(drv_data, SSCR0, 637 pxa2xx_spi_read(drv_data, SSCR0) 638 & ~SSCR0_SSE); 639 pxa2xx_spi_write(drv_data, SSCR1, 640 pxa2xx_spi_read(drv_data, SSCR1) 641 & ~drv_data->int_cr1); 642 if (!pxa25x_ssp_comp(drv_data)) 643 pxa2xx_spi_write(drv_data, SSTO, 0); 644 write_SSSR_CS(drv_data, drv_data->clear_sr); 645 646 dev_err(&drv_data->pdev->dev, 647 "bad message state in interrupt handler\n"); 648 649 /* Never fail */ 650 return IRQ_HANDLED; 651 } 652 653 return drv_data->transfer_handler(drv_data); 654} 655 656/* 657 * The Quark SPI has an additional 24 bit register (DDS_CLK_RATE) to multiply 658 * input frequency by fractions of 2^24. It also has a divider by 5. 659 * 660 * There are formulas to get baud rate value for given input frequency and 661 * divider parameters, such as DDS_CLK_RATE and SCR: 662 * 663 * Fsys = 200MHz 664 * 665 * Fssp = Fsys * DDS_CLK_RATE / 2^24 (1) 666 * Baud rate = Fsclk = Fssp / (2 * (SCR + 1)) (2) 667 * 668 * DDS_CLK_RATE either 2^n or 2^n / 5. 669 * SCR is in range 0 .. 255 670 * 671 * Divisor = 5^i * 2^j * 2 * k 672 * i = [0, 1] i = 1 iff j = 0 or j > 3 673 * j = [0, 23] j = 0 iff i = 1 674 * k = [1, 256] 675 * Special case: j = 0, i = 1: Divisor = 2 / 5 676 * 677 * Accordingly to the specification the recommended values for DDS_CLK_RATE 678 * are: 679 * Case 1: 2^n, n = [0, 23] 680 * Case 2: 2^24 * 2 / 5 (0x666666) 681 * Case 3: less than or equal to 2^24 / 5 / 16 (0x33333) 682 * 683 * In all cases the lowest possible value is better. 684 * 685 * The function calculates parameters for all cases and chooses the one closest 686 * to the asked baud rate. 687 */ 688static unsigned int quark_x1000_get_clk_div(int rate, u32 *dds) 689{ 690 unsigned long xtal = 200000000; 691 unsigned long fref = xtal / 2; /* mandatory division by 2, 692 see (2) */ 693 /* case 3 */ 694 unsigned long fref1 = fref / 2; /* case 1 */ 695 unsigned long fref2 = fref * 2 / 5; /* case 2 */ 696 unsigned long scale; 697 unsigned long q, q1, q2; 698 long r, r1, r2; 699 u32 mul; 700 701 /* Case 1 */ 702 703 /* Set initial value for DDS_CLK_RATE */ 704 mul = (1 << 24) >> 1; 705 706 /* Calculate initial quot */ 707 q1 = DIV_ROUND_CLOSEST(fref1, rate); 708 709 /* Scale q1 if it's too big */ 710 if (q1 > 256) { 711 /* Scale q1 to range [1, 512] */ 712 scale = fls_long(q1 - 1); 713 if (scale > 9) { 714 q1 >>= scale - 9; 715 mul >>= scale - 9; 716 } 717 718 /* Round the result if we have a remainder */ 719 q1 += q1 & 1; 720 } 721 722 /* Decrease DDS_CLK_RATE as much as we can without loss in precision */ 723 scale = __ffs(q1); 724 q1 >>= scale; 725 mul >>= scale; 726 727 /* Get the remainder */ 728 r1 = abs(fref1 / (1 << (24 - fls_long(mul))) / q1 - rate); 729 730 /* Case 2 */ 731 732 q2 = DIV_ROUND_CLOSEST(fref2, rate); 733 r2 = abs(fref2 / q2 - rate); 734 735 /* 736 * Choose the best between two: less remainder we have the better. We 737 * can't go case 2 if q2 is greater than 256 since SCR register can 738 * hold only values 0 .. 255. 739 */ 740 if (r2 >= r1 || q2 > 256) { 741 /* case 1 is better */ 742 r = r1; 743 q = q1; 744 } else { 745 /* case 2 is better */ 746 r = r2; 747 q = q2; 748 mul = (1 << 24) * 2 / 5; 749 } 750 751 /* Check case 3 only If the divisor is big enough */ 752 if (fref / rate >= 80) { 753 u64 fssp; 754 u32 m; 755 756 /* Calculate initial quot */ 757 q1 = DIV_ROUND_CLOSEST(fref, rate); 758 m = (1 << 24) / q1; 759 760 /* Get the remainder */ 761 fssp = (u64)fref * m; 762 do_div(fssp, 1 << 24); 763 r1 = abs(fssp - rate); 764 765 /* Choose this one if it suits better */ 766 if (r1 < r) { 767 /* case 3 is better */ 768 q = 1; 769 mul = m; 770 } 771 } 772 773 *dds = mul; 774 return q - 1; 775} 776 777static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate) 778{ 779 unsigned long ssp_clk = drv_data->max_clk_rate; 780 const struct ssp_device *ssp = drv_data->ssp; 781 782 rate = min_t(int, ssp_clk, rate); 783 784 if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP) 785 return (ssp_clk / (2 * rate) - 1) & 0xff; 786 else 787 return (ssp_clk / rate - 1) & 0xfff; 788} 789 790static unsigned int pxa2xx_ssp_get_clk_div(struct driver_data *drv_data, 791 struct chip_data *chip, int rate) 792{ 793 unsigned int clk_div; 794 795 switch (drv_data->ssp_type) { 796 case QUARK_X1000_SSP: 797 clk_div = quark_x1000_get_clk_div(rate, &chip->dds_rate); 798 break; 799 default: 800 clk_div = ssp_get_clk_div(drv_data, rate); 801 break; 802 } 803 return clk_div << 8; 804} 805 806static void pump_transfers(unsigned long data) 807{ 808 struct driver_data *drv_data = (struct driver_data *)data; 809 struct spi_message *message = NULL; 810 struct spi_transfer *transfer = NULL; 811 struct spi_transfer *previous = NULL; 812 struct chip_data *chip = NULL; 813 u32 clk_div = 0; 814 u8 bits = 0; 815 u32 speed = 0; 816 u32 cr0; 817 u32 cr1; 818 u32 dma_thresh = drv_data->cur_chip->dma_threshold; 819 u32 dma_burst = drv_data->cur_chip->dma_burst_size; 820 u32 change_mask = pxa2xx_spi_get_ssrc1_change_mask(drv_data); 821 822 /* Get current state information */ 823 message = drv_data->cur_msg; 824 transfer = drv_data->cur_transfer; 825 chip = drv_data->cur_chip; 826 827 /* Handle for abort */ 828 if (message->state == ERROR_STATE) { 829 message->status = -EIO; 830 giveback(drv_data); 831 return; 832 } 833 834 /* Handle end of message */ 835 if (message->state == DONE_STATE) { 836 message->status = 0; 837 giveback(drv_data); 838 return; 839 } 840 841 /* Delay if requested at end of transfer before CS change */ 842 if (message->state == RUNNING_STATE) { 843 previous = list_entry(transfer->transfer_list.prev, 844 struct spi_transfer, 845 transfer_list); 846 if (previous->delay_usecs) 847 udelay(previous->delay_usecs); 848 849 /* Drop chip select only if cs_change is requested */ 850 if (previous->cs_change) 851 cs_deassert(drv_data); 852 } 853 854 /* Check if we can DMA this transfer */ 855 if (!pxa2xx_spi_dma_is_possible(transfer->len) && chip->enable_dma) { 856 857 /* reject already-mapped transfers; PIO won't always work */ 858 if (message->is_dma_mapped 859 || transfer->rx_dma || transfer->tx_dma) { 860 dev_err(&drv_data->pdev->dev, 861 "pump_transfers: mapped transfer length of " 862 "%u is greater than %d\n", 863 transfer->len, MAX_DMA_LEN); 864 message->status = -EINVAL; 865 giveback(drv_data); 866 return; 867 } 868 869 /* warn ... we force this to PIO mode */ 870 dev_warn_ratelimited(&message->spi->dev, 871 "pump_transfers: DMA disabled for transfer length %ld " 872 "greater than %d\n", 873 (long)drv_data->len, MAX_DMA_LEN); 874 } 875 876 /* Setup the transfer state based on the type of transfer */ 877 if (pxa2xx_spi_flush(drv_data) == 0) { 878 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n"); 879 message->status = -EIO; 880 giveback(drv_data); 881 return; 882 } 883 drv_data->n_bytes = chip->n_bytes; 884 drv_data->tx = (void *)transfer->tx_buf; 885 drv_data->tx_end = drv_data->tx + transfer->len; 886 drv_data->rx = transfer->rx_buf; 887 drv_data->rx_end = drv_data->rx + transfer->len; 888 drv_data->rx_dma = transfer->rx_dma; 889 drv_data->tx_dma = transfer->tx_dma; 890 drv_data->len = transfer->len; 891 drv_data->write = drv_data->tx ? chip->write : null_writer; 892 drv_data->read = drv_data->rx ? chip->read : null_reader; 893 894 /* Change speed and bit per word on a per transfer */ 895 cr0 = chip->cr0; 896 if (transfer->speed_hz || transfer->bits_per_word) { 897 898 bits = chip->bits_per_word; 899 speed = chip->speed_hz; 900 901 if (transfer->speed_hz) 902 speed = transfer->speed_hz; 903 904 if (transfer->bits_per_word) 905 bits = transfer->bits_per_word; 906 907 clk_div = pxa2xx_ssp_get_clk_div(drv_data, chip, speed); 908 909 if (bits <= 8) { 910 drv_data->n_bytes = 1; 911 drv_data->read = drv_data->read != null_reader ? 912 u8_reader : null_reader; 913 drv_data->write = drv_data->write != null_writer ? 914 u8_writer : null_writer; 915 } else if (bits <= 16) { 916 drv_data->n_bytes = 2; 917 drv_data->read = drv_data->read != null_reader ? 918 u16_reader : null_reader; 919 drv_data->write = drv_data->write != null_writer ? 920 u16_writer : null_writer; 921 } else if (bits <= 32) { 922 drv_data->n_bytes = 4; 923 drv_data->read = drv_data->read != null_reader ? 924 u32_reader : null_reader; 925 drv_data->write = drv_data->write != null_writer ? 926 u32_writer : null_writer; 927 } 928 /* if bits/word is changed in dma mode, then must check the 929 * thresholds and burst also */ 930 if (chip->enable_dma) { 931 if (pxa2xx_spi_set_dma_burst_and_threshold(chip, 932 message->spi, 933 bits, &dma_burst, 934 &dma_thresh)) 935 dev_warn_ratelimited(&message->spi->dev, 936 "pump_transfers: DMA burst size reduced to match bits_per_word\n"); 937 } 938 939 cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, bits); 940 } 941 942 message->state = RUNNING_STATE; 943 944 drv_data->dma_mapped = 0; 945 if (pxa2xx_spi_dma_is_possible(drv_data->len)) 946 drv_data->dma_mapped = pxa2xx_spi_map_dma_buffers(drv_data); 947 if (drv_data->dma_mapped) { 948 949 /* Ensure we have the correct interrupt handler */ 950 drv_data->transfer_handler = pxa2xx_spi_dma_transfer; 951 952 pxa2xx_spi_dma_prepare(drv_data, dma_burst); 953 954 /* Clear status and start DMA engine */ 955 cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1; 956 pxa2xx_spi_write(drv_data, SSSR, drv_data->clear_sr); 957 958 pxa2xx_spi_dma_start(drv_data); 959 } else { 960 /* Ensure we have the correct interrupt handler */ 961 drv_data->transfer_handler = interrupt_transfer; 962 963 /* Clear status */ 964 cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1; 965 write_SSSR_CS(drv_data, drv_data->clear_sr); 966 } 967 968 if (is_lpss_ssp(drv_data)) { 969 if ((pxa2xx_spi_read(drv_data, SSIRF) & 0xff) 970 != chip->lpss_rx_threshold) 971 pxa2xx_spi_write(drv_data, SSIRF, 972 chip->lpss_rx_threshold); 973 if ((pxa2xx_spi_read(drv_data, SSITF) & 0xffff) 974 != chip->lpss_tx_threshold) 975 pxa2xx_spi_write(drv_data, SSITF, 976 chip->lpss_tx_threshold); 977 } 978 979 if (is_quark_x1000_ssp(drv_data) && 980 (pxa2xx_spi_read(drv_data, DDS_RATE) != chip->dds_rate)) 981 pxa2xx_spi_write(drv_data, DDS_RATE, chip->dds_rate); 982 983 /* see if we need to reload the config registers */ 984 if ((pxa2xx_spi_read(drv_data, SSCR0) != cr0) 985 || (pxa2xx_spi_read(drv_data, SSCR1) & change_mask) 986 != (cr1 & change_mask)) { 987 /* stop the SSP, and update the other bits */ 988 pxa2xx_spi_write(drv_data, SSCR0, cr0 & ~SSCR0_SSE); 989 if (!pxa25x_ssp_comp(drv_data)) 990 pxa2xx_spi_write(drv_data, SSTO, chip->timeout); 991 /* first set CR1 without interrupt and service enables */ 992 pxa2xx_spi_write(drv_data, SSCR1, cr1 & change_mask); 993 /* restart the SSP */ 994 pxa2xx_spi_write(drv_data, SSCR0, cr0); 995 996 } else { 997 if (!pxa25x_ssp_comp(drv_data)) 998 pxa2xx_spi_write(drv_data, SSTO, chip->timeout); 999 } 1000 1001 cs_assert(drv_data); 1002 1003 /* after chip select, release the data by enabling service 1004 * requests and interrupts, without changing any mode bits */ 1005 pxa2xx_spi_write(drv_data, SSCR1, cr1); 1006} 1007 1008static int pxa2xx_spi_transfer_one_message(struct spi_master *master, 1009 struct spi_message *msg) 1010{ 1011 struct driver_data *drv_data = spi_master_get_devdata(master); 1012 1013 drv_data->cur_msg = msg; 1014 /* Initial message state*/ 1015 drv_data->cur_msg->state = START_STATE; 1016 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next, 1017 struct spi_transfer, 1018 transfer_list); 1019 1020 /* prepare to setup the SSP, in pump_transfers, using the per 1021 * chip configuration */ 1022 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi); 1023 1024 /* Mark as busy and launch transfers */ 1025 tasklet_schedule(&drv_data->pump_transfers); 1026 return 0; 1027} 1028 1029static int pxa2xx_spi_unprepare_transfer(struct spi_master *master) 1030{ 1031 struct driver_data *drv_data = spi_master_get_devdata(master); 1032 1033 /* Disable the SSP now */ 1034 pxa2xx_spi_write(drv_data, SSCR0, 1035 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE); 1036 1037 return 0; 1038} 1039 1040static int setup_cs(struct spi_device *spi, struct chip_data *chip, 1041 struct pxa2xx_spi_chip *chip_info) 1042{ 1043 int err = 0; 1044 1045 if (chip == NULL || chip_info == NULL) 1046 return 0; 1047 1048 /* NOTE: setup() can be called multiple times, possibly with 1049 * different chip_info, release previously requested GPIO 1050 */ 1051 if (gpio_is_valid(chip->gpio_cs)) 1052 gpio_free(chip->gpio_cs); 1053 1054 /* If (*cs_control) is provided, ignore GPIO chip select */ 1055 if (chip_info->cs_control) { 1056 chip->cs_control = chip_info->cs_control; 1057 return 0; 1058 } 1059 1060 if (gpio_is_valid(chip_info->gpio_cs)) { 1061 err = gpio_request(chip_info->gpio_cs, "SPI_CS"); 1062 if (err) { 1063 dev_err(&spi->dev, "failed to request chip select GPIO%d\n", 1064 chip_info->gpio_cs); 1065 return err; 1066 } 1067 1068 chip->gpio_cs = chip_info->gpio_cs; 1069 chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH; 1070 1071 err = gpio_direction_output(chip->gpio_cs, 1072 !chip->gpio_cs_inverted); 1073 } 1074 1075 return err; 1076} 1077 1078static int setup(struct spi_device *spi) 1079{ 1080 struct pxa2xx_spi_chip *chip_info = NULL; 1081 struct chip_data *chip; 1082 struct driver_data *drv_data = spi_master_get_devdata(spi->master); 1083 unsigned int clk_div; 1084 uint tx_thres, tx_hi_thres, rx_thres; 1085 1086 switch (drv_data->ssp_type) { 1087 case QUARK_X1000_SSP: 1088 tx_thres = TX_THRESH_QUARK_X1000_DFLT; 1089 tx_hi_thres = 0; 1090 rx_thres = RX_THRESH_QUARK_X1000_DFLT; 1091 break; 1092 case LPSS_SSP: 1093 tx_thres = LPSS_TX_LOTHRESH_DFLT; 1094 tx_hi_thres = LPSS_TX_HITHRESH_DFLT; 1095 rx_thres = LPSS_RX_THRESH_DFLT; 1096 break; 1097 default: 1098 tx_thres = TX_THRESH_DFLT; 1099 tx_hi_thres = 0; 1100 rx_thres = RX_THRESH_DFLT; 1101 break; 1102 } 1103 1104 /* Only alloc on first setup */ 1105 chip = spi_get_ctldata(spi); 1106 if (!chip) { 1107 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); 1108 if (!chip) 1109 return -ENOMEM; 1110 1111 if (drv_data->ssp_type == CE4100_SSP) { 1112 if (spi->chip_select > 4) { 1113 dev_err(&spi->dev, 1114 "failed setup: cs number must not be > 4.\n"); 1115 kfree(chip); 1116 return -EINVAL; 1117 } 1118 1119 chip->frm = spi->chip_select; 1120 } else 1121 chip->gpio_cs = -1; 1122 chip->enable_dma = 0; 1123 chip->timeout = TIMOUT_DFLT; 1124 } 1125 1126 /* protocol drivers may change the chip settings, so... 1127 * if chip_info exists, use it */ 1128 chip_info = spi->controller_data; 1129 1130 /* chip_info isn't always needed */ 1131 chip->cr1 = 0; 1132 if (chip_info) { 1133 if (chip_info->timeout) 1134 chip->timeout = chip_info->timeout; 1135 if (chip_info->tx_threshold) 1136 tx_thres = chip_info->tx_threshold; 1137 if (chip_info->tx_hi_threshold) 1138 tx_hi_thres = chip_info->tx_hi_threshold; 1139 if (chip_info->rx_threshold) 1140 rx_thres = chip_info->rx_threshold; 1141 chip->enable_dma = drv_data->master_info->enable_dma; 1142 chip->dma_threshold = 0; 1143 if (chip_info->enable_loopback) 1144 chip->cr1 = SSCR1_LBM; 1145 } else if (ACPI_HANDLE(&spi->dev)) { 1146 /* 1147 * Slave devices enumerated from ACPI namespace don't 1148 * usually have chip_info but we still might want to use 1149 * DMA with them. 1150 */ 1151 chip->enable_dma = drv_data->master_info->enable_dma; 1152 } 1153 1154 chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres); 1155 chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres) 1156 | SSITF_TxHiThresh(tx_hi_thres); 1157 1158 /* set dma burst and threshold outside of chip_info path so that if 1159 * chip_info goes away after setting chip->enable_dma, the 1160 * burst and threshold can still respond to changes in bits_per_word */ 1161 if (chip->enable_dma) { 1162 /* set up legal burst and threshold for dma */ 1163 if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi, 1164 spi->bits_per_word, 1165 &chip->dma_burst_size, 1166 &chip->dma_threshold)) { 1167 dev_warn(&spi->dev, 1168 "in setup: DMA burst size reduced to match bits_per_word\n"); 1169 } 1170 } 1171 1172 clk_div = pxa2xx_ssp_get_clk_div(drv_data, chip, spi->max_speed_hz); 1173 chip->speed_hz = spi->max_speed_hz; 1174 1175 chip->cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, 1176 spi->bits_per_word); 1177 switch (drv_data->ssp_type) { 1178 case QUARK_X1000_SSP: 1179 chip->threshold = (QUARK_X1000_SSCR1_RxTresh(rx_thres) 1180 & QUARK_X1000_SSCR1_RFT) 1181 | (QUARK_X1000_SSCR1_TxTresh(tx_thres) 1182 & QUARK_X1000_SSCR1_TFT); 1183 break; 1184 default: 1185 chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) | 1186 (SSCR1_TxTresh(tx_thres) & SSCR1_TFT); 1187 break; 1188 } 1189 1190 chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH); 1191 chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0) 1192 | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0); 1193 1194 if (spi->mode & SPI_LOOP) 1195 chip->cr1 |= SSCR1_LBM; 1196 1197 /* NOTE: PXA25x_SSP _could_ use external clocking ... */ 1198 if (!pxa25x_ssp_comp(drv_data)) 1199 dev_dbg(&spi->dev, "%ld Hz actual, %s\n", 1200 drv_data->max_clk_rate 1201 / (1 + ((chip->cr0 & SSCR0_SCR(0xfff)) >> 8)), 1202 chip->enable_dma ? "DMA" : "PIO"); 1203 else 1204 dev_dbg(&spi->dev, "%ld Hz actual, %s\n", 1205 drv_data->max_clk_rate / 2 1206 / (1 + ((chip->cr0 & SSCR0_SCR(0x0ff)) >> 8)), 1207 chip->enable_dma ? "DMA" : "PIO"); 1208 1209 if (spi->bits_per_word <= 8) { 1210 chip->n_bytes = 1; 1211 chip->read = u8_reader; 1212 chip->write = u8_writer; 1213 } else if (spi->bits_per_word <= 16) { 1214 chip->n_bytes = 2; 1215 chip->read = u16_reader; 1216 chip->write = u16_writer; 1217 } else if (spi->bits_per_word <= 32) { 1218 if (!is_quark_x1000_ssp(drv_data)) 1219 chip->cr0 |= SSCR0_EDSS; 1220 chip->n_bytes = 4; 1221 chip->read = u32_reader; 1222 chip->write = u32_writer; 1223 } 1224 chip->bits_per_word = spi->bits_per_word; 1225 1226 spi_set_ctldata(spi, chip); 1227 1228 if (drv_data->ssp_type == CE4100_SSP) 1229 return 0; 1230 1231 return setup_cs(spi, chip, chip_info); 1232} 1233 1234static void cleanup(struct spi_device *spi) 1235{ 1236 struct chip_data *chip = spi_get_ctldata(spi); 1237 struct driver_data *drv_data = spi_master_get_devdata(spi->master); 1238 1239 if (!chip) 1240 return; 1241 1242 if (drv_data->ssp_type != CE4100_SSP && gpio_is_valid(chip->gpio_cs)) 1243 gpio_free(chip->gpio_cs); 1244 1245 kfree(chip); 1246} 1247 1248#ifdef CONFIG_ACPI 1249static struct pxa2xx_spi_master * 1250pxa2xx_spi_acpi_get_pdata(struct platform_device *pdev) 1251{ 1252 struct pxa2xx_spi_master *pdata; 1253 struct acpi_device *adev; 1254 struct ssp_device *ssp; 1255 struct resource *res; 1256 int devid; 1257 1258 if (!ACPI_HANDLE(&pdev->dev) || 1259 acpi_bus_get_device(ACPI_HANDLE(&pdev->dev), &adev)) 1260 return NULL; 1261 1262 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 1263 if (!pdata) 1264 return NULL; 1265 1266 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1267 if (!res) 1268 return NULL; 1269 1270 ssp = &pdata->ssp; 1271 1272 ssp->phys_base = res->start; 1273 ssp->mmio_base = devm_ioremap_resource(&pdev->dev, res); 1274 if (IS_ERR(ssp->mmio_base)) 1275 return NULL; 1276 1277 ssp->clk = devm_clk_get(&pdev->dev, NULL); 1278 ssp->irq = platform_get_irq(pdev, 0); 1279 ssp->type = LPSS_SSP; 1280 ssp->pdev = pdev; 1281 1282 ssp->port_id = -1; 1283 if (adev->pnp.unique_id && !kstrtoint(adev->pnp.unique_id, 0, &devid)) 1284 ssp->port_id = devid; 1285 1286 pdata->num_chipselect = 1; 1287 pdata->enable_dma = true; 1288 1289 return pdata; 1290} 1291 1292static struct acpi_device_id pxa2xx_spi_acpi_match[] = { 1293 { "INT33C0", 0 }, 1294 { "INT33C1", 0 }, 1295 { "INT3430", 0 }, 1296 { "INT3431", 0 }, 1297 { "80860F0E", 0 }, 1298 { "8086228E", 0 }, 1299 { }, 1300}; 1301MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match); 1302#else 1303static inline struct pxa2xx_spi_master * 1304pxa2xx_spi_acpi_get_pdata(struct platform_device *pdev) 1305{ 1306 return NULL; 1307} 1308#endif 1309 1310static int pxa2xx_spi_probe(struct platform_device *pdev) 1311{ 1312 struct device *dev = &pdev->dev; 1313 struct pxa2xx_spi_master *platform_info; 1314 struct spi_master *master; 1315 struct driver_data *drv_data; 1316 struct ssp_device *ssp; 1317 int status; 1318 u32 tmp; 1319 1320 platform_info = dev_get_platdata(dev); 1321 if (!platform_info) { 1322 platform_info = pxa2xx_spi_acpi_get_pdata(pdev); 1323 if (!platform_info) { 1324 dev_err(&pdev->dev, "missing platform data\n"); 1325 return -ENODEV; 1326 } 1327 } 1328 1329 ssp = pxa_ssp_request(pdev->id, pdev->name); 1330 if (!ssp) 1331 ssp = &platform_info->ssp; 1332 1333 if (!ssp->mmio_base) { 1334 dev_err(&pdev->dev, "failed to get ssp\n"); 1335 return -ENODEV; 1336 } 1337 1338 /* Allocate master with space for drv_data and null dma buffer */ 1339 master = spi_alloc_master(dev, sizeof(struct driver_data) + 16); 1340 if (!master) { 1341 dev_err(&pdev->dev, "cannot alloc spi_master\n"); 1342 pxa_ssp_free(ssp); 1343 return -ENOMEM; 1344 } 1345 drv_data = spi_master_get_devdata(master); 1346 drv_data->master = master; 1347 drv_data->master_info = platform_info; 1348 drv_data->pdev = pdev; 1349 drv_data->ssp = ssp; 1350 1351 master->dev.parent = &pdev->dev; 1352 master->dev.of_node = pdev->dev.of_node; 1353 /* the spi->mode bits understood by this driver: */ 1354 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; 1355 1356 master->bus_num = ssp->port_id; 1357 master->num_chipselect = platform_info->num_chipselect; 1358 master->dma_alignment = DMA_ALIGNMENT; 1359 master->cleanup = cleanup; 1360 master->setup = setup; 1361 master->transfer_one_message = pxa2xx_spi_transfer_one_message; 1362 master->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer; 1363 master->auto_runtime_pm = true; 1364 1365 drv_data->ssp_type = ssp->type; 1366 drv_data->null_dma_buf = (u32 *)PTR_ALIGN(&drv_data[1], DMA_ALIGNMENT); 1367 1368 drv_data->ioaddr = ssp->mmio_base; 1369 drv_data->ssdr_physical = ssp->phys_base + SSDR; 1370 if (pxa25x_ssp_comp(drv_data)) { 1371 switch (drv_data->ssp_type) { 1372 case QUARK_X1000_SSP: 1373 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); 1374 break; 1375 default: 1376 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16); 1377 break; 1378 } 1379 1380 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE; 1381 drv_data->dma_cr1 = 0; 1382 drv_data->clear_sr = SSSR_ROR; 1383 drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR; 1384 } else { 1385 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); 1386 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE; 1387 drv_data->dma_cr1 = DEFAULT_DMA_CR1; 1388 drv_data->clear_sr = SSSR_ROR | SSSR_TINT; 1389 drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR; 1390 } 1391 1392 status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev), 1393 drv_data); 1394 if (status < 0) { 1395 dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq); 1396 goto out_error_master_alloc; 1397 } 1398 1399 /* Setup DMA if requested */ 1400 drv_data->tx_channel = -1; 1401 drv_data->rx_channel = -1; 1402 if (platform_info->enable_dma) { 1403 status = pxa2xx_spi_dma_setup(drv_data); 1404 if (status) { 1405 dev_dbg(dev, "no DMA channels available, using PIO\n"); 1406 platform_info->enable_dma = false; 1407 } 1408 } 1409 1410 /* Enable SOC clock */ 1411 clk_prepare_enable(ssp->clk); 1412 1413 drv_data->max_clk_rate = clk_get_rate(ssp->clk); 1414 1415 /* Load default SSP configuration */ 1416 pxa2xx_spi_write(drv_data, SSCR0, 0); 1417 switch (drv_data->ssp_type) { 1418 case QUARK_X1000_SSP: 1419 tmp = QUARK_X1000_SSCR1_RxTresh(RX_THRESH_QUARK_X1000_DFLT) 1420 | QUARK_X1000_SSCR1_TxTresh(TX_THRESH_QUARK_X1000_DFLT); 1421 pxa2xx_spi_write(drv_data, SSCR1, tmp); 1422 1423 /* using the Motorola SPI protocol and use 8 bit frame */ 1424 pxa2xx_spi_write(drv_data, SSCR0, 1425 QUARK_X1000_SSCR0_Motorola 1426 | QUARK_X1000_SSCR0_DataSize(8)); 1427 break; 1428 default: 1429 tmp = SSCR1_RxTresh(RX_THRESH_DFLT) | 1430 SSCR1_TxTresh(TX_THRESH_DFLT); 1431 pxa2xx_spi_write(drv_data, SSCR1, tmp); 1432 tmp = SSCR0_SCR(2) | SSCR0_Motorola | SSCR0_DataSize(8); 1433 pxa2xx_spi_write(drv_data, SSCR0, tmp); 1434 break; 1435 } 1436 1437 if (!pxa25x_ssp_comp(drv_data)) 1438 pxa2xx_spi_write(drv_data, SSTO, 0); 1439 1440 if (!is_quark_x1000_ssp(drv_data)) 1441 pxa2xx_spi_write(drv_data, SSPSP, 0); 1442 1443 if (is_lpss_ssp(drv_data)) 1444 lpss_ssp_setup(drv_data); 1445 1446 tasklet_init(&drv_data->pump_transfers, pump_transfers, 1447 (unsigned long)drv_data); 1448 1449 pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 1450 pm_runtime_use_autosuspend(&pdev->dev); 1451 pm_runtime_set_active(&pdev->dev); 1452 pm_runtime_enable(&pdev->dev); 1453 1454 /* Register with the SPI framework */ 1455 platform_set_drvdata(pdev, drv_data); 1456 status = devm_spi_register_master(&pdev->dev, master); 1457 if (status != 0) { 1458 dev_err(&pdev->dev, "problem registering spi master\n"); 1459 goto out_error_clock_enabled; 1460 } 1461 1462 return status; 1463 1464out_error_clock_enabled: 1465 clk_disable_unprepare(ssp->clk); 1466 pxa2xx_spi_dma_release(drv_data); 1467 free_irq(ssp->irq, drv_data); 1468 1469out_error_master_alloc: 1470 spi_master_put(master); 1471 pxa_ssp_free(ssp); 1472 return status; 1473} 1474 1475static int pxa2xx_spi_remove(struct platform_device *pdev) 1476{ 1477 struct driver_data *drv_data = platform_get_drvdata(pdev); 1478 struct ssp_device *ssp; 1479 1480 if (!drv_data) 1481 return 0; 1482 ssp = drv_data->ssp; 1483 1484 pm_runtime_get_sync(&pdev->dev); 1485 1486 /* Disable the SSP at the peripheral and SOC level */ 1487 pxa2xx_spi_write(drv_data, SSCR0, 0); 1488 clk_disable_unprepare(ssp->clk); 1489 1490 /* Release DMA */ 1491 if (drv_data->master_info->enable_dma) 1492 pxa2xx_spi_dma_release(drv_data); 1493 1494 pm_runtime_put_noidle(&pdev->dev); 1495 pm_runtime_disable(&pdev->dev); 1496 1497 /* Release IRQ */ 1498 free_irq(ssp->irq, drv_data); 1499 1500 /* Release SSP */ 1501 pxa_ssp_free(ssp); 1502 1503 return 0; 1504} 1505 1506static void pxa2xx_spi_shutdown(struct platform_device *pdev) 1507{ 1508 int status = 0; 1509 1510 if ((status = pxa2xx_spi_remove(pdev)) != 0) 1511 dev_err(&pdev->dev, "shutdown failed with %d\n", status); 1512} 1513 1514#ifdef CONFIG_PM_SLEEP 1515static int pxa2xx_spi_suspend(struct device *dev) 1516{ 1517 struct driver_data *drv_data = dev_get_drvdata(dev); 1518 struct ssp_device *ssp = drv_data->ssp; 1519 int status = 0; 1520 1521 status = spi_master_suspend(drv_data->master); 1522 if (status != 0) 1523 return status; 1524 pxa2xx_spi_write(drv_data, SSCR0, 0); 1525 1526 if (!pm_runtime_suspended(dev)) 1527 clk_disable_unprepare(ssp->clk); 1528 1529 return 0; 1530} 1531 1532static int pxa2xx_spi_resume(struct device *dev) 1533{ 1534 struct driver_data *drv_data = dev_get_drvdata(dev); 1535 struct ssp_device *ssp = drv_data->ssp; 1536 int status = 0; 1537 1538 pxa2xx_spi_dma_resume(drv_data); 1539 1540 /* Enable the SSP clock */ 1541 if (!pm_runtime_suspended(dev)) 1542 clk_prepare_enable(ssp->clk); 1543 1544 /* Restore LPSS private register bits */ 1545 if (is_lpss_ssp(drv_data)) 1546 lpss_ssp_setup(drv_data); 1547 1548 /* Start the queue running */ 1549 status = spi_master_resume(drv_data->master); 1550 if (status != 0) { 1551 dev_err(dev, "problem starting queue (%d)\n", status); 1552 return status; 1553 } 1554 1555 return 0; 1556} 1557#endif 1558 1559#ifdef CONFIG_PM 1560static int pxa2xx_spi_runtime_suspend(struct device *dev) 1561{ 1562 struct driver_data *drv_data = dev_get_drvdata(dev); 1563 1564 clk_disable_unprepare(drv_data->ssp->clk); 1565 return 0; 1566} 1567 1568static int pxa2xx_spi_runtime_resume(struct device *dev) 1569{ 1570 struct driver_data *drv_data = dev_get_drvdata(dev); 1571 1572 clk_prepare_enable(drv_data->ssp->clk); 1573 return 0; 1574} 1575#endif 1576 1577static const struct dev_pm_ops pxa2xx_spi_pm_ops = { 1578 SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume) 1579 SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend, 1580 pxa2xx_spi_runtime_resume, NULL) 1581}; 1582 1583static struct platform_driver driver = { 1584 .driver = { 1585 .name = "pxa2xx-spi", 1586 .pm = &pxa2xx_spi_pm_ops, 1587 .acpi_match_table = ACPI_PTR(pxa2xx_spi_acpi_match), 1588 }, 1589 .probe = pxa2xx_spi_probe, 1590 .remove = pxa2xx_spi_remove, 1591 .shutdown = pxa2xx_spi_shutdown, 1592}; 1593 1594static int __init pxa2xx_spi_init(void) 1595{ 1596 return platform_driver_register(&driver); 1597} 1598subsys_initcall(pxa2xx_spi_init); 1599 1600static void __exit pxa2xx_spi_exit(void) 1601{ 1602 platform_driver_unregister(&driver); 1603} 1604module_exit(pxa2xx_spi_exit); 1605