1/* 2 * Marvell 88SE64xx/88SE94xx pci init 3 * 4 * Copyright 2007 Red Hat, Inc. 5 * Copyright 2008 Marvell. <kewei@marvell.com> 6 * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com> 7 * 8 * This file is licensed under GPLv2. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; version 2 of the 13 * License. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 18 * General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 23 * USA 24*/ 25 26 27#include "mv_sas.h" 28 29int interrupt_coalescing = 0x80; 30 31static struct scsi_transport_template *mvs_stt; 32static const struct mvs_chip_info mvs_chips[] = { 33 [chip_6320] = { 1, 2, 0x400, 17, 16, 6, 9, &mvs_64xx_dispatch, }, 34 [chip_6440] = { 1, 4, 0x400, 17, 16, 6, 9, &mvs_64xx_dispatch, }, 35 [chip_6485] = { 1, 8, 0x800, 33, 32, 6, 10, &mvs_64xx_dispatch, }, 36 [chip_9180] = { 2, 4, 0x800, 17, 64, 8, 9, &mvs_94xx_dispatch, }, 37 [chip_9480] = { 2, 4, 0x800, 17, 64, 8, 9, &mvs_94xx_dispatch, }, 38 [chip_9445] = { 1, 4, 0x800, 17, 64, 8, 11, &mvs_94xx_dispatch, }, 39 [chip_9485] = { 2, 4, 0x800, 17, 64, 8, 11, &mvs_94xx_dispatch, }, 40 [chip_1300] = { 1, 4, 0x400, 17, 16, 6, 9, &mvs_64xx_dispatch, }, 41 [chip_1320] = { 2, 4, 0x800, 17, 64, 8, 9, &mvs_94xx_dispatch, }, 42}; 43 44struct device_attribute *mvst_host_attrs[]; 45 46#define SOC_SAS_NUM 2 47 48static struct scsi_host_template mvs_sht = { 49 .module = THIS_MODULE, 50 .name = DRV_NAME, 51 .queuecommand = sas_queuecommand, 52 .target_alloc = sas_target_alloc, 53 .slave_configure = sas_slave_configure, 54 .scan_finished = mvs_scan_finished, 55 .scan_start = mvs_scan_start, 56 .change_queue_depth = sas_change_queue_depth, 57 .bios_param = sas_bios_param, 58 .can_queue = 1, 59 .cmd_per_lun = 1, 60 .this_id = -1, 61 .sg_tablesize = SG_ALL, 62 .max_sectors = SCSI_DEFAULT_MAX_SECTORS, 63 .use_clustering = ENABLE_CLUSTERING, 64 .eh_device_reset_handler = sas_eh_device_reset_handler, 65 .eh_bus_reset_handler = sas_eh_bus_reset_handler, 66 .target_destroy = sas_target_destroy, 67 .ioctl = sas_ioctl, 68 .shost_attrs = mvst_host_attrs, 69 .use_blk_tags = 1, 70 .track_queue_depth = 1, 71}; 72 73static struct sas_domain_function_template mvs_transport_ops = { 74 .lldd_dev_found = mvs_dev_found, 75 .lldd_dev_gone = mvs_dev_gone, 76 .lldd_execute_task = mvs_queue_command, 77 .lldd_control_phy = mvs_phy_control, 78 79 .lldd_abort_task = mvs_abort_task, 80 .lldd_abort_task_set = mvs_abort_task_set, 81 .lldd_clear_aca = mvs_clear_aca, 82 .lldd_clear_task_set = mvs_clear_task_set, 83 .lldd_I_T_nexus_reset = mvs_I_T_nexus_reset, 84 .lldd_lu_reset = mvs_lu_reset, 85 .lldd_query_task = mvs_query_task, 86 .lldd_port_formed = mvs_port_formed, 87 .lldd_port_deformed = mvs_port_deformed, 88 89}; 90 91static void mvs_phy_init(struct mvs_info *mvi, int phy_id) 92{ 93 struct mvs_phy *phy = &mvi->phy[phy_id]; 94 struct asd_sas_phy *sas_phy = &phy->sas_phy; 95 96 phy->mvi = mvi; 97 phy->port = NULL; 98 init_timer(&phy->timer); 99 sas_phy->enabled = (phy_id < mvi->chip->n_phy) ? 1 : 0; 100 sas_phy->class = SAS; 101 sas_phy->iproto = SAS_PROTOCOL_ALL; 102 sas_phy->tproto = 0; 103 sas_phy->type = PHY_TYPE_PHYSICAL; 104 sas_phy->role = PHY_ROLE_INITIATOR; 105 sas_phy->oob_mode = OOB_NOT_CONNECTED; 106 sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN; 107 108 sas_phy->id = phy_id; 109 sas_phy->sas_addr = &mvi->sas_addr[0]; 110 sas_phy->frame_rcvd = &phy->frame_rcvd[0]; 111 sas_phy->ha = (struct sas_ha_struct *)mvi->shost->hostdata; 112 sas_phy->lldd_phy = phy; 113} 114 115static void mvs_free(struct mvs_info *mvi) 116{ 117 struct mvs_wq *mwq; 118 int slot_nr; 119 120 if (!mvi) 121 return; 122 123 if (mvi->flags & MVF_FLAG_SOC) 124 slot_nr = MVS_SOC_SLOTS; 125 else 126 slot_nr = MVS_CHIP_SLOT_SZ; 127 128 if (mvi->dma_pool) 129 pci_pool_destroy(mvi->dma_pool); 130 131 if (mvi->tx) 132 dma_free_coherent(mvi->dev, 133 sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ, 134 mvi->tx, mvi->tx_dma); 135 if (mvi->rx_fis) 136 dma_free_coherent(mvi->dev, MVS_RX_FISL_SZ, 137 mvi->rx_fis, mvi->rx_fis_dma); 138 if (mvi->rx) 139 dma_free_coherent(mvi->dev, 140 sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1), 141 mvi->rx, mvi->rx_dma); 142 if (mvi->slot) 143 dma_free_coherent(mvi->dev, 144 sizeof(*mvi->slot) * slot_nr, 145 mvi->slot, mvi->slot_dma); 146 147 if (mvi->bulk_buffer) 148 dma_free_coherent(mvi->dev, TRASH_BUCKET_SIZE, 149 mvi->bulk_buffer, mvi->bulk_buffer_dma); 150 if (mvi->bulk_buffer1) 151 dma_free_coherent(mvi->dev, TRASH_BUCKET_SIZE, 152 mvi->bulk_buffer1, mvi->bulk_buffer_dma1); 153 154 MVS_CHIP_DISP->chip_iounmap(mvi); 155 if (mvi->shost) 156 scsi_host_put(mvi->shost); 157 list_for_each_entry(mwq, &mvi->wq_list, entry) 158 cancel_delayed_work(&mwq->work_q); 159 kfree(mvi->tags); 160 kfree(mvi); 161} 162 163#ifdef CONFIG_SCSI_MVSAS_TASKLET 164static void mvs_tasklet(unsigned long opaque) 165{ 166 u32 stat; 167 u16 core_nr, i = 0; 168 169 struct mvs_info *mvi; 170 struct sas_ha_struct *sha = (struct sas_ha_struct *)opaque; 171 172 core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host; 173 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0]; 174 175 if (unlikely(!mvi)) 176 BUG_ON(1); 177 178 stat = MVS_CHIP_DISP->isr_status(mvi, mvi->pdev->irq); 179 if (!stat) 180 goto out; 181 182 for (i = 0; i < core_nr; i++) { 183 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i]; 184 MVS_CHIP_DISP->isr(mvi, mvi->pdev->irq, stat); 185 } 186out: 187 MVS_CHIP_DISP->interrupt_enable(mvi); 188 189} 190#endif 191 192static irqreturn_t mvs_interrupt(int irq, void *opaque) 193{ 194 u32 core_nr; 195 u32 stat; 196 struct mvs_info *mvi; 197 struct sas_ha_struct *sha = opaque; 198#ifndef CONFIG_SCSI_MVSAS_TASKLET 199 u32 i; 200#endif 201 202 core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host; 203 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0]; 204 205 if (unlikely(!mvi)) 206 return IRQ_NONE; 207#ifdef CONFIG_SCSI_MVSAS_TASKLET 208 MVS_CHIP_DISP->interrupt_disable(mvi); 209#endif 210 211 stat = MVS_CHIP_DISP->isr_status(mvi, irq); 212 if (!stat) { 213 #ifdef CONFIG_SCSI_MVSAS_TASKLET 214 MVS_CHIP_DISP->interrupt_enable(mvi); 215 #endif 216 return IRQ_NONE; 217 } 218 219#ifdef CONFIG_SCSI_MVSAS_TASKLET 220 tasklet_schedule(&((struct mvs_prv_info *)sha->lldd_ha)->mv_tasklet); 221#else 222 for (i = 0; i < core_nr; i++) { 223 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i]; 224 MVS_CHIP_DISP->isr(mvi, irq, stat); 225 } 226#endif 227 return IRQ_HANDLED; 228} 229 230static int mvs_alloc(struct mvs_info *mvi, struct Scsi_Host *shost) 231{ 232 int i = 0, slot_nr; 233 char pool_name[32]; 234 235 if (mvi->flags & MVF_FLAG_SOC) 236 slot_nr = MVS_SOC_SLOTS; 237 else 238 slot_nr = MVS_CHIP_SLOT_SZ; 239 240 spin_lock_init(&mvi->lock); 241 for (i = 0; i < mvi->chip->n_phy; i++) { 242 mvs_phy_init(mvi, i); 243 mvi->port[i].wide_port_phymap = 0; 244 mvi->port[i].port_attached = 0; 245 INIT_LIST_HEAD(&mvi->port[i].list); 246 } 247 for (i = 0; i < MVS_MAX_DEVICES; i++) { 248 mvi->devices[i].taskfileset = MVS_ID_NOT_MAPPED; 249 mvi->devices[i].dev_type = SAS_PHY_UNUSED; 250 mvi->devices[i].device_id = i; 251 mvi->devices[i].dev_status = MVS_DEV_NORMAL; 252 init_timer(&mvi->devices[i].timer); 253 } 254 255 /* 256 * alloc and init our DMA areas 257 */ 258 mvi->tx = dma_alloc_coherent(mvi->dev, 259 sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ, 260 &mvi->tx_dma, GFP_KERNEL); 261 if (!mvi->tx) 262 goto err_out; 263 memset(mvi->tx, 0, sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ); 264 mvi->rx_fis = dma_alloc_coherent(mvi->dev, MVS_RX_FISL_SZ, 265 &mvi->rx_fis_dma, GFP_KERNEL); 266 if (!mvi->rx_fis) 267 goto err_out; 268 memset(mvi->rx_fis, 0, MVS_RX_FISL_SZ); 269 270 mvi->rx = dma_alloc_coherent(mvi->dev, 271 sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1), 272 &mvi->rx_dma, GFP_KERNEL); 273 if (!mvi->rx) 274 goto err_out; 275 memset(mvi->rx, 0, sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1)); 276 mvi->rx[0] = cpu_to_le32(0xfff); 277 mvi->rx_cons = 0xfff; 278 279 mvi->slot = dma_alloc_coherent(mvi->dev, 280 sizeof(*mvi->slot) * slot_nr, 281 &mvi->slot_dma, GFP_KERNEL); 282 if (!mvi->slot) 283 goto err_out; 284 memset(mvi->slot, 0, sizeof(*mvi->slot) * slot_nr); 285 286 mvi->bulk_buffer = dma_alloc_coherent(mvi->dev, 287 TRASH_BUCKET_SIZE, 288 &mvi->bulk_buffer_dma, GFP_KERNEL); 289 if (!mvi->bulk_buffer) 290 goto err_out; 291 292 mvi->bulk_buffer1 = dma_alloc_coherent(mvi->dev, 293 TRASH_BUCKET_SIZE, 294 &mvi->bulk_buffer_dma1, GFP_KERNEL); 295 if (!mvi->bulk_buffer1) 296 goto err_out; 297 298 sprintf(pool_name, "%s%d", "mvs_dma_pool", mvi->id); 299 mvi->dma_pool = pci_pool_create(pool_name, mvi->pdev, MVS_SLOT_BUF_SZ, 16, 0); 300 if (!mvi->dma_pool) { 301 printk(KERN_DEBUG "failed to create dma pool %s.\n", pool_name); 302 goto err_out; 303 } 304 mvi->tags_num = slot_nr; 305 306 /* Initialize tags */ 307 mvs_tag_init(mvi); 308 return 0; 309err_out: 310 return 1; 311} 312 313 314int mvs_ioremap(struct mvs_info *mvi, int bar, int bar_ex) 315{ 316 unsigned long res_start, res_len, res_flag, res_flag_ex = 0; 317 struct pci_dev *pdev = mvi->pdev; 318 if (bar_ex != -1) { 319 /* 320 * ioremap main and peripheral registers 321 */ 322 res_start = pci_resource_start(pdev, bar_ex); 323 res_len = pci_resource_len(pdev, bar_ex); 324 if (!res_start || !res_len) 325 goto err_out; 326 327 res_flag_ex = pci_resource_flags(pdev, bar_ex); 328 if (res_flag_ex & IORESOURCE_MEM) { 329 if (res_flag_ex & IORESOURCE_CACHEABLE) 330 mvi->regs_ex = ioremap(res_start, res_len); 331 else 332 mvi->regs_ex = ioremap_nocache(res_start, 333 res_len); 334 } else 335 mvi->regs_ex = (void *)res_start; 336 if (!mvi->regs_ex) 337 goto err_out; 338 } 339 340 res_start = pci_resource_start(pdev, bar); 341 res_len = pci_resource_len(pdev, bar); 342 if (!res_start || !res_len) 343 goto err_out; 344 345 res_flag = pci_resource_flags(pdev, bar); 346 if (res_flag & IORESOURCE_CACHEABLE) 347 mvi->regs = ioremap(res_start, res_len); 348 else 349 mvi->regs = ioremap_nocache(res_start, res_len); 350 351 if (!mvi->regs) { 352 if (mvi->regs_ex && (res_flag_ex & IORESOURCE_MEM)) 353 iounmap(mvi->regs_ex); 354 mvi->regs_ex = NULL; 355 goto err_out; 356 } 357 358 return 0; 359err_out: 360 return -1; 361} 362 363void mvs_iounmap(void __iomem *regs) 364{ 365 iounmap(regs); 366} 367 368static struct mvs_info *mvs_pci_alloc(struct pci_dev *pdev, 369 const struct pci_device_id *ent, 370 struct Scsi_Host *shost, unsigned int id) 371{ 372 struct mvs_info *mvi = NULL; 373 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 374 375 mvi = kzalloc(sizeof(*mvi) + 376 (1L << mvs_chips[ent->driver_data].slot_width) * 377 sizeof(struct mvs_slot_info), GFP_KERNEL); 378 if (!mvi) 379 return NULL; 380 381 mvi->pdev = pdev; 382 mvi->dev = &pdev->dev; 383 mvi->chip_id = ent->driver_data; 384 mvi->chip = &mvs_chips[mvi->chip_id]; 385 INIT_LIST_HEAD(&mvi->wq_list); 386 387 ((struct mvs_prv_info *)sha->lldd_ha)->mvi[id] = mvi; 388 ((struct mvs_prv_info *)sha->lldd_ha)->n_phy = mvi->chip->n_phy; 389 390 mvi->id = id; 391 mvi->sas = sha; 392 mvi->shost = shost; 393 394 mvi->tags = kzalloc(MVS_CHIP_SLOT_SZ>>3, GFP_KERNEL); 395 if (!mvi->tags) 396 goto err_out; 397 398 if (MVS_CHIP_DISP->chip_ioremap(mvi)) 399 goto err_out; 400 if (!mvs_alloc(mvi, shost)) 401 return mvi; 402err_out: 403 mvs_free(mvi); 404 return NULL; 405} 406 407static int pci_go_64(struct pci_dev *pdev) 408{ 409 int rc; 410 411 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) { 412 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 413 if (rc) { 414 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 415 if (rc) { 416 dev_printk(KERN_ERR, &pdev->dev, 417 "64-bit DMA enable failed\n"); 418 return rc; 419 } 420 } 421 } else { 422 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 423 if (rc) { 424 dev_printk(KERN_ERR, &pdev->dev, 425 "32-bit DMA enable failed\n"); 426 return rc; 427 } 428 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 429 if (rc) { 430 dev_printk(KERN_ERR, &pdev->dev, 431 "32-bit consistent DMA enable failed\n"); 432 return rc; 433 } 434 } 435 436 return rc; 437} 438 439static int mvs_prep_sas_ha_init(struct Scsi_Host *shost, 440 const struct mvs_chip_info *chip_info) 441{ 442 int phy_nr, port_nr; unsigned short core_nr; 443 struct asd_sas_phy **arr_phy; 444 struct asd_sas_port **arr_port; 445 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 446 447 core_nr = chip_info->n_host; 448 phy_nr = core_nr * chip_info->n_phy; 449 port_nr = phy_nr; 450 451 memset(sha, 0x00, sizeof(struct sas_ha_struct)); 452 arr_phy = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL); 453 arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL); 454 if (!arr_phy || !arr_port) 455 goto exit_free; 456 457 sha->sas_phy = arr_phy; 458 sha->sas_port = arr_port; 459 sha->core.shost = shost; 460 461 sha->lldd_ha = kzalloc(sizeof(struct mvs_prv_info), GFP_KERNEL); 462 if (!sha->lldd_ha) 463 goto exit_free; 464 465 ((struct mvs_prv_info *)sha->lldd_ha)->n_host = core_nr; 466 467 shost->transportt = mvs_stt; 468 shost->max_id = MVS_MAX_DEVICES; 469 shost->max_lun = ~0; 470 shost->max_channel = 1; 471 shost->max_cmd_len = 16; 472 473 return 0; 474exit_free: 475 kfree(arr_phy); 476 kfree(arr_port); 477 return -1; 478 479} 480 481static void mvs_post_sas_ha_init(struct Scsi_Host *shost, 482 const struct mvs_chip_info *chip_info) 483{ 484 int can_queue, i = 0, j = 0; 485 struct mvs_info *mvi = NULL; 486 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 487 unsigned short nr_core = ((struct mvs_prv_info *)sha->lldd_ha)->n_host; 488 489 for (j = 0; j < nr_core; j++) { 490 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[j]; 491 for (i = 0; i < chip_info->n_phy; i++) { 492 sha->sas_phy[j * chip_info->n_phy + i] = 493 &mvi->phy[i].sas_phy; 494 sha->sas_port[j * chip_info->n_phy + i] = 495 &mvi->port[i].sas_port; 496 } 497 } 498 499 sha->sas_ha_name = DRV_NAME; 500 sha->dev = mvi->dev; 501 sha->lldd_module = THIS_MODULE; 502 sha->sas_addr = &mvi->sas_addr[0]; 503 504 sha->num_phys = nr_core * chip_info->n_phy; 505 506 if (mvi->flags & MVF_FLAG_SOC) 507 can_queue = MVS_SOC_CAN_QUEUE; 508 else 509 can_queue = MVS_CHIP_SLOT_SZ; 510 511 shost->sg_tablesize = min_t(u16, SG_ALL, MVS_MAX_SG); 512 shost->can_queue = can_queue; 513 mvi->shost->cmd_per_lun = MVS_QUEUE_SIZE; 514 sha->core.shost = mvi->shost; 515} 516 517static void mvs_init_sas_add(struct mvs_info *mvi) 518{ 519 u8 i; 520 for (i = 0; i < mvi->chip->n_phy; i++) { 521 mvi->phy[i].dev_sas_addr = 0x5005043011ab0000ULL; 522 mvi->phy[i].dev_sas_addr = 523 cpu_to_be64((u64)(*(u64 *)&mvi->phy[i].dev_sas_addr)); 524 } 525 526 memcpy(mvi->sas_addr, &mvi->phy[0].dev_sas_addr, SAS_ADDR_SIZE); 527} 528 529static int mvs_pci_init(struct pci_dev *pdev, const struct pci_device_id *ent) 530{ 531 unsigned int rc, nhost = 0; 532 struct mvs_info *mvi; 533 struct mvs_prv_info *mpi; 534 irq_handler_t irq_handler = mvs_interrupt; 535 struct Scsi_Host *shost = NULL; 536 const struct mvs_chip_info *chip; 537 538 dev_printk(KERN_INFO, &pdev->dev, 539 "mvsas: driver version %s\n", DRV_VERSION); 540 rc = pci_enable_device(pdev); 541 if (rc) 542 goto err_out_enable; 543 544 pci_set_master(pdev); 545 546 rc = pci_request_regions(pdev, DRV_NAME); 547 if (rc) 548 goto err_out_disable; 549 550 rc = pci_go_64(pdev); 551 if (rc) 552 goto err_out_regions; 553 554 shost = scsi_host_alloc(&mvs_sht, sizeof(void *)); 555 if (!shost) { 556 rc = -ENOMEM; 557 goto err_out_regions; 558 } 559 560 chip = &mvs_chips[ent->driver_data]; 561 SHOST_TO_SAS_HA(shost) = 562 kcalloc(1, sizeof(struct sas_ha_struct), GFP_KERNEL); 563 if (!SHOST_TO_SAS_HA(shost)) { 564 kfree(shost); 565 rc = -ENOMEM; 566 goto err_out_regions; 567 } 568 569 rc = mvs_prep_sas_ha_init(shost, chip); 570 if (rc) { 571 kfree(shost); 572 rc = -ENOMEM; 573 goto err_out_regions; 574 } 575 576 pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost)); 577 578 do { 579 mvi = mvs_pci_alloc(pdev, ent, shost, nhost); 580 if (!mvi) { 581 rc = -ENOMEM; 582 goto err_out_regions; 583 } 584 585 memset(&mvi->hba_info_param, 0xFF, 586 sizeof(struct hba_info_page)); 587 588 mvs_init_sas_add(mvi); 589 590 mvi->instance = nhost; 591 rc = MVS_CHIP_DISP->chip_init(mvi); 592 if (rc) { 593 mvs_free(mvi); 594 goto err_out_regions; 595 } 596 nhost++; 597 } while (nhost < chip->n_host); 598 mpi = (struct mvs_prv_info *)(SHOST_TO_SAS_HA(shost)->lldd_ha); 599#ifdef CONFIG_SCSI_MVSAS_TASKLET 600 tasklet_init(&(mpi->mv_tasklet), mvs_tasklet, 601 (unsigned long)SHOST_TO_SAS_HA(shost)); 602#endif 603 604 mvs_post_sas_ha_init(shost, chip); 605 606 rc = scsi_add_host(shost, &pdev->dev); 607 if (rc) 608 goto err_out_shost; 609 610 rc = sas_register_ha(SHOST_TO_SAS_HA(shost)); 611 if (rc) 612 goto err_out_shost; 613 rc = request_irq(pdev->irq, irq_handler, IRQF_SHARED, 614 DRV_NAME, SHOST_TO_SAS_HA(shost)); 615 if (rc) 616 goto err_not_sas; 617 618 MVS_CHIP_DISP->interrupt_enable(mvi); 619 620 scsi_scan_host(mvi->shost); 621 622 return 0; 623 624err_not_sas: 625 sas_unregister_ha(SHOST_TO_SAS_HA(shost)); 626err_out_shost: 627 scsi_remove_host(mvi->shost); 628err_out_regions: 629 pci_release_regions(pdev); 630err_out_disable: 631 pci_disable_device(pdev); 632err_out_enable: 633 return rc; 634} 635 636static void mvs_pci_remove(struct pci_dev *pdev) 637{ 638 unsigned short core_nr, i = 0; 639 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 640 struct mvs_info *mvi = NULL; 641 642 core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host; 643 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0]; 644 645#ifdef CONFIG_SCSI_MVSAS_TASKLET 646 tasklet_kill(&((struct mvs_prv_info *)sha->lldd_ha)->mv_tasklet); 647#endif 648 649 sas_unregister_ha(sha); 650 sas_remove_host(mvi->shost); 651 scsi_remove_host(mvi->shost); 652 653 MVS_CHIP_DISP->interrupt_disable(mvi); 654 free_irq(mvi->pdev->irq, sha); 655 for (i = 0; i < core_nr; i++) { 656 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i]; 657 mvs_free(mvi); 658 } 659 kfree(sha->sas_phy); 660 kfree(sha->sas_port); 661 kfree(sha); 662 pci_release_regions(pdev); 663 pci_disable_device(pdev); 664 return; 665} 666 667static struct pci_device_id mvs_pci_table[] = { 668 { PCI_VDEVICE(MARVELL, 0x6320), chip_6320 }, 669 { PCI_VDEVICE(MARVELL, 0x6340), chip_6440 }, 670 { 671 .vendor = PCI_VENDOR_ID_MARVELL, 672 .device = 0x6440, 673 .subvendor = PCI_ANY_ID, 674 .subdevice = 0x6480, 675 .class = 0, 676 .class_mask = 0, 677 .driver_data = chip_6485, 678 }, 679 { PCI_VDEVICE(MARVELL, 0x6440), chip_6440 }, 680 { PCI_VDEVICE(MARVELL, 0x6485), chip_6485 }, 681 { PCI_VDEVICE(MARVELL, 0x9480), chip_9480 }, 682 { PCI_VDEVICE(MARVELL, 0x9180), chip_9180 }, 683 { PCI_VDEVICE(ARECA, PCI_DEVICE_ID_ARECA_1300), chip_1300 }, 684 { PCI_VDEVICE(ARECA, PCI_DEVICE_ID_ARECA_1320), chip_1320 }, 685 { PCI_VDEVICE(ADAPTEC2, 0x0450), chip_6440 }, 686 { PCI_VDEVICE(TTI, 0x2710), chip_9480 }, 687 { PCI_VDEVICE(TTI, 0x2720), chip_9480 }, 688 { PCI_VDEVICE(TTI, 0x2721), chip_9480 }, 689 { PCI_VDEVICE(TTI, 0x2722), chip_9480 }, 690 { PCI_VDEVICE(TTI, 0x2740), chip_9480 }, 691 { PCI_VDEVICE(TTI, 0x2744), chip_9480 }, 692 { PCI_VDEVICE(TTI, 0x2760), chip_9480 }, 693 { 694 .vendor = PCI_VENDOR_ID_MARVELL_EXT, 695 .device = 0x9480, 696 .subvendor = PCI_ANY_ID, 697 .subdevice = 0x9480, 698 .class = 0, 699 .class_mask = 0, 700 .driver_data = chip_9480, 701 }, 702 { 703 .vendor = PCI_VENDOR_ID_MARVELL_EXT, 704 .device = 0x9445, 705 .subvendor = PCI_ANY_ID, 706 .subdevice = 0x9480, 707 .class = 0, 708 .class_mask = 0, 709 .driver_data = chip_9445, 710 }, 711 { 712 .vendor = PCI_VENDOR_ID_MARVELL_EXT, 713 .device = 0x9485, 714 .subvendor = PCI_ANY_ID, 715 .subdevice = 0x9480, 716 .class = 0, 717 .class_mask = 0, 718 .driver_data = chip_9485, 719 }, 720 { 721 .vendor = PCI_VENDOR_ID_MARVELL_EXT, 722 .device = 0x9485, 723 .subvendor = PCI_ANY_ID, 724 .subdevice = 0x9485, 725 .class = 0, 726 .class_mask = 0, 727 .driver_data = chip_9485, 728 }, 729 { PCI_VDEVICE(OCZ, 0x1021), chip_9485}, /* OCZ RevoDrive3 */ 730 { PCI_VDEVICE(OCZ, 0x1022), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */ 731 { PCI_VDEVICE(OCZ, 0x1040), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */ 732 { PCI_VDEVICE(OCZ, 0x1041), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */ 733 { PCI_VDEVICE(OCZ, 0x1042), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */ 734 { PCI_VDEVICE(OCZ, 0x1043), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */ 735 { PCI_VDEVICE(OCZ, 0x1044), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */ 736 { PCI_VDEVICE(OCZ, 0x1080), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */ 737 { PCI_VDEVICE(OCZ, 0x1083), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */ 738 { PCI_VDEVICE(OCZ, 0x1084), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */ 739 740 { } /* terminate list */ 741}; 742 743static struct pci_driver mvs_pci_driver = { 744 .name = DRV_NAME, 745 .id_table = mvs_pci_table, 746 .probe = mvs_pci_init, 747 .remove = mvs_pci_remove, 748}; 749 750static ssize_t 751mvs_show_driver_version(struct device *cdev, 752 struct device_attribute *attr, char *buffer) 753{ 754 return snprintf(buffer, PAGE_SIZE, "%s\n", DRV_VERSION); 755} 756 757static DEVICE_ATTR(driver_version, 758 S_IRUGO, 759 mvs_show_driver_version, 760 NULL); 761 762static ssize_t 763mvs_store_interrupt_coalescing(struct device *cdev, 764 struct device_attribute *attr, 765 const char *buffer, size_t size) 766{ 767 int val = 0; 768 struct mvs_info *mvi = NULL; 769 struct Scsi_Host *shost = class_to_shost(cdev); 770 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 771 u8 i, core_nr; 772 if (buffer == NULL) 773 return size; 774 775 if (sscanf(buffer, "%d", &val) != 1) 776 return -EINVAL; 777 778 if (val >= 0x10000) { 779 mv_dprintk("interrupt coalescing timer %d us is" 780 "too long\n", val); 781 return strlen(buffer); 782 } 783 784 interrupt_coalescing = val; 785 786 core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host; 787 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0]; 788 789 if (unlikely(!mvi)) 790 return -EINVAL; 791 792 for (i = 0; i < core_nr; i++) { 793 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i]; 794 if (MVS_CHIP_DISP->tune_interrupt) 795 MVS_CHIP_DISP->tune_interrupt(mvi, 796 interrupt_coalescing); 797 } 798 mv_dprintk("set interrupt coalescing time to %d us\n", 799 interrupt_coalescing); 800 return strlen(buffer); 801} 802 803static ssize_t mvs_show_interrupt_coalescing(struct device *cdev, 804 struct device_attribute *attr, char *buffer) 805{ 806 return snprintf(buffer, PAGE_SIZE, "%d\n", interrupt_coalescing); 807} 808 809static DEVICE_ATTR(interrupt_coalescing, 810 S_IRUGO|S_IWUSR, 811 mvs_show_interrupt_coalescing, 812 mvs_store_interrupt_coalescing); 813 814/* task handler */ 815struct task_struct *mvs_th; 816static int __init mvs_init(void) 817{ 818 int rc; 819 mvs_stt = sas_domain_attach_transport(&mvs_transport_ops); 820 if (!mvs_stt) 821 return -ENOMEM; 822 823 rc = pci_register_driver(&mvs_pci_driver); 824 if (rc) 825 goto err_out; 826 827 return 0; 828 829err_out: 830 sas_release_transport(mvs_stt); 831 return rc; 832} 833 834static void __exit mvs_exit(void) 835{ 836 pci_unregister_driver(&mvs_pci_driver); 837 sas_release_transport(mvs_stt); 838} 839 840struct device_attribute *mvst_host_attrs[] = { 841 &dev_attr_driver_version, 842 &dev_attr_interrupt_coalescing, 843 NULL, 844}; 845 846module_init(mvs_init); 847module_exit(mvs_exit); 848 849MODULE_AUTHOR("Jeff Garzik <jgarzik@pobox.com>"); 850MODULE_DESCRIPTION("Marvell 88SE6440 SAS/SATA controller driver"); 851MODULE_VERSION(DRV_VERSION); 852MODULE_LICENSE("GPL"); 853#ifdef CONFIG_PCI 854MODULE_DEVICE_TABLE(pci, mvs_pci_table); 855#endif 856