1/*
2 * AMD am53c974 driver.
3 * Copyright (c) 2014 Hannes Reinecke, SUSE Linux GmbH
4 */
5
6#include <linux/kernel.h>
7#include <linux/module.h>
8#include <linux/init.h>
9#include <linux/delay.h>
10#include <linux/pci.h>
11#include <linux/interrupt.h>
12
13#include <scsi/scsi_host.h>
14
15#include "esp_scsi.h"
16
17#define DRV_MODULE_NAME "am53c974"
18#define DRV_MODULE_VERSION "1.00"
19
20static bool am53c974_debug;
21static bool am53c974_fenab = true;
22
23#define esp_dma_log(f, a...)						\
24	do {								\
25		if (am53c974_debug)					\
26			shost_printk(KERN_DEBUG, esp->host, f, ##a);	\
27	} while (0)
28
29#define ESP_DMA_CMD 0x10
30#define ESP_DMA_STC 0x11
31#define ESP_DMA_SPA 0x12
32#define ESP_DMA_WBC 0x13
33#define ESP_DMA_WAC 0x14
34#define ESP_DMA_STATUS 0x15
35#define ESP_DMA_SMDLA 0x16
36#define ESP_DMA_WMAC 0x17
37
38#define ESP_DMA_CMD_IDLE 0x00
39#define ESP_DMA_CMD_BLAST 0x01
40#define ESP_DMA_CMD_ABORT 0x02
41#define ESP_DMA_CMD_START 0x03
42#define ESP_DMA_CMD_MASK  0x03
43#define ESP_DMA_CMD_DIAG 0x04
44#define ESP_DMA_CMD_MDL 0x10
45#define ESP_DMA_CMD_INTE_P 0x20
46#define ESP_DMA_CMD_INTE_D 0x40
47#define ESP_DMA_CMD_DIR 0x80
48
49#define ESP_DMA_STAT_PWDN 0x01
50#define ESP_DMA_STAT_ERROR 0x02
51#define ESP_DMA_STAT_ABORT 0x04
52#define ESP_DMA_STAT_DONE 0x08
53#define ESP_DMA_STAT_SCSIINT 0x10
54#define ESP_DMA_STAT_BCMPLT 0x20
55
56/* EEPROM is accessed with 16-bit values */
57#define DC390_EEPROM_READ 0x80
58#define DC390_EEPROM_LEN 0x40
59
60/*
61 * DC390 EEPROM
62 *
63 * 8 * 4 bytes of per-device options
64 * followed by HBA specific options
65 */
66
67/* Per-device options */
68#define DC390_EE_MODE1 0x00
69#define DC390_EE_SPEED 0x01
70
71/* HBA-specific options */
72#define DC390_EE_ADAPT_SCSI_ID 0x40
73#define DC390_EE_MODE2 0x41
74#define DC390_EE_DELAY 0x42
75#define DC390_EE_TAG_CMD_NUM 0x43
76
77#define DC390_EE_MODE1_PARITY_CHK   0x01
78#define DC390_EE_MODE1_SYNC_NEGO    0x02
79#define DC390_EE_MODE1_EN_DISC      0x04
80#define DC390_EE_MODE1_SEND_START   0x08
81#define DC390_EE_MODE1_TCQ          0x10
82
83#define DC390_EE_MODE2_MORE_2DRV    0x01
84#define DC390_EE_MODE2_GREATER_1G   0x02
85#define DC390_EE_MODE2_RST_SCSI_BUS 0x04
86#define DC390_EE_MODE2_ACTIVE_NEGATION 0x08
87#define DC390_EE_MODE2_NO_SEEK      0x10
88#define DC390_EE_MODE2_LUN_CHECK    0x20
89
90struct pci_esp_priv {
91	struct esp *esp;
92	u8 dma_status;
93};
94
95static void pci_esp_dma_drain(struct esp *esp);
96
97static inline struct pci_esp_priv *pci_esp_get_priv(struct esp *esp)
98{
99	struct pci_dev *pdev = esp->dev;
100
101	return pci_get_drvdata(pdev);
102}
103
104static void pci_esp_write8(struct esp *esp, u8 val, unsigned long reg)
105{
106	iowrite8(val, esp->regs + (reg * 4UL));
107}
108
109static u8 pci_esp_read8(struct esp *esp, unsigned long reg)
110{
111	return ioread8(esp->regs + (reg * 4UL));
112}
113
114static void pci_esp_write32(struct esp *esp, u32 val, unsigned long reg)
115{
116	return iowrite32(val, esp->regs + (reg * 4UL));
117}
118
119static dma_addr_t pci_esp_map_single(struct esp *esp, void *buf,
120				     size_t sz, int dir)
121{
122	return pci_map_single(esp->dev, buf, sz, dir);
123}
124
125static int pci_esp_map_sg(struct esp *esp, struct scatterlist *sg,
126			  int num_sg, int dir)
127{
128	return pci_map_sg(esp->dev, sg, num_sg, dir);
129}
130
131static void pci_esp_unmap_single(struct esp *esp, dma_addr_t addr,
132				 size_t sz, int dir)
133{
134	pci_unmap_single(esp->dev, addr, sz, dir);
135}
136
137static void pci_esp_unmap_sg(struct esp *esp, struct scatterlist *sg,
138			     int num_sg, int dir)
139{
140	pci_unmap_sg(esp->dev, sg, num_sg, dir);
141}
142
143static int pci_esp_irq_pending(struct esp *esp)
144{
145	struct pci_esp_priv *pep = pci_esp_get_priv(esp);
146
147	pep->dma_status = pci_esp_read8(esp, ESP_DMA_STATUS);
148	esp_dma_log("dma intr dreg[%02x]\n", pep->dma_status);
149
150	if (pep->dma_status & (ESP_DMA_STAT_ERROR |
151			       ESP_DMA_STAT_ABORT |
152			       ESP_DMA_STAT_DONE |
153			       ESP_DMA_STAT_SCSIINT))
154		return 1;
155
156	return 0;
157}
158
159static void pci_esp_reset_dma(struct esp *esp)
160{
161	/* Nothing to do ? */
162}
163
164static void pci_esp_dma_drain(struct esp *esp)
165{
166	u8 resid;
167	int lim = 1000;
168
169
170	if ((esp->sreg & ESP_STAT_PMASK) == ESP_DOP ||
171	    (esp->sreg & ESP_STAT_PMASK) == ESP_DIP)
172		/* Data-In or Data-Out, nothing to be done */
173		return;
174
175	while (--lim > 0) {
176		resid = pci_esp_read8(esp, ESP_FFLAGS) & ESP_FF_FBYTES;
177		if (resid <= 1)
178			break;
179		cpu_relax();
180	}
181
182	/*
183	 * When there is a residual BCMPLT will never be set
184	 * (obviously). But we still have to issue the BLAST
185	 * command, otherwise the data will not being transferred.
186	 * But we'll never know when the BLAST operation is
187	 * finished. So check for some time and give up eventually.
188	 */
189	lim = 1000;
190	pci_esp_write8(esp, ESP_DMA_CMD_DIR | ESP_DMA_CMD_BLAST, ESP_DMA_CMD);
191	while (pci_esp_read8(esp, ESP_DMA_STATUS) & ESP_DMA_STAT_BCMPLT) {
192		if (--lim == 0)
193			break;
194		cpu_relax();
195	}
196	pci_esp_write8(esp, ESP_DMA_CMD_DIR | ESP_DMA_CMD_IDLE, ESP_DMA_CMD);
197	esp_dma_log("DMA blast done (%d tries, %d bytes left)\n", lim, resid);
198	/* BLAST residual handling is currently untested */
199	if (WARN_ON_ONCE(resid == 1)) {
200		struct esp_cmd_entry *ent = esp->active_cmd;
201
202		ent->flags |= ESP_CMD_FLAG_RESIDUAL;
203	}
204}
205
206static void pci_esp_dma_invalidate(struct esp *esp)
207{
208	struct pci_esp_priv *pep = pci_esp_get_priv(esp);
209
210	esp_dma_log("invalidate DMA\n");
211
212	pci_esp_write8(esp, ESP_DMA_CMD_IDLE, ESP_DMA_CMD);
213	pep->dma_status = 0;
214}
215
216static int pci_esp_dma_error(struct esp *esp)
217{
218	struct pci_esp_priv *pep = pci_esp_get_priv(esp);
219
220	if (pep->dma_status & ESP_DMA_STAT_ERROR) {
221		u8 dma_cmd = pci_esp_read8(esp, ESP_DMA_CMD);
222
223		if ((dma_cmd & ESP_DMA_CMD_MASK) == ESP_DMA_CMD_START)
224			pci_esp_write8(esp, ESP_DMA_CMD_ABORT, ESP_DMA_CMD);
225
226		return 1;
227	}
228	if (pep->dma_status & ESP_DMA_STAT_ABORT) {
229		pci_esp_write8(esp, ESP_DMA_CMD_IDLE, ESP_DMA_CMD);
230		pep->dma_status = pci_esp_read8(esp, ESP_DMA_CMD);
231		return 1;
232	}
233	return 0;
234}
235
236static void pci_esp_send_dma_cmd(struct esp *esp, u32 addr, u32 esp_count,
237				 u32 dma_count, int write, u8 cmd)
238{
239	struct pci_esp_priv *pep = pci_esp_get_priv(esp);
240	u32 val = 0;
241
242	BUG_ON(!(cmd & ESP_CMD_DMA));
243
244	pep->dma_status = 0;
245
246	/* Set DMA engine to IDLE */
247	if (write)
248		/* DMA write direction logic is inverted */
249		val |= ESP_DMA_CMD_DIR;
250	pci_esp_write8(esp, ESP_DMA_CMD_IDLE | val, ESP_DMA_CMD);
251
252	pci_esp_write8(esp, (esp_count >> 0) & 0xff, ESP_TCLOW);
253	pci_esp_write8(esp, (esp_count >> 8) & 0xff, ESP_TCMED);
254	if (esp->config2 & ESP_CONFIG2_FENAB)
255		pci_esp_write8(esp, (esp_count >> 16) & 0xff, ESP_TCHI);
256
257	pci_esp_write32(esp, esp_count, ESP_DMA_STC);
258	pci_esp_write32(esp, addr, ESP_DMA_SPA);
259
260	esp_dma_log("start dma addr[%x] count[%d:%d]\n",
261		    addr, esp_count, dma_count);
262
263	scsi_esp_cmd(esp, cmd);
264	/* Send DMA Start command */
265	pci_esp_write8(esp, ESP_DMA_CMD_START | val, ESP_DMA_CMD);
266}
267
268static u32 pci_esp_dma_length_limit(struct esp *esp, u32 dma_addr, u32 dma_len)
269{
270	int dma_limit = 16;
271	u32 base, end;
272
273	/*
274	 * If CONFIG2_FENAB is set we can
275	 * handle up to 24 bit addresses
276	 */
277	if (esp->config2 & ESP_CONFIG2_FENAB)
278		dma_limit = 24;
279
280	if (dma_len > (1U << dma_limit))
281		dma_len = (1U << dma_limit);
282
283	/*
284	 * Prevent crossing a 24-bit address boundary.
285	 */
286	base = dma_addr & ((1U << 24) - 1U);
287	end = base + dma_len;
288	if (end > (1U << 24))
289		end = (1U <<24);
290	dma_len = end - base;
291
292	return dma_len;
293}
294
295static const struct esp_driver_ops pci_esp_ops = {
296	.esp_write8	=	pci_esp_write8,
297	.esp_read8	=	pci_esp_read8,
298	.map_single	=	pci_esp_map_single,
299	.map_sg		=	pci_esp_map_sg,
300	.unmap_single	=	pci_esp_unmap_single,
301	.unmap_sg	=	pci_esp_unmap_sg,
302	.irq_pending	=	pci_esp_irq_pending,
303	.reset_dma	=	pci_esp_reset_dma,
304	.dma_drain	=	pci_esp_dma_drain,
305	.dma_invalidate	=	pci_esp_dma_invalidate,
306	.send_dma_cmd	=	pci_esp_send_dma_cmd,
307	.dma_error	=	pci_esp_dma_error,
308	.dma_length_limit =	pci_esp_dma_length_limit,
309};
310
311/*
312 * Read DC-390 eeprom
313 */
314static void dc390_eeprom_prepare_read(struct pci_dev *pdev, u8 cmd)
315{
316	u8 carry_flag = 1, j = 0x80, bval;
317	int i;
318
319	for (i = 0; i < 9; i++) {
320		if (carry_flag) {
321			pci_write_config_byte(pdev, 0x80, 0x40);
322			bval = 0xc0;
323		} else
324			bval = 0x80;
325
326		udelay(160);
327		pci_write_config_byte(pdev, 0x80, bval);
328		udelay(160);
329		pci_write_config_byte(pdev, 0x80, 0);
330		udelay(160);
331
332		carry_flag = (cmd & j) ? 1 : 0;
333		j >>= 1;
334	}
335}
336
337static u16 dc390_eeprom_get_data(struct pci_dev *pdev)
338{
339	int i;
340	u16 wval = 0;
341	u8 bval;
342
343	for (i = 0; i < 16; i++) {
344		wval <<= 1;
345
346		pci_write_config_byte(pdev, 0x80, 0x80);
347		udelay(160);
348		pci_write_config_byte(pdev, 0x80, 0x40);
349		udelay(160);
350		pci_read_config_byte(pdev, 0x00, &bval);
351
352		if (bval == 0x22)
353			wval |= 1;
354	}
355
356	return wval;
357}
358
359static void dc390_read_eeprom(struct pci_dev *pdev, u16 *ptr)
360{
361	u8 cmd = DC390_EEPROM_READ, i;
362
363	for (i = 0; i < DC390_EEPROM_LEN; i++) {
364		pci_write_config_byte(pdev, 0xc0, 0);
365		udelay(160);
366
367		dc390_eeprom_prepare_read(pdev, cmd++);
368		*ptr++ = dc390_eeprom_get_data(pdev);
369
370		pci_write_config_byte(pdev, 0x80, 0);
371		pci_write_config_byte(pdev, 0x80, 0);
372		udelay(160);
373	}
374}
375
376static void dc390_check_eeprom(struct esp *esp)
377{
378	u8 EEbuf[128];
379	u16 *ptr = (u16 *)EEbuf, wval = 0;
380	int i;
381
382	dc390_read_eeprom((struct pci_dev *)esp->dev, ptr);
383
384	for (i = 0; i < DC390_EEPROM_LEN; i++, ptr++)
385		wval += *ptr;
386
387	/* no Tekram EEprom found */
388	if (wval != 0x1234) {
389		struct pci_dev *pdev = esp->dev;
390		dev_printk(KERN_INFO, &pdev->dev,
391			   "No valid Tekram EEprom found\n");
392		return;
393	}
394	esp->scsi_id = EEbuf[DC390_EE_ADAPT_SCSI_ID];
395	esp->num_tags = 2 << EEbuf[DC390_EE_TAG_CMD_NUM];
396	if (EEbuf[DC390_EE_MODE2] & DC390_EE_MODE2_ACTIVE_NEGATION)
397		esp->config4 |= ESP_CONFIG4_RADE | ESP_CONFIG4_RAE;
398}
399
400static int pci_esp_probe_one(struct pci_dev *pdev,
401			      const struct pci_device_id *id)
402{
403	struct scsi_host_template *hostt = &scsi_esp_template;
404	int err = -ENODEV;
405	struct Scsi_Host *shost;
406	struct esp *esp;
407	struct pci_esp_priv *pep;
408
409	if (pci_enable_device(pdev)) {
410		dev_printk(KERN_INFO, &pdev->dev, "cannot enable device\n");
411		return -ENODEV;
412	}
413
414	if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
415		dev_printk(KERN_INFO, &pdev->dev,
416			   "failed to set 32bit DMA mask\n");
417		goto fail_disable_device;
418	}
419
420	shost = scsi_host_alloc(hostt, sizeof(struct esp));
421	if (!shost) {
422		dev_printk(KERN_INFO, &pdev->dev,
423			   "failed to allocate scsi host\n");
424		err = -ENOMEM;
425		goto fail_disable_device;
426	}
427
428	pep = kzalloc(sizeof(struct pci_esp_priv), GFP_KERNEL);
429	if (!pep) {
430		dev_printk(KERN_INFO, &pdev->dev,
431			   "failed to allocate esp_priv\n");
432		err = -ENOMEM;
433		goto fail_host_alloc;
434	}
435
436	esp = shost_priv(shost);
437	esp->host = shost;
438	esp->dev = pdev;
439	esp->ops = &pci_esp_ops;
440	/*
441	 * The am53c974 HBA has a design flaw of generating
442	 * spurious DMA completion interrupts when using
443	 * DMA for command submission.
444	 */
445	esp->flags |= ESP_FLAG_USE_FIFO;
446	/*
447	 * Enable CONFIG2_FENAB to allow for large DMA transfers
448	 */
449	if (am53c974_fenab)
450		esp->config2 |= ESP_CONFIG2_FENAB;
451
452	pep->esp = esp;
453
454	if (pci_request_regions(pdev, DRV_MODULE_NAME)) {
455		dev_printk(KERN_ERR, &pdev->dev,
456			   "pci memory selection failed\n");
457		goto fail_priv_alloc;
458	}
459
460	esp->regs = pci_iomap(pdev, 0, pci_resource_len(pdev, 0));
461	if (!esp->regs) {
462		dev_printk(KERN_ERR, &pdev->dev, "pci I/O map failed\n");
463		err = -EINVAL;
464		goto fail_release_regions;
465	}
466	esp->dma_regs = esp->regs;
467
468	pci_set_master(pdev);
469
470	esp->command_block = pci_alloc_consistent(pdev, 16,
471						  &esp->command_block_dma);
472	if (!esp->command_block) {
473		dev_printk(KERN_ERR, &pdev->dev,
474			   "failed to allocate command block\n");
475		err = -ENOMEM;
476		goto fail_unmap_regs;
477	}
478
479	pci_set_drvdata(pdev, pep);
480
481	err = request_irq(pdev->irq, scsi_esp_intr, IRQF_SHARED,
482			  DRV_MODULE_NAME, esp);
483	if (err < 0) {
484		dev_printk(KERN_ERR, &pdev->dev, "failed to register IRQ\n");
485		goto fail_unmap_command_block;
486	}
487
488	esp->scsi_id = 7;
489	dc390_check_eeprom(esp);
490
491	shost->this_id = esp->scsi_id;
492	shost->max_id = 8;
493	shost->irq = pdev->irq;
494	shost->io_port = pci_resource_start(pdev, 0);
495	shost->n_io_port = pci_resource_len(pdev, 0);
496	shost->unique_id = shost->io_port;
497	esp->scsi_id_mask = (1 << esp->scsi_id);
498	/* Assume 40MHz clock */
499	esp->cfreq = 40000000;
500
501	err = scsi_esp_register(esp, &pdev->dev);
502	if (err)
503		goto fail_free_irq;
504
505	return 0;
506
507fail_free_irq:
508	free_irq(pdev->irq, esp);
509fail_unmap_command_block:
510	pci_set_drvdata(pdev, NULL);
511	pci_free_consistent(pdev, 16, esp->command_block,
512			    esp->command_block_dma);
513fail_unmap_regs:
514	pci_iounmap(pdev, esp->regs);
515fail_release_regions:
516	pci_release_regions(pdev);
517fail_priv_alloc:
518	kfree(pep);
519fail_host_alloc:
520	scsi_host_put(shost);
521fail_disable_device:
522	pci_disable_device(pdev);
523
524	return err;
525}
526
527static void pci_esp_remove_one(struct pci_dev *pdev)
528{
529	struct pci_esp_priv *pep = pci_get_drvdata(pdev);
530	struct esp *esp = pep->esp;
531
532	scsi_esp_unregister(esp);
533	free_irq(pdev->irq, esp);
534	pci_set_drvdata(pdev, NULL);
535	pci_free_consistent(pdev, 16, esp->command_block,
536			    esp->command_block_dma);
537	pci_iounmap(pdev, esp->regs);
538	pci_release_regions(pdev);
539	pci_disable_device(pdev);
540	kfree(pep);
541
542	scsi_host_put(esp->host);
543}
544
545static struct pci_device_id am53c974_pci_tbl[] = {
546	{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_SCSI,
547		PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
548	{ }
549};
550MODULE_DEVICE_TABLE(pci, am53c974_pci_tbl);
551
552static struct pci_driver am53c974_driver = {
553	.name           = DRV_MODULE_NAME,
554	.id_table       = am53c974_pci_tbl,
555	.probe          = pci_esp_probe_one,
556	.remove         = pci_esp_remove_one,
557};
558
559static int __init am53c974_module_init(void)
560{
561	return pci_register_driver(&am53c974_driver);
562}
563
564static void __exit am53c974_module_exit(void)
565{
566	pci_unregister_driver(&am53c974_driver);
567}
568
569MODULE_DESCRIPTION("AM53C974 SCSI driver");
570MODULE_AUTHOR("Hannes Reinecke <hare@suse.de>");
571MODULE_LICENSE("GPL");
572MODULE_VERSION(DRV_MODULE_VERSION);
573MODULE_ALIAS("tmscsim");
574
575module_param(am53c974_debug, bool, 0644);
576MODULE_PARM_DESC(am53c974_debug, "Enable debugging");
577
578module_param(am53c974_fenab, bool, 0444);
579MODULE_PARM_DESC(am53c974_fenab, "Enable 24-bit DMA transfer sizes");
580
581module_init(am53c974_module_init);
582module_exit(am53c974_module_exit);
583