1/*
2 * sh73a0 processor support - PFC hardware block
3 *
4 * Copyright (C) 2010 Renesas Solutions Corp.
5 * Copyright (C) 2010 NISHIMOTO Hiroki
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; version 2 of the
10 * License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
20 */
21#include <linux/io.h>
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/pinctrl/pinconf-generic.h>
25#include <linux/regulator/driver.h>
26#include <linux/regulator/machine.h>
27#include <linux/slab.h>
28
29#ifndef CONFIG_ARCH_MULTIPLATFORM
30#include <mach/irqs.h>
31#endif
32
33#include "core.h"
34#include "sh_pfc.h"
35
36#define CPU_ALL_PORT(fn, pfx, sfx)					\
37	PORT_10(0,  fn, pfx, sfx), PORT_90(0, fn, pfx, sfx),		\
38	PORT_10(100, fn, pfx##10, sfx),					\
39	PORT_1(110, fn, pfx##110, sfx), PORT_1(111, fn, pfx##111, sfx),	\
40	PORT_1(112, fn, pfx##112, sfx), PORT_1(113, fn, pfx##113, sfx),	\
41	PORT_1(114, fn, pfx##114, sfx), PORT_1(115, fn, pfx##115, sfx),	\
42	PORT_1(116, fn, pfx##116, sfx), PORT_1(117, fn, pfx##117, sfx),	\
43	PORT_1(118, fn, pfx##118, sfx),					\
44	PORT_1(128, fn, pfx##128, sfx), PORT_1(129, fn, pfx##129, sfx),	\
45	PORT_10(130, fn, pfx##13, sfx), PORT_10(140, fn, pfx##14, sfx),	\
46	PORT_10(150, fn, pfx##15, sfx),					\
47	PORT_1(160, fn, pfx##160, sfx), PORT_1(161, fn, pfx##161, sfx),	\
48	PORT_1(162, fn, pfx##162, sfx), PORT_1(163, fn, pfx##163, sfx),	\
49	PORT_1(164, fn, pfx##164, sfx),					\
50	PORT_1(192, fn, pfx##192, sfx), PORT_1(193, fn, pfx##193, sfx),	\
51	PORT_1(194, fn, pfx##194, sfx), PORT_1(195, fn, pfx##195, sfx),	\
52	PORT_1(196, fn, pfx##196, sfx), PORT_1(197, fn, pfx##197, sfx),	\
53	PORT_1(198, fn, pfx##198, sfx), PORT_1(199, fn, pfx##199, sfx),	\
54	PORT_10(200, fn, pfx##20, sfx), PORT_10(210, fn, pfx##21, sfx),	\
55	PORT_10(220, fn, pfx##22, sfx), PORT_10(230, fn, pfx##23, sfx),	\
56	PORT_10(240, fn, pfx##24, sfx), PORT_10(250, fn, pfx##25, sfx),	\
57	PORT_10(260, fn, pfx##26, sfx), PORT_10(270, fn, pfx##27, sfx),	\
58	PORT_1(280, fn, pfx##280, sfx), PORT_1(281, fn, pfx##281, sfx),	\
59	PORT_1(282, fn, pfx##282, sfx),					\
60	PORT_1(288, fn, pfx##288, sfx), PORT_1(289, fn, pfx##289, sfx),	\
61	PORT_10(290, fn, pfx##29, sfx), PORT_10(300, fn, pfx##30, sfx)
62
63enum {
64	PINMUX_RESERVED = 0,
65
66	PINMUX_DATA_BEGIN,
67	PORT_ALL(DATA),			/* PORT0_DATA -> PORT309_DATA */
68	PINMUX_DATA_END,
69
70	PINMUX_INPUT_BEGIN,
71	PORT_ALL(IN),			/* PORT0_IN -> PORT309_IN */
72	PINMUX_INPUT_END,
73
74	PINMUX_OUTPUT_BEGIN,
75	PORT_ALL(OUT),			/* PORT0_OUT -> PORT309_OUT */
76	PINMUX_OUTPUT_END,
77
78	PINMUX_FUNCTION_BEGIN,
79	PORT_ALL(FN_IN),		/* PORT0_FN_IN -> PORT309_FN_IN */
80	PORT_ALL(FN_OUT),		/* PORT0_FN_OUT -> PORT309_FN_OUT */
81	PORT_ALL(FN0),			/* PORT0_FN0 -> PORT309_FN0 */
82	PORT_ALL(FN1),			/* PORT0_FN1 -> PORT309_FN1 */
83	PORT_ALL(FN2),			/* PORT0_FN2 -> PORT309_FN2 */
84	PORT_ALL(FN3),			/* PORT0_FN3 -> PORT309_FN3 */
85	PORT_ALL(FN4),			/* PORT0_FN4 -> PORT309_FN4 */
86	PORT_ALL(FN5),			/* PORT0_FN5 -> PORT309_FN5 */
87	PORT_ALL(FN6),			/* PORT0_FN6 -> PORT309_FN6 */
88	PORT_ALL(FN7),			/* PORT0_FN7 -> PORT309_FN7 */
89
90	MSEL2CR_MSEL19_0, MSEL2CR_MSEL19_1,
91	MSEL2CR_MSEL18_0, MSEL2CR_MSEL18_1,
92	MSEL2CR_MSEL17_0, MSEL2CR_MSEL17_1,
93	MSEL2CR_MSEL16_0, MSEL2CR_MSEL16_1,
94	MSEL2CR_MSEL14_0, MSEL2CR_MSEL14_1,
95	MSEL2CR_MSEL13_0, MSEL2CR_MSEL13_1,
96	MSEL2CR_MSEL12_0, MSEL2CR_MSEL12_1,
97	MSEL2CR_MSEL11_0, MSEL2CR_MSEL11_1,
98	MSEL2CR_MSEL10_0, MSEL2CR_MSEL10_1,
99	MSEL2CR_MSEL9_0, MSEL2CR_MSEL9_1,
100	MSEL2CR_MSEL8_0, MSEL2CR_MSEL8_1,
101	MSEL2CR_MSEL7_0, MSEL2CR_MSEL7_1,
102	MSEL2CR_MSEL6_0, MSEL2CR_MSEL6_1,
103	MSEL2CR_MSEL4_0, MSEL2CR_MSEL4_1,
104	MSEL2CR_MSEL5_0, MSEL2CR_MSEL5_1,
105	MSEL2CR_MSEL3_0, MSEL2CR_MSEL3_1,
106	MSEL2CR_MSEL2_0, MSEL2CR_MSEL2_1,
107	MSEL2CR_MSEL1_0, MSEL2CR_MSEL1_1,
108	MSEL2CR_MSEL0_0, MSEL2CR_MSEL0_1,
109	MSEL3CR_MSEL28_0, MSEL3CR_MSEL28_1,
110	MSEL3CR_MSEL15_0, MSEL3CR_MSEL15_1,
111	MSEL3CR_MSEL11_0, MSEL3CR_MSEL11_1,
112	MSEL3CR_MSEL9_0, MSEL3CR_MSEL9_1,
113	MSEL3CR_MSEL6_0, MSEL3CR_MSEL6_1,
114	MSEL3CR_MSEL2_0, MSEL3CR_MSEL2_1,
115	MSEL4CR_MSEL29_0, MSEL4CR_MSEL29_1,
116	MSEL4CR_MSEL27_0, MSEL4CR_MSEL27_1,
117	MSEL4CR_MSEL26_0, MSEL4CR_MSEL26_1,
118	MSEL4CR_MSEL22_0, MSEL4CR_MSEL22_1,
119	MSEL4CR_MSEL21_0, MSEL4CR_MSEL21_1,
120	MSEL4CR_MSEL20_0, MSEL4CR_MSEL20_1,
121	MSEL4CR_MSEL19_0, MSEL4CR_MSEL19_1,
122	MSEL4CR_MSEL15_0, MSEL4CR_MSEL15_1,
123	MSEL4CR_MSEL13_0, MSEL4CR_MSEL13_1,
124	MSEL4CR_MSEL12_0, MSEL4CR_MSEL12_1,
125	MSEL4CR_MSEL11_0, MSEL4CR_MSEL11_1,
126	MSEL4CR_MSEL10_0, MSEL4CR_MSEL10_1,
127	MSEL4CR_MSEL9_0, MSEL4CR_MSEL9_1,
128	MSEL4CR_MSEL8_0, MSEL4CR_MSEL8_1,
129	MSEL4CR_MSEL7_0, MSEL4CR_MSEL7_1,
130	MSEL4CR_MSEL4_0, MSEL4CR_MSEL4_1,
131	MSEL4CR_MSEL1_0, MSEL4CR_MSEL1_1,
132	PINMUX_FUNCTION_END,
133
134	PINMUX_MARK_BEGIN,
135	/* Hardware manual Table 25-1 (Function 0-7) */
136	VBUS_0_MARK,
137	GPI0_MARK,
138	GPI1_MARK,
139	GPI2_MARK,
140	GPI3_MARK,
141	GPI4_MARK,
142	GPI5_MARK,
143	GPI6_MARK,
144	GPI7_MARK,
145	SCIFA7_RXD_MARK,
146	SCIFA7_CTS__MARK,
147	GPO7_MARK, MFG0_OUT2_MARK,
148	GPO6_MARK, MFG1_OUT2_MARK,
149	GPO5_MARK, SCIFA0_SCK_MARK, FSICOSLDT3_MARK, PORT16_VIO_CKOR_MARK,
150	SCIFA0_TXD_MARK,
151	SCIFA7_TXD_MARK,
152	SCIFA7_RTS__MARK, PORT19_VIO_CKO2_MARK,
153	GPO0_MARK,
154	GPO1_MARK,
155	GPO2_MARK, STATUS0_MARK,
156	GPO3_MARK, STATUS1_MARK,
157	GPO4_MARK, STATUS2_MARK,
158	VINT_MARK,
159	TCKON_MARK,
160	XDVFS1_MARK, PORT27_I2C_SCL2_MARK, PORT27_I2C_SCL3_MARK, \
161	MFG0_OUT1_MARK, PORT27_IROUT_MARK,
162	XDVFS2_MARK, PORT28_I2C_SDA2_MARK, PORT28_I2C_SDA3_MARK, \
163	PORT28_TPU1TO1_MARK,
164	SIM_RST_MARK, PORT29_TPU1TO1_MARK,
165	SIM_CLK_MARK, PORT30_VIO_CKOR_MARK,
166	SIM_D_MARK, PORT31_IROUT_MARK,
167	SCIFA4_TXD_MARK,
168	SCIFA4_RXD_MARK, XWUP_MARK,
169	SCIFA4_RTS__MARK,
170	SCIFA4_CTS__MARK,
171	FSIBOBT_MARK, FSIBIBT_MARK,
172	FSIBOLR_MARK, FSIBILR_MARK,
173	FSIBOSLD_MARK,
174	FSIBISLD_MARK,
175	VACK_MARK,
176	XTAL1L_MARK,
177	SCIFA0_RTS__MARK, FSICOSLDT2_MARK,
178	SCIFA0_RXD_MARK,
179	SCIFA0_CTS__MARK, FSICOSLDT1_MARK,
180	FSICOBT_MARK, FSICIBT_MARK, FSIDOBT_MARK, FSIDIBT_MARK,
181	FSICOLR_MARK, FSICILR_MARK, FSIDOLR_MARK, FSIDILR_MARK,
182	FSICOSLD_MARK, PORT47_FSICSPDIF_MARK,
183	FSICISLD_MARK, FSIDISLD_MARK,
184	FSIACK_MARK, PORT49_IRDA_OUT_MARK, PORT49_IROUT_MARK, FSIAOMC_MARK,
185	FSIAOLR_MARK, BBIF2_TSYNC2_MARK, TPU2TO2_MARK, FSIAILR_MARK,
186
187	FSIAOBT_MARK, BBIF2_TSCK2_MARK, TPU2TO3_MARK, FSIAIBT_MARK,
188	FSIAOSLD_MARK, BBIF2_TXD2_MARK,
189	FSIASPDIF_MARK, PORT53_IRDA_IN_MARK, TPU3TO3_MARK, FSIBSPDIF_MARK, \
190	PORT53_FSICSPDIF_MARK,
191	FSIBCK_MARK, PORT54_IRDA_FIRSEL_MARK, TPU3TO2_MARK, FSIBOMC_MARK, \
192	FSICCK_MARK, FSICOMC_MARK,
193	FSIAISLD_MARK, TPU0TO0_MARK,
194	A0_MARK, BS__MARK,
195	A12_MARK, PORT58_KEYOUT7_MARK, TPU4TO2_MARK,
196	A13_MARK, PORT59_KEYOUT6_MARK, TPU0TO1_MARK,
197	A14_MARK, KEYOUT5_MARK,
198	A15_MARK, KEYOUT4_MARK,
199	A16_MARK, KEYOUT3_MARK, MSIOF0_SS1_MARK,
200	A17_MARK, KEYOUT2_MARK, MSIOF0_TSYNC_MARK,
201	A18_MARK, KEYOUT1_MARK, MSIOF0_TSCK_MARK,
202	A19_MARK, KEYOUT0_MARK, MSIOF0_TXD_MARK,
203	A20_MARK, KEYIN0_MARK, MSIOF0_RSCK_MARK,
204	A21_MARK, KEYIN1_MARK, MSIOF0_RSYNC_MARK,
205	A22_MARK, KEYIN2_MARK, MSIOF0_MCK0_MARK,
206	A23_MARK, KEYIN3_MARK, MSIOF0_MCK1_MARK,
207	A24_MARK, KEYIN4_MARK, MSIOF0_RXD_MARK,
208	A25_MARK, KEYIN5_MARK, MSIOF0_SS2_MARK,
209	A26_MARK, KEYIN6_MARK,
210	KEYIN7_MARK,
211	D0_NAF0_MARK,
212	D1_NAF1_MARK,
213	D2_NAF2_MARK,
214	D3_NAF3_MARK,
215	D4_NAF4_MARK,
216	D5_NAF5_MARK,
217	D6_NAF6_MARK,
218	D7_NAF7_MARK,
219	D8_NAF8_MARK,
220	D9_NAF9_MARK,
221	D10_NAF10_MARK,
222	D11_NAF11_MARK,
223	D12_NAF12_MARK,
224	D13_NAF13_MARK,
225	D14_NAF14_MARK,
226	D15_NAF15_MARK,
227	CS4__MARK,
228	CS5A__MARK, PORT91_RDWR_MARK,
229	CS5B__MARK, FCE1__MARK,
230	CS6B__MARK, DACK0_MARK,
231	FCE0__MARK, CS6A__MARK,
232	WAIT__MARK, DREQ0_MARK,
233	RD__FSC_MARK,
234	WE0__FWE_MARK, RDWR_FWE_MARK,
235	WE1__MARK,
236	FRB_MARK,
237	CKO_MARK,
238	NBRSTOUT__MARK,
239	NBRST__MARK,
240	BBIF2_TXD_MARK,
241	BBIF2_RXD_MARK,
242	BBIF2_SYNC_MARK,
243	BBIF2_SCK_MARK,
244	SCIFA3_CTS__MARK, MFG3_IN2_MARK,
245	SCIFA3_RXD_MARK, MFG3_IN1_MARK,
246	BBIF1_SS2_MARK, SCIFA3_RTS__MARK, MFG3_OUT1_MARK,
247	SCIFA3_TXD_MARK,
248	HSI_RX_DATA_MARK, BBIF1_RXD_MARK,
249	HSI_TX_WAKE_MARK, BBIF1_TSCK_MARK,
250	HSI_TX_DATA_MARK, BBIF1_TSYNC_MARK,
251	HSI_TX_READY_MARK, BBIF1_TXD_MARK,
252	HSI_RX_READY_MARK, BBIF1_RSCK_MARK, PORT115_I2C_SCL2_MARK, \
253	PORT115_I2C_SCL3_MARK,
254	HSI_RX_WAKE_MARK, BBIF1_RSYNC_MARK, PORT116_I2C_SDA2_MARK, \
255	PORT116_I2C_SDA3_MARK,
256	HSI_RX_FLAG_MARK, BBIF1_SS1_MARK, BBIF1_FLOW_MARK,
257	HSI_TX_FLAG_MARK,
258	VIO_VD_MARK, PORT128_LCD2VSYN_MARK, VIO2_VD_MARK, LCD2D0_MARK,
259
260	VIO_HD_MARK, PORT129_LCD2HSYN_MARK, PORT129_LCD2CS__MARK, \
261	VIO2_HD_MARK, LCD2D1_MARK,
262	VIO_D0_MARK, PORT130_MSIOF2_RXD_MARK, LCD2D10_MARK,
263	VIO_D1_MARK, PORT131_KEYOUT6_MARK, PORT131_MSIOF2_SS1_MARK, \
264	PORT131_KEYOUT11_MARK, LCD2D11_MARK,
265	VIO_D2_MARK, PORT132_KEYOUT7_MARK, PORT132_MSIOF2_SS2_MARK, \
266	PORT132_KEYOUT10_MARK, LCD2D12_MARK,
267	VIO_D3_MARK, MSIOF2_TSYNC_MARK, LCD2D13_MARK,
268	VIO_D4_MARK, MSIOF2_TXD_MARK, LCD2D14_MARK,
269	VIO_D5_MARK, MSIOF2_TSCK_MARK, LCD2D15_MARK,
270	VIO_D6_MARK, PORT136_KEYOUT8_MARK, LCD2D16_MARK,
271	VIO_D7_MARK, PORT137_KEYOUT9_MARK, LCD2D17_MARK,
272	VIO_D8_MARK, PORT138_KEYOUT8_MARK, VIO2_D0_MARK, LCD2D6_MARK,
273	VIO_D9_MARK, PORT139_KEYOUT9_MARK, VIO2_D1_MARK, LCD2D7_MARK,
274	VIO_D10_MARK, TPU0TO2_MARK, VIO2_D2_MARK, LCD2D8_MARK,
275	VIO_D11_MARK, TPU0TO3_MARK, VIO2_D3_MARK, LCD2D9_MARK,
276	VIO_D12_MARK, PORT142_KEYOUT10_MARK, VIO2_D4_MARK, LCD2D2_MARK,
277	VIO_D13_MARK, PORT143_KEYOUT11_MARK, PORT143_KEYOUT6_MARK, \
278	VIO2_D5_MARK, LCD2D3_MARK,
279	VIO_D14_MARK, PORT144_KEYOUT7_MARK, VIO2_D6_MARK, LCD2D4_MARK,
280	VIO_D15_MARK, TPU1TO3_MARK, PORT145_LCD2DISP_MARK, \
281	PORT145_LCD2RS_MARK, VIO2_D7_MARK, LCD2D5_MARK,
282	VIO_CLK_MARK, LCD2DCK_MARK, PORT146_LCD2WR__MARK, VIO2_CLK_MARK, \
283	LCD2D18_MARK,
284	VIO_FIELD_MARK, LCD2RD__MARK, VIO2_FIELD_MARK, LCD2D19_MARK,
285	VIO_CKO_MARK,
286	A27_MARK, PORT149_RDWR_MARK, MFG0_IN1_MARK, PORT149_KEYOUT9_MARK,
287	MFG0_IN2_MARK,
288	TS_SPSYNC3_MARK, MSIOF2_RSCK_MARK,
289	TS_SDAT3_MARK, MSIOF2_RSYNC_MARK,
290	TPU1TO2_MARK, TS_SDEN3_MARK, PORT153_MSIOF2_SS1_MARK,
291	SCIFA2_TXD1_MARK, MSIOF2_MCK0_MARK,
292	SCIFA2_RXD1_MARK, MSIOF2_MCK1_MARK,
293	SCIFA2_RTS1__MARK, PORT156_MSIOF2_SS2_MARK,
294	SCIFA2_CTS1__MARK, PORT157_MSIOF2_RXD_MARK,
295	DINT__MARK, SCIFA2_SCK1_MARK, TS_SCK3_MARK,
296	PORT159_SCIFB_SCK_MARK, PORT159_SCIFA5_SCK_MARK, NMI_MARK,
297	PORT160_SCIFB_TXD_MARK, PORT160_SCIFA5_TXD_MARK,
298	PORT161_SCIFB_CTS__MARK, PORT161_SCIFA5_CTS__MARK,
299	PORT162_SCIFB_RXD_MARK, PORT162_SCIFA5_RXD_MARK,
300	PORT163_SCIFB_RTS__MARK, PORT163_SCIFA5_RTS__MARK, TPU3TO0_MARK,
301	LCDD0_MARK,
302	LCDD1_MARK, PORT193_SCIFA5_CTS__MARK, BBIF2_TSYNC1_MARK,
303	LCDD2_MARK, PORT194_SCIFA5_RTS__MARK, BBIF2_TSCK1_MARK,
304	LCDD3_MARK, PORT195_SCIFA5_RXD_MARK, BBIF2_TXD1_MARK,
305	LCDD4_MARK, PORT196_SCIFA5_TXD_MARK,
306	LCDD5_MARK, PORT197_SCIFA5_SCK_MARK, MFG2_OUT2_MARK, TPU2TO1_MARK,
307	LCDD6_MARK,
308	LCDD7_MARK, TPU4TO1_MARK, MFG4_OUT2_MARK,
309	LCDD8_MARK, D16_MARK,
310	LCDD9_MARK, D17_MARK,
311	LCDD10_MARK, D18_MARK,
312	LCDD11_MARK, D19_MARK,
313	LCDD12_MARK, D20_MARK,
314	LCDD13_MARK, D21_MARK,
315	LCDD14_MARK, D22_MARK,
316	LCDD15_MARK, PORT207_MSIOF0L_SS1_MARK, D23_MARK,
317	LCDD16_MARK, PORT208_MSIOF0L_SS2_MARK, D24_MARK,
318	LCDD17_MARK, D25_MARK,
319	LCDD18_MARK, DREQ2_MARK, PORT210_MSIOF0L_SS1_MARK, D26_MARK,
320	LCDD19_MARK, PORT211_MSIOF0L_SS2_MARK, D27_MARK,
321	LCDD20_MARK, TS_SPSYNC1_MARK, MSIOF0L_MCK0_MARK, D28_MARK,
322	LCDD21_MARK, TS_SDAT1_MARK, MSIOF0L_MCK1_MARK, D29_MARK,
323	LCDD22_MARK, TS_SDEN1_MARK, MSIOF0L_RSCK_MARK, D30_MARK,
324	LCDD23_MARK, TS_SCK1_MARK, MSIOF0L_RSYNC_MARK, D31_MARK,
325	LCDDCK_MARK, LCDWR__MARK,
326	LCDRD__MARK, DACK2_MARK, PORT217_LCD2RS_MARK, MSIOF0L_TSYNC_MARK, \
327	VIO2_FIELD3_MARK, PORT217_LCD2DISP_MARK,
328	LCDHSYN_MARK, LCDCS__MARK, LCDCS2__MARK, DACK3_MARK, \
329	PORT218_VIO_CKOR_MARK,
330	LCDDISP_MARK, LCDRS_MARK, PORT219_LCD2WR__MARK, DREQ3_MARK, \
331	MSIOF0L_TSCK_MARK, VIO2_CLK3_MARK, LCD2DCK_2_MARK,
332	LCDVSYN_MARK, LCDVSYN2_MARK,
333	LCDLCLK_MARK, DREQ1_MARK, PORT221_LCD2CS__MARK, PWEN_MARK, \
334	MSIOF0L_RXD_MARK, VIO2_HD3_MARK, PORT221_LCD2HSYN_MARK,
335	LCDDON_MARK, LCDDON2_MARK, DACK1_MARK, OVCN_MARK, MSIOF0L_TXD_MARK, \
336	VIO2_VD3_MARK, PORT222_LCD2VSYN_MARK,
337
338	SCIFA1_TXD_MARK, OVCN2_MARK,
339	EXTLP_MARK, SCIFA1_SCK_MARK, PORT226_VIO_CKO2_MARK,
340	SCIFA1_RTS__MARK, IDIN_MARK,
341	SCIFA1_RXD_MARK,
342	SCIFA1_CTS__MARK, MFG1_IN1_MARK,
343	MSIOF1_TXD_MARK, SCIFA2_TXD2_MARK,
344	MSIOF1_TSYNC_MARK, SCIFA2_CTS2__MARK,
345	MSIOF1_TSCK_MARK, SCIFA2_SCK2_MARK,
346	MSIOF1_RXD_MARK, SCIFA2_RXD2_MARK,
347	MSIOF1_RSCK_MARK, SCIFA2_RTS2__MARK, VIO2_CLK2_MARK, LCD2D20_MARK,
348	MSIOF1_RSYNC_MARK, MFG1_IN2_MARK, VIO2_VD2_MARK, LCD2D21_MARK,
349	MSIOF1_MCK0_MARK, PORT236_I2C_SDA2_MARK,
350	MSIOF1_MCK1_MARK, PORT237_I2C_SCL2_MARK,
351	MSIOF1_SS1_MARK, VIO2_FIELD2_MARK, LCD2D22_MARK,
352	MSIOF1_SS2_MARK, VIO2_HD2_MARK, LCD2D23_MARK,
353	SCIFA6_TXD_MARK,
354	PORT241_IRDA_OUT_MARK, PORT241_IROUT_MARK, MFG4_OUT1_MARK, TPU4TO0_MARK,
355	PORT242_IRDA_IN_MARK, MFG4_IN2_MARK,
356	PORT243_IRDA_FIRSEL_MARK, PORT243_VIO_CKO2_MARK,
357	PORT244_SCIFA5_CTS__MARK, MFG2_IN1_MARK, PORT244_SCIFB_CTS__MARK, \
358	MSIOF2R_RXD_MARK,
359	PORT245_SCIFA5_RTS__MARK, MFG2_IN2_MARK, PORT245_SCIFB_RTS__MARK, \
360	MSIOF2R_TXD_MARK,
361	PORT246_SCIFA5_RXD_MARK, MFG1_OUT1_MARK, PORT246_SCIFB_RXD_MARK, \
362	TPU1TO0_MARK,
363	PORT247_SCIFA5_TXD_MARK, MFG3_OUT2_MARK, PORT247_SCIFB_TXD_MARK, \
364	TPU3TO1_MARK,
365	PORT248_SCIFA5_SCK_MARK, MFG2_OUT1_MARK, PORT248_SCIFB_SCK_MARK, \
366	TPU2TO0_MARK, PORT248_I2C_SCL3_MARK, MSIOF2R_TSCK_MARK,
367	PORT249_IROUT_MARK, MFG4_IN1_MARK, PORT249_I2C_SDA3_MARK, \
368	MSIOF2R_TSYNC_MARK,
369	SDHICLK0_MARK,
370	SDHICD0_MARK,
371	SDHID0_0_MARK,
372	SDHID0_1_MARK,
373	SDHID0_2_MARK,
374	SDHID0_3_MARK,
375	SDHICMD0_MARK,
376	SDHIWP0_MARK,
377	SDHICLK1_MARK,
378	SDHID1_0_MARK, TS_SPSYNC2_MARK,
379	SDHID1_1_MARK, TS_SDAT2_MARK,
380	SDHID1_2_MARK, TS_SDEN2_MARK,
381	SDHID1_3_MARK, TS_SCK2_MARK,
382	SDHICMD1_MARK,
383	SDHICLK2_MARK,
384	SDHID2_0_MARK, TS_SPSYNC4_MARK,
385	SDHID2_1_MARK, TS_SDAT4_MARK,
386	SDHID2_2_MARK, TS_SDEN4_MARK,
387	SDHID2_3_MARK, TS_SCK4_MARK,
388	SDHICMD2_MARK,
389	MMCCLK0_MARK,
390	MMCD0_0_MARK,
391	MMCD0_1_MARK,
392	MMCD0_2_MARK,
393	MMCD0_3_MARK,
394	MMCD0_4_MARK, TS_SPSYNC5_MARK,
395	MMCD0_5_MARK, TS_SDAT5_MARK,
396	MMCD0_6_MARK, TS_SDEN5_MARK,
397	MMCD0_7_MARK, TS_SCK5_MARK,
398	MMCCMD0_MARK,
399	RESETOUTS__MARK, EXTAL2OUT_MARK,
400	MCP_WAIT__MCP_FRB_MARK,
401	MCP_CKO_MARK, MMCCLK1_MARK,
402	MCP_D15_MCP_NAF15_MARK,
403	MCP_D14_MCP_NAF14_MARK,
404	MCP_D13_MCP_NAF13_MARK,
405	MCP_D12_MCP_NAF12_MARK,
406	MCP_D11_MCP_NAF11_MARK,
407	MCP_D10_MCP_NAF10_MARK,
408	MCP_D9_MCP_NAF9_MARK,
409	MCP_D8_MCP_NAF8_MARK, MMCCMD1_MARK,
410	MCP_D7_MCP_NAF7_MARK, MMCD1_7_MARK,
411
412	MCP_D6_MCP_NAF6_MARK, MMCD1_6_MARK,
413	MCP_D5_MCP_NAF5_MARK, MMCD1_5_MARK,
414	MCP_D4_MCP_NAF4_MARK, MMCD1_4_MARK,
415	MCP_D3_MCP_NAF3_MARK, MMCD1_3_MARK,
416	MCP_D2_MCP_NAF2_MARK, MMCD1_2_MARK,
417	MCP_D1_MCP_NAF1_MARK, MMCD1_1_MARK,
418	MCP_D0_MCP_NAF0_MARK, MMCD1_0_MARK,
419	MCP_NBRSTOUT__MARK,
420	MCP_WE0__MCP_FWE_MARK, MCP_RDWR_MCP_FWE_MARK,
421
422	/* MSEL2 special cases */
423	TSIF2_TS_XX1_MARK,
424	TSIF2_TS_XX2_MARK,
425	TSIF2_TS_XX3_MARK,
426	TSIF2_TS_XX4_MARK,
427	TSIF2_TS_XX5_MARK,
428	TSIF1_TS_XX1_MARK,
429	TSIF1_TS_XX2_MARK,
430	TSIF1_TS_XX3_MARK,
431	TSIF1_TS_XX4_MARK,
432	TSIF1_TS_XX5_MARK,
433	TSIF0_TS_XX1_MARK,
434	TSIF0_TS_XX2_MARK,
435	TSIF0_TS_XX3_MARK,
436	TSIF0_TS_XX4_MARK,
437	TSIF0_TS_XX5_MARK,
438	MST1_TS_XX1_MARK,
439	MST1_TS_XX2_MARK,
440	MST1_TS_XX3_MARK,
441	MST1_TS_XX4_MARK,
442	MST1_TS_XX5_MARK,
443	MST0_TS_XX1_MARK,
444	MST0_TS_XX2_MARK,
445	MST0_TS_XX3_MARK,
446	MST0_TS_XX4_MARK,
447	MST0_TS_XX5_MARK,
448
449	/* MSEL3 special cases */
450	SDHI0_VCCQ_MC0_ON_MARK,
451	SDHI0_VCCQ_MC0_OFF_MARK,
452	DEBUG_MON_VIO_MARK,
453	DEBUG_MON_LCDD_MARK,
454	LCDC_LCDC0_MARK,
455	LCDC_LCDC1_MARK,
456
457	/* MSEL4 special cases */
458	IRQ9_MEM_INT_MARK,
459	IRQ9_MCP_INT_MARK,
460	A11_MARK,
461	KEYOUT8_MARK,
462	TPU4TO3_MARK,
463	RESETA_N_PU_ON_MARK,
464	RESETA_N_PU_OFF_MARK,
465	EDBGREQ_PD_MARK,
466	EDBGREQ_PU_MARK,
467
468	PINMUX_MARK_END,
469};
470
471static const u16 pinmux_data[] = {
472	/* specify valid pin states for each pin in GPIO mode */
473	PINMUX_DATA_ALL(),
474
475	/* Table 25-1 (Function 0-7) */
476	PINMUX_DATA(VBUS_0_MARK, PORT0_FN1),
477	PINMUX_DATA(GPI0_MARK, PORT1_FN1),
478	PINMUX_DATA(GPI1_MARK, PORT2_FN1),
479	PINMUX_DATA(GPI2_MARK, PORT3_FN1),
480	PINMUX_DATA(GPI3_MARK, PORT4_FN1),
481	PINMUX_DATA(GPI4_MARK, PORT5_FN1),
482	PINMUX_DATA(GPI5_MARK, PORT6_FN1),
483	PINMUX_DATA(GPI6_MARK, PORT7_FN1),
484	PINMUX_DATA(GPI7_MARK, PORT8_FN1),
485	PINMUX_DATA(SCIFA7_RXD_MARK, PORT12_FN2),
486	PINMUX_DATA(SCIFA7_CTS__MARK, PORT13_FN2),
487	PINMUX_DATA(GPO7_MARK, PORT14_FN1), \
488	PINMUX_DATA(MFG0_OUT2_MARK, PORT14_FN4),
489	PINMUX_DATA(GPO6_MARK, PORT15_FN1), \
490	PINMUX_DATA(MFG1_OUT2_MARK, PORT15_FN4),
491	PINMUX_DATA(GPO5_MARK, PORT16_FN1), \
492	PINMUX_DATA(SCIFA0_SCK_MARK, PORT16_FN2), \
493	PINMUX_DATA(FSICOSLDT3_MARK, PORT16_FN3), \
494	PINMUX_DATA(PORT16_VIO_CKOR_MARK, PORT16_FN4),
495	PINMUX_DATA(SCIFA0_TXD_MARK, PORT17_FN2),
496	PINMUX_DATA(SCIFA7_TXD_MARK, PORT18_FN2),
497	PINMUX_DATA(SCIFA7_RTS__MARK, PORT19_FN2), \
498	PINMUX_DATA(PORT19_VIO_CKO2_MARK, PORT19_FN3),
499	PINMUX_DATA(GPO0_MARK, PORT20_FN1),
500	PINMUX_DATA(GPO1_MARK, PORT21_FN1),
501	PINMUX_DATA(GPO2_MARK, PORT22_FN1), \
502	PINMUX_DATA(STATUS0_MARK, PORT22_FN2),
503	PINMUX_DATA(GPO3_MARK, PORT23_FN1), \
504	PINMUX_DATA(STATUS1_MARK, PORT23_FN2),
505	PINMUX_DATA(GPO4_MARK, PORT24_FN1), \
506	PINMUX_DATA(STATUS2_MARK, PORT24_FN2),
507	PINMUX_DATA(VINT_MARK, PORT25_FN1),
508	PINMUX_DATA(TCKON_MARK, PORT26_FN1),
509	PINMUX_DATA(XDVFS1_MARK, PORT27_FN1), \
510	PINMUX_DATA(PORT27_I2C_SCL2_MARK, PORT27_FN2, MSEL2CR_MSEL17_0,
511		MSEL2CR_MSEL16_1), \
512	PINMUX_DATA(PORT27_I2C_SCL3_MARK, PORT27_FN3, MSEL2CR_MSEL19_0,
513		MSEL2CR_MSEL18_1), \
514	PINMUX_DATA(MFG0_OUT1_MARK, PORT27_FN4), \
515	PINMUX_DATA(PORT27_IROUT_MARK, PORT27_FN7),
516	PINMUX_DATA(XDVFS2_MARK, PORT28_FN1), \
517	PINMUX_DATA(PORT28_I2C_SDA2_MARK, PORT28_FN2, MSEL2CR_MSEL17_0,
518		MSEL2CR_MSEL16_1), \
519	PINMUX_DATA(PORT28_I2C_SDA3_MARK, PORT28_FN3, MSEL2CR_MSEL19_0,
520		MSEL2CR_MSEL18_1), \
521	PINMUX_DATA(PORT28_TPU1TO1_MARK, PORT28_FN7),
522	PINMUX_DATA(SIM_RST_MARK, PORT29_FN1), \
523	PINMUX_DATA(PORT29_TPU1TO1_MARK, PORT29_FN4),
524	PINMUX_DATA(SIM_CLK_MARK, PORT30_FN1), \
525	PINMUX_DATA(PORT30_VIO_CKOR_MARK, PORT30_FN4),
526	PINMUX_DATA(SIM_D_MARK, PORT31_FN1), \
527	PINMUX_DATA(PORT31_IROUT_MARK, PORT31_FN4),
528	PINMUX_DATA(SCIFA4_TXD_MARK, PORT32_FN2),
529	PINMUX_DATA(SCIFA4_RXD_MARK, PORT33_FN2), \
530	PINMUX_DATA(XWUP_MARK, PORT33_FN3),
531	PINMUX_DATA(SCIFA4_RTS__MARK, PORT34_FN2),
532	PINMUX_DATA(SCIFA4_CTS__MARK, PORT35_FN2),
533	PINMUX_DATA(FSIBOBT_MARK, PORT36_FN1), \
534	PINMUX_DATA(FSIBIBT_MARK, PORT36_FN2),
535	PINMUX_DATA(FSIBOLR_MARK, PORT37_FN1), \
536	PINMUX_DATA(FSIBILR_MARK, PORT37_FN2),
537	PINMUX_DATA(FSIBOSLD_MARK, PORT38_FN1),
538	PINMUX_DATA(FSIBISLD_MARK, PORT39_FN1),
539	PINMUX_DATA(VACK_MARK, PORT40_FN1),
540	PINMUX_DATA(XTAL1L_MARK, PORT41_FN1),
541	PINMUX_DATA(SCIFA0_RTS__MARK, PORT42_FN2), \
542	PINMUX_DATA(FSICOSLDT2_MARK, PORT42_FN3),
543	PINMUX_DATA(SCIFA0_RXD_MARK, PORT43_FN2),
544	PINMUX_DATA(SCIFA0_CTS__MARK, PORT44_FN2), \
545	PINMUX_DATA(FSICOSLDT1_MARK, PORT44_FN3),
546	PINMUX_DATA(FSICOBT_MARK, PORT45_FN1), \
547	PINMUX_DATA(FSICIBT_MARK, PORT45_FN2), \
548	PINMUX_DATA(FSIDOBT_MARK, PORT45_FN3), \
549	PINMUX_DATA(FSIDIBT_MARK, PORT45_FN4),
550	PINMUX_DATA(FSICOLR_MARK, PORT46_FN1), \
551	PINMUX_DATA(FSICILR_MARK, PORT46_FN2), \
552	PINMUX_DATA(FSIDOLR_MARK, PORT46_FN3), \
553	PINMUX_DATA(FSIDILR_MARK, PORT46_FN4),
554	PINMUX_DATA(FSICOSLD_MARK, PORT47_FN1), \
555	PINMUX_DATA(PORT47_FSICSPDIF_MARK, PORT47_FN2),
556	PINMUX_DATA(FSICISLD_MARK, PORT48_FN1), \
557	PINMUX_DATA(FSIDISLD_MARK, PORT48_FN3),
558	PINMUX_DATA(FSIACK_MARK, PORT49_FN1), \
559	PINMUX_DATA(PORT49_IRDA_OUT_MARK, PORT49_FN2, MSEL4CR_MSEL19_1), \
560	PINMUX_DATA(PORT49_IROUT_MARK, PORT49_FN4), \
561	PINMUX_DATA(FSIAOMC_MARK, PORT49_FN5),
562	PINMUX_DATA(FSIAOLR_MARK, PORT50_FN1), \
563	PINMUX_DATA(BBIF2_TSYNC2_MARK, PORT50_FN2), \
564	PINMUX_DATA(TPU2TO2_MARK, PORT50_FN3), \
565	PINMUX_DATA(FSIAILR_MARK, PORT50_FN5),
566
567	PINMUX_DATA(FSIAOBT_MARK, PORT51_FN1), \
568	PINMUX_DATA(BBIF2_TSCK2_MARK, PORT51_FN2), \
569	PINMUX_DATA(TPU2TO3_MARK, PORT51_FN3), \
570	PINMUX_DATA(FSIAIBT_MARK, PORT51_FN5),
571	PINMUX_DATA(FSIAOSLD_MARK, PORT52_FN1), \
572	PINMUX_DATA(BBIF2_TXD2_MARK, PORT52_FN2),
573	PINMUX_DATA(FSIASPDIF_MARK, PORT53_FN1), \
574	PINMUX_DATA(PORT53_IRDA_IN_MARK, PORT53_FN2, MSEL4CR_MSEL19_1), \
575	PINMUX_DATA(TPU3TO3_MARK, PORT53_FN3), \
576	PINMUX_DATA(FSIBSPDIF_MARK, PORT53_FN5), \
577	PINMUX_DATA(PORT53_FSICSPDIF_MARK, PORT53_FN6),
578	PINMUX_DATA(FSIBCK_MARK, PORT54_FN1), \
579	PINMUX_DATA(PORT54_IRDA_FIRSEL_MARK, PORT54_FN2, MSEL4CR_MSEL19_1), \
580	PINMUX_DATA(TPU3TO2_MARK, PORT54_FN3), \
581	PINMUX_DATA(FSIBOMC_MARK, PORT54_FN5), \
582	PINMUX_DATA(FSICCK_MARK, PORT54_FN6), \
583	PINMUX_DATA(FSICOMC_MARK, PORT54_FN7),
584	PINMUX_DATA(FSIAISLD_MARK, PORT55_FN1), \
585	PINMUX_DATA(TPU0TO0_MARK, PORT55_FN3),
586	PINMUX_DATA(A0_MARK, PORT57_FN1), \
587	PINMUX_DATA(BS__MARK, PORT57_FN2),
588	PINMUX_DATA(A12_MARK, PORT58_FN1), \
589	PINMUX_DATA(PORT58_KEYOUT7_MARK, PORT58_FN2), \
590	PINMUX_DATA(TPU4TO2_MARK, PORT58_FN4),
591	PINMUX_DATA(A13_MARK, PORT59_FN1), \
592	PINMUX_DATA(PORT59_KEYOUT6_MARK, PORT59_FN2), \
593	PINMUX_DATA(TPU0TO1_MARK, PORT59_FN4),
594	PINMUX_DATA(A14_MARK, PORT60_FN1), \
595	PINMUX_DATA(KEYOUT5_MARK, PORT60_FN2),
596	PINMUX_DATA(A15_MARK, PORT61_FN1), \
597	PINMUX_DATA(KEYOUT4_MARK, PORT61_FN2),
598	PINMUX_DATA(A16_MARK, PORT62_FN1), \
599	PINMUX_DATA(KEYOUT3_MARK, PORT62_FN2), \
600	PINMUX_DATA(MSIOF0_SS1_MARK, PORT62_FN4, MSEL3CR_MSEL11_0),
601	PINMUX_DATA(A17_MARK, PORT63_FN1), \
602	PINMUX_DATA(KEYOUT2_MARK, PORT63_FN2), \
603	PINMUX_DATA(MSIOF0_TSYNC_MARK, PORT63_FN4, MSEL3CR_MSEL11_0),
604	PINMUX_DATA(A18_MARK, PORT64_FN1), \
605	PINMUX_DATA(KEYOUT1_MARK, PORT64_FN2), \
606	PINMUX_DATA(MSIOF0_TSCK_MARK, PORT64_FN4, MSEL3CR_MSEL11_0),
607	PINMUX_DATA(A19_MARK, PORT65_FN1), \
608	PINMUX_DATA(KEYOUT0_MARK, PORT65_FN2), \
609	PINMUX_DATA(MSIOF0_TXD_MARK, PORT65_FN4, MSEL3CR_MSEL11_0),
610	PINMUX_DATA(A20_MARK, PORT66_FN1), \
611	PINMUX_DATA(KEYIN0_MARK, PORT66_FN2), \
612	PINMUX_DATA(MSIOF0_RSCK_MARK, PORT66_FN4, MSEL3CR_MSEL11_0),
613	PINMUX_DATA(A21_MARK, PORT67_FN1), \
614	PINMUX_DATA(KEYIN1_MARK, PORT67_FN2), \
615	PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT67_FN4, MSEL3CR_MSEL11_0),
616	PINMUX_DATA(A22_MARK, PORT68_FN1), \
617	PINMUX_DATA(KEYIN2_MARK, PORT68_FN2), \
618	PINMUX_DATA(MSIOF0_MCK0_MARK, PORT68_FN4, MSEL3CR_MSEL11_0),
619	PINMUX_DATA(A23_MARK, PORT69_FN1), \
620	PINMUX_DATA(KEYIN3_MARK, PORT69_FN2), \
621	PINMUX_DATA(MSIOF0_MCK1_MARK, PORT69_FN4, MSEL3CR_MSEL11_0),
622	PINMUX_DATA(A24_MARK, PORT70_FN1), \
623	PINMUX_DATA(KEYIN4_MARK, PORT70_FN2), \
624	PINMUX_DATA(MSIOF0_RXD_MARK, PORT70_FN4, MSEL3CR_MSEL11_0),
625	PINMUX_DATA(A25_MARK, PORT71_FN1), \
626	PINMUX_DATA(KEYIN5_MARK, PORT71_FN2), \
627	PINMUX_DATA(MSIOF0_SS2_MARK, PORT71_FN4, MSEL3CR_MSEL11_0),
628	PINMUX_DATA(A26_MARK, PORT72_FN1), \
629	PINMUX_DATA(KEYIN6_MARK, PORT72_FN2),
630	PINMUX_DATA(KEYIN7_MARK, PORT73_FN2),
631	PINMUX_DATA(D0_NAF0_MARK, PORT74_FN1),
632	PINMUX_DATA(D1_NAF1_MARK, PORT75_FN1),
633	PINMUX_DATA(D2_NAF2_MARK, PORT76_FN1),
634	PINMUX_DATA(D3_NAF3_MARK, PORT77_FN1),
635	PINMUX_DATA(D4_NAF4_MARK, PORT78_FN1),
636	PINMUX_DATA(D5_NAF5_MARK, PORT79_FN1),
637	PINMUX_DATA(D6_NAF6_MARK, PORT80_FN1),
638	PINMUX_DATA(D7_NAF7_MARK, PORT81_FN1),
639	PINMUX_DATA(D8_NAF8_MARK, PORT82_FN1),
640	PINMUX_DATA(D9_NAF9_MARK, PORT83_FN1),
641	PINMUX_DATA(D10_NAF10_MARK, PORT84_FN1),
642	PINMUX_DATA(D11_NAF11_MARK, PORT85_FN1),
643	PINMUX_DATA(D12_NAF12_MARK, PORT86_FN1),
644	PINMUX_DATA(D13_NAF13_MARK, PORT87_FN1),
645	PINMUX_DATA(D14_NAF14_MARK, PORT88_FN1),
646	PINMUX_DATA(D15_NAF15_MARK, PORT89_FN1),
647	PINMUX_DATA(CS4__MARK, PORT90_FN1),
648	PINMUX_DATA(CS5A__MARK, PORT91_FN1), \
649	PINMUX_DATA(PORT91_RDWR_MARK, PORT91_FN2),
650	PINMUX_DATA(CS5B__MARK, PORT92_FN1), \
651	PINMUX_DATA(FCE1__MARK, PORT92_FN2),
652	PINMUX_DATA(CS6B__MARK, PORT93_FN1), \
653	PINMUX_DATA(DACK0_MARK, PORT93_FN4),
654	PINMUX_DATA(FCE0__MARK, PORT94_FN1), \
655	PINMUX_DATA(CS6A__MARK, PORT94_FN2),
656	PINMUX_DATA(WAIT__MARK, PORT95_FN1), \
657	PINMUX_DATA(DREQ0_MARK, PORT95_FN2),
658	PINMUX_DATA(RD__FSC_MARK, PORT96_FN1),
659	PINMUX_DATA(WE0__FWE_MARK, PORT97_FN1), \
660	PINMUX_DATA(RDWR_FWE_MARK, PORT97_FN2),
661	PINMUX_DATA(WE1__MARK, PORT98_FN1),
662	PINMUX_DATA(FRB_MARK, PORT99_FN1),
663	PINMUX_DATA(CKO_MARK, PORT100_FN1),
664	PINMUX_DATA(NBRSTOUT__MARK, PORT101_FN1),
665	PINMUX_DATA(NBRST__MARK, PORT102_FN1),
666	PINMUX_DATA(BBIF2_TXD_MARK, PORT103_FN3),
667	PINMUX_DATA(BBIF2_RXD_MARK, PORT104_FN3),
668	PINMUX_DATA(BBIF2_SYNC_MARK, PORT105_FN3),
669	PINMUX_DATA(BBIF2_SCK_MARK, PORT106_FN3),
670	PINMUX_DATA(SCIFA3_CTS__MARK, PORT107_FN3), \
671	PINMUX_DATA(MFG3_IN2_MARK, PORT107_FN4),
672	PINMUX_DATA(SCIFA3_RXD_MARK, PORT108_FN3), \
673	PINMUX_DATA(MFG3_IN1_MARK, PORT108_FN4),
674	PINMUX_DATA(BBIF1_SS2_MARK, PORT109_FN2), \
675	PINMUX_DATA(SCIFA3_RTS__MARK, PORT109_FN3), \
676	PINMUX_DATA(MFG3_OUT1_MARK, PORT109_FN4),
677	PINMUX_DATA(SCIFA3_TXD_MARK, PORT110_FN3),
678	PINMUX_DATA(HSI_RX_DATA_MARK, PORT111_FN1), \
679	PINMUX_DATA(BBIF1_RXD_MARK, PORT111_FN3),
680	PINMUX_DATA(HSI_TX_WAKE_MARK, PORT112_FN1), \
681	PINMUX_DATA(BBIF1_TSCK_MARK, PORT112_FN3),
682	PINMUX_DATA(HSI_TX_DATA_MARK, PORT113_FN1), \
683	PINMUX_DATA(BBIF1_TSYNC_MARK, PORT113_FN3),
684	PINMUX_DATA(HSI_TX_READY_MARK, PORT114_FN1), \
685	PINMUX_DATA(BBIF1_TXD_MARK, PORT114_FN3),
686	PINMUX_DATA(HSI_RX_READY_MARK, PORT115_FN1), \
687	PINMUX_DATA(BBIF1_RSCK_MARK, PORT115_FN3), \
688	PINMUX_DATA(PORT115_I2C_SCL2_MARK, PORT115_FN5, MSEL2CR_MSEL17_1), \
689	PINMUX_DATA(PORT115_I2C_SCL3_MARK, PORT115_FN6, MSEL2CR_MSEL19_1),
690	PINMUX_DATA(HSI_RX_WAKE_MARK, PORT116_FN1), \
691	PINMUX_DATA(BBIF1_RSYNC_MARK, PORT116_FN3), \
692	PINMUX_DATA(PORT116_I2C_SDA2_MARK, PORT116_FN5, MSEL2CR_MSEL17_1), \
693	PINMUX_DATA(PORT116_I2C_SDA3_MARK, PORT116_FN6, MSEL2CR_MSEL19_1),
694	PINMUX_DATA(HSI_RX_FLAG_MARK, PORT117_FN1), \
695	PINMUX_DATA(BBIF1_SS1_MARK, PORT117_FN2), \
696	PINMUX_DATA(BBIF1_FLOW_MARK, PORT117_FN3),
697	PINMUX_DATA(HSI_TX_FLAG_MARK, PORT118_FN1),
698	PINMUX_DATA(VIO_VD_MARK, PORT128_FN1), \
699	PINMUX_DATA(PORT128_LCD2VSYN_MARK, PORT128_FN4, MSEL3CR_MSEL2_0), \
700	PINMUX_DATA(VIO2_VD_MARK, PORT128_FN6, MSEL4CR_MSEL27_0), \
701	PINMUX_DATA(LCD2D0_MARK, PORT128_FN7),
702
703	PINMUX_DATA(VIO_HD_MARK, PORT129_FN1), \
704	PINMUX_DATA(PORT129_LCD2HSYN_MARK, PORT129_FN4), \
705	PINMUX_DATA(PORT129_LCD2CS__MARK, PORT129_FN5), \
706	PINMUX_DATA(VIO2_HD_MARK, PORT129_FN6, MSEL4CR_MSEL27_0), \
707	PINMUX_DATA(LCD2D1_MARK, PORT129_FN7),
708	PINMUX_DATA(VIO_D0_MARK, PORT130_FN1), \
709	PINMUX_DATA(PORT130_MSIOF2_RXD_MARK, PORT130_FN3, MSEL4CR_MSEL11_0,
710		MSEL4CR_MSEL10_1), \
711	PINMUX_DATA(LCD2D10_MARK, PORT130_FN7),
712	PINMUX_DATA(VIO_D1_MARK, PORT131_FN1), \
713	PINMUX_DATA(PORT131_KEYOUT6_MARK, PORT131_FN2), \
714	PINMUX_DATA(PORT131_MSIOF2_SS1_MARK, PORT131_FN3), \
715	PINMUX_DATA(PORT131_KEYOUT11_MARK, PORT131_FN4), \
716	PINMUX_DATA(LCD2D11_MARK, PORT131_FN7),
717	PINMUX_DATA(VIO_D2_MARK, PORT132_FN1), \
718	PINMUX_DATA(PORT132_KEYOUT7_MARK, PORT132_FN2), \
719	PINMUX_DATA(PORT132_MSIOF2_SS2_MARK, PORT132_FN3), \
720	PINMUX_DATA(PORT132_KEYOUT10_MARK, PORT132_FN4), \
721	PINMUX_DATA(LCD2D12_MARK, PORT132_FN7),
722	PINMUX_DATA(VIO_D3_MARK, PORT133_FN1), \
723	PINMUX_DATA(MSIOF2_TSYNC_MARK, PORT133_FN3, MSEL4CR_MSEL11_0), \
724	PINMUX_DATA(LCD2D13_MARK, PORT133_FN7),
725	PINMUX_DATA(VIO_D4_MARK, PORT134_FN1), \
726	PINMUX_DATA(MSIOF2_TXD_MARK, PORT134_FN3, MSEL4CR_MSEL11_0), \
727	PINMUX_DATA(LCD2D14_MARK, PORT134_FN7),
728	PINMUX_DATA(VIO_D5_MARK, PORT135_FN1), \
729	PINMUX_DATA(MSIOF2_TSCK_MARK, PORT135_FN3, MSEL4CR_MSEL11_0), \
730	PINMUX_DATA(LCD2D15_MARK, PORT135_FN7),
731	PINMUX_DATA(VIO_D6_MARK, PORT136_FN1), \
732	PINMUX_DATA(PORT136_KEYOUT8_MARK, PORT136_FN2), \
733	PINMUX_DATA(LCD2D16_MARK, PORT136_FN7),
734	PINMUX_DATA(VIO_D7_MARK, PORT137_FN1), \
735	PINMUX_DATA(PORT137_KEYOUT9_MARK, PORT137_FN2), \
736	PINMUX_DATA(LCD2D17_MARK, PORT137_FN7),
737	PINMUX_DATA(VIO_D8_MARK, PORT138_FN1), \
738	PINMUX_DATA(PORT138_KEYOUT8_MARK, PORT138_FN2), \
739	PINMUX_DATA(VIO2_D0_MARK, PORT138_FN6), \
740	PINMUX_DATA(LCD2D6_MARK, PORT138_FN7),
741	PINMUX_DATA(VIO_D9_MARK, PORT139_FN1), \
742	PINMUX_DATA(PORT139_KEYOUT9_MARK, PORT139_FN2), \
743	PINMUX_DATA(VIO2_D1_MARK, PORT139_FN6), \
744	PINMUX_DATA(LCD2D7_MARK, PORT139_FN7),
745	PINMUX_DATA(VIO_D10_MARK, PORT140_FN1), \
746	PINMUX_DATA(TPU0TO2_MARK, PORT140_FN4), \
747	PINMUX_DATA(VIO2_D2_MARK, PORT140_FN6), \
748	PINMUX_DATA(LCD2D8_MARK, PORT140_FN7),
749	PINMUX_DATA(VIO_D11_MARK, PORT141_FN1), \
750	PINMUX_DATA(TPU0TO3_MARK, PORT141_FN4), \
751	PINMUX_DATA(VIO2_D3_MARK, PORT141_FN6), \
752	PINMUX_DATA(LCD2D9_MARK, PORT141_FN7),
753	PINMUX_DATA(VIO_D12_MARK, PORT142_FN1), \
754	PINMUX_DATA(PORT142_KEYOUT10_MARK, PORT142_FN2), \
755	PINMUX_DATA(VIO2_D4_MARK, PORT142_FN6), \
756	PINMUX_DATA(LCD2D2_MARK, PORT142_FN7),
757	PINMUX_DATA(VIO_D13_MARK, PORT143_FN1), \
758	PINMUX_DATA(PORT143_KEYOUT11_MARK, PORT143_FN2), \
759	PINMUX_DATA(PORT143_KEYOUT6_MARK, PORT143_FN3), \
760	PINMUX_DATA(VIO2_D5_MARK, PORT143_FN6), \
761	PINMUX_DATA(LCD2D3_MARK, PORT143_FN7),
762	PINMUX_DATA(VIO_D14_MARK, PORT144_FN1), \
763	PINMUX_DATA(PORT144_KEYOUT7_MARK, PORT144_FN2), \
764	PINMUX_DATA(VIO2_D6_MARK, PORT144_FN6), \
765	PINMUX_DATA(LCD2D4_MARK, PORT144_FN7),
766	PINMUX_DATA(VIO_D15_MARK, PORT145_FN1), \
767	PINMUX_DATA(TPU1TO3_MARK, PORT145_FN3), \
768	PINMUX_DATA(PORT145_LCD2DISP_MARK, PORT145_FN4), \
769	PINMUX_DATA(PORT145_LCD2RS_MARK, PORT145_FN5), \
770	PINMUX_DATA(VIO2_D7_MARK, PORT145_FN6), \
771	PINMUX_DATA(LCD2D5_MARK, PORT145_FN7),
772	PINMUX_DATA(VIO_CLK_MARK, PORT146_FN1), \
773	PINMUX_DATA(LCD2DCK_MARK, PORT146_FN4), \
774	PINMUX_DATA(PORT146_LCD2WR__MARK, PORT146_FN5), \
775	PINMUX_DATA(VIO2_CLK_MARK, PORT146_FN6, MSEL4CR_MSEL27_0), \
776	PINMUX_DATA(LCD2D18_MARK, PORT146_FN7),
777	PINMUX_DATA(VIO_FIELD_MARK, PORT147_FN1), \
778	PINMUX_DATA(LCD2RD__MARK, PORT147_FN4), \
779	PINMUX_DATA(VIO2_FIELD_MARK, PORT147_FN6, MSEL4CR_MSEL27_0), \
780	PINMUX_DATA(LCD2D19_MARK, PORT147_FN7),
781	PINMUX_DATA(VIO_CKO_MARK, PORT148_FN1),
782	PINMUX_DATA(A27_MARK, PORT149_FN1), \
783	PINMUX_DATA(PORT149_RDWR_MARK, PORT149_FN2), \
784	PINMUX_DATA(MFG0_IN1_MARK, PORT149_FN3), \
785	PINMUX_DATA(PORT149_KEYOUT9_MARK, PORT149_FN4),
786	PINMUX_DATA(MFG0_IN2_MARK, PORT150_FN3),
787	PINMUX_DATA(TS_SPSYNC3_MARK, PORT151_FN4), \
788	PINMUX_DATA(MSIOF2_RSCK_MARK, PORT151_FN5),
789	PINMUX_DATA(TS_SDAT3_MARK, PORT152_FN4), \
790	PINMUX_DATA(MSIOF2_RSYNC_MARK, PORT152_FN5),
791	PINMUX_DATA(TPU1TO2_MARK, PORT153_FN3), \
792	PINMUX_DATA(TS_SDEN3_MARK, PORT153_FN4), \
793	PINMUX_DATA(PORT153_MSIOF2_SS1_MARK, PORT153_FN5),
794	PINMUX_DATA(SCIFA2_TXD1_MARK, PORT154_FN2, MSEL3CR_MSEL9_0), \
795	PINMUX_DATA(MSIOF2_MCK0_MARK, PORT154_FN5),
796	PINMUX_DATA(SCIFA2_RXD1_MARK, PORT155_FN2, MSEL3CR_MSEL9_0), \
797	PINMUX_DATA(MSIOF2_MCK1_MARK, PORT155_FN5),
798	PINMUX_DATA(SCIFA2_RTS1__MARK, PORT156_FN2, MSEL3CR_MSEL9_0), \
799	PINMUX_DATA(PORT156_MSIOF2_SS2_MARK, PORT156_FN5),
800	PINMUX_DATA(SCIFA2_CTS1__MARK, PORT157_FN2, MSEL3CR_MSEL9_0), \
801	PINMUX_DATA(PORT157_MSIOF2_RXD_MARK, PORT157_FN5, MSEL4CR_MSEL11_0,
802		MSEL4CR_MSEL10_0),
803	PINMUX_DATA(DINT__MARK, PORT158_FN1), \
804	PINMUX_DATA(SCIFA2_SCK1_MARK, PORT158_FN2, MSEL3CR_MSEL9_0), \
805	PINMUX_DATA(TS_SCK3_MARK, PORT158_FN4),
806	PINMUX_DATA(PORT159_SCIFB_SCK_MARK, PORT159_FN1, MSEL4CR_MSEL22_0), \
807	PINMUX_DATA(PORT159_SCIFA5_SCK_MARK, PORT159_FN2, MSEL4CR_MSEL21_1), \
808	PINMUX_DATA(NMI_MARK, PORT159_FN3),
809	PINMUX_DATA(PORT160_SCIFB_TXD_MARK, PORT160_FN1, MSEL4CR_MSEL22_0), \
810	PINMUX_DATA(PORT160_SCIFA5_TXD_MARK, PORT160_FN2, MSEL4CR_MSEL21_1),
811	PINMUX_DATA(PORT161_SCIFB_CTS__MARK, PORT161_FN1, MSEL4CR_MSEL22_0), \
812	PINMUX_DATA(PORT161_SCIFA5_CTS__MARK, PORT161_FN2, MSEL4CR_MSEL21_1),
813	PINMUX_DATA(PORT162_SCIFB_RXD_MARK, PORT162_FN1, MSEL4CR_MSEL22_0), \
814	PINMUX_DATA(PORT162_SCIFA5_RXD_MARK, PORT162_FN2, MSEL4CR_MSEL21_1),
815	PINMUX_DATA(PORT163_SCIFB_RTS__MARK, PORT163_FN1, MSEL4CR_MSEL22_0), \
816	PINMUX_DATA(PORT163_SCIFA5_RTS__MARK, PORT163_FN2, MSEL4CR_MSEL21_1), \
817	PINMUX_DATA(TPU3TO0_MARK, PORT163_FN5),
818	PINMUX_DATA(LCDD0_MARK, PORT192_FN1),
819	PINMUX_DATA(LCDD1_MARK, PORT193_FN1), \
820	PINMUX_DATA(PORT193_SCIFA5_CTS__MARK, PORT193_FN3, MSEL4CR_MSEL21_0,
821		MSEL4CR_MSEL20_1), \
822	PINMUX_DATA(BBIF2_TSYNC1_MARK, PORT193_FN5),
823	PINMUX_DATA(LCDD2_MARK, PORT194_FN1), \
824	PINMUX_DATA(PORT194_SCIFA5_RTS__MARK, PORT194_FN3, MSEL4CR_MSEL21_0,
825		MSEL4CR_MSEL20_1), \
826	PINMUX_DATA(BBIF2_TSCK1_MARK, PORT194_FN5),
827	PINMUX_DATA(LCDD3_MARK, PORT195_FN1), \
828	PINMUX_DATA(PORT195_SCIFA5_RXD_MARK, PORT195_FN3, MSEL4CR_MSEL21_0,
829		MSEL4CR_MSEL20_1), \
830	PINMUX_DATA(BBIF2_TXD1_MARK, PORT195_FN5),
831	PINMUX_DATA(LCDD4_MARK, PORT196_FN1), \
832	PINMUX_DATA(PORT196_SCIFA5_TXD_MARK, PORT196_FN3, MSEL4CR_MSEL21_0,
833		MSEL4CR_MSEL20_1),
834	PINMUX_DATA(LCDD5_MARK, PORT197_FN1), \
835	PINMUX_DATA(PORT197_SCIFA5_SCK_MARK, PORT197_FN3, MSEL4CR_MSEL21_0,
836		MSEL4CR_MSEL20_1), \
837	PINMUX_DATA(MFG2_OUT2_MARK, PORT197_FN5), \
838	PINMUX_DATA(TPU2TO1_MARK, PORT197_FN7),
839	PINMUX_DATA(LCDD6_MARK, PORT198_FN1),
840	PINMUX_DATA(LCDD7_MARK, PORT199_FN1), \
841	PINMUX_DATA(TPU4TO1_MARK, PORT199_FN2), \
842	PINMUX_DATA(MFG4_OUT2_MARK, PORT199_FN5),
843	PINMUX_DATA(LCDD8_MARK, PORT200_FN1), \
844	PINMUX_DATA(D16_MARK, PORT200_FN6),
845	PINMUX_DATA(LCDD9_MARK, PORT201_FN1), \
846	PINMUX_DATA(D17_MARK, PORT201_FN6),
847	PINMUX_DATA(LCDD10_MARK, PORT202_FN1), \
848	PINMUX_DATA(D18_MARK, PORT202_FN6),
849	PINMUX_DATA(LCDD11_MARK, PORT203_FN1), \
850	PINMUX_DATA(D19_MARK, PORT203_FN6),
851	PINMUX_DATA(LCDD12_MARK, PORT204_FN1), \
852	PINMUX_DATA(D20_MARK, PORT204_FN6),
853	PINMUX_DATA(LCDD13_MARK, PORT205_FN1), \
854	PINMUX_DATA(D21_MARK, PORT205_FN6),
855	PINMUX_DATA(LCDD14_MARK, PORT206_FN1), \
856	PINMUX_DATA(D22_MARK, PORT206_FN6),
857	PINMUX_DATA(LCDD15_MARK, PORT207_FN1), \
858	PINMUX_DATA(PORT207_MSIOF0L_SS1_MARK, PORT207_FN2, MSEL3CR_MSEL11_1), \
859	PINMUX_DATA(D23_MARK, PORT207_FN6),
860	PINMUX_DATA(LCDD16_MARK, PORT208_FN1), \
861	PINMUX_DATA(PORT208_MSIOF0L_SS2_MARK, PORT208_FN2, MSEL3CR_MSEL11_1), \
862	PINMUX_DATA(D24_MARK, PORT208_FN6),
863	PINMUX_DATA(LCDD17_MARK, PORT209_FN1), \
864	PINMUX_DATA(D25_MARK, PORT209_FN6),
865	PINMUX_DATA(LCDD18_MARK, PORT210_FN1), \
866	PINMUX_DATA(DREQ2_MARK, PORT210_FN2), \
867	PINMUX_DATA(PORT210_MSIOF0L_SS1_MARK, PORT210_FN5, MSEL3CR_MSEL11_1), \
868	PINMUX_DATA(D26_MARK, PORT210_FN6),
869	PINMUX_DATA(LCDD19_MARK, PORT211_FN1), \
870	PINMUX_DATA(PORT211_MSIOF0L_SS2_MARK, PORT211_FN5, MSEL3CR_MSEL11_1), \
871	PINMUX_DATA(D27_MARK, PORT211_FN6),
872	PINMUX_DATA(LCDD20_MARK, PORT212_FN1), \
873	PINMUX_DATA(TS_SPSYNC1_MARK, PORT212_FN2), \
874	PINMUX_DATA(MSIOF0L_MCK0_MARK, PORT212_FN5, MSEL3CR_MSEL11_1), \
875	PINMUX_DATA(D28_MARK, PORT212_FN6),
876	PINMUX_DATA(LCDD21_MARK, PORT213_FN1), \
877	PINMUX_DATA(TS_SDAT1_MARK, PORT213_FN2), \
878	PINMUX_DATA(MSIOF0L_MCK1_MARK, PORT213_FN5, MSEL3CR_MSEL11_1), \
879	PINMUX_DATA(D29_MARK, PORT213_FN6),
880	PINMUX_DATA(LCDD22_MARK, PORT214_FN1), \
881	PINMUX_DATA(TS_SDEN1_MARK, PORT214_FN2), \
882	PINMUX_DATA(MSIOF0L_RSCK_MARK, PORT214_FN5, MSEL3CR_MSEL11_1), \
883	PINMUX_DATA(D30_MARK, PORT214_FN6),
884	PINMUX_DATA(LCDD23_MARK, PORT215_FN1), \
885	PINMUX_DATA(TS_SCK1_MARK, PORT215_FN2), \
886	PINMUX_DATA(MSIOF0L_RSYNC_MARK, PORT215_FN5, MSEL3CR_MSEL11_1), \
887	PINMUX_DATA(D31_MARK, PORT215_FN6),
888	PINMUX_DATA(LCDDCK_MARK, PORT216_FN1), \
889	PINMUX_DATA(LCDWR__MARK, PORT216_FN2),
890	PINMUX_DATA(LCDRD__MARK, PORT217_FN1), \
891	PINMUX_DATA(DACK2_MARK, PORT217_FN2), \
892	PINMUX_DATA(PORT217_LCD2RS_MARK, PORT217_FN3), \
893	PINMUX_DATA(MSIOF0L_TSYNC_MARK, PORT217_FN5, MSEL3CR_MSEL11_1), \
894	PINMUX_DATA(VIO2_FIELD3_MARK, PORT217_FN6, MSEL4CR_MSEL27_1,
895		MSEL4CR_MSEL26_1), \
896	PINMUX_DATA(PORT217_LCD2DISP_MARK, PORT217_FN7),
897	PINMUX_DATA(LCDHSYN_MARK, PORT218_FN1), \
898	PINMUX_DATA(LCDCS__MARK, PORT218_FN2), \
899	PINMUX_DATA(LCDCS2__MARK, PORT218_FN3), \
900	PINMUX_DATA(DACK3_MARK, PORT218_FN4), \
901	PINMUX_DATA(PORT218_VIO_CKOR_MARK, PORT218_FN5),
902	PINMUX_DATA(LCDDISP_MARK, PORT219_FN1), \
903	PINMUX_DATA(LCDRS_MARK, PORT219_FN2), \
904	PINMUX_DATA(PORT219_LCD2WR__MARK, PORT219_FN3), \
905	PINMUX_DATA(DREQ3_MARK, PORT219_FN4), \
906	PINMUX_DATA(MSIOF0L_TSCK_MARK, PORT219_FN5, MSEL3CR_MSEL11_1), \
907	PINMUX_DATA(VIO2_CLK3_MARK, PORT219_FN6, MSEL4CR_MSEL27_1,
908		MSEL4CR_MSEL26_1), \
909	PINMUX_DATA(LCD2DCK_2_MARK, PORT219_FN7),
910	PINMUX_DATA(LCDVSYN_MARK, PORT220_FN1), \
911	PINMUX_DATA(LCDVSYN2_MARK, PORT220_FN2),
912	PINMUX_DATA(LCDLCLK_MARK, PORT221_FN1), \
913	PINMUX_DATA(DREQ1_MARK, PORT221_FN2), \
914	PINMUX_DATA(PORT221_LCD2CS__MARK, PORT221_FN3), \
915	PINMUX_DATA(PWEN_MARK, PORT221_FN4), \
916	PINMUX_DATA(MSIOF0L_RXD_MARK, PORT221_FN5, MSEL3CR_MSEL11_1), \
917	PINMUX_DATA(VIO2_HD3_MARK, PORT221_FN6, MSEL4CR_MSEL27_1,
918		MSEL4CR_MSEL26_1), \
919	PINMUX_DATA(PORT221_LCD2HSYN_MARK, PORT221_FN7),
920	PINMUX_DATA(LCDDON_MARK, PORT222_FN1), \
921	PINMUX_DATA(LCDDON2_MARK, PORT222_FN2), \
922	PINMUX_DATA(DACK1_MARK, PORT222_FN3), \
923	PINMUX_DATA(OVCN_MARK, PORT222_FN4), \
924	PINMUX_DATA(MSIOF0L_TXD_MARK, PORT222_FN5, MSEL3CR_MSEL11_1), \
925	PINMUX_DATA(VIO2_VD3_MARK, PORT222_FN6, MSEL4CR_MSEL27_1,
926		MSEL4CR_MSEL26_1), \
927	PINMUX_DATA(PORT222_LCD2VSYN_MARK, PORT222_FN7, MSEL3CR_MSEL2_1),
928
929	PINMUX_DATA(SCIFA1_TXD_MARK, PORT225_FN2), \
930	PINMUX_DATA(OVCN2_MARK, PORT225_FN4),
931	PINMUX_DATA(EXTLP_MARK, PORT226_FN1), \
932	PINMUX_DATA(SCIFA1_SCK_MARK, PORT226_FN2), \
933	PINMUX_DATA(PORT226_VIO_CKO2_MARK, PORT226_FN5),
934	PINMUX_DATA(SCIFA1_RTS__MARK, PORT227_FN2), \
935	PINMUX_DATA(IDIN_MARK, PORT227_FN4),
936	PINMUX_DATA(SCIFA1_RXD_MARK, PORT228_FN2),
937	PINMUX_DATA(SCIFA1_CTS__MARK, PORT229_FN2), \
938	PINMUX_DATA(MFG1_IN1_MARK, PORT229_FN3),
939	PINMUX_DATA(MSIOF1_TXD_MARK, PORT230_FN1), \
940	PINMUX_DATA(SCIFA2_TXD2_MARK, PORT230_FN2, MSEL3CR_MSEL9_1),
941	PINMUX_DATA(MSIOF1_TSYNC_MARK, PORT231_FN1), \
942	PINMUX_DATA(SCIFA2_CTS2__MARK, PORT231_FN2, MSEL3CR_MSEL9_1),
943	PINMUX_DATA(MSIOF1_TSCK_MARK, PORT232_FN1), \
944	PINMUX_DATA(SCIFA2_SCK2_MARK, PORT232_FN2, MSEL3CR_MSEL9_1),
945	PINMUX_DATA(MSIOF1_RXD_MARK, PORT233_FN1), \
946	PINMUX_DATA(SCIFA2_RXD2_MARK, PORT233_FN2, MSEL3CR_MSEL9_1),
947	PINMUX_DATA(MSIOF1_RSCK_MARK, PORT234_FN1), \
948	PINMUX_DATA(SCIFA2_RTS2__MARK, PORT234_FN2, MSEL3CR_MSEL9_1), \
949	PINMUX_DATA(VIO2_CLK2_MARK, PORT234_FN6, MSEL4CR_MSEL27_1,
950		MSEL4CR_MSEL26_0), \
951	PINMUX_DATA(LCD2D20_MARK, PORT234_FN7),
952	PINMUX_DATA(MSIOF1_RSYNC_MARK, PORT235_FN1), \
953	PINMUX_DATA(MFG1_IN2_MARK, PORT235_FN3), \
954	PINMUX_DATA(VIO2_VD2_MARK, PORT235_FN6, MSEL4CR_MSEL27_1,
955		MSEL4CR_MSEL26_0), \
956	PINMUX_DATA(LCD2D21_MARK, PORT235_FN7),
957	PINMUX_DATA(MSIOF1_MCK0_MARK, PORT236_FN1), \
958	PINMUX_DATA(PORT236_I2C_SDA2_MARK, PORT236_FN2, MSEL2CR_MSEL17_0,
959		MSEL2CR_MSEL16_0),
960	PINMUX_DATA(MSIOF1_MCK1_MARK, PORT237_FN1), \
961	PINMUX_DATA(PORT237_I2C_SCL2_MARK, PORT237_FN2, MSEL2CR_MSEL17_0,
962		MSEL2CR_MSEL16_0),
963	PINMUX_DATA(MSIOF1_SS1_MARK, PORT238_FN1), \
964	PINMUX_DATA(VIO2_FIELD2_MARK, PORT238_FN6, MSEL4CR_MSEL27_1,
965		MSEL4CR_MSEL26_0), \
966	PINMUX_DATA(LCD2D22_MARK, PORT238_FN7),
967	PINMUX_DATA(MSIOF1_SS2_MARK, PORT239_FN1), \
968	PINMUX_DATA(VIO2_HD2_MARK, PORT239_FN6, MSEL4CR_MSEL27_1,
969		MSEL4CR_MSEL26_0), \
970	PINMUX_DATA(LCD2D23_MARK, PORT239_FN7),
971	PINMUX_DATA(SCIFA6_TXD_MARK, PORT240_FN1),
972	PINMUX_DATA(PORT241_IRDA_OUT_MARK, PORT241_FN1, MSEL4CR_MSEL19_0), \
973	PINMUX_DATA(PORT241_IROUT_MARK, PORT241_FN2), \
974	PINMUX_DATA(MFG4_OUT1_MARK, PORT241_FN3), \
975	PINMUX_DATA(TPU4TO0_MARK, PORT241_FN4),
976	PINMUX_DATA(PORT242_IRDA_IN_MARK, PORT242_FN1, MSEL4CR_MSEL19_0), \
977	PINMUX_DATA(MFG4_IN2_MARK, PORT242_FN3),
978	PINMUX_DATA(PORT243_IRDA_FIRSEL_MARK, PORT243_FN1, MSEL4CR_MSEL19_0), \
979	PINMUX_DATA(PORT243_VIO_CKO2_MARK, PORT243_FN2),
980	PINMUX_DATA(PORT244_SCIFA5_CTS__MARK, PORT244_FN1, MSEL4CR_MSEL21_0,
981		MSEL4CR_MSEL20_0), \
982	PINMUX_DATA(MFG2_IN1_MARK, PORT244_FN2), \
983	PINMUX_DATA(PORT244_SCIFB_CTS__MARK, PORT244_FN3, MSEL4CR_MSEL22_1), \
984	PINMUX_DATA(MSIOF2R_RXD_MARK, PORT244_FN7, MSEL4CR_MSEL11_1),
985	PINMUX_DATA(PORT245_SCIFA5_RTS__MARK, PORT245_FN1, MSEL4CR_MSEL21_0,
986		MSEL4CR_MSEL20_0), \
987	PINMUX_DATA(MFG2_IN2_MARK, PORT245_FN2), \
988	PINMUX_DATA(PORT245_SCIFB_RTS__MARK, PORT245_FN3, MSEL4CR_MSEL22_1), \
989	PINMUX_DATA(MSIOF2R_TXD_MARK, PORT245_FN7, MSEL4CR_MSEL11_1),
990	PINMUX_DATA(PORT246_SCIFA5_RXD_MARK, PORT246_FN1, MSEL4CR_MSEL21_0,
991		MSEL4CR_MSEL20_0), \
992	PINMUX_DATA(MFG1_OUT1_MARK, PORT246_FN2), \
993	PINMUX_DATA(PORT246_SCIFB_RXD_MARK, PORT246_FN3, MSEL4CR_MSEL22_1), \
994	PINMUX_DATA(TPU1TO0_MARK, PORT246_FN4),
995	PINMUX_DATA(PORT247_SCIFA5_TXD_MARK, PORT247_FN1, MSEL4CR_MSEL21_0,
996		MSEL4CR_MSEL20_0), \
997	PINMUX_DATA(MFG3_OUT2_MARK, PORT247_FN2), \
998	PINMUX_DATA(PORT247_SCIFB_TXD_MARK, PORT247_FN3, MSEL4CR_MSEL22_1), \
999	PINMUX_DATA(TPU3TO1_MARK, PORT247_FN4),
1000	PINMUX_DATA(PORT248_SCIFA5_SCK_MARK, PORT248_FN1, MSEL4CR_MSEL21_0,
1001		MSEL4CR_MSEL20_0), \
1002	PINMUX_DATA(MFG2_OUT1_MARK, PORT248_FN2), \
1003	PINMUX_DATA(PORT248_SCIFB_SCK_MARK, PORT248_FN3, MSEL4CR_MSEL22_1), \
1004	PINMUX_DATA(TPU2TO0_MARK, PORT248_FN4), \
1005	PINMUX_DATA(PORT248_I2C_SCL3_MARK, PORT248_FN5, MSEL2CR_MSEL19_0,
1006		MSEL2CR_MSEL18_0), \
1007	PINMUX_DATA(MSIOF2R_TSCK_MARK, PORT248_FN7, MSEL4CR_MSEL11_1),
1008	PINMUX_DATA(PORT249_IROUT_MARK, PORT249_FN1), \
1009	PINMUX_DATA(MFG4_IN1_MARK, PORT249_FN2), \
1010	PINMUX_DATA(PORT249_I2C_SDA3_MARK, PORT249_FN5, MSEL2CR_MSEL19_0,
1011		MSEL2CR_MSEL18_0), \
1012	PINMUX_DATA(MSIOF2R_TSYNC_MARK, PORT249_FN7, MSEL4CR_MSEL11_1),
1013	PINMUX_DATA(SDHICLK0_MARK, PORT250_FN1),
1014	PINMUX_DATA(SDHICD0_MARK, PORT251_FN1),
1015	PINMUX_DATA(SDHID0_0_MARK, PORT252_FN1),
1016	PINMUX_DATA(SDHID0_1_MARK, PORT253_FN1),
1017	PINMUX_DATA(SDHID0_2_MARK, PORT254_FN1),
1018	PINMUX_DATA(SDHID0_3_MARK, PORT255_FN1),
1019	PINMUX_DATA(SDHICMD0_MARK, PORT256_FN1),
1020	PINMUX_DATA(SDHIWP0_MARK, PORT257_FN1),
1021	PINMUX_DATA(SDHICLK1_MARK, PORT258_FN1),
1022	PINMUX_DATA(SDHID1_0_MARK, PORT259_FN1), \
1023	PINMUX_DATA(TS_SPSYNC2_MARK, PORT259_FN3),
1024	PINMUX_DATA(SDHID1_1_MARK, PORT260_FN1), \
1025	PINMUX_DATA(TS_SDAT2_MARK, PORT260_FN3),
1026	PINMUX_DATA(SDHID1_2_MARK, PORT261_FN1), \
1027	PINMUX_DATA(TS_SDEN2_MARK, PORT261_FN3),
1028	PINMUX_DATA(SDHID1_3_MARK, PORT262_FN1), \
1029	PINMUX_DATA(TS_SCK2_MARK, PORT262_FN3),
1030	PINMUX_DATA(SDHICMD1_MARK, PORT263_FN1),
1031	PINMUX_DATA(SDHICLK2_MARK, PORT264_FN1),
1032	PINMUX_DATA(SDHID2_0_MARK, PORT265_FN1), \
1033	PINMUX_DATA(TS_SPSYNC4_MARK, PORT265_FN3),
1034	PINMUX_DATA(SDHID2_1_MARK, PORT266_FN1), \
1035	PINMUX_DATA(TS_SDAT4_MARK, PORT266_FN3),
1036	PINMUX_DATA(SDHID2_2_MARK, PORT267_FN1), \
1037	PINMUX_DATA(TS_SDEN4_MARK, PORT267_FN3),
1038	PINMUX_DATA(SDHID2_3_MARK, PORT268_FN1), \
1039	PINMUX_DATA(TS_SCK4_MARK, PORT268_FN3),
1040	PINMUX_DATA(SDHICMD2_MARK, PORT269_FN1),
1041	PINMUX_DATA(MMCCLK0_MARK, PORT270_FN1, MSEL4CR_MSEL15_0),
1042	PINMUX_DATA(MMCD0_0_MARK, PORT271_FN1, MSEL4CR_MSEL15_0),
1043	PINMUX_DATA(MMCD0_1_MARK, PORT272_FN1, MSEL4CR_MSEL15_0),
1044	PINMUX_DATA(MMCD0_2_MARK, PORT273_FN1, MSEL4CR_MSEL15_0),
1045	PINMUX_DATA(MMCD0_3_MARK, PORT274_FN1, MSEL4CR_MSEL15_0),
1046	PINMUX_DATA(MMCD0_4_MARK, PORT275_FN1, MSEL4CR_MSEL15_0),
1047	PINMUX_DATA(TS_SPSYNC5_MARK, PORT275_FN3),
1048	PINMUX_DATA(MMCD0_5_MARK, PORT276_FN1, MSEL4CR_MSEL15_0),
1049	PINMUX_DATA(TS_SDAT5_MARK, PORT276_FN3),
1050	PINMUX_DATA(MMCD0_6_MARK, PORT277_FN1, MSEL4CR_MSEL15_0),
1051	PINMUX_DATA(TS_SDEN5_MARK, PORT277_FN3),
1052	PINMUX_DATA(MMCD0_7_MARK, PORT278_FN1, MSEL4CR_MSEL15_0),
1053	PINMUX_DATA(TS_SCK5_MARK, PORT278_FN3),
1054	PINMUX_DATA(MMCCMD0_MARK, PORT279_FN1, MSEL4CR_MSEL15_0),
1055	PINMUX_DATA(RESETOUTS__MARK, PORT281_FN1), \
1056	PINMUX_DATA(EXTAL2OUT_MARK, PORT281_FN2),
1057	PINMUX_DATA(MCP_WAIT__MCP_FRB_MARK, PORT288_FN1),
1058	PINMUX_DATA(MCP_CKO_MARK, PORT289_FN1), \
1059	PINMUX_DATA(MMCCLK1_MARK, PORT289_FN2, MSEL4CR_MSEL15_1),
1060	PINMUX_DATA(MCP_D15_MCP_NAF15_MARK, PORT290_FN1),
1061	PINMUX_DATA(MCP_D14_MCP_NAF14_MARK, PORT291_FN1),
1062	PINMUX_DATA(MCP_D13_MCP_NAF13_MARK, PORT292_FN1),
1063	PINMUX_DATA(MCP_D12_MCP_NAF12_MARK, PORT293_FN1),
1064	PINMUX_DATA(MCP_D11_MCP_NAF11_MARK, PORT294_FN1),
1065	PINMUX_DATA(MCP_D10_MCP_NAF10_MARK, PORT295_FN1),
1066	PINMUX_DATA(MCP_D9_MCP_NAF9_MARK, PORT296_FN1),
1067	PINMUX_DATA(MCP_D8_MCP_NAF8_MARK, PORT297_FN1), \
1068	PINMUX_DATA(MMCCMD1_MARK, PORT297_FN2, MSEL4CR_MSEL15_1),
1069	PINMUX_DATA(MCP_D7_MCP_NAF7_MARK, PORT298_FN1), \
1070	PINMUX_DATA(MMCD1_7_MARK, PORT298_FN2, MSEL4CR_MSEL15_1),
1071
1072	PINMUX_DATA(MCP_D6_MCP_NAF6_MARK, PORT299_FN1), \
1073	PINMUX_DATA(MMCD1_6_MARK, PORT299_FN2, MSEL4CR_MSEL15_1),
1074	PINMUX_DATA(MCP_D5_MCP_NAF5_MARK, PORT300_FN1), \
1075	PINMUX_DATA(MMCD1_5_MARK, PORT300_FN2, MSEL4CR_MSEL15_1),
1076	PINMUX_DATA(MCP_D4_MCP_NAF4_MARK, PORT301_FN1), \
1077	PINMUX_DATA(MMCD1_4_MARK, PORT301_FN2, MSEL4CR_MSEL15_1),
1078	PINMUX_DATA(MCP_D3_MCP_NAF3_MARK, PORT302_FN1), \
1079	PINMUX_DATA(MMCD1_3_MARK, PORT302_FN2, MSEL4CR_MSEL15_1),
1080	PINMUX_DATA(MCP_D2_MCP_NAF2_MARK, PORT303_FN1), \
1081	PINMUX_DATA(MMCD1_2_MARK, PORT303_FN2, MSEL4CR_MSEL15_1),
1082	PINMUX_DATA(MCP_D1_MCP_NAF1_MARK, PORT304_FN1), \
1083	PINMUX_DATA(MMCD1_1_MARK, PORT304_FN2, MSEL4CR_MSEL15_1),
1084	PINMUX_DATA(MCP_D0_MCP_NAF0_MARK, PORT305_FN1), \
1085	PINMUX_DATA(MMCD1_0_MARK, PORT305_FN2, MSEL4CR_MSEL15_1),
1086	PINMUX_DATA(MCP_NBRSTOUT__MARK, PORT306_FN1),
1087	PINMUX_DATA(MCP_WE0__MCP_FWE_MARK, PORT309_FN1), \
1088	PINMUX_DATA(MCP_RDWR_MCP_FWE_MARK, PORT309_FN2),
1089
1090	/* MSEL2 special cases */
1091	PINMUX_DATA(TSIF2_TS_XX1_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_0,
1092		MSEL2CR_MSEL12_0),
1093	PINMUX_DATA(TSIF2_TS_XX2_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_0,
1094		MSEL2CR_MSEL12_1),
1095	PINMUX_DATA(TSIF2_TS_XX3_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_1,
1096		MSEL2CR_MSEL12_0),
1097	PINMUX_DATA(TSIF2_TS_XX4_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_1,
1098		MSEL2CR_MSEL12_1),
1099	PINMUX_DATA(TSIF2_TS_XX5_MARK, MSEL2CR_MSEL14_1, MSEL2CR_MSEL13_0,
1100		MSEL2CR_MSEL12_0),
1101	PINMUX_DATA(TSIF1_TS_XX1_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_0,
1102		MSEL2CR_MSEL9_0),
1103	PINMUX_DATA(TSIF1_TS_XX2_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_0,
1104		MSEL2CR_MSEL9_1),
1105	PINMUX_DATA(TSIF1_TS_XX3_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_1,
1106		MSEL2CR_MSEL9_0),
1107	PINMUX_DATA(TSIF1_TS_XX4_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_1,
1108		MSEL2CR_MSEL9_1),
1109	PINMUX_DATA(TSIF1_TS_XX5_MARK, MSEL2CR_MSEL11_1, MSEL2CR_MSEL10_0,
1110		MSEL2CR_MSEL9_0),
1111	PINMUX_DATA(TSIF0_TS_XX1_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_0,
1112		MSEL2CR_MSEL6_0),
1113	PINMUX_DATA(TSIF0_TS_XX2_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_0,
1114		MSEL2CR_MSEL6_1),
1115	PINMUX_DATA(TSIF0_TS_XX3_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_1,
1116		MSEL2CR_MSEL6_0),
1117	PINMUX_DATA(TSIF0_TS_XX4_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_1,
1118		MSEL2CR_MSEL6_1),
1119	PINMUX_DATA(TSIF0_TS_XX5_MARK, MSEL2CR_MSEL8_1, MSEL2CR_MSEL7_0,
1120		MSEL2CR_MSEL6_0),
1121	PINMUX_DATA(MST1_TS_XX1_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_0,
1122		MSEL2CR_MSEL3_0),
1123	PINMUX_DATA(MST1_TS_XX2_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_0,
1124		MSEL2CR_MSEL3_1),
1125	PINMUX_DATA(MST1_TS_XX3_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_1,
1126		MSEL2CR_MSEL3_0),
1127	PINMUX_DATA(MST1_TS_XX4_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_1,
1128		MSEL2CR_MSEL3_1),
1129	PINMUX_DATA(MST1_TS_XX5_MARK, MSEL2CR_MSEL5_1, MSEL2CR_MSEL4_0,
1130		MSEL2CR_MSEL3_0),
1131	PINMUX_DATA(MST0_TS_XX1_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_0,
1132		MSEL2CR_MSEL0_0),
1133	PINMUX_DATA(MST0_TS_XX2_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_0,
1134		MSEL2CR_MSEL0_1),
1135	PINMUX_DATA(MST0_TS_XX3_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_1,
1136		MSEL2CR_MSEL0_0),
1137	PINMUX_DATA(MST0_TS_XX4_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_1,
1138		MSEL2CR_MSEL0_1),
1139	PINMUX_DATA(MST0_TS_XX5_MARK, MSEL2CR_MSEL2_1, MSEL2CR_MSEL1_0,
1140		MSEL2CR_MSEL0_0),
1141
1142	/* MSEL3 special cases */
1143	PINMUX_DATA(SDHI0_VCCQ_MC0_ON_MARK, MSEL3CR_MSEL28_1),
1144	PINMUX_DATA(SDHI0_VCCQ_MC0_OFF_MARK, MSEL3CR_MSEL28_0),
1145	PINMUX_DATA(DEBUG_MON_VIO_MARK, MSEL3CR_MSEL15_0),
1146	PINMUX_DATA(DEBUG_MON_LCDD_MARK, MSEL3CR_MSEL15_1),
1147	PINMUX_DATA(LCDC_LCDC0_MARK, MSEL3CR_MSEL6_0),
1148	PINMUX_DATA(LCDC_LCDC1_MARK, MSEL3CR_MSEL6_1),
1149
1150	/* MSEL4 special cases */
1151	PINMUX_DATA(IRQ9_MEM_INT_MARK, MSEL4CR_MSEL29_0),
1152	PINMUX_DATA(IRQ9_MCP_INT_MARK, MSEL4CR_MSEL29_1),
1153	PINMUX_DATA(A11_MARK, MSEL4CR_MSEL13_0, MSEL4CR_MSEL12_0),
1154	PINMUX_DATA(KEYOUT8_MARK, MSEL4CR_MSEL13_0, MSEL4CR_MSEL12_1),
1155	PINMUX_DATA(TPU4TO3_MARK, MSEL4CR_MSEL13_1, MSEL4CR_MSEL12_0),
1156	PINMUX_DATA(RESETA_N_PU_ON_MARK, MSEL4CR_MSEL4_0),
1157	PINMUX_DATA(RESETA_N_PU_OFF_MARK, MSEL4CR_MSEL4_1),
1158	PINMUX_DATA(EDBGREQ_PD_MARK, MSEL4CR_MSEL1_0),
1159	PINMUX_DATA(EDBGREQ_PU_MARK, MSEL4CR_MSEL1_1),
1160};
1161
1162#define __I		(SH_PFC_PIN_CFG_INPUT)
1163#define __O		(SH_PFC_PIN_CFG_OUTPUT)
1164#define __IO		(SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
1165#define __PD		(SH_PFC_PIN_CFG_PULL_DOWN)
1166#define __PU		(SH_PFC_PIN_CFG_PULL_UP)
1167#define __PUD		(SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP)
1168
1169#define SH73A0_PIN_I_PD(pin)		SH_PFC_PIN_CFG(pin, __I | __PD)
1170#define SH73A0_PIN_I_PU(pin)		SH_PFC_PIN_CFG(pin, __I | __PU)
1171#define SH73A0_PIN_I_PU_PD(pin)		SH_PFC_PIN_CFG(pin, __I | __PUD)
1172#define SH73A0_PIN_IO(pin)		SH_PFC_PIN_CFG(pin, __IO)
1173#define SH73A0_PIN_IO_PD(pin)		SH_PFC_PIN_CFG(pin, __IO | __PD)
1174#define SH73A0_PIN_IO_PU(pin)		SH_PFC_PIN_CFG(pin, __IO | __PU)
1175#define SH73A0_PIN_IO_PU_PD(pin)	SH_PFC_PIN_CFG(pin, __IO | __PUD)
1176#define SH73A0_PIN_O(pin)		SH_PFC_PIN_CFG(pin, __O)
1177
1178/* Pin numbers for pins without a corresponding GPIO port number are computed
1179 * from the row and column numbers with a 1000 offset to avoid collisions with
1180 * GPIO port numbers.
1181 */
1182#define PIN_NUMBER(row, col)		(1000+((row)-1)*34+(col)-1)
1183
1184static const struct sh_pfc_pin pinmux_pins[] = {
1185	/* Table 25-1 (I/O and Pull U/D) */
1186	SH73A0_PIN_I_PD(0),
1187	SH73A0_PIN_I_PU(1),
1188	SH73A0_PIN_I_PU(2),
1189	SH73A0_PIN_I_PU(3),
1190	SH73A0_PIN_I_PU(4),
1191	SH73A0_PIN_I_PU(5),
1192	SH73A0_PIN_I_PU(6),
1193	SH73A0_PIN_I_PU(7),
1194	SH73A0_PIN_I_PU(8),
1195	SH73A0_PIN_I_PD(9),
1196	SH73A0_PIN_I_PD(10),
1197	SH73A0_PIN_I_PU_PD(11),
1198	SH73A0_PIN_IO_PU_PD(12),
1199	SH73A0_PIN_IO_PU_PD(13),
1200	SH73A0_PIN_IO_PU_PD(14),
1201	SH73A0_PIN_IO_PU_PD(15),
1202	SH73A0_PIN_IO_PD(16),
1203	SH73A0_PIN_IO_PD(17),
1204	SH73A0_PIN_IO_PU(18),
1205	SH73A0_PIN_IO_PU(19),
1206	SH73A0_PIN_O(20),
1207	SH73A0_PIN_O(21),
1208	SH73A0_PIN_O(22),
1209	SH73A0_PIN_O(23),
1210	SH73A0_PIN_O(24),
1211	SH73A0_PIN_I_PD(25),
1212	SH73A0_PIN_I_PD(26),
1213	SH73A0_PIN_IO_PU(27),
1214	SH73A0_PIN_IO_PU(28),
1215	SH73A0_PIN_IO_PD(29),
1216	SH73A0_PIN_IO_PD(30),
1217	SH73A0_PIN_IO_PU(31),
1218	SH73A0_PIN_IO_PD(32),
1219	SH73A0_PIN_I_PU_PD(33),
1220	SH73A0_PIN_IO_PD(34),
1221	SH73A0_PIN_I_PU_PD(35),
1222	SH73A0_PIN_IO_PD(36),
1223	SH73A0_PIN_IO(37),
1224	SH73A0_PIN_O(38),
1225	SH73A0_PIN_I_PU(39),
1226	SH73A0_PIN_I_PU_PD(40),
1227	SH73A0_PIN_O(41),
1228	SH73A0_PIN_IO_PD(42),
1229	SH73A0_PIN_IO_PU_PD(43),
1230	SH73A0_PIN_IO_PU_PD(44),
1231	SH73A0_PIN_IO_PD(45),
1232	SH73A0_PIN_IO_PD(46),
1233	SH73A0_PIN_IO_PD(47),
1234	SH73A0_PIN_I_PD(48),
1235	SH73A0_PIN_IO_PU_PD(49),
1236	SH73A0_PIN_IO_PD(50),
1237	SH73A0_PIN_IO_PD(51),
1238	SH73A0_PIN_O(52),
1239	SH73A0_PIN_IO_PU_PD(53),
1240	SH73A0_PIN_IO_PU_PD(54),
1241	SH73A0_PIN_IO_PD(55),
1242	SH73A0_PIN_I_PU_PD(56),
1243	SH73A0_PIN_IO(57),
1244	SH73A0_PIN_IO(58),
1245	SH73A0_PIN_IO(59),
1246	SH73A0_PIN_IO(60),
1247	SH73A0_PIN_IO(61),
1248	SH73A0_PIN_IO_PD(62),
1249	SH73A0_PIN_IO_PD(63),
1250	SH73A0_PIN_IO_PU_PD(64),
1251	SH73A0_PIN_IO_PD(65),
1252	SH73A0_PIN_IO_PU_PD(66),
1253	SH73A0_PIN_IO_PU_PD(67),
1254	SH73A0_PIN_IO_PU_PD(68),
1255	SH73A0_PIN_IO_PU_PD(69),
1256	SH73A0_PIN_IO_PU_PD(70),
1257	SH73A0_PIN_IO_PU_PD(71),
1258	SH73A0_PIN_IO_PU_PD(72),
1259	SH73A0_PIN_I_PU_PD(73),
1260	SH73A0_PIN_IO_PU(74),
1261	SH73A0_PIN_IO_PU(75),
1262	SH73A0_PIN_IO_PU(76),
1263	SH73A0_PIN_IO_PU(77),
1264	SH73A0_PIN_IO_PU(78),
1265	SH73A0_PIN_IO_PU(79),
1266	SH73A0_PIN_IO_PU(80),
1267	SH73A0_PIN_IO_PU(81),
1268	SH73A0_PIN_IO_PU(82),
1269	SH73A0_PIN_IO_PU(83),
1270	SH73A0_PIN_IO_PU(84),
1271	SH73A0_PIN_IO_PU(85),
1272	SH73A0_PIN_IO_PU(86),
1273	SH73A0_PIN_IO_PU(87),
1274	SH73A0_PIN_IO_PU(88),
1275	SH73A0_PIN_IO_PU(89),
1276	SH73A0_PIN_O(90),
1277	SH73A0_PIN_IO_PU(91),
1278	SH73A0_PIN_O(92),
1279	SH73A0_PIN_IO_PU(93),
1280	SH73A0_PIN_O(94),
1281	SH73A0_PIN_I_PU_PD(95),
1282	SH73A0_PIN_IO(96),
1283	SH73A0_PIN_IO(97),
1284	SH73A0_PIN_IO(98),
1285	SH73A0_PIN_I_PU(99),
1286	SH73A0_PIN_O(100),
1287	SH73A0_PIN_O(101),
1288	SH73A0_PIN_I_PU(102),
1289	SH73A0_PIN_IO_PD(103),
1290	SH73A0_PIN_I_PU_PD(104),
1291	SH73A0_PIN_I_PD(105),
1292	SH73A0_PIN_I_PD(106),
1293	SH73A0_PIN_I_PU_PD(107),
1294	SH73A0_PIN_I_PU_PD(108),
1295	SH73A0_PIN_IO_PD(109),
1296	SH73A0_PIN_IO_PD(110),
1297	SH73A0_PIN_IO_PU_PD(111),
1298	SH73A0_PIN_IO_PU_PD(112),
1299	SH73A0_PIN_IO_PU_PD(113),
1300	SH73A0_PIN_IO_PD(114),
1301	SH73A0_PIN_IO_PU(115),
1302	SH73A0_PIN_IO_PU(116),
1303	SH73A0_PIN_IO_PU_PD(117),
1304	SH73A0_PIN_IO_PU_PD(118),
1305	SH73A0_PIN_IO_PD(128),
1306	SH73A0_PIN_IO_PD(129),
1307	SH73A0_PIN_IO_PU_PD(130),
1308	SH73A0_PIN_IO_PD(131),
1309	SH73A0_PIN_IO_PD(132),
1310	SH73A0_PIN_IO_PD(133),
1311	SH73A0_PIN_IO_PU_PD(134),
1312	SH73A0_PIN_IO_PU_PD(135),
1313	SH73A0_PIN_IO_PU_PD(136),
1314	SH73A0_PIN_IO_PU_PD(137),
1315	SH73A0_PIN_IO_PD(138),
1316	SH73A0_PIN_IO_PD(139),
1317	SH73A0_PIN_IO_PD(140),
1318	SH73A0_PIN_IO_PD(141),
1319	SH73A0_PIN_IO_PD(142),
1320	SH73A0_PIN_IO_PD(143),
1321	SH73A0_PIN_IO_PU_PD(144),
1322	SH73A0_PIN_IO_PD(145),
1323	SH73A0_PIN_IO_PU_PD(146),
1324	SH73A0_PIN_IO_PU_PD(147),
1325	SH73A0_PIN_IO_PU_PD(148),
1326	SH73A0_PIN_IO_PU_PD(149),
1327	SH73A0_PIN_I_PU_PD(150),
1328	SH73A0_PIN_IO_PU_PD(151),
1329	SH73A0_PIN_IO_PU_PD(152),
1330	SH73A0_PIN_IO_PD(153),
1331	SH73A0_PIN_IO_PD(154),
1332	SH73A0_PIN_I_PU_PD(155),
1333	SH73A0_PIN_IO_PU_PD(156),
1334	SH73A0_PIN_I_PD(157),
1335	SH73A0_PIN_IO_PD(158),
1336	SH73A0_PIN_IO_PU_PD(159),
1337	SH73A0_PIN_IO_PU_PD(160),
1338	SH73A0_PIN_I_PU_PD(161),
1339	SH73A0_PIN_I_PU_PD(162),
1340	SH73A0_PIN_IO_PU_PD(163),
1341	SH73A0_PIN_I_PU_PD(164),
1342	SH73A0_PIN_IO_PD(192),
1343	SH73A0_PIN_IO_PU_PD(193),
1344	SH73A0_PIN_IO_PD(194),
1345	SH73A0_PIN_IO_PU_PD(195),
1346	SH73A0_PIN_IO_PD(196),
1347	SH73A0_PIN_IO_PD(197),
1348	SH73A0_PIN_IO_PD(198),
1349	SH73A0_PIN_IO_PD(199),
1350	SH73A0_PIN_IO_PU_PD(200),
1351	SH73A0_PIN_IO_PU_PD(201),
1352	SH73A0_PIN_IO_PU_PD(202),
1353	SH73A0_PIN_IO_PU_PD(203),
1354	SH73A0_PIN_IO_PU_PD(204),
1355	SH73A0_PIN_IO_PU_PD(205),
1356	SH73A0_PIN_IO_PU_PD(206),
1357	SH73A0_PIN_IO_PD(207),
1358	SH73A0_PIN_IO_PD(208),
1359	SH73A0_PIN_IO_PD(209),
1360	SH73A0_PIN_IO_PD(210),
1361	SH73A0_PIN_IO_PD(211),
1362	SH73A0_PIN_IO_PD(212),
1363	SH73A0_PIN_IO_PD(213),
1364	SH73A0_PIN_IO_PU_PD(214),
1365	SH73A0_PIN_IO_PU_PD(215),
1366	SH73A0_PIN_IO_PD(216),
1367	SH73A0_PIN_IO_PD(217),
1368	SH73A0_PIN_O(218),
1369	SH73A0_PIN_IO_PD(219),
1370	SH73A0_PIN_IO_PD(220),
1371	SH73A0_PIN_IO_PU_PD(221),
1372	SH73A0_PIN_IO_PU_PD(222),
1373	SH73A0_PIN_I_PU_PD(223),
1374	SH73A0_PIN_I_PU_PD(224),
1375	SH73A0_PIN_IO_PU_PD(225),
1376	SH73A0_PIN_O(226),
1377	SH73A0_PIN_IO_PU_PD(227),
1378	SH73A0_PIN_I_PU_PD(228),
1379	SH73A0_PIN_I_PD(229),
1380	SH73A0_PIN_IO(230),
1381	SH73A0_PIN_IO_PU_PD(231),
1382	SH73A0_PIN_IO_PU_PD(232),
1383	SH73A0_PIN_I_PU_PD(233),
1384	SH73A0_PIN_IO_PU_PD(234),
1385	SH73A0_PIN_IO_PU_PD(235),
1386	SH73A0_PIN_IO_PU_PD(236),
1387	SH73A0_PIN_IO_PD(237),
1388	SH73A0_PIN_IO_PU_PD(238),
1389	SH73A0_PIN_IO_PU_PD(239),
1390	SH73A0_PIN_IO_PU_PD(240),
1391	SH73A0_PIN_O(241),
1392	SH73A0_PIN_I_PD(242),
1393	SH73A0_PIN_IO_PU_PD(243),
1394	SH73A0_PIN_IO_PU_PD(244),
1395	SH73A0_PIN_IO_PU_PD(245),
1396	SH73A0_PIN_IO_PU_PD(246),
1397	SH73A0_PIN_IO_PU_PD(247),
1398	SH73A0_PIN_IO_PU_PD(248),
1399	SH73A0_PIN_IO_PU_PD(249),
1400	SH73A0_PIN_IO_PU_PD(250),
1401	SH73A0_PIN_IO_PU_PD(251),
1402	SH73A0_PIN_IO_PU_PD(252),
1403	SH73A0_PIN_IO_PU_PD(253),
1404	SH73A0_PIN_IO_PU_PD(254),
1405	SH73A0_PIN_IO_PU_PD(255),
1406	SH73A0_PIN_IO_PU_PD(256),
1407	SH73A0_PIN_IO_PU_PD(257),
1408	SH73A0_PIN_IO_PU_PD(258),
1409	SH73A0_PIN_IO_PU_PD(259),
1410	SH73A0_PIN_IO_PU_PD(260),
1411	SH73A0_PIN_IO_PU_PD(261),
1412	SH73A0_PIN_IO_PU_PD(262),
1413	SH73A0_PIN_IO_PU_PD(263),
1414	SH73A0_PIN_IO_PU_PD(264),
1415	SH73A0_PIN_IO_PU_PD(265),
1416	SH73A0_PIN_IO_PU_PD(266),
1417	SH73A0_PIN_IO_PU_PD(267),
1418	SH73A0_PIN_IO_PU_PD(268),
1419	SH73A0_PIN_IO_PU_PD(269),
1420	SH73A0_PIN_IO_PU_PD(270),
1421	SH73A0_PIN_IO_PU_PD(271),
1422	SH73A0_PIN_IO_PU_PD(272),
1423	SH73A0_PIN_IO_PU_PD(273),
1424	SH73A0_PIN_IO_PU_PD(274),
1425	SH73A0_PIN_IO_PU_PD(275),
1426	SH73A0_PIN_IO_PU_PD(276),
1427	SH73A0_PIN_IO_PU_PD(277),
1428	SH73A0_PIN_IO_PU_PD(278),
1429	SH73A0_PIN_IO_PU_PD(279),
1430	SH73A0_PIN_IO_PU_PD(280),
1431	SH73A0_PIN_O(281),
1432	SH73A0_PIN_O(282),
1433	SH73A0_PIN_I_PU(288),
1434	SH73A0_PIN_IO_PU_PD(289),
1435	SH73A0_PIN_IO_PU_PD(290),
1436	SH73A0_PIN_IO_PU_PD(291),
1437	SH73A0_PIN_IO_PU_PD(292),
1438	SH73A0_PIN_IO_PU_PD(293),
1439	SH73A0_PIN_IO_PU_PD(294),
1440	SH73A0_PIN_IO_PU_PD(295),
1441	SH73A0_PIN_IO_PU_PD(296),
1442	SH73A0_PIN_IO_PU_PD(297),
1443	SH73A0_PIN_IO_PU_PD(298),
1444	SH73A0_PIN_IO_PU_PD(299),
1445	SH73A0_PIN_IO_PU_PD(300),
1446	SH73A0_PIN_IO_PU_PD(301),
1447	SH73A0_PIN_IO_PU_PD(302),
1448	SH73A0_PIN_IO_PU_PD(303),
1449	SH73A0_PIN_IO_PU_PD(304),
1450	SH73A0_PIN_IO_PU_PD(305),
1451	SH73A0_PIN_O(306),
1452	SH73A0_PIN_O(307),
1453	SH73A0_PIN_I_PU(308),
1454	SH73A0_PIN_O(309),
1455
1456	/* Pins not associated with a GPIO port */
1457	SH_PFC_PIN_NAMED(6, 26, F26),
1458};
1459
1460/* - BSC -------------------------------------------------------------------- */
1461static const unsigned int bsc_data_0_7_pins[] = {
1462	/* D[0:7] */
1463	74, 75, 76, 77, 78, 79, 80, 81,
1464};
1465static const unsigned int bsc_data_0_7_mux[] = {
1466	D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
1467	D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
1468};
1469static const unsigned int bsc_data_8_15_pins[] = {
1470	/* D[8:15] */
1471	82, 83, 84, 85, 86, 87, 88, 89,
1472};
1473static const unsigned int bsc_data_8_15_mux[] = {
1474	D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
1475	D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
1476};
1477static const unsigned int bsc_cs4_pins[] = {
1478	/* CS */
1479	90,
1480};
1481static const unsigned int bsc_cs4_mux[] = {
1482	CS4__MARK,
1483};
1484static const unsigned int bsc_cs5_a_pins[] = {
1485	/* CS */
1486	91,
1487};
1488static const unsigned int bsc_cs5_a_mux[] = {
1489	CS5A__MARK,
1490};
1491static const unsigned int bsc_cs5_b_pins[] = {
1492	/* CS */
1493	92,
1494};
1495static const unsigned int bsc_cs5_b_mux[] = {
1496	CS5B__MARK,
1497};
1498static const unsigned int bsc_cs6_a_pins[] = {
1499	/* CS */
1500	94,
1501};
1502static const unsigned int bsc_cs6_a_mux[] = {
1503	CS6A__MARK,
1504};
1505static const unsigned int bsc_cs6_b_pins[] = {
1506	/* CS */
1507	93,
1508};
1509static const unsigned int bsc_cs6_b_mux[] = {
1510	CS6B__MARK,
1511};
1512static const unsigned int bsc_rd_pins[] = {
1513	/* RD */
1514	96,
1515};
1516static const unsigned int bsc_rd_mux[] = {
1517	RD__FSC_MARK,
1518};
1519static const unsigned int bsc_rdwr_0_pins[] = {
1520	/* RDWR */
1521	91,
1522};
1523static const unsigned int bsc_rdwr_0_mux[] = {
1524	PORT91_RDWR_MARK,
1525};
1526static const unsigned int bsc_rdwr_1_pins[] = {
1527	/* RDWR */
1528	97,
1529};
1530static const unsigned int bsc_rdwr_1_mux[] = {
1531	RDWR_FWE_MARK,
1532};
1533static const unsigned int bsc_rdwr_2_pins[] = {
1534	/* RDWR */
1535	149,
1536};
1537static const unsigned int bsc_rdwr_2_mux[] = {
1538	PORT149_RDWR_MARK,
1539};
1540static const unsigned int bsc_we0_pins[] = {
1541	/* WE0 */
1542	97,
1543};
1544static const unsigned int bsc_we0_mux[] = {
1545	WE0__FWE_MARK,
1546};
1547static const unsigned int bsc_we1_pins[] = {
1548	/* WE1 */
1549	98,
1550};
1551static const unsigned int bsc_we1_mux[] = {
1552	WE1__MARK,
1553};
1554/* - FSIA ------------------------------------------------------------------- */
1555static const unsigned int fsia_mclk_in_pins[] = {
1556	/* CK */
1557	49,
1558};
1559static const unsigned int fsia_mclk_in_mux[] = {
1560	FSIACK_MARK,
1561};
1562static const unsigned int fsia_mclk_out_pins[] = {
1563	/* OMC */
1564	49,
1565};
1566static const unsigned int fsia_mclk_out_mux[] = {
1567	FSIAOMC_MARK,
1568};
1569static const unsigned int fsia_sclk_in_pins[] = {
1570	/* ILR, IBT */
1571	50, 51,
1572};
1573static const unsigned int fsia_sclk_in_mux[] = {
1574	FSIAILR_MARK, FSIAIBT_MARK,
1575};
1576static const unsigned int fsia_sclk_out_pins[] = {
1577	/* OLR, OBT */
1578	50, 51,
1579};
1580static const unsigned int fsia_sclk_out_mux[] = {
1581	FSIAOLR_MARK, FSIAOBT_MARK,
1582};
1583static const unsigned int fsia_data_in_pins[] = {
1584	/* ISLD */
1585	55,
1586};
1587static const unsigned int fsia_data_in_mux[] = {
1588	FSIAISLD_MARK,
1589};
1590static const unsigned int fsia_data_out_pins[] = {
1591	/* OSLD */
1592	52,
1593};
1594static const unsigned int fsia_data_out_mux[] = {
1595	FSIAOSLD_MARK,
1596};
1597static const unsigned int fsia_spdif_pins[] = {
1598	/* SPDIF */
1599	53,
1600};
1601static const unsigned int fsia_spdif_mux[] = {
1602	FSIASPDIF_MARK,
1603};
1604/* - FSIB ------------------------------------------------------------------- */
1605static const unsigned int fsib_mclk_in_pins[] = {
1606	/* CK */
1607	54,
1608};
1609static const unsigned int fsib_mclk_in_mux[] = {
1610	FSIBCK_MARK,
1611};
1612static const unsigned int fsib_mclk_out_pins[] = {
1613	/* OMC */
1614	54,
1615};
1616static const unsigned int fsib_mclk_out_mux[] = {
1617	FSIBOMC_MARK,
1618};
1619static const unsigned int fsib_sclk_in_pins[] = {
1620	/* ILR, IBT */
1621	37, 36,
1622};
1623static const unsigned int fsib_sclk_in_mux[] = {
1624	FSIBILR_MARK, FSIBIBT_MARK,
1625};
1626static const unsigned int fsib_sclk_out_pins[] = {
1627	/* OLR, OBT */
1628	37, 36,
1629};
1630static const unsigned int fsib_sclk_out_mux[] = {
1631	FSIBOLR_MARK, FSIBOBT_MARK,
1632};
1633static const unsigned int fsib_data_in_pins[] = {
1634	/* ISLD */
1635	39,
1636};
1637static const unsigned int fsib_data_in_mux[] = {
1638	FSIBISLD_MARK,
1639};
1640static const unsigned int fsib_data_out_pins[] = {
1641	/* OSLD */
1642	38,
1643};
1644static const unsigned int fsib_data_out_mux[] = {
1645	FSIBOSLD_MARK,
1646};
1647static const unsigned int fsib_spdif_pins[] = {
1648	/* SPDIF */
1649	53,
1650};
1651static const unsigned int fsib_spdif_mux[] = {
1652	FSIBSPDIF_MARK,
1653};
1654/* - FSIC ------------------------------------------------------------------- */
1655static const unsigned int fsic_mclk_in_pins[] = {
1656	/* CK */
1657	54,
1658};
1659static const unsigned int fsic_mclk_in_mux[] = {
1660	FSICCK_MARK,
1661};
1662static const unsigned int fsic_mclk_out_pins[] = {
1663	/* OMC */
1664	54,
1665};
1666static const unsigned int fsic_mclk_out_mux[] = {
1667	FSICOMC_MARK,
1668};
1669static const unsigned int fsic_sclk_in_pins[] = {
1670	/* ILR, IBT */
1671	46, 45,
1672};
1673static const unsigned int fsic_sclk_in_mux[] = {
1674	FSICILR_MARK, FSICIBT_MARK,
1675};
1676static const unsigned int fsic_sclk_out_pins[] = {
1677	/* OLR, OBT */
1678	46, 45,
1679};
1680static const unsigned int fsic_sclk_out_mux[] = {
1681	FSICOLR_MARK, FSICOBT_MARK,
1682};
1683static const unsigned int fsic_data_in_pins[] = {
1684	/* ISLD */
1685	48,
1686};
1687static const unsigned int fsic_data_in_mux[] = {
1688	FSICISLD_MARK,
1689};
1690static const unsigned int fsic_data_out_pins[] = {
1691	/* OSLD, OSLDT1, OSLDT2, OSLDT3 */
1692	47, 44, 42, 16,
1693};
1694static const unsigned int fsic_data_out_mux[] = {
1695	FSICOSLD_MARK, FSICOSLDT1_MARK, FSICOSLDT2_MARK, FSICOSLDT3_MARK,
1696};
1697static const unsigned int fsic_spdif_0_pins[] = {
1698	/* SPDIF */
1699	53,
1700};
1701static const unsigned int fsic_spdif_0_mux[] = {
1702	PORT53_FSICSPDIF_MARK,
1703};
1704static const unsigned int fsic_spdif_1_pins[] = {
1705	/* SPDIF */
1706	47,
1707};
1708static const unsigned int fsic_spdif_1_mux[] = {
1709	PORT47_FSICSPDIF_MARK,
1710};
1711/* - FSID ------------------------------------------------------------------- */
1712static const unsigned int fsid_sclk_in_pins[] = {
1713	/* ILR, IBT */
1714	46, 45,
1715};
1716static const unsigned int fsid_sclk_in_mux[] = {
1717	FSIDILR_MARK, FSIDIBT_MARK,
1718};
1719static const unsigned int fsid_sclk_out_pins[] = {
1720	/* OLR, OBT */
1721	46, 45,
1722};
1723static const unsigned int fsid_sclk_out_mux[] = {
1724	FSIDOLR_MARK, FSIDOBT_MARK,
1725};
1726static const unsigned int fsid_data_in_pins[] = {
1727	/* ISLD */
1728	48,
1729};
1730static const unsigned int fsid_data_in_mux[] = {
1731	FSIDISLD_MARK,
1732};
1733/* - I2C2 ------------------------------------------------------------------- */
1734static const unsigned int i2c2_0_pins[] = {
1735	/* SCL, SDA */
1736	237, 236,
1737};
1738static const unsigned int i2c2_0_mux[] = {
1739	PORT237_I2C_SCL2_MARK, PORT236_I2C_SDA2_MARK,
1740};
1741static const unsigned int i2c2_1_pins[] = {
1742	/* SCL, SDA */
1743	27, 28,
1744};
1745static const unsigned int i2c2_1_mux[] = {
1746	PORT27_I2C_SCL2_MARK, PORT28_I2C_SDA2_MARK,
1747};
1748static const unsigned int i2c2_2_pins[] = {
1749	/* SCL, SDA */
1750	115, 116,
1751};
1752static const unsigned int i2c2_2_mux[] = {
1753	PORT115_I2C_SCL2_MARK, PORT116_I2C_SDA2_MARK,
1754};
1755/* - I2C3 ------------------------------------------------------------------- */
1756static const unsigned int i2c3_0_pins[] = {
1757	/* SCL, SDA */
1758	248, 249,
1759};
1760static const unsigned int i2c3_0_mux[] = {
1761	PORT248_I2C_SCL3_MARK, PORT249_I2C_SDA3_MARK,
1762};
1763static const unsigned int i2c3_1_pins[] = {
1764	/* SCL, SDA */
1765	27, 28,
1766};
1767static const unsigned int i2c3_1_mux[] = {
1768	PORT27_I2C_SCL3_MARK, PORT28_I2C_SDA3_MARK,
1769};
1770static const unsigned int i2c3_2_pins[] = {
1771	/* SCL, SDA */
1772	115, 116,
1773};
1774static const unsigned int i2c3_2_mux[] = {
1775	PORT115_I2C_SCL3_MARK, PORT116_I2C_SDA3_MARK,
1776};
1777/* - IrDA ------------------------------------------------------------------- */
1778static const unsigned int irda_0_pins[] = {
1779	/* OUT, IN, FIRSEL */
1780	241, 242, 243,
1781};
1782static const unsigned int irda_0_mux[] = {
1783	PORT241_IRDA_OUT_MARK, PORT242_IRDA_IN_MARK, PORT243_IRDA_FIRSEL_MARK,
1784};
1785static const unsigned int irda_1_pins[] = {
1786	/* OUT, IN, FIRSEL */
1787	49, 53, 54,
1788};
1789static const unsigned int irda_1_mux[] = {
1790	PORT49_IRDA_OUT_MARK, PORT53_IRDA_IN_MARK, PORT54_IRDA_FIRSEL_MARK,
1791};
1792/* - KEYSC ------------------------------------------------------------------ */
1793static const unsigned int keysc_in5_pins[] = {
1794	/* KEYIN[0:4] */
1795	66, 67, 68, 69, 70,
1796};
1797static const unsigned int keysc_in5_mux[] = {
1798	KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK,
1799	KEYIN4_MARK,
1800};
1801static const unsigned int keysc_in6_pins[] = {
1802	/* KEYIN[0:5] */
1803	66, 67, 68, 69, 70, 71,
1804};
1805static const unsigned int keysc_in6_mux[] = {
1806	KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK,
1807	KEYIN4_MARK, KEYIN5_MARK,
1808};
1809static const unsigned int keysc_in7_pins[] = {
1810	/* KEYIN[0:6] */
1811	66, 67, 68, 69, 70, 71, 72,
1812};
1813static const unsigned int keysc_in7_mux[] = {
1814	KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK,
1815	KEYIN4_MARK, KEYIN5_MARK, KEYIN6_MARK,
1816};
1817static const unsigned int keysc_in8_pins[] = {
1818	/* KEYIN[0:7] */
1819	66, 67, 68, 69, 70, 71, 72, 73,
1820};
1821static const unsigned int keysc_in8_mux[] = {
1822	KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK,
1823	KEYIN4_MARK, KEYIN5_MARK, KEYIN6_MARK, KEYIN7_MARK,
1824};
1825static const unsigned int keysc_out04_pins[] = {
1826	/* KEYOUT[0:4] */
1827	65, 64, 63, 62, 61,
1828};
1829static const unsigned int keysc_out04_mux[] = {
1830	KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK, KEYOUT4_MARK,
1831};
1832static const unsigned int keysc_out5_pins[] = {
1833	/* KEYOUT5 */
1834	60,
1835};
1836static const unsigned int keysc_out5_mux[] = {
1837	KEYOUT5_MARK,
1838};
1839static const unsigned int keysc_out6_0_pins[] = {
1840	/* KEYOUT6 */
1841	59,
1842};
1843static const unsigned int keysc_out6_0_mux[] = {
1844	PORT59_KEYOUT6_MARK,
1845};
1846static const unsigned int keysc_out6_1_pins[] = {
1847	/* KEYOUT6 */
1848	131,
1849};
1850static const unsigned int keysc_out6_1_mux[] = {
1851	PORT131_KEYOUT6_MARK,
1852};
1853static const unsigned int keysc_out6_2_pins[] = {
1854	/* KEYOUT6 */
1855	143,
1856};
1857static const unsigned int keysc_out6_2_mux[] = {
1858	PORT143_KEYOUT6_MARK,
1859};
1860static const unsigned int keysc_out7_0_pins[] = {
1861	/* KEYOUT7 */
1862	58,
1863};
1864static const unsigned int keysc_out7_0_mux[] = {
1865	PORT58_KEYOUT7_MARK,
1866};
1867static const unsigned int keysc_out7_1_pins[] = {
1868	/* KEYOUT7 */
1869	132,
1870};
1871static const unsigned int keysc_out7_1_mux[] = {
1872	PORT132_KEYOUT7_MARK,
1873};
1874static const unsigned int keysc_out7_2_pins[] = {
1875	/* KEYOUT7 */
1876	144,
1877};
1878static const unsigned int keysc_out7_2_mux[] = {
1879	PORT144_KEYOUT7_MARK,
1880};
1881static const unsigned int keysc_out8_0_pins[] = {
1882	/* KEYOUT8 */
1883	PIN_NUMBER(6, 26),
1884};
1885static const unsigned int keysc_out8_0_mux[] = {
1886	KEYOUT8_MARK,
1887};
1888static const unsigned int keysc_out8_1_pins[] = {
1889	/* KEYOUT8 */
1890	136,
1891};
1892static const unsigned int keysc_out8_1_mux[] = {
1893	PORT136_KEYOUT8_MARK,
1894};
1895static const unsigned int keysc_out8_2_pins[] = {
1896	/* KEYOUT8 */
1897	138,
1898};
1899static const unsigned int keysc_out8_2_mux[] = {
1900	PORT138_KEYOUT8_MARK,
1901};
1902static const unsigned int keysc_out9_0_pins[] = {
1903	/* KEYOUT9 */
1904	137,
1905};
1906static const unsigned int keysc_out9_0_mux[] = {
1907	PORT137_KEYOUT9_MARK,
1908};
1909static const unsigned int keysc_out9_1_pins[] = {
1910	/* KEYOUT9 */
1911	139,
1912};
1913static const unsigned int keysc_out9_1_mux[] = {
1914	PORT139_KEYOUT9_MARK,
1915};
1916static const unsigned int keysc_out9_2_pins[] = {
1917	/* KEYOUT9 */
1918	149,
1919};
1920static const unsigned int keysc_out9_2_mux[] = {
1921	PORT149_KEYOUT9_MARK,
1922};
1923static const unsigned int keysc_out10_0_pins[] = {
1924	/* KEYOUT10 */
1925	132,
1926};
1927static const unsigned int keysc_out10_0_mux[] = {
1928	PORT132_KEYOUT10_MARK,
1929};
1930static const unsigned int keysc_out10_1_pins[] = {
1931	/* KEYOUT10 */
1932	142,
1933};
1934static const unsigned int keysc_out10_1_mux[] = {
1935	PORT142_KEYOUT10_MARK,
1936};
1937static const unsigned int keysc_out11_0_pins[] = {
1938	/* KEYOUT11 */
1939	131,
1940};
1941static const unsigned int keysc_out11_0_mux[] = {
1942	PORT131_KEYOUT11_MARK,
1943};
1944static const unsigned int keysc_out11_1_pins[] = {
1945	/* KEYOUT11 */
1946	143,
1947};
1948static const unsigned int keysc_out11_1_mux[] = {
1949	PORT143_KEYOUT11_MARK,
1950};
1951/* - LCD -------------------------------------------------------------------- */
1952static const unsigned int lcd_data8_pins[] = {
1953	/* D[0:7] */
1954	192, 193, 194, 195, 196, 197, 198, 199,
1955};
1956static const unsigned int lcd_data8_mux[] = {
1957	LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1958	LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1959};
1960static const unsigned int lcd_data9_pins[] = {
1961	/* D[0:8] */
1962	192, 193, 194, 195, 196, 197, 198, 199,
1963	200,
1964};
1965static const unsigned int lcd_data9_mux[] = {
1966	LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1967	LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1968	LCDD8_MARK,
1969};
1970static const unsigned int lcd_data12_pins[] = {
1971	/* D[0:11] */
1972	192, 193, 194, 195, 196, 197, 198, 199,
1973	200, 201, 202, 203,
1974};
1975static const unsigned int lcd_data12_mux[] = {
1976	LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1977	LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1978	LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
1979};
1980static const unsigned int lcd_data16_pins[] = {
1981	/* D[0:15] */
1982	192, 193, 194, 195, 196, 197, 198, 199,
1983	200, 201, 202, 203, 204, 205, 206, 207,
1984};
1985static const unsigned int lcd_data16_mux[] = {
1986	LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1987	LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1988	LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
1989	LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
1990};
1991static const unsigned int lcd_data18_pins[] = {
1992	/* D[0:17] */
1993	192, 193, 194, 195, 196, 197, 198, 199,
1994	200, 201, 202, 203, 204, 205, 206, 207,
1995	208, 209,
1996};
1997static const unsigned int lcd_data18_mux[] = {
1998	LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1999	LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
2000	LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
2001	LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
2002	LCDD16_MARK, LCDD17_MARK,
2003};
2004static const unsigned int lcd_data24_pins[] = {
2005	/* D[0:23] */
2006	192, 193, 194, 195, 196, 197, 198, 199,
2007	200, 201, 202, 203, 204, 205, 206, 207,
2008	208, 209, 210, 211, 212, 213, 214, 215
2009};
2010static const unsigned int lcd_data24_mux[] = {
2011	LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
2012	LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
2013	LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
2014	LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
2015	LCDD16_MARK, LCDD17_MARK, LCDD18_MARK, LCDD19_MARK,
2016	LCDD20_MARK, LCDD21_MARK, LCDD22_MARK, LCDD23_MARK,
2017};
2018static const unsigned int lcd_display_pins[] = {
2019	/* DON */
2020	222,
2021};
2022static const unsigned int lcd_display_mux[] = {
2023	LCDDON_MARK,
2024};
2025static const unsigned int lcd_lclk_pins[] = {
2026	/* LCLK */
2027	221,
2028};
2029static const unsigned int lcd_lclk_mux[] = {
2030	LCDLCLK_MARK,
2031};
2032static const unsigned int lcd_sync_pins[] = {
2033	/* VSYN, HSYN, DCK, DISP */
2034	220, 218, 216, 219,
2035};
2036static const unsigned int lcd_sync_mux[] = {
2037	LCDVSYN_MARK, LCDHSYN_MARK, LCDDCK_MARK, LCDDISP_MARK,
2038};
2039static const unsigned int lcd_sys_pins[] = {
2040	/* CS, WR, RD, RS */
2041	218, 216, 217, 219,
2042};
2043static const unsigned int lcd_sys_mux[] = {
2044	LCDCS__MARK, LCDWR__MARK, LCDRD__MARK, LCDRS_MARK,
2045};
2046/* - LCD2 ------------------------------------------------------------------- */
2047static const unsigned int lcd2_data8_pins[] = {
2048	/* D[0:7] */
2049	128, 129, 142, 143, 144, 145, 138, 139,
2050};
2051static const unsigned int lcd2_data8_mux[] = {
2052	LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
2053	LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
2054};
2055static const unsigned int lcd2_data9_pins[] = {
2056	/* D[0:8] */
2057	128, 129, 142, 143, 144, 145, 138, 139,
2058	140,
2059};
2060static const unsigned int lcd2_data9_mux[] = {
2061	LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
2062	LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
2063	LCD2D8_MARK,
2064};
2065static const unsigned int lcd2_data12_pins[] = {
2066	/* D[0:12] */
2067	128, 129, 142, 143, 144, 145, 138, 139,
2068	140, 141, 130, 131,
2069};
2070static const unsigned int lcd2_data12_mux[] = {
2071	LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
2072	LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
2073	LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK,
2074};
2075static const unsigned int lcd2_data16_pins[] = {
2076	/* D[0:15] */
2077	128, 129, 142, 143, 144, 145, 138, 139,
2078	140, 141, 130, 131, 132, 133, 134, 135,
2079};
2080static const unsigned int lcd2_data16_mux[] = {
2081	LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
2082	LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
2083	LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK,
2084	LCD2D12_MARK, LCD2D13_MARK, LCD2D14_MARK, LCD2D15_MARK,
2085};
2086static const unsigned int lcd2_data18_pins[] = {
2087	/* D[0:17] */
2088	128, 129, 142, 143, 144, 145, 138, 139,
2089	140, 141, 130, 131, 132, 133, 134, 135,
2090	136, 137,
2091};
2092static const unsigned int lcd2_data18_mux[] = {
2093	LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
2094	LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
2095	LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK,
2096	LCD2D12_MARK, LCD2D13_MARK, LCD2D14_MARK, LCD2D15_MARK,
2097	LCD2D16_MARK, LCD2D17_MARK,
2098};
2099static const unsigned int lcd2_data24_pins[] = {
2100	/* D[0:23] */
2101	128, 129, 142, 143, 144, 145, 138, 139,
2102	140, 141, 130, 131, 132, 133, 134, 135,
2103	136, 137, 146, 147, 234, 235, 238, 239
2104};
2105static const unsigned int lcd2_data24_mux[] = {
2106	LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
2107	LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
2108	LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK,
2109	LCD2D12_MARK, LCD2D13_MARK, LCD2D14_MARK, LCD2D15_MARK,
2110	LCD2D16_MARK, LCD2D17_MARK, LCD2D18_MARK, LCD2D19_MARK,
2111	LCD2D20_MARK, LCD2D21_MARK, LCD2D22_MARK, LCD2D23_MARK,
2112};
2113static const unsigned int lcd2_sync_0_pins[] = {
2114	/* VSYN, HSYN, DCK, DISP */
2115	128, 129, 146, 145,
2116};
2117static const unsigned int lcd2_sync_0_mux[] = {
2118	PORT128_LCD2VSYN_MARK, PORT129_LCD2HSYN_MARK,
2119	LCD2DCK_MARK, PORT145_LCD2DISP_MARK,
2120};
2121static const unsigned int lcd2_sync_1_pins[] = {
2122	/* VSYN, HSYN, DCK, DISP */
2123	222, 221, 219, 217,
2124};
2125static const unsigned int lcd2_sync_1_mux[] = {
2126	PORT222_LCD2VSYN_MARK, PORT221_LCD2HSYN_MARK,
2127	LCD2DCK_2_MARK, PORT217_LCD2DISP_MARK,
2128};
2129static const unsigned int lcd2_sys_0_pins[] = {
2130	/* CS, WR, RD, RS */
2131	129, 146, 147, 145,
2132};
2133static const unsigned int lcd2_sys_0_mux[] = {
2134	PORT129_LCD2CS__MARK, PORT146_LCD2WR__MARK,
2135	LCD2RD__MARK, PORT145_LCD2RS_MARK,
2136};
2137static const unsigned int lcd2_sys_1_pins[] = {
2138	/* CS, WR, RD, RS */
2139	221, 219, 147, 217,
2140};
2141static const unsigned int lcd2_sys_1_mux[] = {
2142	PORT221_LCD2CS__MARK, PORT219_LCD2WR__MARK,
2143	LCD2RD__MARK, PORT217_LCD2RS_MARK,
2144};
2145/* - MMCIF ------------------------------------------------------------------ */
2146static const unsigned int mmc0_data1_0_pins[] = {
2147	/* D[0] */
2148	271,
2149};
2150static const unsigned int mmc0_data1_0_mux[] = {
2151	MMCD0_0_MARK,
2152};
2153static const unsigned int mmc0_data4_0_pins[] = {
2154	/* D[0:3] */
2155	271, 272, 273, 274,
2156};
2157static const unsigned int mmc0_data4_0_mux[] = {
2158	MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
2159};
2160static const unsigned int mmc0_data8_0_pins[] = {
2161	/* D[0:7] */
2162	271, 272, 273, 274, 275, 276, 277, 278,
2163};
2164static const unsigned int mmc0_data8_0_mux[] = {
2165	MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
2166	MMCD0_4_MARK, MMCD0_5_MARK, MMCD0_6_MARK, MMCD0_7_MARK,
2167};
2168static const unsigned int mmc0_ctrl_0_pins[] = {
2169	/* CMD, CLK */
2170	279, 270,
2171};
2172static const unsigned int mmc0_ctrl_0_mux[] = {
2173	MMCCMD0_MARK, MMCCLK0_MARK,
2174};
2175
2176static const unsigned int mmc0_data1_1_pins[] = {
2177	/* D[0] */
2178	305,
2179};
2180static const unsigned int mmc0_data1_1_mux[] = {
2181	MMCD1_0_MARK,
2182};
2183static const unsigned int mmc0_data4_1_pins[] = {
2184	/* D[0:3] */
2185	305, 304, 303, 302,
2186};
2187static const unsigned int mmc0_data4_1_mux[] = {
2188	MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
2189};
2190static const unsigned int mmc0_data8_1_pins[] = {
2191	/* D[0:7] */
2192	305, 304, 303, 302, 301, 300, 299, 298,
2193};
2194static const unsigned int mmc0_data8_1_mux[] = {
2195	MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
2196	MMCD1_4_MARK, MMCD1_5_MARK, MMCD1_6_MARK, MMCD1_7_MARK,
2197};
2198static const unsigned int mmc0_ctrl_1_pins[] = {
2199	/* CMD, CLK */
2200	297, 289,
2201};
2202static const unsigned int mmc0_ctrl_1_mux[] = {
2203	MMCCMD1_MARK, MMCCLK1_MARK,
2204};
2205/* - SCIFA0 ----------------------------------------------------------------- */
2206static const unsigned int scifa0_data_pins[] = {
2207	/* RXD, TXD */
2208	43, 17,
2209};
2210static const unsigned int scifa0_data_mux[] = {
2211	SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
2212};
2213static const unsigned int scifa0_clk_pins[] = {
2214	/* SCK */
2215	16,
2216};
2217static const unsigned int scifa0_clk_mux[] = {
2218	SCIFA0_SCK_MARK,
2219};
2220static const unsigned int scifa0_ctrl_pins[] = {
2221	/* RTS, CTS */
2222	42, 44,
2223};
2224static const unsigned int scifa0_ctrl_mux[] = {
2225	SCIFA0_RTS__MARK, SCIFA0_CTS__MARK,
2226};
2227/* - SCIFA1 ----------------------------------------------------------------- */
2228static const unsigned int scifa1_data_pins[] = {
2229	/* RXD, TXD */
2230	228, 225,
2231};
2232static const unsigned int scifa1_data_mux[] = {
2233	SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
2234};
2235static const unsigned int scifa1_clk_pins[] = {
2236	/* SCK */
2237	226,
2238};
2239static const unsigned int scifa1_clk_mux[] = {
2240	SCIFA1_SCK_MARK,
2241};
2242static const unsigned int scifa1_ctrl_pins[] = {
2243	/* RTS, CTS */
2244	227, 229,
2245};
2246static const unsigned int scifa1_ctrl_mux[] = {
2247	SCIFA1_RTS__MARK, SCIFA1_CTS__MARK,
2248};
2249/* - SCIFA2 ----------------------------------------------------------------- */
2250static const unsigned int scifa2_data_0_pins[] = {
2251	/* RXD, TXD */
2252	155, 154,
2253};
2254static const unsigned int scifa2_data_0_mux[] = {
2255	SCIFA2_RXD1_MARK, SCIFA2_TXD1_MARK,
2256};
2257static const unsigned int scifa2_clk_0_pins[] = {
2258	/* SCK */
2259	158,
2260};
2261static const unsigned int scifa2_clk_0_mux[] = {
2262	SCIFA2_SCK1_MARK,
2263};
2264static const unsigned int scifa2_ctrl_0_pins[] = {
2265	/* RTS, CTS */
2266	156, 157,
2267};
2268static const unsigned int scifa2_ctrl_0_mux[] = {
2269	SCIFA2_RTS1__MARK, SCIFA2_CTS1__MARK,
2270};
2271static const unsigned int scifa2_data_1_pins[] = {
2272	/* RXD, TXD */
2273	233, 230,
2274};
2275static const unsigned int scifa2_data_1_mux[] = {
2276	SCIFA2_RXD2_MARK, SCIFA2_TXD2_MARK,
2277};
2278static const unsigned int scifa2_clk_1_pins[] = {
2279	/* SCK */
2280	232,
2281};
2282static const unsigned int scifa2_clk_1_mux[] = {
2283	SCIFA2_SCK2_MARK,
2284};
2285static const unsigned int scifa2_ctrl_1_pins[] = {
2286	/* RTS, CTS */
2287	234, 231,
2288};
2289static const unsigned int scifa2_ctrl_1_mux[] = {
2290	SCIFA2_RTS2__MARK, SCIFA2_CTS2__MARK,
2291};
2292/* - SCIFA3 ----------------------------------------------------------------- */
2293static const unsigned int scifa3_data_pins[] = {
2294	/* RXD, TXD */
2295	108, 110,
2296};
2297static const unsigned int scifa3_data_mux[] = {
2298	SCIFA3_RXD_MARK, SCIFA3_TXD_MARK,
2299};
2300static const unsigned int scifa3_ctrl_pins[] = {
2301	/* RTS, CTS */
2302	109, 107,
2303};
2304static const unsigned int scifa3_ctrl_mux[] = {
2305	SCIFA3_RTS__MARK, SCIFA3_CTS__MARK,
2306};
2307/* - SCIFA4 ----------------------------------------------------------------- */
2308static const unsigned int scifa4_data_pins[] = {
2309	/* RXD, TXD */
2310	33, 32,
2311};
2312static const unsigned int scifa4_data_mux[] = {
2313	SCIFA4_RXD_MARK, SCIFA4_TXD_MARK,
2314};
2315static const unsigned int scifa4_ctrl_pins[] = {
2316	/* RTS, CTS */
2317	34, 35,
2318};
2319static const unsigned int scifa4_ctrl_mux[] = {
2320	SCIFA4_RTS__MARK, SCIFA4_CTS__MARK,
2321};
2322/* - SCIFA5 ----------------------------------------------------------------- */
2323static const unsigned int scifa5_data_0_pins[] = {
2324	/* RXD, TXD */
2325	246, 247,
2326};
2327static const unsigned int scifa5_data_0_mux[] = {
2328	PORT246_SCIFA5_RXD_MARK, PORT247_SCIFA5_TXD_MARK,
2329};
2330static const unsigned int scifa5_clk_0_pins[] = {
2331	/* SCK */
2332	248,
2333};
2334static const unsigned int scifa5_clk_0_mux[] = {
2335	PORT248_SCIFA5_SCK_MARK,
2336};
2337static const unsigned int scifa5_ctrl_0_pins[] = {
2338	/* RTS, CTS */
2339	245, 244,
2340};
2341static const unsigned int scifa5_ctrl_0_mux[] = {
2342	PORT245_SCIFA5_RTS__MARK, PORT244_SCIFA5_CTS__MARK,
2343};
2344static const unsigned int scifa5_data_1_pins[] = {
2345	/* RXD, TXD */
2346	195, 196,
2347};
2348static const unsigned int scifa5_data_1_mux[] = {
2349	PORT195_SCIFA5_RXD_MARK, PORT196_SCIFA5_TXD_MARK,
2350};
2351static const unsigned int scifa5_clk_1_pins[] = {
2352	/* SCK */
2353	197,
2354};
2355static const unsigned int scifa5_clk_1_mux[] = {
2356	PORT197_SCIFA5_SCK_MARK,
2357};
2358static const unsigned int scifa5_ctrl_1_pins[] = {
2359	/* RTS, CTS */
2360	194, 193,
2361};
2362static const unsigned int scifa5_ctrl_1_mux[] = {
2363	PORT194_SCIFA5_RTS__MARK, PORT193_SCIFA5_CTS__MARK,
2364};
2365static const unsigned int scifa5_data_2_pins[] = {
2366	/* RXD, TXD */
2367	162, 160,
2368};
2369static const unsigned int scifa5_data_2_mux[] = {
2370	PORT162_SCIFA5_RXD_MARK, PORT160_SCIFA5_TXD_MARK,
2371};
2372static const unsigned int scifa5_clk_2_pins[] = {
2373	/* SCK */
2374	159,
2375};
2376static const unsigned int scifa5_clk_2_mux[] = {
2377	PORT159_SCIFA5_SCK_MARK,
2378};
2379static const unsigned int scifa5_ctrl_2_pins[] = {
2380	/* RTS, CTS */
2381	163, 161,
2382};
2383static const unsigned int scifa5_ctrl_2_mux[] = {
2384	PORT163_SCIFA5_RTS__MARK, PORT161_SCIFA5_CTS__MARK,
2385};
2386/* - SCIFA6 ----------------------------------------------------------------- */
2387static const unsigned int scifa6_pins[] = {
2388	/* TXD */
2389	240,
2390};
2391static const unsigned int scifa6_mux[] = {
2392	SCIFA6_TXD_MARK,
2393};
2394/* - SCIFA7 ----------------------------------------------------------------- */
2395static const unsigned int scifa7_data_pins[] = {
2396	/* RXD, TXD */
2397	12, 18,
2398};
2399static const unsigned int scifa7_data_mux[] = {
2400	SCIFA7_RXD_MARK, SCIFA7_TXD_MARK,
2401};
2402static const unsigned int scifa7_ctrl_pins[] = {
2403	/* RTS, CTS */
2404	19, 13,
2405};
2406static const unsigned int scifa7_ctrl_mux[] = {
2407	SCIFA7_RTS__MARK, SCIFA7_CTS__MARK,
2408};
2409/* - SCIFB ------------------------------------------------------------------ */
2410static const unsigned int scifb_data_0_pins[] = {
2411	/* RXD, TXD */
2412	162, 160,
2413};
2414static const unsigned int scifb_data_0_mux[] = {
2415	PORT162_SCIFB_RXD_MARK, PORT160_SCIFB_TXD_MARK,
2416};
2417static const unsigned int scifb_clk_0_pins[] = {
2418	/* SCK */
2419	159,
2420};
2421static const unsigned int scifb_clk_0_mux[] = {
2422	PORT159_SCIFB_SCK_MARK,
2423};
2424static const unsigned int scifb_ctrl_0_pins[] = {
2425	/* RTS, CTS */
2426	163, 161,
2427};
2428static const unsigned int scifb_ctrl_0_mux[] = {
2429	PORT163_SCIFB_RTS__MARK, PORT161_SCIFB_CTS__MARK,
2430};
2431static const unsigned int scifb_data_1_pins[] = {
2432	/* RXD, TXD */
2433	246, 247,
2434};
2435static const unsigned int scifb_data_1_mux[] = {
2436	PORT246_SCIFB_RXD_MARK, PORT247_SCIFB_TXD_MARK,
2437};
2438static const unsigned int scifb_clk_1_pins[] = {
2439	/* SCK */
2440	248,
2441};
2442static const unsigned int scifb_clk_1_mux[] = {
2443	PORT248_SCIFB_SCK_MARK,
2444};
2445static const unsigned int scifb_ctrl_1_pins[] = {
2446	/* RTS, CTS */
2447	245, 244,
2448};
2449static const unsigned int scifb_ctrl_1_mux[] = {
2450	PORT245_SCIFB_RTS__MARK, PORT244_SCIFB_CTS__MARK,
2451};
2452/* - SDHI0 ------------------------------------------------------------------ */
2453static const unsigned int sdhi0_data1_pins[] = {
2454	/* D0 */
2455	252,
2456};
2457static const unsigned int sdhi0_data1_mux[] = {
2458	SDHID0_0_MARK,
2459};
2460static const unsigned int sdhi0_data4_pins[] = {
2461	/* D[0:3] */
2462	252, 253, 254, 255,
2463};
2464static const unsigned int sdhi0_data4_mux[] = {
2465	SDHID0_0_MARK, SDHID0_1_MARK, SDHID0_2_MARK, SDHID0_3_MARK,
2466};
2467static const unsigned int sdhi0_ctrl_pins[] = {
2468	/* CMD, CLK */
2469	256, 250,
2470};
2471static const unsigned int sdhi0_ctrl_mux[] = {
2472	SDHICMD0_MARK, SDHICLK0_MARK,
2473};
2474static const unsigned int sdhi0_cd_pins[] = {
2475	/* CD */
2476	251,
2477};
2478static const unsigned int sdhi0_cd_mux[] = {
2479	SDHICD0_MARK,
2480};
2481static const unsigned int sdhi0_wp_pins[] = {
2482	/* WP */
2483	257,
2484};
2485static const unsigned int sdhi0_wp_mux[] = {
2486	SDHIWP0_MARK,
2487};
2488/* - SDHI1 ------------------------------------------------------------------ */
2489static const unsigned int sdhi1_data1_pins[] = {
2490	/* D0 */
2491	259,
2492};
2493static const unsigned int sdhi1_data1_mux[] = {
2494	SDHID1_0_MARK,
2495};
2496static const unsigned int sdhi1_data4_pins[] = {
2497	/* D[0:3] */
2498	259, 260, 261, 262,
2499};
2500static const unsigned int sdhi1_data4_mux[] = {
2501	SDHID1_0_MARK, SDHID1_1_MARK, SDHID1_2_MARK, SDHID1_3_MARK,
2502};
2503static const unsigned int sdhi1_ctrl_pins[] = {
2504	/* CMD, CLK */
2505	263, 258,
2506};
2507static const unsigned int sdhi1_ctrl_mux[] = {
2508	SDHICMD1_MARK, SDHICLK1_MARK,
2509};
2510/* - SDHI2 ------------------------------------------------------------------ */
2511static const unsigned int sdhi2_data1_pins[] = {
2512	/* D0 */
2513	265,
2514};
2515static const unsigned int sdhi2_data1_mux[] = {
2516	SDHID2_0_MARK,
2517};
2518static const unsigned int sdhi2_data4_pins[] = {
2519	/* D[0:3] */
2520	265, 266, 267, 268,
2521};
2522static const unsigned int sdhi2_data4_mux[] = {
2523	SDHID2_0_MARK, SDHID2_1_MARK, SDHID2_2_MARK, SDHID2_3_MARK,
2524};
2525static const unsigned int sdhi2_ctrl_pins[] = {
2526	/* CMD, CLK */
2527	269, 264,
2528};
2529static const unsigned int sdhi2_ctrl_mux[] = {
2530	SDHICMD2_MARK, SDHICLK2_MARK,
2531};
2532/* - TPU0 ------------------------------------------------------------------- */
2533static const unsigned int tpu0_to0_pins[] = {
2534	/* TO */
2535	55,
2536};
2537static const unsigned int tpu0_to0_mux[] = {
2538	TPU0TO0_MARK,
2539};
2540static const unsigned int tpu0_to1_pins[] = {
2541	/* TO */
2542	59,
2543};
2544static const unsigned int tpu0_to1_mux[] = {
2545	TPU0TO1_MARK,
2546};
2547static const unsigned int tpu0_to2_pins[] = {
2548	/* TO */
2549	140,
2550};
2551static const unsigned int tpu0_to2_mux[] = {
2552	TPU0TO2_MARK,
2553};
2554static const unsigned int tpu0_to3_pins[] = {
2555	/* TO */
2556	141,
2557};
2558static const unsigned int tpu0_to3_mux[] = {
2559	TPU0TO3_MARK,
2560};
2561/* - TPU1 ------------------------------------------------------------------- */
2562static const unsigned int tpu1_to0_pins[] = {
2563	/* TO */
2564	246,
2565};
2566static const unsigned int tpu1_to0_mux[] = {
2567	TPU1TO0_MARK,
2568};
2569static const unsigned int tpu1_to1_0_pins[] = {
2570	/* TO */
2571	28,
2572};
2573static const unsigned int tpu1_to1_0_mux[] = {
2574	PORT28_TPU1TO1_MARK,
2575};
2576static const unsigned int tpu1_to1_1_pins[] = {
2577	/* TO */
2578	29,
2579};
2580static const unsigned int tpu1_to1_1_mux[] = {
2581	PORT29_TPU1TO1_MARK,
2582};
2583static const unsigned int tpu1_to2_pins[] = {
2584	/* TO */
2585	153,
2586};
2587static const unsigned int tpu1_to2_mux[] = {
2588	TPU1TO2_MARK,
2589};
2590static const unsigned int tpu1_to3_pins[] = {
2591	/* TO */
2592	145,
2593};
2594static const unsigned int tpu1_to3_mux[] = {
2595	TPU1TO3_MARK,
2596};
2597/* - TPU2 ------------------------------------------------------------------- */
2598static const unsigned int tpu2_to0_pins[] = {
2599	/* TO */
2600	248,
2601};
2602static const unsigned int tpu2_to0_mux[] = {
2603	TPU2TO0_MARK,
2604};
2605static const unsigned int tpu2_to1_pins[] = {
2606	/* TO */
2607	197,
2608};
2609static const unsigned int tpu2_to1_mux[] = {
2610	TPU2TO1_MARK,
2611};
2612static const unsigned int tpu2_to2_pins[] = {
2613	/* TO */
2614	50,
2615};
2616static const unsigned int tpu2_to2_mux[] = {
2617	TPU2TO2_MARK,
2618};
2619static const unsigned int tpu2_to3_pins[] = {
2620	/* TO */
2621	51,
2622};
2623static const unsigned int tpu2_to3_mux[] = {
2624	TPU2TO3_MARK,
2625};
2626/* - TPU3 ------------------------------------------------------------------- */
2627static const unsigned int tpu3_to0_pins[] = {
2628	/* TO */
2629	163,
2630};
2631static const unsigned int tpu3_to0_mux[] = {
2632	TPU3TO0_MARK,
2633};
2634static const unsigned int tpu3_to1_pins[] = {
2635	/* TO */
2636	247,
2637};
2638static const unsigned int tpu3_to1_mux[] = {
2639	TPU3TO1_MARK,
2640};
2641static const unsigned int tpu3_to2_pins[] = {
2642	/* TO */
2643	54,
2644};
2645static const unsigned int tpu3_to2_mux[] = {
2646	TPU3TO2_MARK,
2647};
2648static const unsigned int tpu3_to3_pins[] = {
2649	/* TO */
2650	53,
2651};
2652static const unsigned int tpu3_to3_mux[] = {
2653	TPU3TO3_MARK,
2654};
2655/* - TPU4 ------------------------------------------------------------------- */
2656static const unsigned int tpu4_to0_pins[] = {
2657	/* TO */
2658	241,
2659};
2660static const unsigned int tpu4_to0_mux[] = {
2661	TPU4TO0_MARK,
2662};
2663static const unsigned int tpu4_to1_pins[] = {
2664	/* TO */
2665	199,
2666};
2667static const unsigned int tpu4_to1_mux[] = {
2668	TPU4TO1_MARK,
2669};
2670static const unsigned int tpu4_to2_pins[] = {
2671	/* TO */
2672	58,
2673};
2674static const unsigned int tpu4_to2_mux[] = {
2675	TPU4TO2_MARK,
2676};
2677static const unsigned int tpu4_to3_pins[] = {
2678	/* TO */
2679};
2680static const unsigned int tpu4_to3_mux[] = {
2681	TPU4TO3_MARK,
2682};
2683/* - USB -------------------------------------------------------------------- */
2684static const unsigned int usb_vbus_pins[] = {
2685	/* VBUS */
2686	0,
2687};
2688static const unsigned int usb_vbus_mux[] = {
2689	VBUS_0_MARK,
2690};
2691
2692static const struct sh_pfc_pin_group pinmux_groups[] = {
2693	SH_PFC_PIN_GROUP(bsc_data_0_7),
2694	SH_PFC_PIN_GROUP(bsc_data_8_15),
2695	SH_PFC_PIN_GROUP(bsc_cs4),
2696	SH_PFC_PIN_GROUP(bsc_cs5_a),
2697	SH_PFC_PIN_GROUP(bsc_cs5_b),
2698	SH_PFC_PIN_GROUP(bsc_cs6_a),
2699	SH_PFC_PIN_GROUP(bsc_cs6_b),
2700	SH_PFC_PIN_GROUP(bsc_rd),
2701	SH_PFC_PIN_GROUP(bsc_rdwr_0),
2702	SH_PFC_PIN_GROUP(bsc_rdwr_1),
2703	SH_PFC_PIN_GROUP(bsc_rdwr_2),
2704	SH_PFC_PIN_GROUP(bsc_we0),
2705	SH_PFC_PIN_GROUP(bsc_we1),
2706	SH_PFC_PIN_GROUP(fsia_mclk_in),
2707	SH_PFC_PIN_GROUP(fsia_mclk_out),
2708	SH_PFC_PIN_GROUP(fsia_sclk_in),
2709	SH_PFC_PIN_GROUP(fsia_sclk_out),
2710	SH_PFC_PIN_GROUP(fsia_data_in),
2711	SH_PFC_PIN_GROUP(fsia_data_out),
2712	SH_PFC_PIN_GROUP(fsia_spdif),
2713	SH_PFC_PIN_GROUP(fsib_mclk_in),
2714	SH_PFC_PIN_GROUP(fsib_mclk_out),
2715	SH_PFC_PIN_GROUP(fsib_sclk_in),
2716	SH_PFC_PIN_GROUP(fsib_sclk_out),
2717	SH_PFC_PIN_GROUP(fsib_data_in),
2718	SH_PFC_PIN_GROUP(fsib_data_out),
2719	SH_PFC_PIN_GROUP(fsib_spdif),
2720	SH_PFC_PIN_GROUP(fsic_mclk_in),
2721	SH_PFC_PIN_GROUP(fsic_mclk_out),
2722	SH_PFC_PIN_GROUP(fsic_sclk_in),
2723	SH_PFC_PIN_GROUP(fsic_sclk_out),
2724	SH_PFC_PIN_GROUP(fsic_data_in),
2725	SH_PFC_PIN_GROUP(fsic_data_out),
2726	SH_PFC_PIN_GROUP(fsic_spdif_0),
2727	SH_PFC_PIN_GROUP(fsic_spdif_1),
2728	SH_PFC_PIN_GROUP(fsid_sclk_in),
2729	SH_PFC_PIN_GROUP(fsid_sclk_out),
2730	SH_PFC_PIN_GROUP(fsid_data_in),
2731	SH_PFC_PIN_GROUP(i2c2_0),
2732	SH_PFC_PIN_GROUP(i2c2_1),
2733	SH_PFC_PIN_GROUP(i2c2_2),
2734	SH_PFC_PIN_GROUP(i2c3_0),
2735	SH_PFC_PIN_GROUP(i2c3_1),
2736	SH_PFC_PIN_GROUP(i2c3_2),
2737	SH_PFC_PIN_GROUP(irda_0),
2738	SH_PFC_PIN_GROUP(irda_1),
2739	SH_PFC_PIN_GROUP(keysc_in5),
2740	SH_PFC_PIN_GROUP(keysc_in6),
2741	SH_PFC_PIN_GROUP(keysc_in7),
2742	SH_PFC_PIN_GROUP(keysc_in8),
2743	SH_PFC_PIN_GROUP(keysc_out04),
2744	SH_PFC_PIN_GROUP(keysc_out5),
2745	SH_PFC_PIN_GROUP(keysc_out6_0),
2746	SH_PFC_PIN_GROUP(keysc_out6_1),
2747	SH_PFC_PIN_GROUP(keysc_out6_2),
2748	SH_PFC_PIN_GROUP(keysc_out7_0),
2749	SH_PFC_PIN_GROUP(keysc_out7_1),
2750	SH_PFC_PIN_GROUP(keysc_out7_2),
2751	SH_PFC_PIN_GROUP(keysc_out8_0),
2752	SH_PFC_PIN_GROUP(keysc_out8_1),
2753	SH_PFC_PIN_GROUP(keysc_out8_2),
2754	SH_PFC_PIN_GROUP(keysc_out9_0),
2755	SH_PFC_PIN_GROUP(keysc_out9_1),
2756	SH_PFC_PIN_GROUP(keysc_out9_2),
2757	SH_PFC_PIN_GROUP(keysc_out10_0),
2758	SH_PFC_PIN_GROUP(keysc_out10_1),
2759	SH_PFC_PIN_GROUP(keysc_out11_0),
2760	SH_PFC_PIN_GROUP(keysc_out11_1),
2761	SH_PFC_PIN_GROUP(lcd_data8),
2762	SH_PFC_PIN_GROUP(lcd_data9),
2763	SH_PFC_PIN_GROUP(lcd_data12),
2764	SH_PFC_PIN_GROUP(lcd_data16),
2765	SH_PFC_PIN_GROUP(lcd_data18),
2766	SH_PFC_PIN_GROUP(lcd_data24),
2767	SH_PFC_PIN_GROUP(lcd_display),
2768	SH_PFC_PIN_GROUP(lcd_lclk),
2769	SH_PFC_PIN_GROUP(lcd_sync),
2770	SH_PFC_PIN_GROUP(lcd_sys),
2771	SH_PFC_PIN_GROUP(lcd2_data8),
2772	SH_PFC_PIN_GROUP(lcd2_data9),
2773	SH_PFC_PIN_GROUP(lcd2_data12),
2774	SH_PFC_PIN_GROUP(lcd2_data16),
2775	SH_PFC_PIN_GROUP(lcd2_data18),
2776	SH_PFC_PIN_GROUP(lcd2_data24),
2777	SH_PFC_PIN_GROUP(lcd2_sync_0),
2778	SH_PFC_PIN_GROUP(lcd2_sync_1),
2779	SH_PFC_PIN_GROUP(lcd2_sys_0),
2780	SH_PFC_PIN_GROUP(lcd2_sys_1),
2781	SH_PFC_PIN_GROUP(mmc0_data1_0),
2782	SH_PFC_PIN_GROUP(mmc0_data4_0),
2783	SH_PFC_PIN_GROUP(mmc0_data8_0),
2784	SH_PFC_PIN_GROUP(mmc0_ctrl_0),
2785	SH_PFC_PIN_GROUP(mmc0_data1_1),
2786	SH_PFC_PIN_GROUP(mmc0_data4_1),
2787	SH_PFC_PIN_GROUP(mmc0_data8_1),
2788	SH_PFC_PIN_GROUP(mmc0_ctrl_1),
2789	SH_PFC_PIN_GROUP(scifa0_data),
2790	SH_PFC_PIN_GROUP(scifa0_clk),
2791	SH_PFC_PIN_GROUP(scifa0_ctrl),
2792	SH_PFC_PIN_GROUP(scifa1_data),
2793	SH_PFC_PIN_GROUP(scifa1_clk),
2794	SH_PFC_PIN_GROUP(scifa1_ctrl),
2795	SH_PFC_PIN_GROUP(scifa2_data_0),
2796	SH_PFC_PIN_GROUP(scifa2_clk_0),
2797	SH_PFC_PIN_GROUP(scifa2_ctrl_0),
2798	SH_PFC_PIN_GROUP(scifa2_data_1),
2799	SH_PFC_PIN_GROUP(scifa2_clk_1),
2800	SH_PFC_PIN_GROUP(scifa2_ctrl_1),
2801	SH_PFC_PIN_GROUP(scifa3_data),
2802	SH_PFC_PIN_GROUP(scifa3_ctrl),
2803	SH_PFC_PIN_GROUP(scifa4_data),
2804	SH_PFC_PIN_GROUP(scifa4_ctrl),
2805	SH_PFC_PIN_GROUP(scifa5_data_0),
2806	SH_PFC_PIN_GROUP(scifa5_clk_0),
2807	SH_PFC_PIN_GROUP(scifa5_ctrl_0),
2808	SH_PFC_PIN_GROUP(scifa5_data_1),
2809	SH_PFC_PIN_GROUP(scifa5_clk_1),
2810	SH_PFC_PIN_GROUP(scifa5_ctrl_1),
2811	SH_PFC_PIN_GROUP(scifa5_data_2),
2812	SH_PFC_PIN_GROUP(scifa5_clk_2),
2813	SH_PFC_PIN_GROUP(scifa5_ctrl_2),
2814	SH_PFC_PIN_GROUP(scifa6),
2815	SH_PFC_PIN_GROUP(scifa7_data),
2816	SH_PFC_PIN_GROUP(scifa7_ctrl),
2817	SH_PFC_PIN_GROUP(scifb_data_0),
2818	SH_PFC_PIN_GROUP(scifb_clk_0),
2819	SH_PFC_PIN_GROUP(scifb_ctrl_0),
2820	SH_PFC_PIN_GROUP(scifb_data_1),
2821	SH_PFC_PIN_GROUP(scifb_clk_1),
2822	SH_PFC_PIN_GROUP(scifb_ctrl_1),
2823	SH_PFC_PIN_GROUP(sdhi0_data1),
2824	SH_PFC_PIN_GROUP(sdhi0_data4),
2825	SH_PFC_PIN_GROUP(sdhi0_ctrl),
2826	SH_PFC_PIN_GROUP(sdhi0_cd),
2827	SH_PFC_PIN_GROUP(sdhi0_wp),
2828	SH_PFC_PIN_GROUP(sdhi1_data1),
2829	SH_PFC_PIN_GROUP(sdhi1_data4),
2830	SH_PFC_PIN_GROUP(sdhi1_ctrl),
2831	SH_PFC_PIN_GROUP(sdhi2_data1),
2832	SH_PFC_PIN_GROUP(sdhi2_data4),
2833	SH_PFC_PIN_GROUP(sdhi2_ctrl),
2834	SH_PFC_PIN_GROUP(tpu0_to0),
2835	SH_PFC_PIN_GROUP(tpu0_to1),
2836	SH_PFC_PIN_GROUP(tpu0_to2),
2837	SH_PFC_PIN_GROUP(tpu0_to3),
2838	SH_PFC_PIN_GROUP(tpu1_to0),
2839	SH_PFC_PIN_GROUP(tpu1_to1_0),
2840	SH_PFC_PIN_GROUP(tpu1_to1_1),
2841	SH_PFC_PIN_GROUP(tpu1_to2),
2842	SH_PFC_PIN_GROUP(tpu1_to3),
2843	SH_PFC_PIN_GROUP(tpu2_to0),
2844	SH_PFC_PIN_GROUP(tpu2_to1),
2845	SH_PFC_PIN_GROUP(tpu2_to2),
2846	SH_PFC_PIN_GROUP(tpu2_to3),
2847	SH_PFC_PIN_GROUP(tpu3_to0),
2848	SH_PFC_PIN_GROUP(tpu3_to1),
2849	SH_PFC_PIN_GROUP(tpu3_to2),
2850	SH_PFC_PIN_GROUP(tpu3_to3),
2851	SH_PFC_PIN_GROUP(tpu4_to0),
2852	SH_PFC_PIN_GROUP(tpu4_to1),
2853	SH_PFC_PIN_GROUP(tpu4_to2),
2854	SH_PFC_PIN_GROUP(tpu4_to3),
2855	SH_PFC_PIN_GROUP(usb_vbus),
2856};
2857
2858static const char * const bsc_groups[] = {
2859	"bsc_data_0_7",
2860	"bsc_data_8_15",
2861	"bsc_cs4",
2862	"bsc_cs5_a",
2863	"bsc_cs5_b",
2864	"bsc_cs6_a",
2865	"bsc_cs6_b",
2866	"bsc_rd",
2867	"bsc_rdwr_0",
2868	"bsc_rdwr_1",
2869	"bsc_rdwr_2",
2870	"bsc_we0",
2871	"bsc_we1",
2872};
2873
2874static const char * const fsia_groups[] = {
2875	"fsia_mclk_in",
2876	"fsia_mclk_out",
2877	"fsia_sclk_in",
2878	"fsia_sclk_out",
2879	"fsia_data_in",
2880	"fsia_data_out",
2881	"fsia_spdif",
2882};
2883
2884static const char * const fsib_groups[] = {
2885	"fsib_mclk_in",
2886	"fsib_mclk_out",
2887	"fsib_sclk_in",
2888	"fsib_sclk_out",
2889	"fsib_data_in",
2890	"fsib_data_out",
2891	"fsib_spdif",
2892};
2893
2894static const char * const fsic_groups[] = {
2895	"fsic_mclk_in",
2896	"fsic_mclk_out",
2897	"fsic_sclk_in",
2898	"fsic_sclk_out",
2899	"fsic_data_in",
2900	"fsic_data_out",
2901	"fsic_spdif",
2902};
2903
2904static const char * const fsid_groups[] = {
2905	"fsid_sclk_in",
2906	"fsid_sclk_out",
2907	"fsid_data_in",
2908};
2909
2910static const char * const i2c2_groups[] = {
2911	"i2c2_0",
2912	"i2c2_1",
2913	"i2c2_2",
2914};
2915
2916static const char * const i2c3_groups[] = {
2917	"i2c3_0",
2918	"i2c3_1",
2919	"i2c3_2",
2920};
2921
2922static const char * const irda_groups[] = {
2923	"irda_0",
2924	"irda_1",
2925};
2926
2927static const char * const keysc_groups[] = {
2928	"keysc_in5",
2929	"keysc_in6",
2930	"keysc_in7",
2931	"keysc_in8",
2932	"keysc_out04",
2933	"keysc_out5",
2934	"keysc_out6_0",
2935	"keysc_out6_1",
2936	"keysc_out6_2",
2937	"keysc_out7_0",
2938	"keysc_out7_1",
2939	"keysc_out7_2",
2940	"keysc_out8_0",
2941	"keysc_out8_1",
2942	"keysc_out8_2",
2943	"keysc_out9_0",
2944	"keysc_out9_1",
2945	"keysc_out9_2",
2946	"keysc_out10_0",
2947	"keysc_out10_1",
2948	"keysc_out11_0",
2949	"keysc_out11_1",
2950};
2951
2952static const char * const lcd_groups[] = {
2953	"lcd_data8",
2954	"lcd_data9",
2955	"lcd_data12",
2956	"lcd_data16",
2957	"lcd_data18",
2958	"lcd_data24",
2959	"lcd_display",
2960	"lcd_lclk",
2961	"lcd_sync",
2962	"lcd_sys",
2963};
2964
2965static const char * const lcd2_groups[] = {
2966	"lcd2_data8",
2967	"lcd2_data9",
2968	"lcd2_data12",
2969	"lcd2_data16",
2970	"lcd2_data18",
2971	"lcd2_data24",
2972	"lcd2_sync_0",
2973	"lcd2_sync_1",
2974	"lcd2_sys_0",
2975	"lcd2_sys_1",
2976};
2977
2978static const char * const mmc0_groups[] = {
2979	"mmc0_data1_0",
2980	"mmc0_data4_0",
2981	"mmc0_data8_0",
2982	"mmc0_ctrl_0",
2983	"mmc0_data1_1",
2984	"mmc0_data4_1",
2985	"mmc0_data8_1",
2986	"mmc0_ctrl_1",
2987};
2988
2989static const char * const scifa0_groups[] = {
2990	"scifa0_data",
2991	"scifa0_clk",
2992	"scifa0_ctrl",
2993};
2994
2995static const char * const scifa1_groups[] = {
2996	"scifa1_data",
2997	"scifa1_clk",
2998	"scifa1_ctrl",
2999};
3000
3001static const char * const scifa2_groups[] = {
3002	"scifa2_data_0",
3003	"scifa2_clk_0",
3004	"scifa2_ctrl_0",
3005	"scifa2_data_1",
3006	"scifa2_clk_1",
3007	"scifa2_ctrl_1",
3008};
3009
3010static const char * const scifa3_groups[] = {
3011	"scifa3_data",
3012	"scifa3_ctrl",
3013};
3014
3015static const char * const scifa4_groups[] = {
3016	"scifa4_data",
3017	"scifa4_ctrl",
3018};
3019
3020static const char * const scifa5_groups[] = {
3021	"scifa5_data_0",
3022	"scifa5_clk_0",
3023	"scifa5_ctrl_0",
3024	"scifa5_data_1",
3025	"scifa5_clk_1",
3026	"scifa5_ctrl_1",
3027	"scifa5_data_2",
3028	"scifa5_clk_2",
3029	"scifa5_ctrl_2",
3030};
3031
3032static const char * const scifa6_groups[] = {
3033	"scifa6",
3034};
3035
3036static const char * const scifa7_groups[] = {
3037	"scifa7_data",
3038	"scifa7_ctrl",
3039};
3040
3041static const char * const scifb_groups[] = {
3042	"scifb_data_0",
3043	"scifb_clk_0",
3044	"scifb_ctrl_0",
3045	"scifb_data_1",
3046	"scifb_clk_1",
3047	"scifb_ctrl_1",
3048};
3049
3050static const char * const sdhi0_groups[] = {
3051	"sdhi0_data1",
3052	"sdhi0_data4",
3053	"sdhi0_ctrl",
3054	"sdhi0_cd",
3055	"sdhi0_wp",
3056};
3057
3058static const char * const sdhi1_groups[] = {
3059	"sdhi1_data1",
3060	"sdhi1_data4",
3061	"sdhi1_ctrl",
3062};
3063
3064static const char * const sdhi2_groups[] = {
3065	"sdhi2_data1",
3066	"sdhi2_data4",
3067	"sdhi2_ctrl",
3068};
3069
3070static const char * const usb_groups[] = {
3071	"usb_vbus",
3072};
3073
3074static const char * const tpu0_groups[] = {
3075	"tpu0_to0",
3076	"tpu0_to1",
3077	"tpu0_to2",
3078	"tpu0_to3",
3079};
3080
3081static const char * const tpu1_groups[] = {
3082	"tpu1_to0",
3083	"tpu1_to1_0",
3084	"tpu1_to1_1",
3085	"tpu1_to2",
3086	"tpu1_to3",
3087};
3088
3089static const char * const tpu2_groups[] = {
3090	"tpu2_to0",
3091	"tpu2_to1",
3092	"tpu2_to2",
3093	"tpu2_to3",
3094};
3095
3096static const char * const tpu3_groups[] = {
3097	"tpu3_to0",
3098	"tpu3_to1",
3099	"tpu3_to2",
3100	"tpu3_to3",
3101};
3102
3103static const char * const tpu4_groups[] = {
3104	"tpu4_to0",
3105	"tpu4_to1",
3106	"tpu4_to2",
3107	"tpu4_to3",
3108};
3109
3110static const struct sh_pfc_function pinmux_functions[] = {
3111	SH_PFC_FUNCTION(bsc),
3112	SH_PFC_FUNCTION(fsia),
3113	SH_PFC_FUNCTION(fsib),
3114	SH_PFC_FUNCTION(fsic),
3115	SH_PFC_FUNCTION(fsid),
3116	SH_PFC_FUNCTION(i2c2),
3117	SH_PFC_FUNCTION(i2c3),
3118	SH_PFC_FUNCTION(irda),
3119	SH_PFC_FUNCTION(keysc),
3120	SH_PFC_FUNCTION(lcd),
3121	SH_PFC_FUNCTION(lcd2),
3122	SH_PFC_FUNCTION(mmc0),
3123	SH_PFC_FUNCTION(scifa0),
3124	SH_PFC_FUNCTION(scifa1),
3125	SH_PFC_FUNCTION(scifa2),
3126	SH_PFC_FUNCTION(scifa3),
3127	SH_PFC_FUNCTION(scifa4),
3128	SH_PFC_FUNCTION(scifa5),
3129	SH_PFC_FUNCTION(scifa6),
3130	SH_PFC_FUNCTION(scifa7),
3131	SH_PFC_FUNCTION(scifb),
3132	SH_PFC_FUNCTION(sdhi0),
3133	SH_PFC_FUNCTION(sdhi1),
3134	SH_PFC_FUNCTION(sdhi2),
3135	SH_PFC_FUNCTION(tpu0),
3136	SH_PFC_FUNCTION(tpu1),
3137	SH_PFC_FUNCTION(tpu2),
3138	SH_PFC_FUNCTION(tpu3),
3139	SH_PFC_FUNCTION(tpu4),
3140	SH_PFC_FUNCTION(usb),
3141};
3142
3143static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3144	PORTCR(0, 0xe6050000), /* PORT0CR */
3145	PORTCR(1, 0xe6050001), /* PORT1CR */
3146	PORTCR(2, 0xe6050002), /* PORT2CR */
3147	PORTCR(3, 0xe6050003), /* PORT3CR */
3148	PORTCR(4, 0xe6050004), /* PORT4CR */
3149	PORTCR(5, 0xe6050005), /* PORT5CR */
3150	PORTCR(6, 0xe6050006), /* PORT6CR */
3151	PORTCR(7, 0xe6050007), /* PORT7CR */
3152	PORTCR(8, 0xe6050008), /* PORT8CR */
3153	PORTCR(9, 0xe6050009), /* PORT9CR */
3154
3155	PORTCR(10, 0xe605000a), /* PORT10CR */
3156	PORTCR(11, 0xe605000b), /* PORT11CR */
3157	PORTCR(12, 0xe605000c), /* PORT12CR */
3158	PORTCR(13, 0xe605000d), /* PORT13CR */
3159	PORTCR(14, 0xe605000e), /* PORT14CR */
3160	PORTCR(15, 0xe605000f), /* PORT15CR */
3161	PORTCR(16, 0xe6050010), /* PORT16CR */
3162	PORTCR(17, 0xe6050011), /* PORT17CR */
3163	PORTCR(18, 0xe6050012), /* PORT18CR */
3164	PORTCR(19, 0xe6050013), /* PORT19CR */
3165
3166	PORTCR(20, 0xe6050014), /* PORT20CR */
3167	PORTCR(21, 0xe6050015), /* PORT21CR */
3168	PORTCR(22, 0xe6050016), /* PORT22CR */
3169	PORTCR(23, 0xe6050017), /* PORT23CR */
3170	PORTCR(24, 0xe6050018), /* PORT24CR */
3171	PORTCR(25, 0xe6050019), /* PORT25CR */
3172	PORTCR(26, 0xe605001a), /* PORT26CR */
3173	PORTCR(27, 0xe605001b), /* PORT27CR */
3174	PORTCR(28, 0xe605001c), /* PORT28CR */
3175	PORTCR(29, 0xe605001d), /* PORT29CR */
3176
3177	PORTCR(30, 0xe605001e), /* PORT30CR */
3178	PORTCR(31, 0xe605001f), /* PORT31CR */
3179	PORTCR(32, 0xe6051020), /* PORT32CR */
3180	PORTCR(33, 0xe6051021), /* PORT33CR */
3181	PORTCR(34, 0xe6051022), /* PORT34CR */
3182	PORTCR(35, 0xe6051023), /* PORT35CR */
3183	PORTCR(36, 0xe6051024), /* PORT36CR */
3184	PORTCR(37, 0xe6051025), /* PORT37CR */
3185	PORTCR(38, 0xe6051026), /* PORT38CR */
3186	PORTCR(39, 0xe6051027), /* PORT39CR */
3187
3188	PORTCR(40, 0xe6051028), /* PORT40CR */
3189	PORTCR(41, 0xe6051029), /* PORT41CR */
3190	PORTCR(42, 0xe605102a), /* PORT42CR */
3191	PORTCR(43, 0xe605102b), /* PORT43CR */
3192	PORTCR(44, 0xe605102c), /* PORT44CR */
3193	PORTCR(45, 0xe605102d), /* PORT45CR */
3194	PORTCR(46, 0xe605102e), /* PORT46CR */
3195	PORTCR(47, 0xe605102f), /* PORT47CR */
3196	PORTCR(48, 0xe6051030), /* PORT48CR */
3197	PORTCR(49, 0xe6051031), /* PORT49CR */
3198
3199	PORTCR(50, 0xe6051032), /* PORT50CR */
3200	PORTCR(51, 0xe6051033), /* PORT51CR */
3201	PORTCR(52, 0xe6051034), /* PORT52CR */
3202	PORTCR(53, 0xe6051035), /* PORT53CR */
3203	PORTCR(54, 0xe6051036), /* PORT54CR */
3204	PORTCR(55, 0xe6051037), /* PORT55CR */
3205	PORTCR(56, 0xe6051038), /* PORT56CR */
3206	PORTCR(57, 0xe6051039), /* PORT57CR */
3207	PORTCR(58, 0xe605103a), /* PORT58CR */
3208	PORTCR(59, 0xe605103b), /* PORT59CR */
3209
3210	PORTCR(60, 0xe605103c), /* PORT60CR */
3211	PORTCR(61, 0xe605103d), /* PORT61CR */
3212	PORTCR(62, 0xe605103e), /* PORT62CR */
3213	PORTCR(63, 0xe605103f), /* PORT63CR */
3214	PORTCR(64, 0xe6051040), /* PORT64CR */
3215	PORTCR(65, 0xe6051041), /* PORT65CR */
3216	PORTCR(66, 0xe6051042), /* PORT66CR */
3217	PORTCR(67, 0xe6051043), /* PORT67CR */
3218	PORTCR(68, 0xe6051044), /* PORT68CR */
3219	PORTCR(69, 0xe6051045), /* PORT69CR */
3220
3221	PORTCR(70, 0xe6051046), /* PORT70CR */
3222	PORTCR(71, 0xe6051047), /* PORT71CR */
3223	PORTCR(72, 0xe6051048), /* PORT72CR */
3224	PORTCR(73, 0xe6051049), /* PORT73CR */
3225	PORTCR(74, 0xe605104a), /* PORT74CR */
3226	PORTCR(75, 0xe605104b), /* PORT75CR */
3227	PORTCR(76, 0xe605104c), /* PORT76CR */
3228	PORTCR(77, 0xe605104d), /* PORT77CR */
3229	PORTCR(78, 0xe605104e), /* PORT78CR */
3230	PORTCR(79, 0xe605104f), /* PORT79CR */
3231
3232	PORTCR(80, 0xe6051050), /* PORT80CR */
3233	PORTCR(81, 0xe6051051), /* PORT81CR */
3234	PORTCR(82, 0xe6051052), /* PORT82CR */
3235	PORTCR(83, 0xe6051053), /* PORT83CR */
3236	PORTCR(84, 0xe6051054), /* PORT84CR */
3237	PORTCR(85, 0xe6051055), /* PORT85CR */
3238	PORTCR(86, 0xe6051056), /* PORT86CR */
3239	PORTCR(87, 0xe6051057), /* PORT87CR */
3240	PORTCR(88, 0xe6051058), /* PORT88CR */
3241	PORTCR(89, 0xe6051059), /* PORT89CR */
3242
3243	PORTCR(90, 0xe605105a), /* PORT90CR */
3244	PORTCR(91, 0xe605105b), /* PORT91CR */
3245	PORTCR(92, 0xe605105c), /* PORT92CR */
3246	PORTCR(93, 0xe605105d), /* PORT93CR */
3247	PORTCR(94, 0xe605105e), /* PORT94CR */
3248	PORTCR(95, 0xe605105f), /* PORT95CR */
3249	PORTCR(96, 0xe6052060), /* PORT96CR */
3250	PORTCR(97, 0xe6052061), /* PORT97CR */
3251	PORTCR(98, 0xe6052062), /* PORT98CR */
3252	PORTCR(99, 0xe6052063), /* PORT99CR */
3253
3254	PORTCR(100, 0xe6052064), /* PORT100CR */
3255	PORTCR(101, 0xe6052065), /* PORT101CR */
3256	PORTCR(102, 0xe6052066), /* PORT102CR */
3257	PORTCR(103, 0xe6052067), /* PORT103CR */
3258	PORTCR(104, 0xe6052068), /* PORT104CR */
3259	PORTCR(105, 0xe6052069), /* PORT105CR */
3260	PORTCR(106, 0xe605206a), /* PORT106CR */
3261	PORTCR(107, 0xe605206b), /* PORT107CR */
3262	PORTCR(108, 0xe605206c), /* PORT108CR */
3263	PORTCR(109, 0xe605206d), /* PORT109CR */
3264
3265	PORTCR(110, 0xe605206e), /* PORT110CR */
3266	PORTCR(111, 0xe605206f), /* PORT111CR */
3267	PORTCR(112, 0xe6052070), /* PORT112CR */
3268	PORTCR(113, 0xe6052071), /* PORT113CR */
3269	PORTCR(114, 0xe6052072), /* PORT114CR */
3270	PORTCR(115, 0xe6052073), /* PORT115CR */
3271	PORTCR(116, 0xe6052074), /* PORT116CR */
3272	PORTCR(117, 0xe6052075), /* PORT117CR */
3273	PORTCR(118, 0xe6052076), /* PORT118CR */
3274
3275	PORTCR(128, 0xe6052080), /* PORT128CR */
3276	PORTCR(129, 0xe6052081), /* PORT129CR */
3277
3278	PORTCR(130, 0xe6052082), /* PORT130CR */
3279	PORTCR(131, 0xe6052083), /* PORT131CR */
3280	PORTCR(132, 0xe6052084), /* PORT132CR */
3281	PORTCR(133, 0xe6052085), /* PORT133CR */
3282	PORTCR(134, 0xe6052086), /* PORT134CR */
3283	PORTCR(135, 0xe6052087), /* PORT135CR */
3284	PORTCR(136, 0xe6052088), /* PORT136CR */
3285	PORTCR(137, 0xe6052089), /* PORT137CR */
3286	PORTCR(138, 0xe605208a), /* PORT138CR */
3287	PORTCR(139, 0xe605208b), /* PORT139CR */
3288
3289	PORTCR(140, 0xe605208c), /* PORT140CR */
3290	PORTCR(141, 0xe605208d), /* PORT141CR */
3291	PORTCR(142, 0xe605208e), /* PORT142CR */
3292	PORTCR(143, 0xe605208f), /* PORT143CR */
3293	PORTCR(144, 0xe6052090), /* PORT144CR */
3294	PORTCR(145, 0xe6052091), /* PORT145CR */
3295	PORTCR(146, 0xe6052092), /* PORT146CR */
3296	PORTCR(147, 0xe6052093), /* PORT147CR */
3297	PORTCR(148, 0xe6052094), /* PORT148CR */
3298	PORTCR(149, 0xe6052095), /* PORT149CR */
3299
3300	PORTCR(150, 0xe6052096), /* PORT150CR */
3301	PORTCR(151, 0xe6052097), /* PORT151CR */
3302	PORTCR(152, 0xe6052098), /* PORT152CR */
3303	PORTCR(153, 0xe6052099), /* PORT153CR */
3304	PORTCR(154, 0xe605209a), /* PORT154CR */
3305	PORTCR(155, 0xe605209b), /* PORT155CR */
3306	PORTCR(156, 0xe605209c), /* PORT156CR */
3307	PORTCR(157, 0xe605209d), /* PORT157CR */
3308	PORTCR(158, 0xe605209e), /* PORT158CR */
3309	PORTCR(159, 0xe605209f), /* PORT159CR */
3310
3311	PORTCR(160, 0xe60520a0), /* PORT160CR */
3312	PORTCR(161, 0xe60520a1), /* PORT161CR */
3313	PORTCR(162, 0xe60520a2), /* PORT162CR */
3314	PORTCR(163, 0xe60520a3), /* PORT163CR */
3315	PORTCR(164, 0xe60520a4), /* PORT164CR */
3316
3317	PORTCR(192, 0xe60520c0), /* PORT192CR */
3318	PORTCR(193, 0xe60520c1), /* PORT193CR */
3319	PORTCR(194, 0xe60520c2), /* PORT194CR */
3320	PORTCR(195, 0xe60520c3), /* PORT195CR */
3321	PORTCR(196, 0xe60520c4), /* PORT196CR */
3322	PORTCR(197, 0xe60520c5), /* PORT197CR */
3323	PORTCR(198, 0xe60520c6), /* PORT198CR */
3324	PORTCR(199, 0xe60520c7), /* PORT199CR */
3325
3326	PORTCR(200, 0xe60520c8), /* PORT200CR */
3327	PORTCR(201, 0xe60520c9), /* PORT201CR */
3328	PORTCR(202, 0xe60520ca), /* PORT202CR */
3329	PORTCR(203, 0xe60520cb), /* PORT203CR */
3330	PORTCR(204, 0xe60520cc), /* PORT204CR */
3331	PORTCR(205, 0xe60520cd), /* PORT205CR */
3332	PORTCR(206, 0xe60520ce), /* PORT206CR */
3333	PORTCR(207, 0xe60520cf), /* PORT207CR */
3334	PORTCR(208, 0xe60520d0), /* PORT208CR */
3335	PORTCR(209, 0xe60520d1), /* PORT209CR */
3336
3337	PORTCR(210, 0xe60520d2), /* PORT210CR */
3338	PORTCR(211, 0xe60520d3), /* PORT211CR */
3339	PORTCR(212, 0xe60520d4), /* PORT212CR */
3340	PORTCR(213, 0xe60520d5), /* PORT213CR */
3341	PORTCR(214, 0xe60520d6), /* PORT214CR */
3342	PORTCR(215, 0xe60520d7), /* PORT215CR */
3343	PORTCR(216, 0xe60520d8), /* PORT216CR */
3344	PORTCR(217, 0xe60520d9), /* PORT217CR */
3345	PORTCR(218, 0xe60520da), /* PORT218CR */
3346	PORTCR(219, 0xe60520db), /* PORT219CR */
3347
3348	PORTCR(220, 0xe60520dc), /* PORT220CR */
3349	PORTCR(221, 0xe60520dd), /* PORT221CR */
3350	PORTCR(222, 0xe60520de), /* PORT222CR */
3351	PORTCR(223, 0xe60520df), /* PORT223CR */
3352	PORTCR(224, 0xe60530e0), /* PORT224CR */
3353	PORTCR(225, 0xe60530e1), /* PORT225CR */
3354	PORTCR(226, 0xe60530e2), /* PORT226CR */
3355	PORTCR(227, 0xe60530e3), /* PORT227CR */
3356	PORTCR(228, 0xe60530e4), /* PORT228CR */
3357	PORTCR(229, 0xe60530e5), /* PORT229CR */
3358
3359	PORTCR(230, 0xe60530e6), /* PORT230CR */
3360	PORTCR(231, 0xe60530e7), /* PORT231CR */
3361	PORTCR(232, 0xe60530e8), /* PORT232CR */
3362	PORTCR(233, 0xe60530e9), /* PORT233CR */
3363	PORTCR(234, 0xe60530ea), /* PORT234CR */
3364	PORTCR(235, 0xe60530eb), /* PORT235CR */
3365	PORTCR(236, 0xe60530ec), /* PORT236CR */
3366	PORTCR(237, 0xe60530ed), /* PORT237CR */
3367	PORTCR(238, 0xe60530ee), /* PORT238CR */
3368	PORTCR(239, 0xe60530ef), /* PORT239CR */
3369
3370	PORTCR(240, 0xe60530f0), /* PORT240CR */
3371	PORTCR(241, 0xe60530f1), /* PORT241CR */
3372	PORTCR(242, 0xe60530f2), /* PORT242CR */
3373	PORTCR(243, 0xe60530f3), /* PORT243CR */
3374	PORTCR(244, 0xe60530f4), /* PORT244CR */
3375	PORTCR(245, 0xe60530f5), /* PORT245CR */
3376	PORTCR(246, 0xe60530f6), /* PORT246CR */
3377	PORTCR(247, 0xe60530f7), /* PORT247CR */
3378	PORTCR(248, 0xe60530f8), /* PORT248CR */
3379	PORTCR(249, 0xe60530f9), /* PORT249CR */
3380
3381	PORTCR(250, 0xe60530fa), /* PORT250CR */
3382	PORTCR(251, 0xe60530fb), /* PORT251CR */
3383	PORTCR(252, 0xe60530fc), /* PORT252CR */
3384	PORTCR(253, 0xe60530fd), /* PORT253CR */
3385	PORTCR(254, 0xe60530fe), /* PORT254CR */
3386	PORTCR(255, 0xe60530ff), /* PORT255CR */
3387	PORTCR(256, 0xe6053100), /* PORT256CR */
3388	PORTCR(257, 0xe6053101), /* PORT257CR */
3389	PORTCR(258, 0xe6053102), /* PORT258CR */
3390	PORTCR(259, 0xe6053103), /* PORT259CR */
3391
3392	PORTCR(260, 0xe6053104), /* PORT260CR */
3393	PORTCR(261, 0xe6053105), /* PORT261CR */
3394	PORTCR(262, 0xe6053106), /* PORT262CR */
3395	PORTCR(263, 0xe6053107), /* PORT263CR */
3396	PORTCR(264, 0xe6053108), /* PORT264CR */
3397	PORTCR(265, 0xe6053109), /* PORT265CR */
3398	PORTCR(266, 0xe605310a), /* PORT266CR */
3399	PORTCR(267, 0xe605310b), /* PORT267CR */
3400	PORTCR(268, 0xe605310c), /* PORT268CR */
3401	PORTCR(269, 0xe605310d), /* PORT269CR */
3402
3403	PORTCR(270, 0xe605310e), /* PORT270CR */
3404	PORTCR(271, 0xe605310f), /* PORT271CR */
3405	PORTCR(272, 0xe6053110), /* PORT272CR */
3406	PORTCR(273, 0xe6053111), /* PORT273CR */
3407	PORTCR(274, 0xe6053112), /* PORT274CR */
3408	PORTCR(275, 0xe6053113), /* PORT275CR */
3409	PORTCR(276, 0xe6053114), /* PORT276CR */
3410	PORTCR(277, 0xe6053115), /* PORT277CR */
3411	PORTCR(278, 0xe6053116), /* PORT278CR */
3412	PORTCR(279, 0xe6053117), /* PORT279CR */
3413
3414	PORTCR(280, 0xe6053118), /* PORT280CR */
3415	PORTCR(281, 0xe6053119), /* PORT281CR */
3416	PORTCR(282, 0xe605311a), /* PORT282CR */
3417
3418	PORTCR(288, 0xe6052120), /* PORT288CR */
3419	PORTCR(289, 0xe6052121), /* PORT289CR */
3420
3421	PORTCR(290, 0xe6052122), /* PORT290CR */
3422	PORTCR(291, 0xe6052123), /* PORT291CR */
3423	PORTCR(292, 0xe6052124), /* PORT292CR */
3424	PORTCR(293, 0xe6052125), /* PORT293CR */
3425	PORTCR(294, 0xe6052126), /* PORT294CR */
3426	PORTCR(295, 0xe6052127), /* PORT295CR */
3427	PORTCR(296, 0xe6052128), /* PORT296CR */
3428	PORTCR(297, 0xe6052129), /* PORT297CR */
3429	PORTCR(298, 0xe605212a), /* PORT298CR */
3430	PORTCR(299, 0xe605212b), /* PORT299CR */
3431
3432	PORTCR(300, 0xe605212c), /* PORT300CR */
3433	PORTCR(301, 0xe605212d), /* PORT301CR */
3434	PORTCR(302, 0xe605212e), /* PORT302CR */
3435	PORTCR(303, 0xe605212f), /* PORT303CR */
3436	PORTCR(304, 0xe6052130), /* PORT304CR */
3437	PORTCR(305, 0xe6052131), /* PORT305CR */
3438	PORTCR(306, 0xe6052132), /* PORT306CR */
3439	PORTCR(307, 0xe6052133), /* PORT307CR */
3440	PORTCR(308, 0xe6052134), /* PORT308CR */
3441	PORTCR(309, 0xe6052135), /* PORT309CR */
3442
3443	{ PINMUX_CFG_REG("MSEL2CR", 0xe605801c, 32, 1) {
3444			0, 0,
3445			0, 0,
3446			0, 0,
3447			0, 0,
3448			0, 0,
3449			0, 0,
3450			0, 0,
3451			0, 0,
3452			0, 0,
3453			0, 0,
3454			0, 0,
3455			0, 0,
3456			MSEL2CR_MSEL19_0, MSEL2CR_MSEL19_1,
3457			MSEL2CR_MSEL18_0, MSEL2CR_MSEL18_1,
3458			MSEL2CR_MSEL17_0, MSEL2CR_MSEL17_1,
3459			MSEL2CR_MSEL16_0, MSEL2CR_MSEL16_1,
3460			0, 0,
3461			MSEL2CR_MSEL14_0, MSEL2CR_MSEL14_1,
3462			MSEL2CR_MSEL13_0, MSEL2CR_MSEL13_1,
3463			MSEL2CR_MSEL12_0, MSEL2CR_MSEL12_1,
3464			MSEL2CR_MSEL11_0, MSEL2CR_MSEL11_1,
3465			MSEL2CR_MSEL10_0, MSEL2CR_MSEL10_1,
3466			MSEL2CR_MSEL9_0, MSEL2CR_MSEL9_1,
3467			MSEL2CR_MSEL8_0, MSEL2CR_MSEL8_1,
3468			MSEL2CR_MSEL7_0, MSEL2CR_MSEL7_1,
3469			MSEL2CR_MSEL6_0, MSEL2CR_MSEL6_1,
3470			MSEL2CR_MSEL5_0, MSEL2CR_MSEL5_1,
3471			MSEL2CR_MSEL4_0, MSEL2CR_MSEL4_1,
3472			MSEL2CR_MSEL3_0, MSEL2CR_MSEL3_1,
3473			MSEL2CR_MSEL2_0, MSEL2CR_MSEL2_1,
3474			MSEL2CR_MSEL1_0, MSEL2CR_MSEL1_1,
3475			MSEL2CR_MSEL0_0, MSEL2CR_MSEL0_1,
3476		}
3477	},
3478	{ PINMUX_CFG_REG("MSEL3CR", 0xe6058020, 32, 1) {
3479			0, 0,
3480			0, 0,
3481			0, 0,
3482			MSEL3CR_MSEL28_0, MSEL3CR_MSEL28_1,
3483			0, 0,
3484			0, 0,
3485			0, 0,
3486			0, 0,
3487			0, 0,
3488			0, 0,
3489			0, 0,
3490			0, 0,
3491			0, 0,
3492			0, 0,
3493			0, 0,
3494			0, 0,
3495			MSEL3CR_MSEL15_0, MSEL3CR_MSEL15_1,
3496			0, 0,
3497			0, 0,
3498			0, 0,
3499			MSEL3CR_MSEL11_0, MSEL3CR_MSEL11_1,
3500			0, 0,
3501			MSEL3CR_MSEL9_0, MSEL3CR_MSEL9_1,
3502			0, 0,
3503			0, 0,
3504			MSEL3CR_MSEL6_0, MSEL3CR_MSEL6_1,
3505			0, 0,
3506			0, 0,
3507			0, 0,
3508			MSEL3CR_MSEL2_0, MSEL3CR_MSEL2_1,
3509			0, 0,
3510			0, 0,
3511		}
3512	},
3513	{ PINMUX_CFG_REG("MSEL4CR", 0xe6058024, 32, 1) {
3514			0, 0,
3515			0, 0,
3516			MSEL4CR_MSEL29_0, MSEL4CR_MSEL29_1,
3517			0, 0,
3518			MSEL4CR_MSEL27_0, MSEL4CR_MSEL27_1,
3519			MSEL4CR_MSEL26_0, MSEL4CR_MSEL26_1,
3520			0, 0,
3521			0, 0,
3522			0, 0,
3523			MSEL4CR_MSEL22_0, MSEL4CR_MSEL22_1,
3524			MSEL4CR_MSEL21_0, MSEL4CR_MSEL21_1,
3525			MSEL4CR_MSEL20_0, MSEL4CR_MSEL20_1,
3526			MSEL4CR_MSEL19_0, MSEL4CR_MSEL19_1,
3527			0, 0,
3528			0, 0,
3529			0, 0,
3530			MSEL4CR_MSEL15_0, MSEL4CR_MSEL15_1,
3531			0, 0,
3532			MSEL4CR_MSEL13_0, MSEL4CR_MSEL13_1,
3533			MSEL4CR_MSEL12_0, MSEL4CR_MSEL12_1,
3534			MSEL4CR_MSEL11_0, MSEL4CR_MSEL11_1,
3535			MSEL4CR_MSEL10_0, MSEL4CR_MSEL10_1,
3536			MSEL4CR_MSEL9_0, MSEL4CR_MSEL9_1,
3537			MSEL4CR_MSEL8_0, MSEL4CR_MSEL8_1,
3538			MSEL4CR_MSEL7_0, MSEL4CR_MSEL7_1,
3539			0, 0,
3540			0, 0,
3541			MSEL4CR_MSEL4_0, MSEL4CR_MSEL4_1,
3542			0, 0,
3543			0, 0,
3544			MSEL4CR_MSEL1_0, MSEL4CR_MSEL1_1,
3545			0, 0,
3546		}
3547	},
3548	{ },
3549};
3550
3551static const struct pinmux_data_reg pinmux_data_regs[] = {
3552	{ PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32) {
3553			PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
3554			PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
3555			PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
3556			PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
3557			PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
3558			PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
3559			PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
3560			PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA }
3561	},
3562	{ PINMUX_DATA_REG("PORTD063_032DR", 0xe6055000, 32) {
3563			PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA,
3564			PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA,
3565			PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA,
3566			PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA,
3567			PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA,
3568			PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA,
3569			PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
3570			PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA }
3571	},
3572	{ PINMUX_DATA_REG("PORTD095_064DR", 0xe6055004, 32) {
3573			PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA,
3574			PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA,
3575			PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA,
3576			PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
3577			PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
3578			PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
3579			PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
3580			PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA }
3581	},
3582	{ PINMUX_DATA_REG("PORTR127_096DR", 0xe6056000, 32) {
3583			0, 0, 0, 0,
3584			0, 0, 0, 0,
3585			0, PORT118_DATA, PORT117_DATA, PORT116_DATA,
3586			PORT115_DATA, PORT114_DATA, PORT113_DATA, PORT112_DATA,
3587			PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
3588			PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
3589			PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
3590			PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA }
3591	},
3592	{ PINMUX_DATA_REG("PORTR159_128DR", 0xe6056004, 32) {
3593			PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA,
3594			PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA,
3595			PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA,
3596			PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA,
3597			PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA,
3598			PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA,
3599			PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA,
3600			PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA }
3601	},
3602	{ PINMUX_DATA_REG("PORTR191_160DR", 0xe6056008, 32) {
3603			0, 0, 0, 0,
3604			0, 0, 0, 0,
3605			0, 0, 0, 0,
3606			0, 0, 0, 0,
3607			0, 0, 0, 0,
3608			0, 0, 0, 0,
3609			0, 0, 0, PORT164_DATA,
3610			PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA }
3611	},
3612	{ PINMUX_DATA_REG("PORTR223_192DR", 0xe605600C, 32) {
3613			PORT223_DATA, PORT222_DATA, PORT221_DATA, PORT220_DATA,
3614			PORT219_DATA, PORT218_DATA, PORT217_DATA, PORT216_DATA,
3615			PORT215_DATA, PORT214_DATA, PORT213_DATA, PORT212_DATA,
3616			PORT211_DATA, PORT210_DATA, PORT209_DATA, PORT208_DATA,
3617			PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
3618			PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
3619			PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
3620			PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA }
3621	},
3622	{ PINMUX_DATA_REG("PORTU255_224DR", 0xe6057000, 32) {
3623			PORT255_DATA, PORT254_DATA, PORT253_DATA, PORT252_DATA,
3624			PORT251_DATA, PORT250_DATA, PORT249_DATA, PORT248_DATA,
3625			PORT247_DATA, PORT246_DATA, PORT245_DATA, PORT244_DATA,
3626			PORT243_DATA, PORT242_DATA, PORT241_DATA, PORT240_DATA,
3627			PORT239_DATA, PORT238_DATA, PORT237_DATA, PORT236_DATA,
3628			PORT235_DATA, PORT234_DATA, PORT233_DATA, PORT232_DATA,
3629			PORT231_DATA, PORT230_DATA, PORT229_DATA, PORT228_DATA,
3630			PORT227_DATA, PORT226_DATA, PORT225_DATA, PORT224_DATA }
3631	},
3632	{ PINMUX_DATA_REG("PORTU287_256DR", 0xe6057004, 32) {
3633			0, 0, 0, 0,
3634			0, PORT282_DATA, PORT281_DATA, PORT280_DATA,
3635			PORT279_DATA, PORT278_DATA, PORT277_DATA, PORT276_DATA,
3636			PORT275_DATA, PORT274_DATA, PORT273_DATA, PORT272_DATA,
3637			PORT271_DATA, PORT270_DATA, PORT269_DATA, PORT268_DATA,
3638			PORT267_DATA, PORT266_DATA, PORT265_DATA, PORT264_DATA,
3639			PORT263_DATA, PORT262_DATA, PORT261_DATA, PORT260_DATA,
3640			PORT259_DATA, PORT258_DATA, PORT257_DATA, PORT256_DATA }
3641	},
3642	{ PINMUX_DATA_REG("PORTR319_288DR", 0xe6056010, 32) {
3643			0, 0, 0, 0,
3644			0, 0, 0, 0,
3645			0, 0, PORT309_DATA, PORT308_DATA,
3646			PORT307_DATA, PORT306_DATA, PORT305_DATA, PORT304_DATA,
3647			PORT303_DATA, PORT302_DATA, PORT301_DATA, PORT300_DATA,
3648			PORT299_DATA, PORT298_DATA, PORT297_DATA, PORT296_DATA,
3649			PORT295_DATA, PORT294_DATA, PORT293_DATA, PORT292_DATA,
3650			PORT291_DATA, PORT290_DATA, PORT289_DATA, PORT288_DATA }
3651	},
3652	{ },
3653};
3654
3655static const struct pinmux_irq pinmux_irqs[] = {
3656	PINMUX_IRQ(irq_pin(0), 11),
3657	PINMUX_IRQ(irq_pin(1), 10),
3658	PINMUX_IRQ(irq_pin(2), 149),
3659	PINMUX_IRQ(irq_pin(3), 224),
3660	PINMUX_IRQ(irq_pin(4), 159),
3661	PINMUX_IRQ(irq_pin(5), 227),
3662	PINMUX_IRQ(irq_pin(6), 147),
3663	PINMUX_IRQ(irq_pin(7), 150),
3664	PINMUX_IRQ(irq_pin(8), 223),
3665	PINMUX_IRQ(irq_pin(9), 56, 308),
3666	PINMUX_IRQ(irq_pin(10), 54),
3667	PINMUX_IRQ(irq_pin(11), 238),
3668	PINMUX_IRQ(irq_pin(12), 156),
3669	PINMUX_IRQ(irq_pin(13), 239),
3670	PINMUX_IRQ(irq_pin(14), 251),
3671	PINMUX_IRQ(irq_pin(15), 0),
3672	PINMUX_IRQ(irq_pin(16), 249),
3673	PINMUX_IRQ(irq_pin(17), 234),
3674	PINMUX_IRQ(irq_pin(18), 13),
3675	PINMUX_IRQ(irq_pin(19), 9),
3676	PINMUX_IRQ(irq_pin(20), 14),
3677	PINMUX_IRQ(irq_pin(21), 15),
3678	PINMUX_IRQ(irq_pin(22), 40),
3679	PINMUX_IRQ(irq_pin(23), 53),
3680	PINMUX_IRQ(irq_pin(24), 118),
3681	PINMUX_IRQ(irq_pin(25), 164),
3682	PINMUX_IRQ(irq_pin(26), 115),
3683	PINMUX_IRQ(irq_pin(27), 116),
3684	PINMUX_IRQ(irq_pin(28), 117),
3685	PINMUX_IRQ(irq_pin(29), 28),
3686	PINMUX_IRQ(irq_pin(30), 27),
3687	PINMUX_IRQ(irq_pin(31), 26),
3688};
3689
3690/* -----------------------------------------------------------------------------
3691 * VCCQ MC0 regulator
3692 */
3693
3694static void sh73a0_vccq_mc0_endisable(struct regulator_dev *reg, bool enable)
3695{
3696	struct sh_pfc *pfc = reg->reg_data;
3697	void __iomem *addr = pfc->windows[1].virt + 4;
3698	unsigned long flags;
3699	u32 value;
3700
3701	spin_lock_irqsave(&pfc->lock, flags);
3702
3703	value = ioread32(addr);
3704
3705	if (enable)
3706		value |= BIT(28);
3707	else
3708		value &= ~BIT(28);
3709
3710	iowrite32(value, addr);
3711
3712	spin_unlock_irqrestore(&pfc->lock, flags);
3713}
3714
3715static int sh73a0_vccq_mc0_enable(struct regulator_dev *reg)
3716{
3717	sh73a0_vccq_mc0_endisable(reg, true);
3718	return 0;
3719}
3720
3721static int sh73a0_vccq_mc0_disable(struct regulator_dev *reg)
3722{
3723	sh73a0_vccq_mc0_endisable(reg, false);
3724	return 0;
3725}
3726
3727static int sh73a0_vccq_mc0_is_enabled(struct regulator_dev *reg)
3728{
3729	struct sh_pfc *pfc = reg->reg_data;
3730	void __iomem *addr = pfc->windows[1].virt + 4;
3731	unsigned long flags;
3732	u32 value;
3733
3734	spin_lock_irqsave(&pfc->lock, flags);
3735	value = ioread32(addr);
3736	spin_unlock_irqrestore(&pfc->lock, flags);
3737
3738	return !!(value & BIT(28));
3739}
3740
3741static int sh73a0_vccq_mc0_get_voltage(struct regulator_dev *reg)
3742{
3743	return 3300000;
3744}
3745
3746static struct regulator_ops sh73a0_vccq_mc0_ops = {
3747	.enable = sh73a0_vccq_mc0_enable,
3748	.disable = sh73a0_vccq_mc0_disable,
3749	.is_enabled = sh73a0_vccq_mc0_is_enabled,
3750	.get_voltage = sh73a0_vccq_mc0_get_voltage,
3751};
3752
3753static const struct regulator_desc sh73a0_vccq_mc0_desc = {
3754	.owner = THIS_MODULE,
3755	.name = "vccq_mc0",
3756	.type = REGULATOR_VOLTAGE,
3757	.ops = &sh73a0_vccq_mc0_ops,
3758};
3759
3760static struct regulator_consumer_supply sh73a0_vccq_mc0_consumers[] = {
3761	REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
3762	REGULATOR_SUPPLY("vqmmc", "ee100000.sdhi"),
3763};
3764
3765static const struct regulator_init_data sh73a0_vccq_mc0_init_data = {
3766	.constraints = {
3767		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
3768	},
3769	.num_consumer_supplies = ARRAY_SIZE(sh73a0_vccq_mc0_consumers),
3770	.consumer_supplies = sh73a0_vccq_mc0_consumers,
3771};
3772
3773/* -----------------------------------------------------------------------------
3774 * Pin bias
3775 */
3776
3777#define PORTnCR_PULMD_OFF	(0 << 6)
3778#define PORTnCR_PULMD_DOWN	(2 << 6)
3779#define PORTnCR_PULMD_UP	(3 << 6)
3780#define PORTnCR_PULMD_MASK	(3 << 6)
3781
3782static const unsigned int sh73a0_portcr_offsets[] = {
3783	0x00000000, 0x00001000, 0x00001000, 0x00002000, 0x00002000,
3784	0x00002000, 0x00002000, 0x00003000, 0x00003000, 0x00002000,
3785};
3786
3787static unsigned int sh73a0_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin)
3788{
3789	void __iomem *addr = pfc->windows->virt
3790			   + sh73a0_portcr_offsets[pin >> 5] + pin;
3791	u32 value = ioread8(addr) & PORTnCR_PULMD_MASK;
3792
3793	switch (value) {
3794	case PORTnCR_PULMD_UP:
3795		return PIN_CONFIG_BIAS_PULL_UP;
3796	case PORTnCR_PULMD_DOWN:
3797		return PIN_CONFIG_BIAS_PULL_DOWN;
3798	case PORTnCR_PULMD_OFF:
3799	default:
3800		return PIN_CONFIG_BIAS_DISABLE;
3801	}
3802}
3803
3804static void sh73a0_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
3805				   unsigned int bias)
3806{
3807	void __iomem *addr = pfc->windows->virt
3808			   + sh73a0_portcr_offsets[pin >> 5] + pin;
3809	u32 value = ioread8(addr) & ~PORTnCR_PULMD_MASK;
3810
3811	switch (bias) {
3812	case PIN_CONFIG_BIAS_PULL_UP:
3813		value |= PORTnCR_PULMD_UP;
3814		break;
3815	case PIN_CONFIG_BIAS_PULL_DOWN:
3816		value |= PORTnCR_PULMD_DOWN;
3817		break;
3818	}
3819
3820	iowrite8(value, addr);
3821}
3822
3823/* -----------------------------------------------------------------------------
3824 * SoC information
3825 */
3826
3827static int sh73a0_pinmux_soc_init(struct sh_pfc *pfc)
3828{
3829	struct regulator_config cfg = { };
3830	struct regulator_dev *vccq;
3831	int ret;
3832
3833	cfg.dev = pfc->dev;
3834	cfg.init_data = &sh73a0_vccq_mc0_init_data;
3835	cfg.driver_data = pfc;
3836
3837	vccq = devm_regulator_register(pfc->dev, &sh73a0_vccq_mc0_desc, &cfg);
3838	if (IS_ERR(vccq)) {
3839		ret = PTR_ERR(vccq);
3840		dev_err(pfc->dev, "Failed to register VCCQ MC0 regulator: %d\n",
3841			ret);
3842		return ret;
3843	}
3844
3845	return 0;
3846}
3847
3848static const struct sh_pfc_soc_operations sh73a0_pfc_ops = {
3849	.init = sh73a0_pinmux_soc_init,
3850	.get_bias = sh73a0_pinmux_get_bias,
3851	.set_bias = sh73a0_pinmux_set_bias,
3852};
3853
3854const struct sh_pfc_soc_info sh73a0_pinmux_info = {
3855	.name = "sh73a0_pfc",
3856	.ops = &sh73a0_pfc_ops,
3857
3858	.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
3859	.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
3860	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
3861
3862	.pins = pinmux_pins,
3863	.nr_pins = ARRAY_SIZE(pinmux_pins),
3864	.groups = pinmux_groups,
3865	.nr_groups = ARRAY_SIZE(pinmux_groups),
3866	.functions = pinmux_functions,
3867	.nr_functions = ARRAY_SIZE(pinmux_functions),
3868
3869	.cfg_regs = pinmux_config_regs,
3870	.data_regs = pinmux_data_regs,
3871
3872	.gpio_data = pinmux_data,
3873	.gpio_data_size = ARRAY_SIZE(pinmux_data),
3874
3875	.gpio_irq = pinmux_irqs,
3876	.gpio_irq_size = ARRAY_SIZE(pinmux_irqs),
3877};
3878