1/* 2 * drivers/pci/setup-bus.c 3 * 4 * Extruded from code written by 5 * Dave Rusling (david.rusling@reo.mts.dec.com) 6 * David Mosberger (davidm@cs.arizona.edu) 7 * David Miller (davem@redhat.com) 8 * 9 * Support routines for initializing a PCI subsystem. 10 */ 11 12/* 13 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru> 14 * PCI-PCI bridges cleanup, sorted resource allocation. 15 * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru> 16 * Converted to allocation in 3 passes, which gives 17 * tighter packing. Prefetchable range support. 18 */ 19 20#include <linux/init.h> 21#include <linux/kernel.h> 22#include <linux/module.h> 23#include <linux/pci.h> 24#include <linux/errno.h> 25#include <linux/ioport.h> 26#include <linux/cache.h> 27#include <linux/slab.h> 28#include <asm-generic/pci-bridge.h> 29#include "pci.h" 30 31unsigned int pci_flags; 32 33struct pci_dev_resource { 34 struct list_head list; 35 struct resource *res; 36 struct pci_dev *dev; 37 resource_size_t start; 38 resource_size_t end; 39 resource_size_t add_size; 40 resource_size_t min_align; 41 unsigned long flags; 42}; 43 44static void free_list(struct list_head *head) 45{ 46 struct pci_dev_resource *dev_res, *tmp; 47 48 list_for_each_entry_safe(dev_res, tmp, head, list) { 49 list_del(&dev_res->list); 50 kfree(dev_res); 51 } 52} 53 54/** 55 * add_to_list() - add a new resource tracker to the list 56 * @head: Head of the list 57 * @dev: device corresponding to which the resource 58 * belongs 59 * @res: The resource to be tracked 60 * @add_size: additional size to be optionally added 61 * to the resource 62 */ 63static int add_to_list(struct list_head *head, 64 struct pci_dev *dev, struct resource *res, 65 resource_size_t add_size, resource_size_t min_align) 66{ 67 struct pci_dev_resource *tmp; 68 69 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL); 70 if (!tmp) { 71 pr_warn("add_to_list: kmalloc() failed!\n"); 72 return -ENOMEM; 73 } 74 75 tmp->res = res; 76 tmp->dev = dev; 77 tmp->start = res->start; 78 tmp->end = res->end; 79 tmp->flags = res->flags; 80 tmp->add_size = add_size; 81 tmp->min_align = min_align; 82 83 list_add(&tmp->list, head); 84 85 return 0; 86} 87 88static void remove_from_list(struct list_head *head, 89 struct resource *res) 90{ 91 struct pci_dev_resource *dev_res, *tmp; 92 93 list_for_each_entry_safe(dev_res, tmp, head, list) { 94 if (dev_res->res == res) { 95 list_del(&dev_res->list); 96 kfree(dev_res); 97 break; 98 } 99 } 100} 101 102static struct pci_dev_resource *res_to_dev_res(struct list_head *head, 103 struct resource *res) 104{ 105 struct pci_dev_resource *dev_res; 106 107 list_for_each_entry(dev_res, head, list) { 108 if (dev_res->res == res) { 109 int idx = res - &dev_res->dev->resource[0]; 110 111 dev_printk(KERN_DEBUG, &dev_res->dev->dev, 112 "res[%d]=%pR res_to_dev_res add_size %llx min_align %llx\n", 113 idx, dev_res->res, 114 (unsigned long long)dev_res->add_size, 115 (unsigned long long)dev_res->min_align); 116 117 return dev_res; 118 } 119 } 120 121 return NULL; 122} 123 124static resource_size_t get_res_add_size(struct list_head *head, 125 struct resource *res) 126{ 127 struct pci_dev_resource *dev_res; 128 129 dev_res = res_to_dev_res(head, res); 130 return dev_res ? dev_res->add_size : 0; 131} 132 133static resource_size_t get_res_add_align(struct list_head *head, 134 struct resource *res) 135{ 136 struct pci_dev_resource *dev_res; 137 138 dev_res = res_to_dev_res(head, res); 139 return dev_res ? dev_res->min_align : 0; 140} 141 142 143/* Sort resources by alignment */ 144static void pdev_sort_resources(struct pci_dev *dev, struct list_head *head) 145{ 146 int i; 147 148 for (i = 0; i < PCI_NUM_RESOURCES; i++) { 149 struct resource *r; 150 struct pci_dev_resource *dev_res, *tmp; 151 resource_size_t r_align; 152 struct list_head *n; 153 154 r = &dev->resource[i]; 155 156 if (r->flags & IORESOURCE_PCI_FIXED) 157 continue; 158 159 if (!(r->flags) || r->parent) 160 continue; 161 162 r_align = pci_resource_alignment(dev, r); 163 if (!r_align) { 164 dev_warn(&dev->dev, "BAR %d: %pR has bogus alignment\n", 165 i, r); 166 continue; 167 } 168 169 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL); 170 if (!tmp) 171 panic("pdev_sort_resources(): kmalloc() failed!\n"); 172 tmp->res = r; 173 tmp->dev = dev; 174 175 /* fallback is smallest one or list is empty*/ 176 n = head; 177 list_for_each_entry(dev_res, head, list) { 178 resource_size_t align; 179 180 align = pci_resource_alignment(dev_res->dev, 181 dev_res->res); 182 183 if (r_align > align) { 184 n = &dev_res->list; 185 break; 186 } 187 } 188 /* Insert it just before n*/ 189 list_add_tail(&tmp->list, n); 190 } 191} 192 193static void __dev_sort_resources(struct pci_dev *dev, 194 struct list_head *head) 195{ 196 u16 class = dev->class >> 8; 197 198 /* Don't touch classless devices or host bridges or ioapics. */ 199 if (class == PCI_CLASS_NOT_DEFINED || class == PCI_CLASS_BRIDGE_HOST) 200 return; 201 202 /* Don't touch ioapic devices already enabled by firmware */ 203 if (class == PCI_CLASS_SYSTEM_PIC) { 204 u16 command; 205 pci_read_config_word(dev, PCI_COMMAND, &command); 206 if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) 207 return; 208 } 209 210 pdev_sort_resources(dev, head); 211} 212 213static inline void reset_resource(struct resource *res) 214{ 215 res->start = 0; 216 res->end = 0; 217 res->flags = 0; 218} 219 220/** 221 * reassign_resources_sorted() - satisfy any additional resource requests 222 * 223 * @realloc_head : head of the list tracking requests requiring additional 224 * resources 225 * @head : head of the list tracking requests with allocated 226 * resources 227 * 228 * Walk through each element of the realloc_head and try to procure 229 * additional resources for the element, provided the element 230 * is in the head list. 231 */ 232static void reassign_resources_sorted(struct list_head *realloc_head, 233 struct list_head *head) 234{ 235 struct resource *res; 236 struct pci_dev_resource *add_res, *tmp; 237 struct pci_dev_resource *dev_res; 238 resource_size_t add_size, align; 239 int idx; 240 241 list_for_each_entry_safe(add_res, tmp, realloc_head, list) { 242 bool found_match = false; 243 244 res = add_res->res; 245 /* skip resource that has been reset */ 246 if (!res->flags) 247 goto out; 248 249 /* skip this resource if not found in head list */ 250 list_for_each_entry(dev_res, head, list) { 251 if (dev_res->res == res) { 252 found_match = true; 253 break; 254 } 255 } 256 if (!found_match)/* just skip */ 257 continue; 258 259 idx = res - &add_res->dev->resource[0]; 260 add_size = add_res->add_size; 261 align = add_res->min_align; 262 if (!resource_size(res)) { 263 res->start = align; 264 res->end = res->start + add_size - 1; 265 if (pci_assign_resource(add_res->dev, idx)) 266 reset_resource(res); 267 } else { 268 res->flags |= add_res->flags & 269 (IORESOURCE_STARTALIGN|IORESOURCE_SIZEALIGN); 270 if (pci_reassign_resource(add_res->dev, idx, 271 add_size, align)) 272 dev_printk(KERN_DEBUG, &add_res->dev->dev, 273 "failed to add %llx res[%d]=%pR\n", 274 (unsigned long long)add_size, 275 idx, res); 276 } 277out: 278 list_del(&add_res->list); 279 kfree(add_res); 280 } 281} 282 283/** 284 * assign_requested_resources_sorted() - satisfy resource requests 285 * 286 * @head : head of the list tracking requests for resources 287 * @fail_head : head of the list tracking requests that could 288 * not be allocated 289 * 290 * Satisfy resource requests of each element in the list. Add 291 * requests that could not satisfied to the failed_list. 292 */ 293static void assign_requested_resources_sorted(struct list_head *head, 294 struct list_head *fail_head) 295{ 296 struct resource *res; 297 struct pci_dev_resource *dev_res; 298 int idx; 299 300 list_for_each_entry(dev_res, head, list) { 301 res = dev_res->res; 302 idx = res - &dev_res->dev->resource[0]; 303 if (resource_size(res) && 304 pci_assign_resource(dev_res->dev, idx)) { 305 if (fail_head) { 306 /* 307 * if the failed res is for ROM BAR, and it will 308 * be enabled later, don't add it to the list 309 */ 310 if (!((idx == PCI_ROM_RESOURCE) && 311 (!(res->flags & IORESOURCE_ROM_ENABLE)))) 312 add_to_list(fail_head, 313 dev_res->dev, res, 314 0 /* don't care */, 315 0 /* don't care */); 316 } 317 reset_resource(res); 318 } 319 } 320} 321 322static unsigned long pci_fail_res_type_mask(struct list_head *fail_head) 323{ 324 struct pci_dev_resource *fail_res; 325 unsigned long mask = 0; 326 327 /* check failed type */ 328 list_for_each_entry(fail_res, fail_head, list) 329 mask |= fail_res->flags; 330 331 /* 332 * one pref failed resource will set IORESOURCE_MEM, 333 * as we can allocate pref in non-pref range. 334 * Will release all assigned non-pref sibling resources 335 * according to that bit. 336 */ 337 return mask & (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH); 338} 339 340static bool pci_need_to_release(unsigned long mask, struct resource *res) 341{ 342 if (res->flags & IORESOURCE_IO) 343 return !!(mask & IORESOURCE_IO); 344 345 /* check pref at first */ 346 if (res->flags & IORESOURCE_PREFETCH) { 347 if (mask & IORESOURCE_PREFETCH) 348 return true; 349 /* count pref if its parent is non-pref */ 350 else if ((mask & IORESOURCE_MEM) && 351 !(res->parent->flags & IORESOURCE_PREFETCH)) 352 return true; 353 else 354 return false; 355 } 356 357 if (res->flags & IORESOURCE_MEM) 358 return !!(mask & IORESOURCE_MEM); 359 360 return false; /* should not get here */ 361} 362 363static void __assign_resources_sorted(struct list_head *head, 364 struct list_head *realloc_head, 365 struct list_head *fail_head) 366{ 367 /* 368 * Should not assign requested resources at first. 369 * they could be adjacent, so later reassign can not reallocate 370 * them one by one in parent resource window. 371 * Try to assign requested + add_size at beginning 372 * if could do that, could get out early. 373 * if could not do that, we still try to assign requested at first, 374 * then try to reassign add_size for some resources. 375 * 376 * Separate three resource type checking if we need to release 377 * assigned resource after requested + add_size try. 378 * 1. if there is io port assign fail, will release assigned 379 * io port. 380 * 2. if there is pref mmio assign fail, release assigned 381 * pref mmio. 382 * if assigned pref mmio's parent is non-pref mmio and there 383 * is non-pref mmio assign fail, will release that assigned 384 * pref mmio. 385 * 3. if there is non-pref mmio assign fail or pref mmio 386 * assigned fail, will release assigned non-pref mmio. 387 */ 388 LIST_HEAD(save_head); 389 LIST_HEAD(local_fail_head); 390 struct pci_dev_resource *save_res; 391 struct pci_dev_resource *dev_res, *tmp_res, *dev_res2; 392 unsigned long fail_type; 393 resource_size_t add_align, align; 394 395 /* Check if optional add_size is there */ 396 if (!realloc_head || list_empty(realloc_head)) 397 goto requested_and_reassign; 398 399 /* Save original start, end, flags etc at first */ 400 list_for_each_entry(dev_res, head, list) { 401 if (add_to_list(&save_head, dev_res->dev, dev_res->res, 0, 0)) { 402 free_list(&save_head); 403 goto requested_and_reassign; 404 } 405 } 406 407 /* Update res in head list with add_size in realloc_head list */ 408 list_for_each_entry_safe(dev_res, tmp_res, head, list) { 409 dev_res->res->end += get_res_add_size(realloc_head, 410 dev_res->res); 411 412 /* 413 * There are two kinds of additional resources in the list: 414 * 1. bridge resource -- IORESOURCE_STARTALIGN 415 * 2. SR-IOV resource -- IORESOURCE_SIZEALIGN 416 * Here just fix the additional alignment for bridge 417 */ 418 if (!(dev_res->res->flags & IORESOURCE_STARTALIGN)) 419 continue; 420 421 add_align = get_res_add_align(realloc_head, dev_res->res); 422 423 /* 424 * The "head" list is sorted by the alignment to make sure 425 * resources with bigger alignment will be assigned first. 426 * After we change the alignment of a dev_res in "head" list, 427 * we need to reorder the list by alignment to make it 428 * consistent. 429 */ 430 if (add_align > dev_res->res->start) { 431 resource_size_t r_size = resource_size(dev_res->res); 432 433 dev_res->res->start = add_align; 434 dev_res->res->end = add_align + r_size - 1; 435 436 list_for_each_entry(dev_res2, head, list) { 437 align = pci_resource_alignment(dev_res2->dev, 438 dev_res2->res); 439 if (add_align > align) { 440 list_move_tail(&dev_res->list, 441 &dev_res2->list); 442 break; 443 } 444 } 445 } 446 447 } 448 449 /* Try updated head list with add_size added */ 450 assign_requested_resources_sorted(head, &local_fail_head); 451 452 /* all assigned with add_size ? */ 453 if (list_empty(&local_fail_head)) { 454 /* Remove head list from realloc_head list */ 455 list_for_each_entry(dev_res, head, list) 456 remove_from_list(realloc_head, dev_res->res); 457 free_list(&save_head); 458 free_list(head); 459 return; 460 } 461 462 /* check failed type */ 463 fail_type = pci_fail_res_type_mask(&local_fail_head); 464 /* remove not need to be released assigned res from head list etc */ 465 list_for_each_entry_safe(dev_res, tmp_res, head, list) 466 if (dev_res->res->parent && 467 !pci_need_to_release(fail_type, dev_res->res)) { 468 /* remove it from realloc_head list */ 469 remove_from_list(realloc_head, dev_res->res); 470 remove_from_list(&save_head, dev_res->res); 471 list_del(&dev_res->list); 472 kfree(dev_res); 473 } 474 475 free_list(&local_fail_head); 476 /* Release assigned resource */ 477 list_for_each_entry(dev_res, head, list) 478 if (dev_res->res->parent) 479 release_resource(dev_res->res); 480 /* Restore start/end/flags from saved list */ 481 list_for_each_entry(save_res, &save_head, list) { 482 struct resource *res = save_res->res; 483 484 res->start = save_res->start; 485 res->end = save_res->end; 486 res->flags = save_res->flags; 487 } 488 free_list(&save_head); 489 490requested_and_reassign: 491 /* Satisfy the must-have resource requests */ 492 assign_requested_resources_sorted(head, fail_head); 493 494 /* Try to satisfy any additional optional resource 495 requests */ 496 if (realloc_head) 497 reassign_resources_sorted(realloc_head, head); 498 free_list(head); 499} 500 501static void pdev_assign_resources_sorted(struct pci_dev *dev, 502 struct list_head *add_head, 503 struct list_head *fail_head) 504{ 505 LIST_HEAD(head); 506 507 __dev_sort_resources(dev, &head); 508 __assign_resources_sorted(&head, add_head, fail_head); 509 510} 511 512static void pbus_assign_resources_sorted(const struct pci_bus *bus, 513 struct list_head *realloc_head, 514 struct list_head *fail_head) 515{ 516 struct pci_dev *dev; 517 LIST_HEAD(head); 518 519 list_for_each_entry(dev, &bus->devices, bus_list) 520 __dev_sort_resources(dev, &head); 521 522 __assign_resources_sorted(&head, realloc_head, fail_head); 523} 524 525void pci_setup_cardbus(struct pci_bus *bus) 526{ 527 struct pci_dev *bridge = bus->self; 528 struct resource *res; 529 struct pci_bus_region region; 530 531 dev_info(&bridge->dev, "CardBus bridge to %pR\n", 532 &bus->busn_res); 533 534 res = bus->resource[0]; 535 pcibios_resource_to_bus(bridge->bus, ®ion, res); 536 if (res->flags & IORESOURCE_IO) { 537 /* 538 * The IO resource is allocated a range twice as large as it 539 * would normally need. This allows us to set both IO regs. 540 */ 541 dev_info(&bridge->dev, " bridge window %pR\n", res); 542 pci_write_config_dword(bridge, PCI_CB_IO_BASE_0, 543 region.start); 544 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0, 545 region.end); 546 } 547 548 res = bus->resource[1]; 549 pcibios_resource_to_bus(bridge->bus, ®ion, res); 550 if (res->flags & IORESOURCE_IO) { 551 dev_info(&bridge->dev, " bridge window %pR\n", res); 552 pci_write_config_dword(bridge, PCI_CB_IO_BASE_1, 553 region.start); 554 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1, 555 region.end); 556 } 557 558 res = bus->resource[2]; 559 pcibios_resource_to_bus(bridge->bus, ®ion, res); 560 if (res->flags & IORESOURCE_MEM) { 561 dev_info(&bridge->dev, " bridge window %pR\n", res); 562 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0, 563 region.start); 564 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0, 565 region.end); 566 } 567 568 res = bus->resource[3]; 569 pcibios_resource_to_bus(bridge->bus, ®ion, res); 570 if (res->flags & IORESOURCE_MEM) { 571 dev_info(&bridge->dev, " bridge window %pR\n", res); 572 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1, 573 region.start); 574 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1, 575 region.end); 576 } 577} 578EXPORT_SYMBOL(pci_setup_cardbus); 579 580/* Initialize bridges with base/limit values we have collected. 581 PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998) 582 requires that if there is no I/O ports or memory behind the 583 bridge, corresponding range must be turned off by writing base 584 value greater than limit to the bridge's base/limit registers. 585 586 Note: care must be taken when updating I/O base/limit registers 587 of bridges which support 32-bit I/O. This update requires two 588 config space writes, so it's quite possible that an I/O window of 589 the bridge will have some undesirable address (e.g. 0) after the 590 first write. Ditto 64-bit prefetchable MMIO. */ 591static void pci_setup_bridge_io(struct pci_dev *bridge) 592{ 593 struct resource *res; 594 struct pci_bus_region region; 595 unsigned long io_mask; 596 u8 io_base_lo, io_limit_lo; 597 u16 l; 598 u32 io_upper16; 599 600 io_mask = PCI_IO_RANGE_MASK; 601 if (bridge->io_window_1k) 602 io_mask = PCI_IO_1K_RANGE_MASK; 603 604 /* Set up the top and bottom of the PCI I/O segment for this bus. */ 605 res = &bridge->resource[PCI_BRIDGE_RESOURCES + 0]; 606 pcibios_resource_to_bus(bridge->bus, ®ion, res); 607 if (res->flags & IORESOURCE_IO) { 608 pci_read_config_word(bridge, PCI_IO_BASE, &l); 609 io_base_lo = (region.start >> 8) & io_mask; 610 io_limit_lo = (region.end >> 8) & io_mask; 611 l = ((u16) io_limit_lo << 8) | io_base_lo; 612 /* Set up upper 16 bits of I/O base/limit. */ 613 io_upper16 = (region.end & 0xffff0000) | (region.start >> 16); 614 dev_info(&bridge->dev, " bridge window %pR\n", res); 615 } else { 616 /* Clear upper 16 bits of I/O base/limit. */ 617 io_upper16 = 0; 618 l = 0x00f0; 619 } 620 /* Temporarily disable the I/O range before updating PCI_IO_BASE. */ 621 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff); 622 /* Update lower 16 bits of I/O base/limit. */ 623 pci_write_config_word(bridge, PCI_IO_BASE, l); 624 /* Update upper 16 bits of I/O base/limit. */ 625 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16); 626} 627 628static void pci_setup_bridge_mmio(struct pci_dev *bridge) 629{ 630 struct resource *res; 631 struct pci_bus_region region; 632 u32 l; 633 634 /* Set up the top and bottom of the PCI Memory segment for this bus. */ 635 res = &bridge->resource[PCI_BRIDGE_RESOURCES + 1]; 636 pcibios_resource_to_bus(bridge->bus, ®ion, res); 637 if (res->flags & IORESOURCE_MEM) { 638 l = (region.start >> 16) & 0xfff0; 639 l |= region.end & 0xfff00000; 640 dev_info(&bridge->dev, " bridge window %pR\n", res); 641 } else { 642 l = 0x0000fff0; 643 } 644 pci_write_config_dword(bridge, PCI_MEMORY_BASE, l); 645} 646 647static void pci_setup_bridge_mmio_pref(struct pci_dev *bridge) 648{ 649 struct resource *res; 650 struct pci_bus_region region; 651 u32 l, bu, lu; 652 653 /* Clear out the upper 32 bits of PREF limit. 654 If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily 655 disables PREF range, which is ok. */ 656 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0); 657 658 /* Set up PREF base/limit. */ 659 bu = lu = 0; 660 res = &bridge->resource[PCI_BRIDGE_RESOURCES + 2]; 661 pcibios_resource_to_bus(bridge->bus, ®ion, res); 662 if (res->flags & IORESOURCE_PREFETCH) { 663 l = (region.start >> 16) & 0xfff0; 664 l |= region.end & 0xfff00000; 665 if (res->flags & IORESOURCE_MEM_64) { 666 bu = upper_32_bits(region.start); 667 lu = upper_32_bits(region.end); 668 } 669 dev_info(&bridge->dev, " bridge window %pR\n", res); 670 } else { 671 l = 0x0000fff0; 672 } 673 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l); 674 675 /* Set the upper 32 bits of PREF base & limit. */ 676 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu); 677 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu); 678} 679 680static void __pci_setup_bridge(struct pci_bus *bus, unsigned long type) 681{ 682 struct pci_dev *bridge = bus->self; 683 684 dev_info(&bridge->dev, "PCI bridge to %pR\n", 685 &bus->busn_res); 686 687 if (type & IORESOURCE_IO) 688 pci_setup_bridge_io(bridge); 689 690 if (type & IORESOURCE_MEM) 691 pci_setup_bridge_mmio(bridge); 692 693 if (type & IORESOURCE_PREFETCH) 694 pci_setup_bridge_mmio_pref(bridge); 695 696 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl); 697} 698 699void pci_setup_bridge(struct pci_bus *bus) 700{ 701 unsigned long type = IORESOURCE_IO | IORESOURCE_MEM | 702 IORESOURCE_PREFETCH; 703 704 __pci_setup_bridge(bus, type); 705} 706 707 708int pci_claim_bridge_resource(struct pci_dev *bridge, int i) 709{ 710 if (i < PCI_BRIDGE_RESOURCES || i > PCI_BRIDGE_RESOURCE_END) 711 return 0; 712 713 if (pci_claim_resource(bridge, i) == 0) 714 return 0; /* claimed the window */ 715 716 if ((bridge->class >> 8) != PCI_CLASS_BRIDGE_PCI) 717 return 0; 718 719 if (!pci_bus_clip_resource(bridge, i)) 720 return -EINVAL; /* clipping didn't change anything */ 721 722 switch (i - PCI_BRIDGE_RESOURCES) { 723 case 0: 724 pci_setup_bridge_io(bridge); 725 break; 726 case 1: 727 pci_setup_bridge_mmio(bridge); 728 break; 729 case 2: 730 pci_setup_bridge_mmio_pref(bridge); 731 break; 732 default: 733 return -EINVAL; 734 } 735 736 if (pci_claim_resource(bridge, i) == 0) 737 return 0; /* claimed a smaller window */ 738 739 return -EINVAL; 740} 741 742/* Check whether the bridge supports optional I/O and 743 prefetchable memory ranges. If not, the respective 744 base/limit registers must be read-only and read as 0. */ 745static void pci_bridge_check_ranges(struct pci_bus *bus) 746{ 747 u16 io; 748 u32 pmem; 749 struct pci_dev *bridge = bus->self; 750 struct resource *b_res; 751 752 b_res = &bridge->resource[PCI_BRIDGE_RESOURCES]; 753 b_res[1].flags |= IORESOURCE_MEM; 754 755 pci_read_config_word(bridge, PCI_IO_BASE, &io); 756 if (!io) { 757 pci_write_config_word(bridge, PCI_IO_BASE, 0xe0f0); 758 pci_read_config_word(bridge, PCI_IO_BASE, &io); 759 pci_write_config_word(bridge, PCI_IO_BASE, 0x0); 760 } 761 if (io) 762 b_res[0].flags |= IORESOURCE_IO; 763 764 /* DECchip 21050 pass 2 errata: the bridge may miss an address 765 disconnect boundary by one PCI data phase. 766 Workaround: do not use prefetching on this device. */ 767 if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001) 768 return; 769 770 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); 771 if (!pmem) { 772 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 773 0xffe0fff0); 774 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); 775 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0); 776 } 777 if (pmem) { 778 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH; 779 if ((pmem & PCI_PREF_RANGE_TYPE_MASK) == 780 PCI_PREF_RANGE_TYPE_64) { 781 b_res[2].flags |= IORESOURCE_MEM_64; 782 b_res[2].flags |= PCI_PREF_RANGE_TYPE_64; 783 } 784 } 785 786 /* double check if bridge does support 64 bit pref */ 787 if (b_res[2].flags & IORESOURCE_MEM_64) { 788 u32 mem_base_hi, tmp; 789 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, 790 &mem_base_hi); 791 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, 792 0xffffffff); 793 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp); 794 if (!tmp) 795 b_res[2].flags &= ~IORESOURCE_MEM_64; 796 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, 797 mem_base_hi); 798 } 799} 800 801/* Helper function for sizing routines: find first available 802 bus resource of a given type. Note: we intentionally skip 803 the bus resources which have already been assigned (that is, 804 have non-NULL parent resource). */ 805static struct resource *find_free_bus_resource(struct pci_bus *bus, 806 unsigned long type_mask, unsigned long type) 807{ 808 int i; 809 struct resource *r; 810 811 pci_bus_for_each_resource(bus, r, i) { 812 if (r == &ioport_resource || r == &iomem_resource) 813 continue; 814 if (r && (r->flags & type_mask) == type && !r->parent) 815 return r; 816 } 817 return NULL; 818} 819 820static resource_size_t calculate_iosize(resource_size_t size, 821 resource_size_t min_size, 822 resource_size_t size1, 823 resource_size_t old_size, 824 resource_size_t align) 825{ 826 if (size < min_size) 827 size = min_size; 828 if (old_size == 1) 829 old_size = 0; 830 /* To be fixed in 2.5: we should have sort of HAVE_ISA 831 flag in the struct pci_bus. */ 832#if defined(CONFIG_ISA) || defined(CONFIG_EISA) 833 size = (size & 0xff) + ((size & ~0xffUL) << 2); 834#endif 835 size = ALIGN(size + size1, align); 836 if (size < old_size) 837 size = old_size; 838 return size; 839} 840 841static resource_size_t calculate_memsize(resource_size_t size, 842 resource_size_t min_size, 843 resource_size_t size1, 844 resource_size_t old_size, 845 resource_size_t align) 846{ 847 if (size < min_size) 848 size = min_size; 849 if (old_size == 1) 850 old_size = 0; 851 if (size < old_size) 852 size = old_size; 853 size = ALIGN(size + size1, align); 854 return size; 855} 856 857resource_size_t __weak pcibios_window_alignment(struct pci_bus *bus, 858 unsigned long type) 859{ 860 return 1; 861} 862 863#define PCI_P2P_DEFAULT_MEM_ALIGN 0x100000 /* 1MiB */ 864#define PCI_P2P_DEFAULT_IO_ALIGN 0x1000 /* 4KiB */ 865#define PCI_P2P_DEFAULT_IO_ALIGN_1K 0x400 /* 1KiB */ 866 867static resource_size_t window_alignment(struct pci_bus *bus, 868 unsigned long type) 869{ 870 resource_size_t align = 1, arch_align; 871 872 if (type & IORESOURCE_MEM) 873 align = PCI_P2P_DEFAULT_MEM_ALIGN; 874 else if (type & IORESOURCE_IO) { 875 /* 876 * Per spec, I/O windows are 4K-aligned, but some 877 * bridges have an extension to support 1K alignment. 878 */ 879 if (bus->self->io_window_1k) 880 align = PCI_P2P_DEFAULT_IO_ALIGN_1K; 881 else 882 align = PCI_P2P_DEFAULT_IO_ALIGN; 883 } 884 885 arch_align = pcibios_window_alignment(bus, type); 886 return max(align, arch_align); 887} 888 889/** 890 * pbus_size_io() - size the io window of a given bus 891 * 892 * @bus : the bus 893 * @min_size : the minimum io window that must to be allocated 894 * @add_size : additional optional io window 895 * @realloc_head : track the additional io window on this list 896 * 897 * Sizing the IO windows of the PCI-PCI bridge is trivial, 898 * since these windows have 1K or 4K granularity and the IO ranges 899 * of non-bridge PCI devices are limited to 256 bytes. 900 * We must be careful with the ISA aliasing though. 901 */ 902static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size, 903 resource_size_t add_size, struct list_head *realloc_head) 904{ 905 struct pci_dev *dev; 906 struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO, 907 IORESOURCE_IO); 908 resource_size_t size = 0, size0 = 0, size1 = 0; 909 resource_size_t children_add_size = 0; 910 resource_size_t min_align, align; 911 912 if (!b_res) 913 return; 914 915 min_align = window_alignment(bus, IORESOURCE_IO); 916 list_for_each_entry(dev, &bus->devices, bus_list) { 917 int i; 918 919 for (i = 0; i < PCI_NUM_RESOURCES; i++) { 920 struct resource *r = &dev->resource[i]; 921 unsigned long r_size; 922 923 if (r->parent || !(r->flags & IORESOURCE_IO)) 924 continue; 925 r_size = resource_size(r); 926 927 if (r_size < 0x400) 928 /* Might be re-aligned for ISA */ 929 size += r_size; 930 else 931 size1 += r_size; 932 933 align = pci_resource_alignment(dev, r); 934 if (align > min_align) 935 min_align = align; 936 937 if (realloc_head) 938 children_add_size += get_res_add_size(realloc_head, r); 939 } 940 } 941 942 size0 = calculate_iosize(size, min_size, size1, 943 resource_size(b_res), min_align); 944 if (children_add_size > add_size) 945 add_size = children_add_size; 946 size1 = (!realloc_head || (realloc_head && !add_size)) ? size0 : 947 calculate_iosize(size, min_size, add_size + size1, 948 resource_size(b_res), min_align); 949 if (!size0 && !size1) { 950 if (b_res->start || b_res->end) 951 dev_info(&bus->self->dev, "disabling bridge window %pR to %pR (unused)\n", 952 b_res, &bus->busn_res); 953 b_res->flags = 0; 954 return; 955 } 956 957 b_res->start = min_align; 958 b_res->end = b_res->start + size0 - 1; 959 b_res->flags |= IORESOURCE_STARTALIGN; 960 if (size1 > size0 && realloc_head) { 961 add_to_list(realloc_head, bus->self, b_res, size1-size0, 962 min_align); 963 dev_printk(KERN_DEBUG, &bus->self->dev, "bridge window %pR to %pR add_size %llx\n", 964 b_res, &bus->busn_res, 965 (unsigned long long)size1-size0); 966 } 967} 968 969static inline resource_size_t calculate_mem_align(resource_size_t *aligns, 970 int max_order) 971{ 972 resource_size_t align = 0; 973 resource_size_t min_align = 0; 974 int order; 975 976 for (order = 0; order <= max_order; order++) { 977 resource_size_t align1 = 1; 978 979 align1 <<= (order + 20); 980 981 if (!align) 982 min_align = align1; 983 else if (ALIGN(align + min_align, min_align) < align1) 984 min_align = align1 >> 1; 985 align += aligns[order]; 986 } 987 988 return min_align; 989} 990 991/** 992 * pbus_size_mem() - size the memory window of a given bus 993 * 994 * @bus : the bus 995 * @mask: mask the resource flag, then compare it with type 996 * @type: the type of free resource from bridge 997 * @type2: second match type 998 * @type3: third match type 999 * @min_size : the minimum memory window that must to be allocated 1000 * @add_size : additional optional memory window 1001 * @realloc_head : track the additional memory window on this list 1002 * 1003 * Calculate the size of the bus and minimal alignment which 1004 * guarantees that all child resources fit in this size. 1005 * 1006 * Returns -ENOSPC if there's no available bus resource of the desired type. 1007 * Otherwise, sets the bus resource start/end to indicate the required 1008 * size, adds things to realloc_head (if supplied), and returns 0. 1009 */ 1010static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, 1011 unsigned long type, unsigned long type2, 1012 unsigned long type3, 1013 resource_size_t min_size, resource_size_t add_size, 1014 struct list_head *realloc_head) 1015{ 1016 struct pci_dev *dev; 1017 resource_size_t min_align, align, size, size0, size1; 1018 resource_size_t aligns[18]; /* Alignments from 1Mb to 128Gb */ 1019 int order, max_order; 1020 struct resource *b_res = find_free_bus_resource(bus, 1021 mask | IORESOURCE_PREFETCH, type); 1022 resource_size_t children_add_size = 0; 1023 resource_size_t children_add_align = 0; 1024 resource_size_t add_align = 0; 1025 1026 if (!b_res) 1027 return -ENOSPC; 1028 1029 memset(aligns, 0, sizeof(aligns)); 1030 max_order = 0; 1031 size = 0; 1032 1033 list_for_each_entry(dev, &bus->devices, bus_list) { 1034 int i; 1035 1036 for (i = 0; i < PCI_NUM_RESOURCES; i++) { 1037 struct resource *r = &dev->resource[i]; 1038 resource_size_t r_size; 1039 1040 if (r->parent || ((r->flags & mask) != type && 1041 (r->flags & mask) != type2 && 1042 (r->flags & mask) != type3)) 1043 continue; 1044 r_size = resource_size(r); 1045#ifdef CONFIG_PCI_IOV 1046 /* put SRIOV requested res to the optional list */ 1047 if (realloc_head && i >= PCI_IOV_RESOURCES && 1048 i <= PCI_IOV_RESOURCE_END) { 1049 add_align = max(pci_resource_alignment(dev, r), add_align); 1050 r->end = r->start - 1; 1051 add_to_list(realloc_head, dev, r, r_size, 0/* don't care */); 1052 children_add_size += r_size; 1053 continue; 1054 } 1055#endif 1056 /* 1057 * aligns[0] is for 1MB (since bridge memory 1058 * windows are always at least 1MB aligned), so 1059 * keep "order" from being negative for smaller 1060 * resources. 1061 */ 1062 align = pci_resource_alignment(dev, r); 1063 order = __ffs(align) - 20; 1064 if (order < 0) 1065 order = 0; 1066 if (order >= ARRAY_SIZE(aligns)) { 1067 dev_warn(&dev->dev, "disabling BAR %d: %pR (bad alignment %#llx)\n", 1068 i, r, (unsigned long long) align); 1069 r->flags = 0; 1070 continue; 1071 } 1072 size += r_size; 1073 /* Exclude ranges with size > align from 1074 calculation of the alignment. */ 1075 if (r_size == align) 1076 aligns[order] += align; 1077 if (order > max_order) 1078 max_order = order; 1079 1080 if (realloc_head) { 1081 children_add_size += get_res_add_size(realloc_head, r); 1082 children_add_align = get_res_add_align(realloc_head, r); 1083 add_align = max(add_align, children_add_align); 1084 } 1085 } 1086 } 1087 1088 min_align = calculate_mem_align(aligns, max_order); 1089 min_align = max(min_align, window_alignment(bus, b_res->flags)); 1090 size0 = calculate_memsize(size, min_size, 0, resource_size(b_res), min_align); 1091 add_align = max(min_align, add_align); 1092 if (children_add_size > add_size) 1093 add_size = children_add_size; 1094 size1 = (!realloc_head || (realloc_head && !add_size)) ? size0 : 1095 calculate_memsize(size, min_size, add_size, 1096 resource_size(b_res), add_align); 1097 if (!size0 && !size1) { 1098 if (b_res->start || b_res->end) 1099 dev_info(&bus->self->dev, "disabling bridge window %pR to %pR (unused)\n", 1100 b_res, &bus->busn_res); 1101 b_res->flags = 0; 1102 return 0; 1103 } 1104 b_res->start = min_align; 1105 b_res->end = size0 + min_align - 1; 1106 b_res->flags |= IORESOURCE_STARTALIGN; 1107 if (size1 > size0 && realloc_head) { 1108 add_to_list(realloc_head, bus->self, b_res, size1-size0, add_align); 1109 dev_printk(KERN_DEBUG, &bus->self->dev, "bridge window %pR to %pR add_size %llx add_align %llx\n", 1110 b_res, &bus->busn_res, 1111 (unsigned long long) (size1 - size0), 1112 (unsigned long long) add_align); 1113 } 1114 return 0; 1115} 1116 1117unsigned long pci_cardbus_resource_alignment(struct resource *res) 1118{ 1119 if (res->flags & IORESOURCE_IO) 1120 return pci_cardbus_io_size; 1121 if (res->flags & IORESOURCE_MEM) 1122 return pci_cardbus_mem_size; 1123 return 0; 1124} 1125 1126static void pci_bus_size_cardbus(struct pci_bus *bus, 1127 struct list_head *realloc_head) 1128{ 1129 struct pci_dev *bridge = bus->self; 1130 struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES]; 1131 resource_size_t b_res_3_size = pci_cardbus_mem_size * 2; 1132 u16 ctrl; 1133 1134 if (b_res[0].parent) 1135 goto handle_b_res_1; 1136 /* 1137 * Reserve some resources for CardBus. We reserve 1138 * a fixed amount of bus space for CardBus bridges. 1139 */ 1140 b_res[0].start = pci_cardbus_io_size; 1141 b_res[0].end = b_res[0].start + pci_cardbus_io_size - 1; 1142 b_res[0].flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN; 1143 if (realloc_head) { 1144 b_res[0].end -= pci_cardbus_io_size; 1145 add_to_list(realloc_head, bridge, b_res, pci_cardbus_io_size, 1146 pci_cardbus_io_size); 1147 } 1148 1149handle_b_res_1: 1150 if (b_res[1].parent) 1151 goto handle_b_res_2; 1152 b_res[1].start = pci_cardbus_io_size; 1153 b_res[1].end = b_res[1].start + pci_cardbus_io_size - 1; 1154 b_res[1].flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN; 1155 if (realloc_head) { 1156 b_res[1].end -= pci_cardbus_io_size; 1157 add_to_list(realloc_head, bridge, b_res+1, pci_cardbus_io_size, 1158 pci_cardbus_io_size); 1159 } 1160 1161handle_b_res_2: 1162 /* MEM1 must not be pref mmio */ 1163 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); 1164 if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM1) { 1165 ctrl &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1; 1166 pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl); 1167 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); 1168 } 1169 1170 /* 1171 * Check whether prefetchable memory is supported 1172 * by this bridge. 1173 */ 1174 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); 1175 if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) { 1176 ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0; 1177 pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl); 1178 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); 1179 } 1180 1181 if (b_res[2].parent) 1182 goto handle_b_res_3; 1183 /* 1184 * If we have prefetchable memory support, allocate 1185 * two regions. Otherwise, allocate one region of 1186 * twice the size. 1187 */ 1188 if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) { 1189 b_res[2].start = pci_cardbus_mem_size; 1190 b_res[2].end = b_res[2].start + pci_cardbus_mem_size - 1; 1191 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH | 1192 IORESOURCE_STARTALIGN; 1193 if (realloc_head) { 1194 b_res[2].end -= pci_cardbus_mem_size; 1195 add_to_list(realloc_head, bridge, b_res+2, 1196 pci_cardbus_mem_size, pci_cardbus_mem_size); 1197 } 1198 1199 /* reduce that to half */ 1200 b_res_3_size = pci_cardbus_mem_size; 1201 } 1202 1203handle_b_res_3: 1204 if (b_res[3].parent) 1205 goto handle_done; 1206 b_res[3].start = pci_cardbus_mem_size; 1207 b_res[3].end = b_res[3].start + b_res_3_size - 1; 1208 b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_STARTALIGN; 1209 if (realloc_head) { 1210 b_res[3].end -= b_res_3_size; 1211 add_to_list(realloc_head, bridge, b_res+3, b_res_3_size, 1212 pci_cardbus_mem_size); 1213 } 1214 1215handle_done: 1216 ; 1217} 1218 1219void __pci_bus_size_bridges(struct pci_bus *bus, struct list_head *realloc_head) 1220{ 1221 struct pci_dev *dev; 1222 unsigned long mask, prefmask, type2 = 0, type3 = 0; 1223 resource_size_t additional_mem_size = 0, additional_io_size = 0; 1224 struct resource *b_res; 1225 int ret; 1226 1227 list_for_each_entry(dev, &bus->devices, bus_list) { 1228 struct pci_bus *b = dev->subordinate; 1229 if (!b) 1230 continue; 1231 1232 switch (dev->class >> 8) { 1233 case PCI_CLASS_BRIDGE_CARDBUS: 1234 pci_bus_size_cardbus(b, realloc_head); 1235 break; 1236 1237 case PCI_CLASS_BRIDGE_PCI: 1238 default: 1239 __pci_bus_size_bridges(b, realloc_head); 1240 break; 1241 } 1242 } 1243 1244 /* The root bus? */ 1245 if (pci_is_root_bus(bus)) 1246 return; 1247 1248 switch (bus->self->class >> 8) { 1249 case PCI_CLASS_BRIDGE_CARDBUS: 1250 /* don't size cardbuses yet. */ 1251 break; 1252 1253 case PCI_CLASS_BRIDGE_PCI: 1254 pci_bridge_check_ranges(bus); 1255 if (bus->self->is_hotplug_bridge) { 1256 additional_io_size = pci_hotplug_io_size; 1257 additional_mem_size = pci_hotplug_mem_size; 1258 } 1259 /* Fall through */ 1260 default: 1261 pbus_size_io(bus, realloc_head ? 0 : additional_io_size, 1262 additional_io_size, realloc_head); 1263 1264 /* 1265 * If there's a 64-bit prefetchable MMIO window, compute 1266 * the size required to put all 64-bit prefetchable 1267 * resources in it. 1268 */ 1269 b_res = &bus->self->resource[PCI_BRIDGE_RESOURCES]; 1270 mask = IORESOURCE_MEM; 1271 prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH; 1272 if (b_res[2].flags & IORESOURCE_MEM_64) { 1273 prefmask |= IORESOURCE_MEM_64; 1274 ret = pbus_size_mem(bus, prefmask, prefmask, 1275 prefmask, prefmask, 1276 realloc_head ? 0 : additional_mem_size, 1277 additional_mem_size, realloc_head); 1278 1279 /* 1280 * If successful, all non-prefetchable resources 1281 * and any 32-bit prefetchable resources will go in 1282 * the non-prefetchable window. 1283 */ 1284 if (ret == 0) { 1285 mask = prefmask; 1286 type2 = prefmask & ~IORESOURCE_MEM_64; 1287 type3 = prefmask & ~IORESOURCE_PREFETCH; 1288 } 1289 } 1290 1291 /* 1292 * If there is no 64-bit prefetchable window, compute the 1293 * size required to put all prefetchable resources in the 1294 * 32-bit prefetchable window (if there is one). 1295 */ 1296 if (!type2) { 1297 prefmask &= ~IORESOURCE_MEM_64; 1298 ret = pbus_size_mem(bus, prefmask, prefmask, 1299 prefmask, prefmask, 1300 realloc_head ? 0 : additional_mem_size, 1301 additional_mem_size, realloc_head); 1302 1303 /* 1304 * If successful, only non-prefetchable resources 1305 * will go in the non-prefetchable window. 1306 */ 1307 if (ret == 0) 1308 mask = prefmask; 1309 else 1310 additional_mem_size += additional_mem_size; 1311 1312 type2 = type3 = IORESOURCE_MEM; 1313 } 1314 1315 /* 1316 * Compute the size required to put everything else in the 1317 * non-prefetchable window. This includes: 1318 * 1319 * - all non-prefetchable resources 1320 * - 32-bit prefetchable resources if there's a 64-bit 1321 * prefetchable window or no prefetchable window at all 1322 * - 64-bit prefetchable resources if there's no 1323 * prefetchable window at all 1324 * 1325 * Note that the strategy in __pci_assign_resource() must 1326 * match that used here. Specifically, we cannot put a 1327 * 32-bit prefetchable resource in a 64-bit prefetchable 1328 * window. 1329 */ 1330 pbus_size_mem(bus, mask, IORESOURCE_MEM, type2, type3, 1331 realloc_head ? 0 : additional_mem_size, 1332 additional_mem_size, realloc_head); 1333 break; 1334 } 1335} 1336 1337void pci_bus_size_bridges(struct pci_bus *bus) 1338{ 1339 __pci_bus_size_bridges(bus, NULL); 1340} 1341EXPORT_SYMBOL(pci_bus_size_bridges); 1342 1343void __pci_bus_assign_resources(const struct pci_bus *bus, 1344 struct list_head *realloc_head, 1345 struct list_head *fail_head) 1346{ 1347 struct pci_bus *b; 1348 struct pci_dev *dev; 1349 1350 pbus_assign_resources_sorted(bus, realloc_head, fail_head); 1351 1352 list_for_each_entry(dev, &bus->devices, bus_list) { 1353 b = dev->subordinate; 1354 if (!b) 1355 continue; 1356 1357 __pci_bus_assign_resources(b, realloc_head, fail_head); 1358 1359 switch (dev->class >> 8) { 1360 case PCI_CLASS_BRIDGE_PCI: 1361 if (!pci_is_enabled(dev)) 1362 pci_setup_bridge(b); 1363 break; 1364 1365 case PCI_CLASS_BRIDGE_CARDBUS: 1366 pci_setup_cardbus(b); 1367 break; 1368 1369 default: 1370 dev_info(&dev->dev, "not setting up bridge for bus %04x:%02x\n", 1371 pci_domain_nr(b), b->number); 1372 break; 1373 } 1374 } 1375} 1376 1377void pci_bus_assign_resources(const struct pci_bus *bus) 1378{ 1379 __pci_bus_assign_resources(bus, NULL, NULL); 1380} 1381EXPORT_SYMBOL(pci_bus_assign_resources); 1382 1383static void __pci_bridge_assign_resources(const struct pci_dev *bridge, 1384 struct list_head *add_head, 1385 struct list_head *fail_head) 1386{ 1387 struct pci_bus *b; 1388 1389 pdev_assign_resources_sorted((struct pci_dev *)bridge, 1390 add_head, fail_head); 1391 1392 b = bridge->subordinate; 1393 if (!b) 1394 return; 1395 1396 __pci_bus_assign_resources(b, add_head, fail_head); 1397 1398 switch (bridge->class >> 8) { 1399 case PCI_CLASS_BRIDGE_PCI: 1400 pci_setup_bridge(b); 1401 break; 1402 1403 case PCI_CLASS_BRIDGE_CARDBUS: 1404 pci_setup_cardbus(b); 1405 break; 1406 1407 default: 1408 dev_info(&bridge->dev, "not setting up bridge for bus %04x:%02x\n", 1409 pci_domain_nr(b), b->number); 1410 break; 1411 } 1412} 1413static void pci_bridge_release_resources(struct pci_bus *bus, 1414 unsigned long type) 1415{ 1416 struct pci_dev *dev = bus->self; 1417 struct resource *r; 1418 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | 1419 IORESOURCE_PREFETCH | IORESOURCE_MEM_64; 1420 unsigned old_flags = 0; 1421 struct resource *b_res; 1422 int idx = 1; 1423 1424 b_res = &dev->resource[PCI_BRIDGE_RESOURCES]; 1425 1426 /* 1427 * 1. if there is io port assign fail, will release bridge 1428 * io port. 1429 * 2. if there is non pref mmio assign fail, release bridge 1430 * nonpref mmio. 1431 * 3. if there is 64bit pref mmio assign fail, and bridge pref 1432 * is 64bit, release bridge pref mmio. 1433 * 4. if there is pref mmio assign fail, and bridge pref is 1434 * 32bit mmio, release bridge pref mmio 1435 * 5. if there is pref mmio assign fail, and bridge pref is not 1436 * assigned, release bridge nonpref mmio. 1437 */ 1438 if (type & IORESOURCE_IO) 1439 idx = 0; 1440 else if (!(type & IORESOURCE_PREFETCH)) 1441 idx = 1; 1442 else if ((type & IORESOURCE_MEM_64) && 1443 (b_res[2].flags & IORESOURCE_MEM_64)) 1444 idx = 2; 1445 else if (!(b_res[2].flags & IORESOURCE_MEM_64) && 1446 (b_res[2].flags & IORESOURCE_PREFETCH)) 1447 idx = 2; 1448 else 1449 idx = 1; 1450 1451 r = &b_res[idx]; 1452 1453 if (!r->parent) 1454 return; 1455 1456 /* 1457 * if there are children under that, we should release them 1458 * all 1459 */ 1460 release_child_resources(r); 1461 if (!release_resource(r)) { 1462 type = old_flags = r->flags & type_mask; 1463 dev_printk(KERN_DEBUG, &dev->dev, "resource %d %pR released\n", 1464 PCI_BRIDGE_RESOURCES + idx, r); 1465 /* keep the old size */ 1466 r->end = resource_size(r) - 1; 1467 r->start = 0; 1468 r->flags = 0; 1469 1470 /* avoiding touch the one without PREF */ 1471 if (type & IORESOURCE_PREFETCH) 1472 type = IORESOURCE_PREFETCH; 1473 __pci_setup_bridge(bus, type); 1474 /* for next child res under same bridge */ 1475 r->flags = old_flags; 1476 } 1477} 1478 1479enum release_type { 1480 leaf_only, 1481 whole_subtree, 1482}; 1483/* 1484 * try to release pci bridge resources that is from leaf bridge, 1485 * so we can allocate big new one later 1486 */ 1487static void pci_bus_release_bridge_resources(struct pci_bus *bus, 1488 unsigned long type, 1489 enum release_type rel_type) 1490{ 1491 struct pci_dev *dev; 1492 bool is_leaf_bridge = true; 1493 1494 list_for_each_entry(dev, &bus->devices, bus_list) { 1495 struct pci_bus *b = dev->subordinate; 1496 if (!b) 1497 continue; 1498 1499 is_leaf_bridge = false; 1500 1501 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI) 1502 continue; 1503 1504 if (rel_type == whole_subtree) 1505 pci_bus_release_bridge_resources(b, type, 1506 whole_subtree); 1507 } 1508 1509 if (pci_is_root_bus(bus)) 1510 return; 1511 1512 if ((bus->self->class >> 8) != PCI_CLASS_BRIDGE_PCI) 1513 return; 1514 1515 if ((rel_type == whole_subtree) || is_leaf_bridge) 1516 pci_bridge_release_resources(bus, type); 1517} 1518 1519static void pci_bus_dump_res(struct pci_bus *bus) 1520{ 1521 struct resource *res; 1522 int i; 1523 1524 pci_bus_for_each_resource(bus, res, i) { 1525 if (!res || !res->end || !res->flags) 1526 continue; 1527 1528 dev_printk(KERN_DEBUG, &bus->dev, "resource %d %pR\n", i, res); 1529 } 1530} 1531 1532static void pci_bus_dump_resources(struct pci_bus *bus) 1533{ 1534 struct pci_bus *b; 1535 struct pci_dev *dev; 1536 1537 1538 pci_bus_dump_res(bus); 1539 1540 list_for_each_entry(dev, &bus->devices, bus_list) { 1541 b = dev->subordinate; 1542 if (!b) 1543 continue; 1544 1545 pci_bus_dump_resources(b); 1546 } 1547} 1548 1549static int pci_bus_get_depth(struct pci_bus *bus) 1550{ 1551 int depth = 0; 1552 struct pci_bus *child_bus; 1553 1554 list_for_each_entry(child_bus, &bus->children, node) { 1555 int ret; 1556 1557 ret = pci_bus_get_depth(child_bus); 1558 if (ret + 1 > depth) 1559 depth = ret + 1; 1560 } 1561 1562 return depth; 1563} 1564 1565/* 1566 * -1: undefined, will auto detect later 1567 * 0: disabled by user 1568 * 1: disabled by auto detect 1569 * 2: enabled by user 1570 * 3: enabled by auto detect 1571 */ 1572enum enable_type { 1573 undefined = -1, 1574 user_disabled, 1575 auto_disabled, 1576 user_enabled, 1577 auto_enabled, 1578}; 1579 1580static enum enable_type pci_realloc_enable = undefined; 1581void __init pci_realloc_get_opt(char *str) 1582{ 1583 if (!strncmp(str, "off", 3)) 1584 pci_realloc_enable = user_disabled; 1585 else if (!strncmp(str, "on", 2)) 1586 pci_realloc_enable = user_enabled; 1587} 1588static bool pci_realloc_enabled(enum enable_type enable) 1589{ 1590 return enable >= user_enabled; 1591} 1592 1593#if defined(CONFIG_PCI_IOV) && defined(CONFIG_PCI_REALLOC_ENABLE_AUTO) 1594static int iov_resources_unassigned(struct pci_dev *dev, void *data) 1595{ 1596 int i; 1597 bool *unassigned = data; 1598 1599 for (i = PCI_IOV_RESOURCES; i <= PCI_IOV_RESOURCE_END; i++) { 1600 struct resource *r = &dev->resource[i]; 1601 struct pci_bus_region region; 1602 1603 /* Not assigned or rejected by kernel? */ 1604 if (!r->flags) 1605 continue; 1606 1607 pcibios_resource_to_bus(dev->bus, ®ion, r); 1608 if (!region.start) { 1609 *unassigned = true; 1610 return 1; /* return early from pci_walk_bus() */ 1611 } 1612 } 1613 1614 return 0; 1615} 1616 1617static enum enable_type pci_realloc_detect(struct pci_bus *bus, 1618 enum enable_type enable_local) 1619{ 1620 bool unassigned = false; 1621 1622 if (enable_local != undefined) 1623 return enable_local; 1624 1625 pci_walk_bus(bus, iov_resources_unassigned, &unassigned); 1626 if (unassigned) 1627 return auto_enabled; 1628 1629 return enable_local; 1630} 1631#else 1632static enum enable_type pci_realloc_detect(struct pci_bus *bus, 1633 enum enable_type enable_local) 1634{ 1635 return enable_local; 1636} 1637#endif 1638 1639/* 1640 * first try will not touch pci bridge res 1641 * second and later try will clear small leaf bridge res 1642 * will stop till to the max depth if can not find good one 1643 */ 1644void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus) 1645{ 1646 LIST_HEAD(realloc_head); /* list of resources that 1647 want additional resources */ 1648 struct list_head *add_list = NULL; 1649 int tried_times = 0; 1650 enum release_type rel_type = leaf_only; 1651 LIST_HEAD(fail_head); 1652 struct pci_dev_resource *fail_res; 1653 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | 1654 IORESOURCE_PREFETCH | IORESOURCE_MEM_64; 1655 int pci_try_num = 1; 1656 enum enable_type enable_local; 1657 1658 /* don't realloc if asked to do so */ 1659 enable_local = pci_realloc_detect(bus, pci_realloc_enable); 1660 if (pci_realloc_enabled(enable_local)) { 1661 int max_depth = pci_bus_get_depth(bus); 1662 1663 pci_try_num = max_depth + 1; 1664 dev_printk(KERN_DEBUG, &bus->dev, 1665 "max bus depth: %d pci_try_num: %d\n", 1666 max_depth, pci_try_num); 1667 } 1668 1669again: 1670 /* 1671 * last try will use add_list, otherwise will try good to have as 1672 * must have, so can realloc parent bridge resource 1673 */ 1674 if (tried_times + 1 == pci_try_num) 1675 add_list = &realloc_head; 1676 /* Depth first, calculate sizes and alignments of all 1677 subordinate buses. */ 1678 __pci_bus_size_bridges(bus, add_list); 1679 1680 /* Depth last, allocate resources and update the hardware. */ 1681 __pci_bus_assign_resources(bus, add_list, &fail_head); 1682 if (add_list) 1683 BUG_ON(!list_empty(add_list)); 1684 tried_times++; 1685 1686 /* any device complain? */ 1687 if (list_empty(&fail_head)) 1688 goto dump; 1689 1690 if (tried_times >= pci_try_num) { 1691 if (enable_local == undefined) 1692 dev_info(&bus->dev, "Some PCI device resources are unassigned, try booting with pci=realloc\n"); 1693 else if (enable_local == auto_enabled) 1694 dev_info(&bus->dev, "Automatically enabled pci realloc, if you have problem, try booting with pci=realloc=off\n"); 1695 1696 free_list(&fail_head); 1697 goto dump; 1698 } 1699 1700 dev_printk(KERN_DEBUG, &bus->dev, 1701 "No. %d try to assign unassigned res\n", tried_times + 1); 1702 1703 /* third times and later will not check if it is leaf */ 1704 if ((tried_times + 1) > 2) 1705 rel_type = whole_subtree; 1706 1707 /* 1708 * Try to release leaf bridge's resources that doesn't fit resource of 1709 * child device under that bridge 1710 */ 1711 list_for_each_entry(fail_res, &fail_head, list) 1712 pci_bus_release_bridge_resources(fail_res->dev->bus, 1713 fail_res->flags & type_mask, 1714 rel_type); 1715 1716 /* restore size and flags */ 1717 list_for_each_entry(fail_res, &fail_head, list) { 1718 struct resource *res = fail_res->res; 1719 1720 res->start = fail_res->start; 1721 res->end = fail_res->end; 1722 res->flags = fail_res->flags; 1723 if (fail_res->dev->subordinate) 1724 res->flags = 0; 1725 } 1726 free_list(&fail_head); 1727 1728 goto again; 1729 1730dump: 1731 /* dump the resource on buses */ 1732 pci_bus_dump_resources(bus); 1733} 1734 1735void __init pci_assign_unassigned_resources(void) 1736{ 1737 struct pci_bus *root_bus; 1738 1739 list_for_each_entry(root_bus, &pci_root_buses, node) 1740 pci_assign_unassigned_root_bus_resources(root_bus); 1741} 1742 1743void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge) 1744{ 1745 struct pci_bus *parent = bridge->subordinate; 1746 LIST_HEAD(add_list); /* list of resources that 1747 want additional resources */ 1748 int tried_times = 0; 1749 LIST_HEAD(fail_head); 1750 struct pci_dev_resource *fail_res; 1751 int retval; 1752 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | 1753 IORESOURCE_PREFETCH | IORESOURCE_MEM_64; 1754 1755again: 1756 __pci_bus_size_bridges(parent, &add_list); 1757 __pci_bridge_assign_resources(bridge, &add_list, &fail_head); 1758 BUG_ON(!list_empty(&add_list)); 1759 tried_times++; 1760 1761 if (list_empty(&fail_head)) 1762 goto enable_all; 1763 1764 if (tried_times >= 2) { 1765 /* still fail, don't need to try more */ 1766 free_list(&fail_head); 1767 goto enable_all; 1768 } 1769 1770 printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n", 1771 tried_times + 1); 1772 1773 /* 1774 * Try to release leaf bridge's resources that doesn't fit resource of 1775 * child device under that bridge 1776 */ 1777 list_for_each_entry(fail_res, &fail_head, list) 1778 pci_bus_release_bridge_resources(fail_res->dev->bus, 1779 fail_res->flags & type_mask, 1780 whole_subtree); 1781 1782 /* restore size and flags */ 1783 list_for_each_entry(fail_res, &fail_head, list) { 1784 struct resource *res = fail_res->res; 1785 1786 res->start = fail_res->start; 1787 res->end = fail_res->end; 1788 res->flags = fail_res->flags; 1789 if (fail_res->dev->subordinate) 1790 res->flags = 0; 1791 } 1792 free_list(&fail_head); 1793 1794 goto again; 1795 1796enable_all: 1797 retval = pci_reenable_device(bridge); 1798 if (retval) 1799 dev_err(&bridge->dev, "Error reenabling bridge (%d)\n", retval); 1800 pci_set_master(bridge); 1801} 1802EXPORT_SYMBOL_GPL(pci_assign_unassigned_bridge_resources); 1803 1804void pci_assign_unassigned_bus_resources(struct pci_bus *bus) 1805{ 1806 struct pci_dev *dev; 1807 LIST_HEAD(add_list); /* list of resources that 1808 want additional resources */ 1809 1810 down_read(&pci_bus_sem); 1811 list_for_each_entry(dev, &bus->devices, bus_list) 1812 if (pci_is_bridge(dev) && pci_has_subordinate(dev)) 1813 __pci_bus_size_bridges(dev->subordinate, 1814 &add_list); 1815 up_read(&pci_bus_sem); 1816 __pci_bus_assign_resources(bus, &add_list, NULL); 1817 BUG_ON(!list_empty(&add_list)); 1818} 1819EXPORT_SYMBOL_GPL(pci_assign_unassigned_bus_resources); 1820