1/****************************************************************************** 2 * 3 * Copyright(c) 2009-2012 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 * 18 * The full GNU General Public License is included in this distribution in the 19 * file called LICENSE. 20 * 21 * Contact Information: 22 * wlanfae <wlanfae@realtek.com> 23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 24 * Hsinchu 300, Taiwan. 25 * 26 * Larry Finger <Larry.Finger@lwfinger.net> 27 * 28 *****************************************************************************/ 29 30#include <linux/export.h> 31#include "dm_common.h" 32#include "phy_common.h" 33#include "../pci.h" 34#include "../base.h" 35#include "../core.h" 36 37#define BT_RSSI_STATE_NORMAL_POWER BIT_OFFSET_LEN_MASK_32(0, 1) 38#define BT_RSSI_STATE_AMDPU_OFF BIT_OFFSET_LEN_MASK_32(1, 1) 39#define BT_RSSI_STATE_SPECIAL_LOW BIT_OFFSET_LEN_MASK_32(2, 1) 40#define BT_RSSI_STATE_BG_EDCA_LOW BIT_OFFSET_LEN_MASK_32(3, 1) 41#define BT_RSSI_STATE_TXPOWER_LOW BIT_OFFSET_LEN_MASK_32(4, 1) 42 43#define RTLPRIV (struct rtl_priv *) 44#define GET_UNDECORATED_AVERAGE_RSSI(_priv) \ 45 ((RTLPRIV(_priv))->mac80211.opmode == \ 46 NL80211_IFTYPE_ADHOC) ? \ 47 ((RTLPRIV(_priv))->dm.entry_min_undec_sm_pwdb) : \ 48 ((RTLPRIV(_priv))->dm.undec_sm_pwdb) 49 50static const u32 ofdmswing_table[OFDM_TABLE_SIZE] = { 51 0x7f8001fe, 52 0x788001e2, 53 0x71c001c7, 54 0x6b8001ae, 55 0x65400195, 56 0x5fc0017f, 57 0x5a400169, 58 0x55400155, 59 0x50800142, 60 0x4c000130, 61 0x47c0011f, 62 0x43c0010f, 63 0x40000100, 64 0x3c8000f2, 65 0x390000e4, 66 0x35c000d7, 67 0x32c000cb, 68 0x300000c0, 69 0x2d4000b5, 70 0x2ac000ab, 71 0x288000a2, 72 0x26000098, 73 0x24000090, 74 0x22000088, 75 0x20000080, 76 0x1e400079, 77 0x1c800072, 78 0x1b00006c, 79 0x19800066, 80 0x18000060, 81 0x16c0005b, 82 0x15800056, 83 0x14400051, 84 0x1300004c, 85 0x12000048, 86 0x11000044, 87 0x10000040, 88}; 89 90static const u8 cckswing_table_ch1ch13[CCK_TABLE_SIZE][8] = { 91 {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, 92 {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, 93 {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, 94 {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, 95 {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, 96 {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, 97 {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, 98 {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, 99 {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, 100 {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, 101 {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, 102 {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, 103 {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, 104 {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, 105 {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, 106 {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, 107 {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, 108 {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, 109 {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, 110 {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, 111 {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, 112 {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, 113 {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, 114 {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, 115 {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, 116 {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, 117 {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, 118 {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, 119 {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, 120 {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, 121 {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, 122 {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, 123 {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} 124}; 125 126static const u8 cckswing_table_ch14[CCK_TABLE_SIZE][8] = { 127 {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, 128 {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, 129 {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, 130 {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, 131 {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, 132 {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, 133 {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, 134 {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, 135 {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, 136 {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, 137 {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, 138 {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, 139 {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, 140 {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, 141 {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, 142 {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, 143 {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, 144 {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, 145 {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, 146 {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, 147 {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, 148 {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, 149 {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, 150 {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, 151 {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, 152 {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, 153 {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, 154 {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, 155 {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, 156 {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, 157 {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, 158 {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, 159 {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00} 160}; 161 162static u32 power_index_reg[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a}; 163 164void dm_restorepowerindex(struct ieee80211_hw *hw) 165{ 166 struct rtl_priv *rtlpriv = rtl_priv(hw); 167 u8 index; 168 169 for (index = 0; index < 6; index++) 170 rtl_write_byte(rtlpriv, power_index_reg[index], 171 rtlpriv->dm.powerindex_backup[index]); 172} 173EXPORT_SYMBOL_GPL(dm_restorepowerindex); 174 175void dm_writepowerindex(struct ieee80211_hw *hw, u8 value) 176{ 177 struct rtl_priv *rtlpriv = rtl_priv(hw); 178 u8 index; 179 180 for (index = 0; index < 6; index++) 181 rtl_write_byte(rtlpriv, power_index_reg[index], value); 182} 183EXPORT_SYMBOL_GPL(dm_writepowerindex); 184 185void dm_savepowerindex(struct ieee80211_hw *hw) 186{ 187 struct rtl_priv *rtlpriv = rtl_priv(hw); 188 u8 index; 189 u8 tmp; 190 191 for (index = 0; index < 6; index++) { 192 tmp = rtl_read_byte(rtlpriv, power_index_reg[index]); 193 rtlpriv->dm.powerindex_backup[index] = tmp; 194 } 195} 196EXPORT_SYMBOL_GPL(dm_savepowerindex); 197 198static u8 rtl92c_dm_initial_gain_min_pwdb(struct ieee80211_hw *hw) 199{ 200 struct rtl_priv *rtlpriv = rtl_priv(hw); 201 struct dig_t *dm_digtable = &rtlpriv->dm_digtable; 202 long rssi_val_min = 0; 203 204 if ((dm_digtable->curmultista_cstate == DIG_MULTISTA_CONNECT) && 205 (dm_digtable->cursta_cstate == DIG_STA_CONNECT)) { 206 if (rtlpriv->dm.entry_min_undec_sm_pwdb != 0) 207 rssi_val_min = 208 (rtlpriv->dm.entry_min_undec_sm_pwdb > 209 rtlpriv->dm.undec_sm_pwdb) ? 210 rtlpriv->dm.undec_sm_pwdb : 211 rtlpriv->dm.entry_min_undec_sm_pwdb; 212 else 213 rssi_val_min = rtlpriv->dm.undec_sm_pwdb; 214 } else if (dm_digtable->cursta_cstate == DIG_STA_CONNECT || 215 dm_digtable->cursta_cstate == DIG_STA_BEFORE_CONNECT) { 216 rssi_val_min = rtlpriv->dm.undec_sm_pwdb; 217 } else if (dm_digtable->curmultista_cstate == DIG_MULTISTA_CONNECT) { 218 rssi_val_min = rtlpriv->dm.entry_min_undec_sm_pwdb; 219 } 220 221 if (rssi_val_min > 100) 222 rssi_val_min = 100; 223 return (u8)rssi_val_min; 224} 225 226static void rtl92c_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw) 227{ 228 u32 ret_value; 229 struct rtl_priv *rtlpriv = rtl_priv(hw); 230 struct false_alarm_statistics *falsealm_cnt = &(rtlpriv->falsealm_cnt); 231 232 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER1, MASKDWORD); 233 falsealm_cnt->cnt_parity_fail = ((ret_value & 0xffff0000) >> 16); 234 235 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER2, MASKDWORD); 236 falsealm_cnt->cnt_rate_illegal = (ret_value & 0xffff); 237 falsealm_cnt->cnt_crc8_fail = ((ret_value & 0xffff0000) >> 16); 238 239 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER3, MASKDWORD); 240 falsealm_cnt->cnt_mcs_fail = (ret_value & 0xffff); 241 242 ret_value = rtl_get_bbreg(hw, ROFDM0_FRAMESYNC, MASKDWORD); 243 falsealm_cnt->cnt_fast_fsync_fail = (ret_value & 0xffff); 244 falsealm_cnt->cnt_sb_search_fail = ((ret_value & 0xffff0000) >> 16); 245 246 falsealm_cnt->cnt_ofdm_fail = falsealm_cnt->cnt_parity_fail + 247 falsealm_cnt->cnt_rate_illegal + 248 falsealm_cnt->cnt_crc8_fail + 249 falsealm_cnt->cnt_mcs_fail + 250 falsealm_cnt->cnt_fast_fsync_fail + 251 falsealm_cnt->cnt_sb_search_fail; 252 253 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, BIT(14), 1); 254 ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERLOWER, MASKBYTE0); 255 falsealm_cnt->cnt_cck_fail = ret_value; 256 257 ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERUPPER, MASKBYTE3); 258 falsealm_cnt->cnt_cck_fail += (ret_value & 0xff) << 8; 259 falsealm_cnt->cnt_all = (falsealm_cnt->cnt_parity_fail + 260 falsealm_cnt->cnt_rate_illegal + 261 falsealm_cnt->cnt_crc8_fail + 262 falsealm_cnt->cnt_mcs_fail + 263 falsealm_cnt->cnt_cck_fail); 264 265 rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 1); 266 rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 0); 267 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 0); 268 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 2); 269 270 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE, 271 "cnt_parity_fail = %d, cnt_rate_illegal = %d, cnt_crc8_fail = %d, cnt_mcs_fail = %d\n", 272 falsealm_cnt->cnt_parity_fail, 273 falsealm_cnt->cnt_rate_illegal, 274 falsealm_cnt->cnt_crc8_fail, falsealm_cnt->cnt_mcs_fail); 275 276 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE, 277 "cnt_ofdm_fail = %x, cnt_cck_fail = %x, cnt_all = %x\n", 278 falsealm_cnt->cnt_ofdm_fail, 279 falsealm_cnt->cnt_cck_fail, falsealm_cnt->cnt_all); 280} 281 282static void rtl92c_dm_ctrl_initgain_by_fa(struct ieee80211_hw *hw) 283{ 284 struct rtl_priv *rtlpriv = rtl_priv(hw); 285 struct dig_t *dm_digtable = &rtlpriv->dm_digtable; 286 u8 value_igi = dm_digtable->cur_igvalue; 287 288 if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH0) 289 value_igi--; 290 else if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH1) 291 value_igi += 0; 292 else if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH2) 293 value_igi++; 294 else if (rtlpriv->falsealm_cnt.cnt_all >= DM_DIG_FA_TH2) 295 value_igi += 2; 296 297 if (value_igi > DM_DIG_FA_UPPER) 298 value_igi = DM_DIG_FA_UPPER; 299 else if (value_igi < DM_DIG_FA_LOWER) 300 value_igi = DM_DIG_FA_LOWER; 301 302 if (rtlpriv->falsealm_cnt.cnt_all > 10000) 303 value_igi = DM_DIG_FA_UPPER; 304 305 dm_digtable->cur_igvalue = value_igi; 306 rtl92c_dm_write_dig(hw); 307} 308 309static void rtl92c_dm_ctrl_initgain_by_rssi(struct ieee80211_hw *hw) 310{ 311 struct rtl_priv *rtlpriv = rtl_priv(hw); 312 struct dig_t *digtable = &rtlpriv->dm_digtable; 313 u32 isbt; 314 315 /* modify DIG lower bound, deal with abnorally large false alarm */ 316 if (rtlpriv->falsealm_cnt.cnt_all > 10000) { 317 digtable->large_fa_hit++; 318 if (digtable->forbidden_igi < digtable->cur_igvalue) { 319 digtable->forbidden_igi = digtable->cur_igvalue; 320 digtable->large_fa_hit = 1; 321 } 322 323 if (digtable->large_fa_hit >= 3) { 324 if ((digtable->forbidden_igi + 1) > 325 digtable->rx_gain_max) 326 digtable->rx_gain_min = digtable->rx_gain_max; 327 else 328 digtable->rx_gain_min = (digtable->forbidden_igi + 1); 329 digtable->recover_cnt = 3600; /* 3600=2hr */ 330 } 331 } else { 332 /* Recovery mechanism for IGI lower bound */ 333 if (digtable->recover_cnt != 0) { 334 digtable->recover_cnt--; 335 } else { 336 if (digtable->large_fa_hit == 0) { 337 if ((digtable->forbidden_igi-1) < DM_DIG_MIN) { 338 digtable->forbidden_igi = DM_DIG_MIN; 339 digtable->rx_gain_min = DM_DIG_MIN; 340 } else { 341 digtable->forbidden_igi--; 342 digtable->rx_gain_min = digtable->forbidden_igi + 1; 343 } 344 } else if (digtable->large_fa_hit == 3) { 345 digtable->large_fa_hit = 0; 346 } 347 } 348 } 349 if (rtlpriv->falsealm_cnt.cnt_all < 250) { 350 isbt = rtl_read_byte(rtlpriv, 0x4fd) & 0x01; 351 352 if (!isbt) { 353 if (rtlpriv->falsealm_cnt.cnt_all > 354 digtable->fa_lowthresh) { 355 if ((digtable->back_val - 2) < 356 digtable->back_range_min) 357 digtable->back_val = digtable->back_range_min; 358 else 359 digtable->back_val -= 2; 360 } else if (rtlpriv->falsealm_cnt.cnt_all < 361 digtable->fa_lowthresh) { 362 if ((digtable->back_val + 2) > 363 digtable->back_range_max) 364 digtable->back_val = digtable->back_range_max; 365 else 366 digtable->back_val += 2; 367 } 368 } else { 369 digtable->back_val = DM_DIG_BACKOFF_DEFAULT; 370 } 371 } else { 372 /* Adjust initial gain by false alarm */ 373 if (rtlpriv->falsealm_cnt.cnt_all > 1000) 374 digtable->cur_igvalue = digtable->pre_igvalue + 2; 375 else if (rtlpriv->falsealm_cnt.cnt_all > 750) 376 digtable->cur_igvalue = digtable->pre_igvalue + 1; 377 else if (rtlpriv->falsealm_cnt.cnt_all < 500) 378 digtable->cur_igvalue = digtable->pre_igvalue - 1; 379 } 380 381 /* Check initial gain by upper/lower bound */ 382 if (digtable->cur_igvalue > digtable->rx_gain_max) 383 digtable->cur_igvalue = digtable->rx_gain_max; 384 385 if (digtable->cur_igvalue < digtable->rx_gain_min) 386 digtable->cur_igvalue = digtable->rx_gain_min; 387 388 rtl92c_dm_write_dig(hw); 389} 390 391static void rtl92c_dm_initial_gain_multi_sta(struct ieee80211_hw *hw) 392{ 393 static u8 initialized; /* initialized to false */ 394 struct rtl_priv *rtlpriv = rtl_priv(hw); 395 struct dig_t *dm_digtable = &rtlpriv->dm_digtable; 396 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 397 long rssi_strength = rtlpriv->dm.entry_min_undec_sm_pwdb; 398 bool multi_sta = false; 399 400 if (mac->opmode == NL80211_IFTYPE_ADHOC) 401 multi_sta = true; 402 403 if (!multi_sta || 404 dm_digtable->cursta_cstate == DIG_STA_DISCONNECT) { 405 initialized = false; 406 dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX; 407 return; 408 } else if (initialized == false) { 409 initialized = true; 410 dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_0; 411 dm_digtable->cur_igvalue = 0x20; 412 rtl92c_dm_write_dig(hw); 413 } 414 415 if (dm_digtable->curmultista_cstate == DIG_MULTISTA_CONNECT) { 416 if ((rssi_strength < dm_digtable->rssi_lowthresh) && 417 (dm_digtable->dig_ext_port_stage != DIG_EXT_PORT_STAGE_1)) { 418 419 if (dm_digtable->dig_ext_port_stage == 420 DIG_EXT_PORT_STAGE_2) { 421 dm_digtable->cur_igvalue = 0x20; 422 rtl92c_dm_write_dig(hw); 423 } 424 425 dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_1; 426 } else if (rssi_strength > dm_digtable->rssi_highthresh) { 427 dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_2; 428 rtl92c_dm_ctrl_initgain_by_fa(hw); 429 } 430 } else if (dm_digtable->dig_ext_port_stage != DIG_EXT_PORT_STAGE_0) { 431 dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_0; 432 dm_digtable->cur_igvalue = 0x20; 433 rtl92c_dm_write_dig(hw); 434 } 435 436 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE, 437 "curmultista_cstate = %x dig_ext_port_stage %x\n", 438 dm_digtable->curmultista_cstate, 439 dm_digtable->dig_ext_port_stage); 440} 441 442static void rtl92c_dm_initial_gain_sta(struct ieee80211_hw *hw) 443{ 444 struct rtl_priv *rtlpriv = rtl_priv(hw); 445 struct dig_t *dm_digtable = &rtlpriv->dm_digtable; 446 447 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE, 448 "presta_cstate = %x, cursta_cstate = %x\n", 449 dm_digtable->presta_cstate, dm_digtable->cursta_cstate); 450 if (dm_digtable->presta_cstate == dm_digtable->cursta_cstate || 451 dm_digtable->cursta_cstate == DIG_STA_BEFORE_CONNECT || 452 dm_digtable->cursta_cstate == DIG_STA_CONNECT) { 453 454 if (dm_digtable->cursta_cstate != DIG_STA_DISCONNECT) { 455 dm_digtable->rssi_val_min = 456 rtl92c_dm_initial_gain_min_pwdb(hw); 457 if (dm_digtable->rssi_val_min > 100) 458 dm_digtable->rssi_val_min = 100; 459 rtl92c_dm_ctrl_initgain_by_rssi(hw); 460 } 461 } else { 462 dm_digtable->rssi_val_min = 0; 463 dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX; 464 dm_digtable->back_val = DM_DIG_BACKOFF_DEFAULT; 465 dm_digtable->cur_igvalue = 0x20; 466 dm_digtable->pre_igvalue = 0; 467 rtl92c_dm_write_dig(hw); 468 } 469} 470 471static void rtl92c_dm_cck_packet_detection_thresh(struct ieee80211_hw *hw) 472{ 473 struct rtl_priv *rtlpriv = rtl_priv(hw); 474 struct dig_t *dm_digtable = &rtlpriv->dm_digtable; 475 476 if (dm_digtable->cursta_cstate == DIG_STA_CONNECT) { 477 dm_digtable->rssi_val_min = rtl92c_dm_initial_gain_min_pwdb(hw); 478 if (dm_digtable->rssi_val_min > 100) 479 dm_digtable->rssi_val_min = 100; 480 481 if (dm_digtable->pre_cck_pd_state == CCK_PD_STAGE_LOWRSSI) { 482 if (dm_digtable->rssi_val_min <= 25) 483 dm_digtable->cur_cck_pd_state = 484 CCK_PD_STAGE_LOWRSSI; 485 else 486 dm_digtable->cur_cck_pd_state = 487 CCK_PD_STAGE_HIGHRSSI; 488 } else { 489 if (dm_digtable->rssi_val_min <= 20) 490 dm_digtable->cur_cck_pd_state = 491 CCK_PD_STAGE_LOWRSSI; 492 else 493 dm_digtable->cur_cck_pd_state = 494 CCK_PD_STAGE_HIGHRSSI; 495 } 496 } else { 497 dm_digtable->cur_cck_pd_state = CCK_PD_STAGE_MAX; 498 } 499 500 if (dm_digtable->pre_cck_pd_state != dm_digtable->cur_cck_pd_state) { 501 if ((dm_digtable->cur_cck_pd_state == CCK_PD_STAGE_LOWRSSI) || 502 (dm_digtable->cur_cck_pd_state == CCK_PD_STAGE_MAX)) 503 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0x83); 504 else 505 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd); 506 507 dm_digtable->pre_cck_pd_state = dm_digtable->cur_cck_pd_state; 508 } 509} 510 511static void rtl92c_dm_ctrl_initgain_by_twoport(struct ieee80211_hw *hw) 512{ 513 struct rtl_priv *rtlpriv = rtl_priv(hw); 514 struct dig_t *dm_digtable = &rtlpriv->dm_digtable; 515 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 516 517 if (mac->act_scanning) 518 return; 519 520 if (mac->link_state >= MAC80211_LINKED) 521 dm_digtable->cursta_cstate = DIG_STA_CONNECT; 522 else 523 dm_digtable->cursta_cstate = DIG_STA_DISCONNECT; 524 525 dm_digtable->curmultista_cstate = DIG_MULTISTA_DISCONNECT; 526 527 rtl92c_dm_initial_gain_sta(hw); 528 rtl92c_dm_initial_gain_multi_sta(hw); 529 rtl92c_dm_cck_packet_detection_thresh(hw); 530 531 dm_digtable->presta_cstate = dm_digtable->cursta_cstate; 532 533} 534 535static void rtl92c_dm_dig(struct ieee80211_hw *hw) 536{ 537 struct rtl_priv *rtlpriv = rtl_priv(hw); 538 539 if (rtlpriv->dm.dm_initialgain_enable == false) 540 return; 541 if (!(rtlpriv->dm.dm_flag & DYNAMIC_FUNC_DIG)) 542 return; 543 544 rtl92c_dm_ctrl_initgain_by_twoport(hw); 545} 546 547static void rtl92c_dm_init_dynamic_txpower(struct ieee80211_hw *hw) 548{ 549 struct rtl_priv *rtlpriv = rtl_priv(hw); 550 551 if (rtlpriv->rtlhal.interface == INTF_USB && 552 rtlpriv->rtlhal.board_type & 0x1) { 553 dm_savepowerindex(hw); 554 rtlpriv->dm.dynamic_txpower_enable = true; 555 } else { 556 rtlpriv->dm.dynamic_txpower_enable = false; 557 } 558 rtlpriv->dm.last_dtp_lvl = TXHIGHPWRLEVEL_NORMAL; 559 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL; 560} 561 562void rtl92c_dm_write_dig(struct ieee80211_hw *hw) 563{ 564 struct rtl_priv *rtlpriv = rtl_priv(hw); 565 struct dig_t *dm_digtable = &rtlpriv->dm_digtable; 566 567 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD, 568 "cur_igvalue = 0x%x, pre_igvalue = 0x%x, back_val = %d\n", 569 dm_digtable->cur_igvalue, dm_digtable->pre_igvalue, 570 dm_digtable->back_val); 571 572 if (rtlpriv->rtlhal.interface == INTF_USB && 573 !dm_digtable->dig_enable_flag) { 574 dm_digtable->pre_igvalue = 0x17; 575 return; 576 } 577 dm_digtable->cur_igvalue -= 1; 578 if (dm_digtable->cur_igvalue < DM_DIG_MIN) 579 dm_digtable->cur_igvalue = DM_DIG_MIN; 580 581 if (dm_digtable->pre_igvalue != dm_digtable->cur_igvalue) { 582 rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, 0x7f, 583 dm_digtable->cur_igvalue); 584 rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, 0x7f, 585 dm_digtable->cur_igvalue); 586 587 dm_digtable->pre_igvalue = dm_digtable->cur_igvalue; 588 } 589 RT_TRACE(rtlpriv, COMP_DIG, DBG_WARNING, 590 "dig values 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", 591 dm_digtable->cur_igvalue, dm_digtable->pre_igvalue, 592 dm_digtable->rssi_val_min, dm_digtable->back_val, 593 dm_digtable->rx_gain_max, dm_digtable->rx_gain_min, 594 dm_digtable->large_fa_hit, dm_digtable->forbidden_igi); 595} 596EXPORT_SYMBOL(rtl92c_dm_write_dig); 597 598static void rtl92c_dm_pwdb_monitor(struct ieee80211_hw *hw) 599{ 600 struct rtl_priv *rtlpriv = rtl_priv(hw); 601 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 602 long tmpentry_max_pwdb = 0, tmpentry_min_pwdb = 0xff; 603 604 if (mac->link_state != MAC80211_LINKED) 605 return; 606 607 if (mac->opmode == NL80211_IFTYPE_ADHOC || 608 mac->opmode == NL80211_IFTYPE_AP) { 609 /* TODO: Handle ADHOC and AP Mode */ 610 } 611 612 if (tmpentry_max_pwdb != 0) 613 rtlpriv->dm.entry_max_undec_sm_pwdb = tmpentry_max_pwdb; 614 else 615 rtlpriv->dm.entry_max_undec_sm_pwdb = 0; 616 617 if (tmpentry_min_pwdb != 0xff) 618 rtlpriv->dm.entry_min_undec_sm_pwdb = tmpentry_min_pwdb; 619 else 620 rtlpriv->dm.entry_min_undec_sm_pwdb = 0; 621 622/* TODO: 623 * if (mac->opmode == NL80211_IFTYPE_STATION) { 624 * if (rtlpriv->rtlhal.fw_ready) { 625 * u32 param = (u32)(rtlpriv->dm.undec_sm_pwdb << 16); 626 * rtl8192c_set_rssi_cmd(hw, param); 627 * } 628 * } 629 */ 630} 631 632void rtl92c_dm_init_edca_turbo(struct ieee80211_hw *hw) 633{ 634 struct rtl_priv *rtlpriv = rtl_priv(hw); 635 rtlpriv->dm.current_turbo_edca = false; 636 rtlpriv->dm.is_any_nonbepkts = false; 637 rtlpriv->dm.is_cur_rdlstate = false; 638} 639EXPORT_SYMBOL(rtl92c_dm_init_edca_turbo); 640 641static void rtl92c_dm_check_edca_turbo(struct ieee80211_hw *hw) 642{ 643 struct rtl_priv *rtlpriv = rtl_priv(hw); 644 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw); 645 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 646 647 static u64 last_txok_cnt; 648 static u64 last_rxok_cnt; 649 static u32 last_bt_edca_ul; 650 static u32 last_bt_edca_dl; 651 u64 cur_txok_cnt = 0; 652 u64 cur_rxok_cnt = 0; 653 u32 edca_be_ul = 0x5ea42b; 654 u32 edca_be_dl = 0x5ea42b; 655 bool bt_change_edca = false; 656 657 if ((last_bt_edca_ul != rtlpcipriv->bt_coexist.bt_edca_ul) || 658 (last_bt_edca_dl != rtlpcipriv->bt_coexist.bt_edca_dl)) { 659 rtlpriv->dm.current_turbo_edca = false; 660 last_bt_edca_ul = rtlpcipriv->bt_coexist.bt_edca_ul; 661 last_bt_edca_dl = rtlpcipriv->bt_coexist.bt_edca_dl; 662 } 663 664 if (rtlpcipriv->bt_coexist.bt_edca_ul != 0) { 665 edca_be_ul = rtlpcipriv->bt_coexist.bt_edca_ul; 666 bt_change_edca = true; 667 } 668 669 if (rtlpcipriv->bt_coexist.bt_edca_dl != 0) { 670 edca_be_ul = rtlpcipriv->bt_coexist.bt_edca_dl; 671 bt_change_edca = true; 672 } 673 674 if (mac->link_state != MAC80211_LINKED) { 675 rtlpriv->dm.current_turbo_edca = false; 676 return; 677 } 678 679 if ((!mac->ht_enable) && (!rtlpcipriv->bt_coexist.bt_coexistence)) { 680 if (!(edca_be_ul & 0xffff0000)) 681 edca_be_ul |= 0x005e0000; 682 683 if (!(edca_be_dl & 0xffff0000)) 684 edca_be_dl |= 0x005e0000; 685 } 686 687 if ((bt_change_edca) || ((!rtlpriv->dm.is_any_nonbepkts) && 688 (!rtlpriv->dm.disable_framebursting))) { 689 690 cur_txok_cnt = rtlpriv->stats.txbytesunicast - last_txok_cnt; 691 cur_rxok_cnt = rtlpriv->stats.rxbytesunicast - last_rxok_cnt; 692 693 if (cur_rxok_cnt > 4 * cur_txok_cnt) { 694 if (!rtlpriv->dm.is_cur_rdlstate || 695 !rtlpriv->dm.current_turbo_edca) { 696 rtl_write_dword(rtlpriv, 697 REG_EDCA_BE_PARAM, 698 edca_be_dl); 699 rtlpriv->dm.is_cur_rdlstate = true; 700 } 701 } else { 702 if (rtlpriv->dm.is_cur_rdlstate || 703 !rtlpriv->dm.current_turbo_edca) { 704 rtl_write_dword(rtlpriv, 705 REG_EDCA_BE_PARAM, 706 edca_be_ul); 707 rtlpriv->dm.is_cur_rdlstate = false; 708 } 709 } 710 rtlpriv->dm.current_turbo_edca = true; 711 } else { 712 if (rtlpriv->dm.current_turbo_edca) { 713 u8 tmp = AC0_BE; 714 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM, 715 &tmp); 716 rtlpriv->dm.current_turbo_edca = false; 717 } 718 } 719 720 rtlpriv->dm.is_any_nonbepkts = false; 721 last_txok_cnt = rtlpriv->stats.txbytesunicast; 722 last_rxok_cnt = rtlpriv->stats.rxbytesunicast; 723} 724 725static void rtl92c_dm_txpower_tracking_callback_thermalmeter(struct ieee80211_hw 726 *hw) 727{ 728 struct rtl_priv *rtlpriv = rtl_priv(hw); 729 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 730 struct rtl_phy *rtlphy = &(rtlpriv->phy); 731 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 732 u8 thermalvalue, delta, delta_lck, delta_iqk; 733 long ele_a, ele_d, temp_cck, val_x, value32; 734 long val_y, ele_c = 0; 735 u8 ofdm_index[2], ofdm_index_old[2] = {0, 0}, cck_index_old = 0; 736 s8 cck_index = 0; 737 int i; 738 bool is2t = IS_92C_SERIAL(rtlhal->version); 739 s8 txpwr_level[3] = {0, 0, 0}; 740 u8 ofdm_min_index = 6, rf; 741 742 rtlpriv->dm.txpower_trackinginit = true; 743 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, 744 "rtl92c_dm_txpower_tracking_callback_thermalmeter\n"); 745 746 thermalvalue = (u8) rtl_get_rfreg(hw, RF90_PATH_A, RF_T_METER, 0x1f); 747 748 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, 749 "Readback Thermal Meter = 0x%x pre thermal meter 0x%x eeprom_thermalmeter 0x%x\n", 750 thermalvalue, rtlpriv->dm.thermalvalue, 751 rtlefuse->eeprom_thermalmeter); 752 753 rtl92c_phy_ap_calibrate(hw, (thermalvalue - 754 rtlefuse->eeprom_thermalmeter)); 755 if (is2t) 756 rf = 2; 757 else 758 rf = 1; 759 760 if (thermalvalue) { 761 ele_d = rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 762 MASKDWORD) & MASKOFDM_D; 763 764 for (i = 0; i < OFDM_TABLE_LENGTH; i++) { 765 if (ele_d == (ofdmswing_table[i] & MASKOFDM_D)) { 766 ofdm_index_old[0] = (u8) i; 767 768 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, 769 "Initial pathA ele_d reg0x%x = 0x%lx, ofdm_index=0x%x\n", 770 ROFDM0_XATXIQIMBALANCE, 771 ele_d, ofdm_index_old[0]); 772 break; 773 } 774 } 775 776 if (is2t) { 777 ele_d = rtl_get_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 778 MASKDWORD) & MASKOFDM_D; 779 780 for (i = 0; i < OFDM_TABLE_LENGTH; i++) { 781 if (ele_d == (ofdmswing_table[i] & 782 MASKOFDM_D)) { 783 ofdm_index_old[1] = (u8) i; 784 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, 785 DBG_LOUD, 786 "Initial pathB ele_d reg0x%x = 0x%lx, ofdm_index=0x%x\n", 787 ROFDM0_XBTXIQIMBALANCE, ele_d, 788 ofdm_index_old[1]); 789 break; 790 } 791 } 792 } 793 794 temp_cck = 795 rtl_get_bbreg(hw, RCCK0_TXFILTER2, MASKDWORD) & MASKCCK; 796 797 for (i = 0; i < CCK_TABLE_LENGTH; i++) { 798 if (rtlpriv->dm.cck_inch14) { 799 if (memcmp((void *)&temp_cck, 800 (void *)&cckswing_table_ch14[i][2], 801 4) == 0) { 802 cck_index_old = (u8) i; 803 804 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, 805 DBG_LOUD, 806 "Initial reg0x%x = 0x%lx, cck_index=0x%x, ch 14 %d\n", 807 RCCK0_TXFILTER2, temp_cck, 808 cck_index_old, 809 rtlpriv->dm.cck_inch14); 810 break; 811 } 812 } else { 813 if (memcmp((void *)&temp_cck, 814 (void *) 815 &cckswing_table_ch1ch13[i][2], 816 4) == 0) { 817 cck_index_old = (u8) i; 818 819 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, 820 DBG_LOUD, 821 "Initial reg0x%x = 0x%lx, cck_index=0x%x, ch14 %d\n", 822 RCCK0_TXFILTER2, temp_cck, 823 cck_index_old, 824 rtlpriv->dm.cck_inch14); 825 break; 826 } 827 } 828 } 829 830 if (!rtlpriv->dm.thermalvalue) { 831 rtlpriv->dm.thermalvalue = 832 rtlefuse->eeprom_thermalmeter; 833 rtlpriv->dm.thermalvalue_lck = thermalvalue; 834 rtlpriv->dm.thermalvalue_iqk = thermalvalue; 835 for (i = 0; i < rf; i++) 836 rtlpriv->dm.ofdm_index[i] = ofdm_index_old[i]; 837 rtlpriv->dm.cck_index = cck_index_old; 838 } 839 /* Handle USB High PA boards */ 840 841 delta = (thermalvalue > rtlpriv->dm.thermalvalue) ? 842 (thermalvalue - rtlpriv->dm.thermalvalue) : 843 (rtlpriv->dm.thermalvalue - thermalvalue); 844 845 delta_lck = (thermalvalue > rtlpriv->dm.thermalvalue_lck) ? 846 (thermalvalue - rtlpriv->dm.thermalvalue_lck) : 847 (rtlpriv->dm.thermalvalue_lck - thermalvalue); 848 849 delta_iqk = (thermalvalue > rtlpriv->dm.thermalvalue_iqk) ? 850 (thermalvalue - rtlpriv->dm.thermalvalue_iqk) : 851 (rtlpriv->dm.thermalvalue_iqk - thermalvalue); 852 853 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, 854 "Readback Thermal Meter = 0x%x pre thermal meter 0x%x eeprom_thermalmeter 0x%x delta 0x%x delta_lck 0x%x delta_iqk 0x%x\n", 855 thermalvalue, rtlpriv->dm.thermalvalue, 856 rtlefuse->eeprom_thermalmeter, delta, delta_lck, 857 delta_iqk); 858 859 if (delta_lck > 1) { 860 rtlpriv->dm.thermalvalue_lck = thermalvalue; 861 rtl92c_phy_lc_calibrate(hw); 862 } 863 864 if (delta > 0 && rtlpriv->dm.txpower_track_control) { 865 if (thermalvalue > rtlpriv->dm.thermalvalue) { 866 for (i = 0; i < rf; i++) 867 rtlpriv->dm.ofdm_index[i] -= delta; 868 rtlpriv->dm.cck_index -= delta; 869 } else { 870 for (i = 0; i < rf; i++) 871 rtlpriv->dm.ofdm_index[i] += delta; 872 rtlpriv->dm.cck_index += delta; 873 } 874 875 if (is2t) { 876 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, 877 "temp OFDM_A_index=0x%x, OFDM_B_index=0x%x, cck_index=0x%x\n", 878 rtlpriv->dm.ofdm_index[0], 879 rtlpriv->dm.ofdm_index[1], 880 rtlpriv->dm.cck_index); 881 } else { 882 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, 883 "temp OFDM_A_index=0x%x, cck_index=0x%x\n", 884 rtlpriv->dm.ofdm_index[0], 885 rtlpriv->dm.cck_index); 886 } 887 888 if (thermalvalue > rtlefuse->eeprom_thermalmeter) { 889 for (i = 0; i < rf; i++) 890 ofdm_index[i] = 891 rtlpriv->dm.ofdm_index[i] 892 + 1; 893 cck_index = rtlpriv->dm.cck_index + 1; 894 } else { 895 for (i = 0; i < rf; i++) 896 ofdm_index[i] = 897 rtlpriv->dm.ofdm_index[i]; 898 cck_index = rtlpriv->dm.cck_index; 899 } 900 901 for (i = 0; i < rf; i++) { 902 if (txpwr_level[i] >= 0 && 903 txpwr_level[i] <= 26) { 904 if (thermalvalue > 905 rtlefuse->eeprom_thermalmeter) { 906 if (delta < 5) 907 ofdm_index[i] -= 1; 908 909 else 910 ofdm_index[i] -= 2; 911 } else if (delta > 5 && thermalvalue < 912 rtlefuse-> 913 eeprom_thermalmeter) { 914 ofdm_index[i] += 1; 915 } 916 } else if (txpwr_level[i] >= 27 && 917 txpwr_level[i] <= 32 918 && thermalvalue > 919 rtlefuse->eeprom_thermalmeter) { 920 if (delta < 5) 921 ofdm_index[i] -= 1; 922 923 else 924 ofdm_index[i] -= 2; 925 } else if (txpwr_level[i] >= 32 && 926 txpwr_level[i] <= 38 && 927 thermalvalue > 928 rtlefuse->eeprom_thermalmeter 929 && delta > 5) { 930 ofdm_index[i] -= 1; 931 } 932 } 933 934 if (txpwr_level[i] >= 0 && txpwr_level[i] <= 26) { 935 if (thermalvalue > 936 rtlefuse->eeprom_thermalmeter) { 937 if (delta < 5) 938 cck_index -= 1; 939 940 else 941 cck_index -= 2; 942 } else if (delta > 5 && thermalvalue < 943 rtlefuse->eeprom_thermalmeter) { 944 cck_index += 1; 945 } 946 } else if (txpwr_level[i] >= 27 && 947 txpwr_level[i] <= 32 && 948 thermalvalue > 949 rtlefuse->eeprom_thermalmeter) { 950 if (delta < 5) 951 cck_index -= 1; 952 953 else 954 cck_index -= 2; 955 } else if (txpwr_level[i] >= 32 && 956 txpwr_level[i] <= 38 && 957 thermalvalue > rtlefuse->eeprom_thermalmeter 958 && delta > 5) { 959 cck_index -= 1; 960 } 961 962 for (i = 0; i < rf; i++) { 963 if (ofdm_index[i] > OFDM_TABLE_SIZE - 1) 964 ofdm_index[i] = OFDM_TABLE_SIZE - 1; 965 966 else if (ofdm_index[i] < ofdm_min_index) 967 ofdm_index[i] = ofdm_min_index; 968 } 969 970 if (cck_index > CCK_TABLE_SIZE - 1) 971 cck_index = CCK_TABLE_SIZE - 1; 972 else if (cck_index < 0) 973 cck_index = 0; 974 975 if (is2t) { 976 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, 977 "new OFDM_A_index=0x%x, OFDM_B_index=0x%x, cck_index=0x%x\n", 978 ofdm_index[0], ofdm_index[1], 979 cck_index); 980 } else { 981 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, 982 "new OFDM_A_index=0x%x, cck_index=0x%x\n", 983 ofdm_index[0], cck_index); 984 } 985 } 986 987 if (rtlpriv->dm.txpower_track_control && delta != 0) { 988 ele_d = 989 (ofdmswing_table[ofdm_index[0]] & 0xFFC00000) >> 22; 990 val_x = rtlphy->reg_e94; 991 val_y = rtlphy->reg_e9c; 992 993 if (val_x != 0) { 994 if ((val_x & 0x00000200) != 0) 995 val_x = val_x | 0xFFFFFC00; 996 ele_a = ((val_x * ele_d) >> 8) & 0x000003FF; 997 998 if ((val_y & 0x00000200) != 0) 999 val_y = val_y | 0xFFFFFC00; 1000 ele_c = ((val_y * ele_d) >> 8) & 0x000003FF; 1001 1002 value32 = (ele_d << 22) | 1003 ((ele_c & 0x3F) << 16) | ele_a; 1004 1005 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 1006 MASKDWORD, value32); 1007 1008 value32 = (ele_c & 0x000003C0) >> 6; 1009 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, MASKH4BITS, 1010 value32); 1011 1012 value32 = ((val_x * ele_d) >> 7) & 0x01; 1013 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, 1014 BIT(31), value32); 1015 1016 value32 = ((val_y * ele_d) >> 7) & 0x01; 1017 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, 1018 BIT(29), value32); 1019 } else { 1020 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 1021 MASKDWORD, 1022 ofdmswing_table[ofdm_index[0]]); 1023 1024 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, MASKH4BITS, 1025 0x00); 1026 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, 1027 BIT(31) | BIT(29), 0x00); 1028 } 1029 1030 if (!rtlpriv->dm.cck_inch14) { 1031 rtl_write_byte(rtlpriv, 0xa22, 1032 cckswing_table_ch1ch13[cck_index] 1033 [0]); 1034 rtl_write_byte(rtlpriv, 0xa23, 1035 cckswing_table_ch1ch13[cck_index] 1036 [1]); 1037 rtl_write_byte(rtlpriv, 0xa24, 1038 cckswing_table_ch1ch13[cck_index] 1039 [2]); 1040 rtl_write_byte(rtlpriv, 0xa25, 1041 cckswing_table_ch1ch13[cck_index] 1042 [3]); 1043 rtl_write_byte(rtlpriv, 0xa26, 1044 cckswing_table_ch1ch13[cck_index] 1045 [4]); 1046 rtl_write_byte(rtlpriv, 0xa27, 1047 cckswing_table_ch1ch13[cck_index] 1048 [5]); 1049 rtl_write_byte(rtlpriv, 0xa28, 1050 cckswing_table_ch1ch13[cck_index] 1051 [6]); 1052 rtl_write_byte(rtlpriv, 0xa29, 1053 cckswing_table_ch1ch13[cck_index] 1054 [7]); 1055 } else { 1056 rtl_write_byte(rtlpriv, 0xa22, 1057 cckswing_table_ch14[cck_index] 1058 [0]); 1059 rtl_write_byte(rtlpriv, 0xa23, 1060 cckswing_table_ch14[cck_index] 1061 [1]); 1062 rtl_write_byte(rtlpriv, 0xa24, 1063 cckswing_table_ch14[cck_index] 1064 [2]); 1065 rtl_write_byte(rtlpriv, 0xa25, 1066 cckswing_table_ch14[cck_index] 1067 [3]); 1068 rtl_write_byte(rtlpriv, 0xa26, 1069 cckswing_table_ch14[cck_index] 1070 [4]); 1071 rtl_write_byte(rtlpriv, 0xa27, 1072 cckswing_table_ch14[cck_index] 1073 [5]); 1074 rtl_write_byte(rtlpriv, 0xa28, 1075 cckswing_table_ch14[cck_index] 1076 [6]); 1077 rtl_write_byte(rtlpriv, 0xa29, 1078 cckswing_table_ch14[cck_index] 1079 [7]); 1080 } 1081 1082 if (is2t) { 1083 ele_d = (ofdmswing_table[ofdm_index[1]] & 1084 0xFFC00000) >> 22; 1085 1086 val_x = rtlphy->reg_eb4; 1087 val_y = rtlphy->reg_ebc; 1088 1089 if (val_x != 0) { 1090 if ((val_x & 0x00000200) != 0) 1091 val_x = val_x | 0xFFFFFC00; 1092 ele_a = ((val_x * ele_d) >> 8) & 1093 0x000003FF; 1094 1095 if ((val_y & 0x00000200) != 0) 1096 val_y = val_y | 0xFFFFFC00; 1097 ele_c = ((val_y * ele_d) >> 8) & 1098 0x00003FF; 1099 1100 value32 = (ele_d << 22) | 1101 ((ele_c & 0x3F) << 16) | ele_a; 1102 rtl_set_bbreg(hw, 1103 ROFDM0_XBTXIQIMBALANCE, 1104 MASKDWORD, value32); 1105 1106 value32 = (ele_c & 0x000003C0) >> 6; 1107 rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 1108 MASKH4BITS, value32); 1109 1110 value32 = ((val_x * ele_d) >> 7) & 0x01; 1111 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, 1112 BIT(27), value32); 1113 1114 value32 = ((val_y * ele_d) >> 7) & 0x01; 1115 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, 1116 BIT(25), value32); 1117 } else { 1118 rtl_set_bbreg(hw, 1119 ROFDM0_XBTXIQIMBALANCE, 1120 MASKDWORD, 1121 ofdmswing_table[ofdm_index 1122 [1]]); 1123 rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 1124 MASKH4BITS, 0x00); 1125 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, 1126 BIT(27) | BIT(25), 0x00); 1127 } 1128 1129 } 1130 } 1131 1132 if (delta_iqk > 3) { 1133 rtlpriv->dm.thermalvalue_iqk = thermalvalue; 1134 rtl92c_phy_iq_calibrate(hw, false); 1135 } 1136 1137 if (rtlpriv->dm.txpower_track_control) 1138 rtlpriv->dm.thermalvalue = thermalvalue; 1139 } 1140 1141 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, "<===\n"); 1142 1143} 1144 1145static void rtl92c_dm_initialize_txpower_tracking_thermalmeter( 1146 struct ieee80211_hw *hw) 1147{ 1148 struct rtl_priv *rtlpriv = rtl_priv(hw); 1149 1150 rtlpriv->dm.txpower_tracking = true; 1151 rtlpriv->dm.txpower_trackinginit = false; 1152 1153 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, 1154 "pMgntInfo->txpower_tracking = %d\n", 1155 rtlpriv->dm.txpower_tracking); 1156} 1157 1158static void rtl92c_dm_initialize_txpower_tracking(struct ieee80211_hw *hw) 1159{ 1160 rtl92c_dm_initialize_txpower_tracking_thermalmeter(hw); 1161} 1162 1163static void rtl92c_dm_txpower_tracking_directcall(struct ieee80211_hw *hw) 1164{ 1165 rtl92c_dm_txpower_tracking_callback_thermalmeter(hw); 1166} 1167 1168static void rtl92c_dm_check_txpower_tracking_thermal_meter( 1169 struct ieee80211_hw *hw) 1170{ 1171 struct rtl_priv *rtlpriv = rtl_priv(hw); 1172 static u8 tm_trigger; 1173 1174 if (!rtlpriv->dm.txpower_tracking) 1175 return; 1176 1177 if (!tm_trigger) { 1178 rtl_set_rfreg(hw, RF90_PATH_A, RF_T_METER, RFREG_OFFSET_MASK, 1179 0x60); 1180 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, 1181 "Trigger 92S Thermal Meter!!\n"); 1182 tm_trigger = 1; 1183 return; 1184 } else { 1185 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, 1186 "Schedule TxPowerTracking direct call!!\n"); 1187 rtl92c_dm_txpower_tracking_directcall(hw); 1188 tm_trigger = 0; 1189 } 1190} 1191 1192void rtl92c_dm_check_txpower_tracking(struct ieee80211_hw *hw) 1193{ 1194 rtl92c_dm_check_txpower_tracking_thermal_meter(hw); 1195} 1196EXPORT_SYMBOL(rtl92c_dm_check_txpower_tracking); 1197 1198void rtl92c_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw) 1199{ 1200 struct rtl_priv *rtlpriv = rtl_priv(hw); 1201 struct rate_adaptive *p_ra = &(rtlpriv->ra); 1202 1203 p_ra->ratr_state = DM_RATR_STA_INIT; 1204 p_ra->pre_ratr_state = DM_RATR_STA_INIT; 1205 1206 if (rtlpriv->dm.dm_type == DM_TYPE_BYDRIVER) 1207 rtlpriv->dm.useramask = true; 1208 else 1209 rtlpriv->dm.useramask = false; 1210 1211} 1212EXPORT_SYMBOL(rtl92c_dm_init_rate_adaptive_mask); 1213 1214static void rtl92c_dm_init_dynamic_bb_powersaving(struct ieee80211_hw *hw) 1215{ 1216 struct rtl_priv *rtlpriv = rtl_priv(hw); 1217 struct ps_t *dm_pstable = &rtlpriv->dm_pstable; 1218 1219 dm_pstable->pre_ccastate = CCA_MAX; 1220 dm_pstable->cur_ccasate = CCA_MAX; 1221 dm_pstable->pre_rfstate = RF_MAX; 1222 dm_pstable->cur_rfstate = RF_MAX; 1223 dm_pstable->rssi_val_min = 0; 1224} 1225 1226void rtl92c_dm_rf_saving(struct ieee80211_hw *hw, u8 bforce_in_normal) 1227{ 1228 struct rtl_priv *rtlpriv = rtl_priv(hw); 1229 struct ps_t *dm_pstable = &rtlpriv->dm_pstable; 1230 1231 if (!rtlpriv->reg_init) { 1232 rtlpriv->reg_874 = (rtl_get_bbreg(hw, 1233 RFPGA0_XCD_RFINTERFACESW, 1234 MASKDWORD) & 0x1CC000) >> 14; 1235 1236 rtlpriv->reg_c70 = (rtl_get_bbreg(hw, ROFDM0_AGCPARAMETER1, 1237 MASKDWORD) & BIT(3)) >> 3; 1238 1239 rtlpriv->reg_85c = (rtl_get_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL, 1240 MASKDWORD) & 0xFF000000) >> 24; 1241 1242 rtlpriv->reg_a74 = (rtl_get_bbreg(hw, 0xa74, MASKDWORD) & 1243 0xF000) >> 12; 1244 1245 rtlpriv->reg_init = true; 1246 } 1247 1248 if (!bforce_in_normal) { 1249 if (dm_pstable->rssi_val_min != 0) { 1250 if (dm_pstable->pre_rfstate == RF_NORMAL) { 1251 if (dm_pstable->rssi_val_min >= 30) 1252 dm_pstable->cur_rfstate = RF_SAVE; 1253 else 1254 dm_pstable->cur_rfstate = RF_NORMAL; 1255 } else { 1256 if (dm_pstable->rssi_val_min <= 25) 1257 dm_pstable->cur_rfstate = RF_NORMAL; 1258 else 1259 dm_pstable->cur_rfstate = RF_SAVE; 1260 } 1261 } else { 1262 dm_pstable->cur_rfstate = RF_MAX; 1263 } 1264 } else { 1265 dm_pstable->cur_rfstate = RF_NORMAL; 1266 } 1267 1268 if (dm_pstable->pre_rfstate != dm_pstable->cur_rfstate) { 1269 if (dm_pstable->cur_rfstate == RF_SAVE) { 1270 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, 1271 0x1C0000, 0x2); 1272 rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, BIT(3), 0); 1273 rtl_set_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL, 1274 0xFF000000, 0x63); 1275 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, 1276 0xC000, 0x2); 1277 rtl_set_bbreg(hw, 0xa74, 0xF000, 0x3); 1278 rtl_set_bbreg(hw, 0x818, BIT(28), 0x0); 1279 rtl_set_bbreg(hw, 0x818, BIT(28), 0x1); 1280 } else { 1281 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, 1282 0x1CC000, rtlpriv->reg_874); 1283 rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, BIT(3), 1284 rtlpriv->reg_c70); 1285 rtl_set_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL, 0xFF000000, 1286 rtlpriv->reg_85c); 1287 rtl_set_bbreg(hw, 0xa74, 0xF000, rtlpriv->reg_a74); 1288 rtl_set_bbreg(hw, 0x818, BIT(28), 0x0); 1289 } 1290 1291 dm_pstable->pre_rfstate = dm_pstable->cur_rfstate; 1292 } 1293} 1294EXPORT_SYMBOL(rtl92c_dm_rf_saving); 1295 1296static void rtl92c_dm_dynamic_bb_powersaving(struct ieee80211_hw *hw) 1297{ 1298 struct rtl_priv *rtlpriv = rtl_priv(hw); 1299 struct ps_t *dm_pstable = &rtlpriv->dm_pstable; 1300 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1301 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1302 1303 /* Determine the minimum RSSI */ 1304 if (((mac->link_state == MAC80211_NOLINK)) && 1305 (rtlpriv->dm.entry_min_undec_sm_pwdb == 0)) { 1306 dm_pstable->rssi_val_min = 0; 1307 RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD, "Not connected to any\n"); 1308 } 1309 1310 if (mac->link_state == MAC80211_LINKED) { 1311 if (mac->opmode == NL80211_IFTYPE_ADHOC) { 1312 dm_pstable->rssi_val_min = 1313 rtlpriv->dm.entry_min_undec_sm_pwdb; 1314 RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD, 1315 "AP Client PWDB = 0x%lx\n", 1316 dm_pstable->rssi_val_min); 1317 } else { 1318 dm_pstable->rssi_val_min = rtlpriv->dm.undec_sm_pwdb; 1319 RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD, 1320 "STA Default Port PWDB = 0x%lx\n", 1321 dm_pstable->rssi_val_min); 1322 } 1323 } else { 1324 dm_pstable->rssi_val_min = 1325 rtlpriv->dm.entry_min_undec_sm_pwdb; 1326 1327 RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD, 1328 "AP Ext Port PWDB = 0x%lx\n", 1329 dm_pstable->rssi_val_min); 1330 } 1331 1332 /* Power Saving for 92C */ 1333 if (IS_92C_SERIAL(rtlhal->version)) 1334 ;/* rtl92c_dm_1r_cca(hw); */ 1335 else 1336 rtl92c_dm_rf_saving(hw, false); 1337} 1338 1339void rtl92c_dm_init(struct ieee80211_hw *hw) 1340{ 1341 struct rtl_priv *rtlpriv = rtl_priv(hw); 1342 1343 rtlpriv->dm.dm_type = DM_TYPE_BYDRIVER; 1344 rtlpriv->dm.dm_flag = DYNAMIC_FUNC_DISABLE | DYNAMIC_FUNC_DIG; 1345 rtlpriv->dm.undec_sm_pwdb = -1; 1346 rtlpriv->dm.undec_sm_cck = -1; 1347 rtlpriv->dm.dm_initialgain_enable = true; 1348 rtl_dm_diginit(hw, 0x20); 1349 1350 rtlpriv->dm.dm_flag |= HAL_DM_HIPWR_DISABLE; 1351 rtl92c_dm_init_dynamic_txpower(hw); 1352 1353 rtl92c_dm_init_edca_turbo(hw); 1354 rtl92c_dm_init_rate_adaptive_mask(hw); 1355 rtlpriv->dm.dm_flag |= DYNAMIC_FUNC_SS; 1356 rtl92c_dm_initialize_txpower_tracking(hw); 1357 rtl92c_dm_init_dynamic_bb_powersaving(hw); 1358 1359 rtlpriv->dm.ofdm_pkt_cnt = 0; 1360 rtlpriv->dm.dm_rssi_sel = RSSI_DEFAULT; 1361} 1362EXPORT_SYMBOL(rtl92c_dm_init); 1363 1364void rtl92c_dm_dynamic_txpower(struct ieee80211_hw *hw) 1365{ 1366 struct rtl_priv *rtlpriv = rtl_priv(hw); 1367 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1368 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1369 long undec_sm_pwdb; 1370 1371 if (!rtlpriv->dm.dynamic_txpower_enable) 1372 return; 1373 1374 if (rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) { 1375 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL; 1376 return; 1377 } 1378 1379 if ((mac->link_state < MAC80211_LINKED) && 1380 (rtlpriv->dm.entry_min_undec_sm_pwdb == 0)) { 1381 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE, 1382 "Not connected to any\n"); 1383 1384 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL; 1385 1386 rtlpriv->dm.last_dtp_lvl = TXHIGHPWRLEVEL_NORMAL; 1387 return; 1388 } 1389 1390 if (mac->link_state >= MAC80211_LINKED) { 1391 if (mac->opmode == NL80211_IFTYPE_ADHOC) { 1392 undec_sm_pwdb = rtlpriv->dm.entry_min_undec_sm_pwdb; 1393 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 1394 "AP Client PWDB = 0x%lx\n", 1395 undec_sm_pwdb); 1396 } else { 1397 undec_sm_pwdb = rtlpriv->dm.undec_sm_pwdb; 1398 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 1399 "STA Default Port PWDB = 0x%lx\n", 1400 undec_sm_pwdb); 1401 } 1402 } else { 1403 undec_sm_pwdb = rtlpriv->dm.entry_min_undec_sm_pwdb; 1404 1405 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 1406 "AP Ext Port PWDB = 0x%lx\n", 1407 undec_sm_pwdb); 1408 } 1409 1410 if (undec_sm_pwdb >= TX_POWER_NEAR_FIELD_THRESH_LVL2) { 1411 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_LEVEL2; 1412 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 1413 "TXHIGHPWRLEVEL_LEVEL1 (TxPwr=0x0)\n"); 1414 } else if ((undec_sm_pwdb < (TX_POWER_NEAR_FIELD_THRESH_LVL2 - 3)) && 1415 (undec_sm_pwdb >= TX_POWER_NEAR_FIELD_THRESH_LVL1)) { 1416 1417 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_LEVEL1; 1418 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 1419 "TXHIGHPWRLEVEL_LEVEL1 (TxPwr=0x10)\n"); 1420 } else if (undec_sm_pwdb < (TX_POWER_NEAR_FIELD_THRESH_LVL1 - 5)) { 1421 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL; 1422 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 1423 "TXHIGHPWRLEVEL_NORMAL\n"); 1424 } 1425 1426 if ((rtlpriv->dm.dynamic_txhighpower_lvl != rtlpriv->dm.last_dtp_lvl)) { 1427 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 1428 "PHY_SetTxPowerLevel8192S() Channel = %d\n", 1429 rtlphy->current_channel); 1430 rtl92c_phy_set_txpower_level(hw, rtlphy->current_channel); 1431 if (rtlpriv->dm.dynamic_txhighpower_lvl == 1432 TXHIGHPWRLEVEL_NORMAL) 1433 dm_restorepowerindex(hw); 1434 else if (rtlpriv->dm.dynamic_txhighpower_lvl == 1435 TXHIGHPWRLEVEL_LEVEL1) 1436 dm_writepowerindex(hw, 0x14); 1437 else if (rtlpriv->dm.dynamic_txhighpower_lvl == 1438 TXHIGHPWRLEVEL_LEVEL2) 1439 dm_writepowerindex(hw, 0x10); 1440 } 1441 rtlpriv->dm.last_dtp_lvl = rtlpriv->dm.dynamic_txhighpower_lvl; 1442} 1443 1444void rtl92c_dm_watchdog(struct ieee80211_hw *hw) 1445{ 1446 struct rtl_priv *rtlpriv = rtl_priv(hw); 1447 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1448 bool fw_current_inpsmode = false; 1449 bool fw_ps_awake = true; 1450 1451 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS, 1452 (u8 *) (&fw_current_inpsmode)); 1453 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FWLPS_RF_ON, 1454 (u8 *) (&fw_ps_awake)); 1455 1456 if (ppsc->p2p_ps_info.p2p_ps_mode) 1457 fw_ps_awake = false; 1458 1459 if ((ppsc->rfpwr_state == ERFON) && ((!fw_current_inpsmode) && 1460 fw_ps_awake) 1461 && (!ppsc->rfchange_inprogress)) { 1462 rtl92c_dm_pwdb_monitor(hw); 1463 rtl92c_dm_dig(hw); 1464 rtl92c_dm_false_alarm_counter_statistics(hw); 1465 rtl92c_dm_dynamic_bb_powersaving(hw); 1466 rtl92c_dm_dynamic_txpower(hw); 1467 rtl92c_dm_check_txpower_tracking(hw); 1468 /* rtl92c_dm_refresh_rate_adaptive_mask(hw); */ 1469 rtl92c_dm_bt_coexist(hw); 1470 rtl92c_dm_check_edca_turbo(hw); 1471 } 1472} 1473EXPORT_SYMBOL(rtl92c_dm_watchdog); 1474 1475u8 rtl92c_bt_rssi_state_change(struct ieee80211_hw *hw) 1476{ 1477 struct rtl_priv *rtlpriv = rtl_priv(hw); 1478 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw); 1479 long undec_sm_pwdb; 1480 u8 curr_bt_rssi_state = 0x00; 1481 1482 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) { 1483 undec_sm_pwdb = GET_UNDECORATED_AVERAGE_RSSI(rtlpriv); 1484 } else { 1485 if (rtlpriv->dm.entry_min_undec_sm_pwdb == 0) 1486 undec_sm_pwdb = 100; 1487 else 1488 undec_sm_pwdb = rtlpriv->dm.entry_min_undec_sm_pwdb; 1489 } 1490 1491 /* Check RSSI to determine HighPower/NormalPower state for 1492 * BT coexistence. */ 1493 if (undec_sm_pwdb >= 67) 1494 curr_bt_rssi_state &= (~BT_RSSI_STATE_NORMAL_POWER); 1495 else if (undec_sm_pwdb < 62) 1496 curr_bt_rssi_state |= BT_RSSI_STATE_NORMAL_POWER; 1497 1498 /* Check RSSI to determine AMPDU setting for BT coexistence. */ 1499 if (undec_sm_pwdb >= 40) 1500 curr_bt_rssi_state &= (~BT_RSSI_STATE_AMDPU_OFF); 1501 else if (undec_sm_pwdb <= 32) 1502 curr_bt_rssi_state |= BT_RSSI_STATE_AMDPU_OFF; 1503 1504 /* Marked RSSI state. It will be used to determine BT coexistence 1505 * setting later. */ 1506 if (undec_sm_pwdb < 35) 1507 curr_bt_rssi_state |= BT_RSSI_STATE_SPECIAL_LOW; 1508 else 1509 curr_bt_rssi_state &= (~BT_RSSI_STATE_SPECIAL_LOW); 1510 1511 /* Check BT state related to BT_Idle in B/G mode. */ 1512 if (undec_sm_pwdb < 15) 1513 curr_bt_rssi_state |= BT_RSSI_STATE_BG_EDCA_LOW; 1514 else 1515 curr_bt_rssi_state &= (~BT_RSSI_STATE_BG_EDCA_LOW); 1516 1517 if (curr_bt_rssi_state != rtlpcipriv->bt_coexist.bt_rssi_state) { 1518 rtlpcipriv->bt_coexist.bt_rssi_state = curr_bt_rssi_state; 1519 return true; 1520 } else { 1521 return false; 1522 } 1523} 1524EXPORT_SYMBOL(rtl92c_bt_rssi_state_change); 1525 1526static bool rtl92c_bt_state_change(struct ieee80211_hw *hw) 1527{ 1528 struct rtl_priv *rtlpriv = rtl_priv(hw); 1529 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw); 1530 1531 u32 polling, ratio_tx, ratio_pri; 1532 u32 bt_tx, bt_pri; 1533 u8 bt_state; 1534 u8 cur_service_type; 1535 1536 if (rtlpriv->mac80211.link_state < MAC80211_LINKED) 1537 return false; 1538 1539 bt_state = rtl_read_byte(rtlpriv, 0x4fd); 1540 bt_tx = rtl_read_dword(rtlpriv, 0x488); 1541 bt_tx = bt_tx & 0x00ffffff; 1542 bt_pri = rtl_read_dword(rtlpriv, 0x48c); 1543 bt_pri = bt_pri & 0x00ffffff; 1544 polling = rtl_read_dword(rtlpriv, 0x490); 1545 1546 if (bt_tx == 0xffffffff && bt_pri == 0xffffffff && 1547 polling == 0xffffffff && bt_state == 0xff) 1548 return false; 1549 1550 bt_state &= BIT_OFFSET_LEN_MASK_32(0, 1); 1551 if (bt_state != rtlpcipriv->bt_coexist.bt_cur_state) { 1552 rtlpcipriv->bt_coexist.bt_cur_state = bt_state; 1553 1554 if (rtlpcipriv->bt_coexist.reg_bt_sco == 3) { 1555 rtlpcipriv->bt_coexist.bt_service = BT_IDLE; 1556 1557 bt_state = bt_state | 1558 ((rtlpcipriv->bt_coexist.bt_ant_isolation == 1) ? 1559 0 : BIT_OFFSET_LEN_MASK_32(1, 1)) | 1560 BIT_OFFSET_LEN_MASK_32(2, 1); 1561 rtl_write_byte(rtlpriv, 0x4fd, bt_state); 1562 } 1563 return true; 1564 } 1565 1566 ratio_tx = bt_tx * 1000 / polling; 1567 ratio_pri = bt_pri * 1000 / polling; 1568 rtlpcipriv->bt_coexist.ratio_tx = ratio_tx; 1569 rtlpcipriv->bt_coexist.ratio_pri = ratio_pri; 1570 1571 if (bt_state && rtlpcipriv->bt_coexist.reg_bt_sco == 3) { 1572 1573 if ((ratio_tx < 30) && (ratio_pri < 30)) 1574 cur_service_type = BT_IDLE; 1575 else if ((ratio_pri > 110) && (ratio_pri < 250)) 1576 cur_service_type = BT_SCO; 1577 else if ((ratio_tx >= 200) && (ratio_pri >= 200)) 1578 cur_service_type = BT_BUSY; 1579 else if ((ratio_tx >= 350) && (ratio_tx < 500)) 1580 cur_service_type = BT_OTHERBUSY; 1581 else if (ratio_tx >= 500) 1582 cur_service_type = BT_PAN; 1583 else 1584 cur_service_type = BT_OTHER_ACTION; 1585 1586 if (cur_service_type != rtlpcipriv->bt_coexist.bt_service) { 1587 rtlpcipriv->bt_coexist.bt_service = cur_service_type; 1588 bt_state = bt_state | 1589 ((rtlpcipriv->bt_coexist.bt_ant_isolation == 1) ? 1590 0 : BIT_OFFSET_LEN_MASK_32(1, 1)) | 1591 ((rtlpcipriv->bt_coexist.bt_service != BT_IDLE) ? 1592 0 : BIT_OFFSET_LEN_MASK_32(2, 1)); 1593 1594 /* Add interrupt migration when bt is not ini 1595 * idle state (no traffic). */ 1596 if (rtlpcipriv->bt_coexist.bt_service != BT_IDLE) { 1597 rtl_write_word(rtlpriv, 0x504, 0x0ccc); 1598 rtl_write_byte(rtlpriv, 0x506, 0x54); 1599 rtl_write_byte(rtlpriv, 0x507, 0x54); 1600 } else { 1601 rtl_write_byte(rtlpriv, 0x506, 0x00); 1602 rtl_write_byte(rtlpriv, 0x507, 0x00); 1603 } 1604 1605 rtl_write_byte(rtlpriv, 0x4fd, bt_state); 1606 return true; 1607 } 1608 } 1609 1610 return false; 1611 1612} 1613 1614static bool rtl92c_bt_wifi_connect_change(struct ieee80211_hw *hw) 1615{ 1616 struct rtl_priv *rtlpriv = rtl_priv(hw); 1617 static bool media_connect; 1618 1619 if (rtlpriv->mac80211.link_state < MAC80211_LINKED) { 1620 media_connect = false; 1621 } else { 1622 if (!media_connect) { 1623 media_connect = true; 1624 return true; 1625 } 1626 media_connect = true; 1627 } 1628 1629 return false; 1630} 1631 1632static void rtl92c_bt_set_normal(struct ieee80211_hw *hw) 1633{ 1634 struct rtl_priv *rtlpriv = rtl_priv(hw); 1635 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw); 1636 1637 1638 if (rtlpcipriv->bt_coexist.bt_service == BT_OTHERBUSY) { 1639 rtlpcipriv->bt_coexist.bt_edca_ul = 0x5ea72b; 1640 rtlpcipriv->bt_coexist.bt_edca_dl = 0x5ea72b; 1641 } else if (rtlpcipriv->bt_coexist.bt_service == BT_BUSY) { 1642 rtlpcipriv->bt_coexist.bt_edca_ul = 0x5eb82f; 1643 rtlpcipriv->bt_coexist.bt_edca_dl = 0x5eb82f; 1644 } else if (rtlpcipriv->bt_coexist.bt_service == BT_SCO) { 1645 if (rtlpcipriv->bt_coexist.ratio_tx > 160) { 1646 rtlpcipriv->bt_coexist.bt_edca_ul = 0x5ea72f; 1647 rtlpcipriv->bt_coexist.bt_edca_dl = 0x5ea72f; 1648 } else { 1649 rtlpcipriv->bt_coexist.bt_edca_ul = 0x5ea32b; 1650 rtlpcipriv->bt_coexist.bt_edca_dl = 0x5ea42b; 1651 } 1652 } else { 1653 rtlpcipriv->bt_coexist.bt_edca_ul = 0; 1654 rtlpcipriv->bt_coexist.bt_edca_dl = 0; 1655 } 1656 1657 if ((rtlpcipriv->bt_coexist.bt_service != BT_IDLE) && 1658 (rtlpriv->mac80211.mode == WIRELESS_MODE_G || 1659 (rtlpriv->mac80211.mode == (WIRELESS_MODE_G | WIRELESS_MODE_B))) && 1660 (rtlpcipriv->bt_coexist.bt_rssi_state & 1661 BT_RSSI_STATE_BG_EDCA_LOW)) { 1662 rtlpcipriv->bt_coexist.bt_edca_ul = 0x5eb82b; 1663 rtlpcipriv->bt_coexist.bt_edca_dl = 0x5eb82b; 1664 } 1665} 1666 1667static void rtl92c_bt_ant_isolation(struct ieee80211_hw *hw, u8 tmp1byte) 1668{ 1669 struct rtl_priv *rtlpriv = rtl_priv(hw); 1670 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw); 1671 1672 1673 /* Only enable HW BT coexist when BT in "Busy" state. */ 1674 if (rtlpriv->mac80211.vendor == PEER_CISCO && 1675 rtlpcipriv->bt_coexist.bt_service == BT_OTHER_ACTION) { 1676 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0); 1677 } else { 1678 if ((rtlpcipriv->bt_coexist.bt_service == BT_BUSY) && 1679 (rtlpcipriv->bt_coexist.bt_rssi_state & 1680 BT_RSSI_STATE_NORMAL_POWER)) { 1681 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0); 1682 } else if ((rtlpcipriv->bt_coexist.bt_service == 1683 BT_OTHER_ACTION) && (rtlpriv->mac80211.mode < 1684 WIRELESS_MODE_N_24G) && 1685 (rtlpcipriv->bt_coexist.bt_rssi_state & 1686 BT_RSSI_STATE_SPECIAL_LOW)) { 1687 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0); 1688 } else if (rtlpcipriv->bt_coexist.bt_service == BT_PAN) { 1689 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, tmp1byte); 1690 } else { 1691 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, tmp1byte); 1692 } 1693 } 1694 1695 if (rtlpcipriv->bt_coexist.bt_service == BT_PAN) 1696 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x10100); 1697 else 1698 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x0); 1699 1700 if (rtlpcipriv->bt_coexist.bt_rssi_state & 1701 BT_RSSI_STATE_NORMAL_POWER) { 1702 rtl92c_bt_set_normal(hw); 1703 } else { 1704 rtlpcipriv->bt_coexist.bt_edca_ul = 0; 1705 rtlpcipriv->bt_coexist.bt_edca_dl = 0; 1706 } 1707 1708 if (rtlpcipriv->bt_coexist.bt_service != BT_IDLE) { 1709 rtlpriv->cfg->ops->set_rfreg(hw, 1710 RF90_PATH_A, 1711 0x1e, 1712 0xf0, 0xf); 1713 } else { 1714 rtlpriv->cfg->ops->set_rfreg(hw, 1715 RF90_PATH_A, 0x1e, 0xf0, 1716 rtlpcipriv->bt_coexist.bt_rfreg_origin_1e); 1717 } 1718 1719 if (!rtlpriv->dm.dynamic_txpower_enable) { 1720 if (rtlpcipriv->bt_coexist.bt_service != BT_IDLE) { 1721 if (rtlpcipriv->bt_coexist.bt_rssi_state & 1722 BT_RSSI_STATE_TXPOWER_LOW) { 1723 rtlpriv->dm.dynamic_txhighpower_lvl = 1724 TXHIGHPWRLEVEL_BT2; 1725 } else { 1726 rtlpriv->dm.dynamic_txhighpower_lvl = 1727 TXHIGHPWRLEVEL_BT1; 1728 } 1729 } else { 1730 rtlpriv->dm.dynamic_txhighpower_lvl = 1731 TXHIGHPWRLEVEL_NORMAL; 1732 } 1733 rtl92c_phy_set_txpower_level(hw, 1734 rtlpriv->phy.current_channel); 1735 } 1736} 1737 1738static void rtl92c_check_bt_change(struct ieee80211_hw *hw) 1739{ 1740 struct rtl_priv *rtlpriv = rtl_priv(hw); 1741 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw); 1742 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1743 u8 tmp1byte = 0; 1744 1745 if (IS_81XXC_VENDOR_UMC_B_CUT(rtlhal->version) && 1746 rtlpcipriv->bt_coexist.bt_coexistence) 1747 tmp1byte |= BIT(5); 1748 if (rtlpcipriv->bt_coexist.bt_cur_state) { 1749 if (rtlpcipriv->bt_coexist.bt_ant_isolation) 1750 rtl92c_bt_ant_isolation(hw, tmp1byte); 1751 } else { 1752 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, tmp1byte); 1753 rtlpriv->cfg->ops->set_rfreg(hw, RF90_PATH_A, 0x1e, 0xf0, 1754 rtlpcipriv->bt_coexist.bt_rfreg_origin_1e); 1755 1756 rtlpcipriv->bt_coexist.bt_edca_ul = 0; 1757 rtlpcipriv->bt_coexist.bt_edca_dl = 0; 1758 } 1759} 1760 1761void rtl92c_dm_bt_coexist(struct ieee80211_hw *hw) 1762{ 1763 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw); 1764 1765 bool wifi_connect_change; 1766 bool bt_state_change; 1767 bool rssi_state_change; 1768 1769 if ((rtlpcipriv->bt_coexist.bt_coexistence) && 1770 (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4)) { 1771 1772 wifi_connect_change = rtl92c_bt_wifi_connect_change(hw); 1773 bt_state_change = rtl92c_bt_state_change(hw); 1774 rssi_state_change = rtl92c_bt_rssi_state_change(hw); 1775 1776 if (wifi_connect_change || bt_state_change || rssi_state_change) 1777 rtl92c_check_bt_change(hw); 1778 } 1779} 1780EXPORT_SYMBOL(rtl92c_dm_bt_coexist); 1781