1/****************************************************************************** 2 * 3 * GPL LICENSE SUMMARY 4 * 5 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of version 2 of the GNU General Public License as 9 * published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, but 12 * WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, 19 * USA 20 * 21 * The full GNU General Public License is included in this distribution 22 * in the file called LICENSE.GPL. 23 * 24 * Contact Information: 25 * Intel Linux Wireless <ilw@linux.intel.com> 26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 27 * 28 *****************************************************************************/ 29 30#ifndef __il_4965_h__ 31#define __il_4965_h__ 32 33struct il_rx_queue; 34struct il_rx_buf; 35struct il_rx_pkt; 36struct il_tx_queue; 37struct il_rxon_context; 38 39/* configuration for the _4965 devices */ 40extern struct il_cfg il4965_cfg; 41extern const struct il_ops il4965_ops; 42 43extern struct il_mod_params il4965_mod_params; 44 45/* tx queue */ 46void il4965_free_tfds_in_queue(struct il_priv *il, int sta_id, int tid, 47 int freed); 48 49/* RXON */ 50void il4965_set_rxon_chain(struct il_priv *il); 51 52/* uCode */ 53int il4965_verify_ucode(struct il_priv *il); 54 55/* lib */ 56void il4965_check_abort_status(struct il_priv *il, u8 frame_count, u32 status); 57 58void il4965_rx_queue_reset(struct il_priv *il, struct il_rx_queue *rxq); 59int il4965_rx_init(struct il_priv *il, struct il_rx_queue *rxq); 60int il4965_hw_nic_init(struct il_priv *il); 61int il4965_dump_fh(struct il_priv *il, char **buf, bool display); 62 63void il4965_nic_config(struct il_priv *il); 64 65/* rx */ 66void il4965_rx_queue_restock(struct il_priv *il); 67void il4965_rx_replenish(struct il_priv *il); 68void il4965_rx_replenish_now(struct il_priv *il); 69void il4965_rx_queue_free(struct il_priv *il, struct il_rx_queue *rxq); 70int il4965_rxq_stop(struct il_priv *il); 71int il4965_hwrate_to_mac80211_idx(u32 rate_n_flags, enum ieee80211_band band); 72void il4965_rx_handle(struct il_priv *il); 73 74/* tx */ 75void il4965_hw_txq_free_tfd(struct il_priv *il, struct il_tx_queue *txq); 76int il4965_hw_txq_attach_buf_to_tfd(struct il_priv *il, struct il_tx_queue *txq, 77 dma_addr_t addr, u16 len, u8 reset, u8 pad); 78int il4965_hw_tx_queue_init(struct il_priv *il, struct il_tx_queue *txq); 79void il4965_hwrate_to_tx_control(struct il_priv *il, u32 rate_n_flags, 80 struct ieee80211_tx_info *info); 81int il4965_tx_skb(struct il_priv *il, 82 struct ieee80211_sta *sta, 83 struct sk_buff *skb); 84int il4965_tx_agg_start(struct il_priv *il, struct ieee80211_vif *vif, 85 struct ieee80211_sta *sta, u16 tid, u16 * ssn); 86int il4965_tx_agg_stop(struct il_priv *il, struct ieee80211_vif *vif, 87 struct ieee80211_sta *sta, u16 tid); 88int il4965_txq_check_empty(struct il_priv *il, int sta_id, u8 tid, int txq_id); 89int il4965_tx_queue_reclaim(struct il_priv *il, int txq_id, int idx); 90void il4965_hw_txq_ctx_free(struct il_priv *il); 91int il4965_txq_ctx_alloc(struct il_priv *il); 92void il4965_txq_ctx_reset(struct il_priv *il); 93void il4965_txq_ctx_stop(struct il_priv *il); 94void il4965_txq_set_sched(struct il_priv *il, u32 mask); 95 96/* 97 * Acquire il->lock before calling this function ! 98 */ 99void il4965_set_wr_ptrs(struct il_priv *il, int txq_id, u32 idx); 100/** 101 * il4965_tx_queue_set_status - (optionally) start Tx/Cmd queue 102 * @tx_fifo_id: Tx DMA/FIFO channel (range 0-7) that the queue will feed 103 * @scd_retry: (1) Indicates queue will be used in aggregation mode 104 * 105 * NOTE: Acquire il->lock before calling this function ! 106 */ 107void il4965_tx_queue_set_status(struct il_priv *il, struct il_tx_queue *txq, 108 int tx_fifo_id, int scd_retry); 109 110/* scan */ 111int il4965_request_scan(struct il_priv *il, struct ieee80211_vif *vif); 112 113/* station mgmt */ 114int il4965_manage_ibss_station(struct il_priv *il, struct ieee80211_vif *vif, 115 bool add); 116 117/* hcmd */ 118int il4965_send_beacon_cmd(struct il_priv *il); 119 120#ifdef CONFIG_IWLEGACY_DEBUG 121const char *il4965_get_tx_fail_reason(u32 status); 122#else 123static inline const char * 124il4965_get_tx_fail_reason(u32 status) 125{ 126 return ""; 127} 128#endif 129 130/* station management */ 131int il4965_alloc_bcast_station(struct il_priv *il); 132int il4965_add_bssid_station(struct il_priv *il, const u8 *addr, u8 *sta_id_r); 133int il4965_remove_default_wep_key(struct il_priv *il, 134 struct ieee80211_key_conf *key); 135int il4965_set_default_wep_key(struct il_priv *il, 136 struct ieee80211_key_conf *key); 137int il4965_restore_default_wep_keys(struct il_priv *il); 138int il4965_set_dynamic_key(struct il_priv *il, 139 struct ieee80211_key_conf *key, u8 sta_id); 140int il4965_remove_dynamic_key(struct il_priv *il, 141 struct ieee80211_key_conf *key, u8 sta_id); 142void il4965_update_tkip_key(struct il_priv *il, 143 struct ieee80211_key_conf *keyconf, 144 struct ieee80211_sta *sta, u32 iv32, 145 u16 *phase1key); 146int il4965_sta_tx_modify_enable_tid(struct il_priv *il, int sta_id, int tid); 147int il4965_sta_rx_agg_start(struct il_priv *il, struct ieee80211_sta *sta, 148 int tid, u16 ssn); 149int il4965_sta_rx_agg_stop(struct il_priv *il, struct ieee80211_sta *sta, 150 int tid); 151void il4965_sta_modify_sleep_tx_count(struct il_priv *il, int sta_id, int cnt); 152int il4965_update_bcast_stations(struct il_priv *il); 153 154/* rate */ 155static inline u8 156il4965_hw_get_rate(__le32 rate_n_flags) 157{ 158 return le32_to_cpu(rate_n_flags) & 0xFF; 159} 160 161/* eeprom */ 162void il4965_eeprom_get_mac(const struct il_priv *il, u8 * mac); 163int il4965_eeprom_acquire_semaphore(struct il_priv *il); 164void il4965_eeprom_release_semaphore(struct il_priv *il); 165int il4965_eeprom_check_version(struct il_priv *il); 166 167/* mac80211 handlers (for 4965) */ 168void il4965_mac_tx(struct ieee80211_hw *hw, 169 struct ieee80211_tx_control *control, 170 struct sk_buff *skb); 171int il4965_mac_start(struct ieee80211_hw *hw); 172void il4965_mac_stop(struct ieee80211_hw *hw); 173void il4965_configure_filter(struct ieee80211_hw *hw, 174 unsigned int changed_flags, 175 unsigned int *total_flags, u64 multicast); 176int il4965_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, 177 struct ieee80211_vif *vif, struct ieee80211_sta *sta, 178 struct ieee80211_key_conf *key); 179void il4965_mac_update_tkip_key(struct ieee80211_hw *hw, 180 struct ieee80211_vif *vif, 181 struct ieee80211_key_conf *keyconf, 182 struct ieee80211_sta *sta, u32 iv32, 183 u16 *phase1key); 184int il4965_mac_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 185 enum ieee80211_ampdu_mlme_action action, 186 struct ieee80211_sta *sta, u16 tid, u16 * ssn, 187 u8 buf_size); 188int il4965_mac_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 189 struct ieee80211_sta *sta); 190void 191il4965_mac_channel_switch(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 192 struct ieee80211_channel_switch *ch_switch); 193 194void il4965_led_enable(struct il_priv *il); 195 196/* EEPROM */ 197#define IL4965_EEPROM_IMG_SIZE 1024 198 199/* 200 * uCode queue management definitions ... 201 * The first queue used for block-ack aggregation is #7 (4965 only). 202 * All block-ack aggregation queues should map to Tx DMA/FIFO channel 7. 203 */ 204#define IL49_FIRST_AMPDU_QUEUE 7 205 206/* Sizes and addresses for instruction and data memory (SRAM) in 207 * 4965's embedded processor. Driver access is via HBUS_TARG_MEM_* regs. */ 208#define IL49_RTC_INST_LOWER_BOUND (0x000000) 209#define IL49_RTC_INST_UPPER_BOUND (0x018000) 210 211#define IL49_RTC_DATA_LOWER_BOUND (0x800000) 212#define IL49_RTC_DATA_UPPER_BOUND (0x80A000) 213 214#define IL49_RTC_INST_SIZE (IL49_RTC_INST_UPPER_BOUND - \ 215 IL49_RTC_INST_LOWER_BOUND) 216#define IL49_RTC_DATA_SIZE (IL49_RTC_DATA_UPPER_BOUND - \ 217 IL49_RTC_DATA_LOWER_BOUND) 218 219#define IL49_MAX_INST_SIZE IL49_RTC_INST_SIZE 220#define IL49_MAX_DATA_SIZE IL49_RTC_DATA_SIZE 221 222/* Size of uCode instruction memory in bootstrap state machine */ 223#define IL49_MAX_BSM_SIZE BSM_SRAM_SIZE 224 225static inline int 226il4965_hw_valid_rtc_data_addr(u32 addr) 227{ 228 return (addr >= IL49_RTC_DATA_LOWER_BOUND && 229 addr < IL49_RTC_DATA_UPPER_BOUND); 230} 231 232/********************* START TEMPERATURE *************************************/ 233 234/** 235 * 4965 temperature calculation. 236 * 237 * The driver must calculate the device temperature before calculating 238 * a txpower setting (amplifier gain is temperature dependent). The 239 * calculation uses 4 measurements, 3 of which (R1, R2, R3) are calibration 240 * values used for the life of the driver, and one of which (R4) is the 241 * real-time temperature indicator. 242 * 243 * uCode provides all 4 values to the driver via the "initialize alive" 244 * notification (see struct il4965_init_alive_resp). After the runtime uCode 245 * image loads, uCode updates the R4 value via stats notifications 246 * (see N_STATS), which occur after each received beacon 247 * when associated, or can be requested via C_STATS. 248 * 249 * NOTE: uCode provides the R4 value as a 23-bit signed value. Driver 250 * must sign-extend to 32 bits before applying formula below. 251 * 252 * Formula: 253 * 254 * degrees Kelvin = ((97 * 259 * (R4 - R2) / (R3 - R1)) / 100) + 8 255 * 256 * NOTE: The basic formula is 259 * (R4-R2) / (R3-R1). The 97/100 is 257 * an additional correction, which should be centered around 0 degrees 258 * Celsius (273 degrees Kelvin). The 8 (3 percent of 273) compensates for 259 * centering the 97/100 correction around 0 degrees K. 260 * 261 * Add 273 to Kelvin value to find degrees Celsius, for comparing current 262 * temperature with factory-measured temperatures when calculating txpower 263 * settings. 264 */ 265#define TEMPERATURE_CALIB_KELVIN_OFFSET 8 266#define TEMPERATURE_CALIB_A_VAL 259 267 268/* Limit range of calculated temperature to be between these Kelvin values */ 269#define IL_TX_POWER_TEMPERATURE_MIN (263) 270#define IL_TX_POWER_TEMPERATURE_MAX (410) 271 272#define IL_TX_POWER_TEMPERATURE_OUT_OF_RANGE(t) \ 273 ((t) < IL_TX_POWER_TEMPERATURE_MIN || \ 274 (t) > IL_TX_POWER_TEMPERATURE_MAX) 275 276void il4965_temperature_calib(struct il_priv *il); 277/********************* END TEMPERATURE ***************************************/ 278 279/********************* START TXPOWER *****************************************/ 280 281/** 282 * 4965 txpower calculations rely on information from three sources: 283 * 284 * 1) EEPROM 285 * 2) "initialize" alive notification 286 * 3) stats notifications 287 * 288 * EEPROM data consists of: 289 * 290 * 1) Regulatory information (max txpower and channel usage flags) is provided 291 * separately for each channel that can possibly supported by 4965. 292 * 40 MHz wide (.11n HT40) channels are listed separately from 20 MHz 293 * (legacy) channels. 294 * 295 * See struct il4965_eeprom_channel for format, and struct il4965_eeprom 296 * for locations in EEPROM. 297 * 298 * 2) Factory txpower calibration information is provided separately for 299 * sub-bands of contiguous channels. 2.4GHz has just one sub-band, 300 * but 5 GHz has several sub-bands. 301 * 302 * In addition, per-band (2.4 and 5 Ghz) saturation txpowers are provided. 303 * 304 * See struct il4965_eeprom_calib_info (and the tree of structures 305 * contained within it) for format, and struct il4965_eeprom for 306 * locations in EEPROM. 307 * 308 * "Initialization alive" notification (see struct il4965_init_alive_resp) 309 * consists of: 310 * 311 * 1) Temperature calculation parameters. 312 * 313 * 2) Power supply voltage measurement. 314 * 315 * 3) Tx gain compensation to balance 2 transmitters for MIMO use. 316 * 317 * Statistics notifications deliver: 318 * 319 * 1) Current values for temperature param R4. 320 */ 321 322/** 323 * To calculate a txpower setting for a given desired target txpower, channel, 324 * modulation bit rate, and transmitter chain (4965 has 2 transmitters to 325 * support MIMO and transmit diversity), driver must do the following: 326 * 327 * 1) Compare desired txpower vs. (EEPROM) regulatory limit for this channel. 328 * Do not exceed regulatory limit; reduce target txpower if necessary. 329 * 330 * If setting up txpowers for MIMO rates (rate idxes 8-15, 24-31), 331 * 2 transmitters will be used simultaneously; driver must reduce the 332 * regulatory limit by 3 dB (half-power) for each transmitter, so the 333 * combined total output of the 2 transmitters is within regulatory limits. 334 * 335 * 336 * 2) Compare target txpower vs. (EEPROM) saturation txpower *reduced by 337 * backoff for this bit rate*. Do not exceed (saturation - backoff[rate]); 338 * reduce target txpower if necessary. 339 * 340 * Backoff values below are in 1/2 dB units (equivalent to steps in 341 * txpower gain tables): 342 * 343 * OFDM 6 - 36 MBit: 10 steps (5 dB) 344 * OFDM 48 MBit: 15 steps (7.5 dB) 345 * OFDM 54 MBit: 17 steps (8.5 dB) 346 * OFDM 60 MBit: 20 steps (10 dB) 347 * CCK all rates: 10 steps (5 dB) 348 * 349 * Backoff values apply to saturation txpower on a per-transmitter basis; 350 * when using MIMO (2 transmitters), each transmitter uses the same 351 * saturation level provided in EEPROM, and the same backoff values; 352 * no reduction (such as with regulatory txpower limits) is required. 353 * 354 * Saturation and Backoff values apply equally to 20 Mhz (legacy) channel 355 * widths and 40 Mhz (.11n HT40) channel widths; there is no separate 356 * factory measurement for ht40 channels. 357 * 358 * The result of this step is the final target txpower. The rest of 359 * the steps figure out the proper settings for the device to achieve 360 * that target txpower. 361 * 362 * 363 * 3) Determine (EEPROM) calibration sub band for the target channel, by 364 * comparing against first and last channels in each sub band 365 * (see struct il4965_eeprom_calib_subband_info). 366 * 367 * 368 * 4) Linearly interpolate (EEPROM) factory calibration measurement sets, 369 * referencing the 2 factory-measured (sample) channels within the sub band. 370 * 371 * Interpolation is based on difference between target channel's frequency 372 * and the sample channels' frequencies. Since channel numbers are based 373 * on frequency (5 MHz between each channel number), this is equivalent 374 * to interpolating based on channel number differences. 375 * 376 * Note that the sample channels may or may not be the channels at the 377 * edges of the sub band. The target channel may be "outside" of the 378 * span of the sampled channels. 379 * 380 * Driver may choose the pair (for 2 Tx chains) of measurements (see 381 * struct il4965_eeprom_calib_ch_info) for which the actual measured 382 * txpower comes closest to the desired txpower. Usually, though, 383 * the middle set of measurements is closest to the regulatory limits, 384 * and is therefore a good choice for all txpower calculations (this 385 * assumes that high accuracy is needed for maximizing legal txpower, 386 * while lower txpower configurations do not need as much accuracy). 387 * 388 * Driver should interpolate both members of the chosen measurement pair, 389 * i.e. for both Tx chains (radio transmitters), unless the driver knows 390 * that only one of the chains will be used (e.g. only one tx antenna 391 * connected, but this should be unusual). The rate scaling algorithm 392 * switches antennas to find best performance, so both Tx chains will 393 * be used (although only one at a time) even for non-MIMO transmissions. 394 * 395 * Driver should interpolate factory values for temperature, gain table 396 * idx, and actual power. The power amplifier detector values are 397 * not used by the driver. 398 * 399 * Sanity check: If the target channel happens to be one of the sample 400 * channels, the results should agree with the sample channel's 401 * measurements! 402 * 403 * 404 * 5) Find difference between desired txpower and (interpolated) 405 * factory-measured txpower. Using (interpolated) factory gain table idx 406 * (shown elsewhere) as a starting point, adjust this idx lower to 407 * increase txpower, or higher to decrease txpower, until the target 408 * txpower is reached. Each step in the gain table is 1/2 dB. 409 * 410 * For example, if factory measured txpower is 16 dBm, and target txpower 411 * is 13 dBm, add 6 steps to the factory gain idx to reduce txpower 412 * by 3 dB. 413 * 414 * 415 * 6) Find difference between current device temperature and (interpolated) 416 * factory-measured temperature for sub-band. Factory values are in 417 * degrees Celsius. To calculate current temperature, see comments for 418 * "4965 temperature calculation". 419 * 420 * If current temperature is higher than factory temperature, driver must 421 * increase gain (lower gain table idx), and vice verse. 422 * 423 * Temperature affects gain differently for different channels: 424 * 425 * 2.4 GHz all channels: 3.5 degrees per half-dB step 426 * 5 GHz channels 34-43: 4.5 degrees per half-dB step 427 * 5 GHz channels >= 44: 4.0 degrees per half-dB step 428 * 429 * NOTE: Temperature can increase rapidly when transmitting, especially 430 * with heavy traffic at high txpowers. Driver should update 431 * temperature calculations often under these conditions to 432 * maintain strong txpower in the face of rising temperature. 433 * 434 * 435 * 7) Find difference between current power supply voltage indicator 436 * (from "initialize alive") and factory-measured power supply voltage 437 * indicator (EEPROM). 438 * 439 * If the current voltage is higher (indicator is lower) than factory 440 * voltage, gain should be reduced (gain table idx increased) by: 441 * 442 * (eeprom - current) / 7 443 * 444 * If the current voltage is lower (indicator is higher) than factory 445 * voltage, gain should be increased (gain table idx decreased) by: 446 * 447 * 2 * (current - eeprom) / 7 448 * 449 * If number of idx steps in either direction turns out to be > 2, 450 * something is wrong ... just use 0. 451 * 452 * NOTE: Voltage compensation is independent of band/channel. 453 * 454 * NOTE: "Initialize" uCode measures current voltage, which is assumed 455 * to be constant after this initial measurement. Voltage 456 * compensation for txpower (number of steps in gain table) 457 * may be calculated once and used until the next uCode bootload. 458 * 459 * 460 * 8) If setting up txpowers for MIMO rates (rate idxes 8-15, 24-31), 461 * adjust txpower for each transmitter chain, so txpower is balanced 462 * between the two chains. There are 5 pairs of tx_atten[group][chain] 463 * values in "initialize alive", one pair for each of 5 channel ranges: 464 * 465 * Group 0: 5 GHz channel 34-43 466 * Group 1: 5 GHz channel 44-70 467 * Group 2: 5 GHz channel 71-124 468 * Group 3: 5 GHz channel 125-200 469 * Group 4: 2.4 GHz all channels 470 * 471 * Add the tx_atten[group][chain] value to the idx for the target chain. 472 * The values are signed, but are in pairs of 0 and a non-negative number, 473 * so as to reduce gain (if necessary) of the "hotter" channel. This 474 * avoids any need to double-check for regulatory compliance after 475 * this step. 476 * 477 * 478 * 9) If setting up for a CCK rate, lower the gain by adding a CCK compensation 479 * value to the idx: 480 * 481 * Hardware rev B: 9 steps (4.5 dB) 482 * Hardware rev C: 5 steps (2.5 dB) 483 * 484 * Hardware rev for 4965 can be determined by reading CSR_HW_REV_WA_REG, 485 * bits [3:2], 1 = B, 2 = C. 486 * 487 * NOTE: This compensation is in addition to any saturation backoff that 488 * might have been applied in an earlier step. 489 * 490 * 491 * 10) Select the gain table, based on band (2.4 vs 5 GHz). 492 * 493 * Limit the adjusted idx to stay within the table! 494 * 495 * 496 * 11) Read gain table entries for DSP and radio gain, place into appropriate 497 * location(s) in command (struct il4965_txpowertable_cmd). 498 */ 499 500/** 501 * When MIMO is used (2 transmitters operating simultaneously), driver should 502 * limit each transmitter to deliver a max of 3 dB below the regulatory limit 503 * for the device. That is, use half power for each transmitter, so total 504 * txpower is within regulatory limits. 505 * 506 * The value "6" represents number of steps in gain table to reduce power 3 dB. 507 * Each step is 1/2 dB. 508 */ 509#define IL_TX_POWER_MIMO_REGULATORY_COMPENSATION (6) 510 511/** 512 * CCK gain compensation. 513 * 514 * When calculating txpowers for CCK, after making sure that the target power 515 * is within regulatory and saturation limits, driver must additionally 516 * back off gain by adding these values to the gain table idx. 517 * 518 * Hardware rev for 4965 can be determined by reading CSR_HW_REV_WA_REG, 519 * bits [3:2], 1 = B, 2 = C. 520 */ 521#define IL_TX_POWER_CCK_COMPENSATION_B_STEP (9) 522#define IL_TX_POWER_CCK_COMPENSATION_C_STEP (5) 523 524/* 525 * 4965 power supply voltage compensation for txpower 526 */ 527#define TX_POWER_IL_VOLTAGE_CODES_PER_03V (7) 528 529/** 530 * Gain tables. 531 * 532 * The following tables contain pair of values for setting txpower, i.e. 533 * gain settings for the output of the device's digital signal processor (DSP), 534 * and for the analog gain structure of the transmitter. 535 * 536 * Each entry in the gain tables represents a step of 1/2 dB. Note that these 537 * are *relative* steps, not indications of absolute output power. Output 538 * power varies with temperature, voltage, and channel frequency, and also 539 * requires consideration of average power (to satisfy regulatory constraints), 540 * and peak power (to avoid distortion of the output signal). 541 * 542 * Each entry contains two values: 543 * 1) DSP gain (or sometimes called DSP attenuation). This is a fine-grained 544 * linear value that multiplies the output of the digital signal processor, 545 * before being sent to the analog radio. 546 * 2) Radio gain. This sets the analog gain of the radio Tx path. 547 * It is a coarser setting, and behaves in a logarithmic (dB) fashion. 548 * 549 * EEPROM contains factory calibration data for txpower. This maps actual 550 * measured txpower levels to gain settings in the "well known" tables 551 * below ("well-known" means here that both factory calibration *and* the 552 * driver work with the same table). 553 * 554 * There are separate tables for 2.4 GHz and 5 GHz bands. The 5 GHz table 555 * has an extension (into negative idxes), in case the driver needs to 556 * boost power setting for high device temperatures (higher than would be 557 * present during factory calibration). A 5 Ghz EEPROM idx of "40" 558 * corresponds to the 49th entry in the table used by the driver. 559 */ 560#define MIN_TX_GAIN_IDX (0) /* highest gain, lowest idx, 2.4 */ 561#define MIN_TX_GAIN_IDX_52GHZ_EXT (-9) /* highest gain, lowest idx, 5 */ 562 563/** 564 * 2.4 GHz gain table 565 * 566 * Index Dsp gain Radio gain 567 * 0 110 0x3f (highest gain) 568 * 1 104 0x3f 569 * 2 98 0x3f 570 * 3 110 0x3e 571 * 4 104 0x3e 572 * 5 98 0x3e 573 * 6 110 0x3d 574 * 7 104 0x3d 575 * 8 98 0x3d 576 * 9 110 0x3c 577 * 10 104 0x3c 578 * 11 98 0x3c 579 * 12 110 0x3b 580 * 13 104 0x3b 581 * 14 98 0x3b 582 * 15 110 0x3a 583 * 16 104 0x3a 584 * 17 98 0x3a 585 * 18 110 0x39 586 * 19 104 0x39 587 * 20 98 0x39 588 * 21 110 0x38 589 * 22 104 0x38 590 * 23 98 0x38 591 * 24 110 0x37 592 * 25 104 0x37 593 * 26 98 0x37 594 * 27 110 0x36 595 * 28 104 0x36 596 * 29 98 0x36 597 * 30 110 0x35 598 * 31 104 0x35 599 * 32 98 0x35 600 * 33 110 0x34 601 * 34 104 0x34 602 * 35 98 0x34 603 * 36 110 0x33 604 * 37 104 0x33 605 * 38 98 0x33 606 * 39 110 0x32 607 * 40 104 0x32 608 * 41 98 0x32 609 * 42 110 0x31 610 * 43 104 0x31 611 * 44 98 0x31 612 * 45 110 0x30 613 * 46 104 0x30 614 * 47 98 0x30 615 * 48 110 0x6 616 * 49 104 0x6 617 * 50 98 0x6 618 * 51 110 0x5 619 * 52 104 0x5 620 * 53 98 0x5 621 * 54 110 0x4 622 * 55 104 0x4 623 * 56 98 0x4 624 * 57 110 0x3 625 * 58 104 0x3 626 * 59 98 0x3 627 * 60 110 0x2 628 * 61 104 0x2 629 * 62 98 0x2 630 * 63 110 0x1 631 * 64 104 0x1 632 * 65 98 0x1 633 * 66 110 0x0 634 * 67 104 0x0 635 * 68 98 0x0 636 * 69 97 0 637 * 70 96 0 638 * 71 95 0 639 * 72 94 0 640 * 73 93 0 641 * 74 92 0 642 * 75 91 0 643 * 76 90 0 644 * 77 89 0 645 * 78 88 0 646 * 79 87 0 647 * 80 86 0 648 * 81 85 0 649 * 82 84 0 650 * 83 83 0 651 * 84 82 0 652 * 85 81 0 653 * 86 80 0 654 * 87 79 0 655 * 88 78 0 656 * 89 77 0 657 * 90 76 0 658 * 91 75 0 659 * 92 74 0 660 * 93 73 0 661 * 94 72 0 662 * 95 71 0 663 * 96 70 0 664 * 97 69 0 665 * 98 68 0 666 */ 667 668/** 669 * 5 GHz gain table 670 * 671 * Index Dsp gain Radio gain 672 * -9 123 0x3F (highest gain) 673 * -8 117 0x3F 674 * -7 110 0x3F 675 * -6 104 0x3F 676 * -5 98 0x3F 677 * -4 110 0x3E 678 * -3 104 0x3E 679 * -2 98 0x3E 680 * -1 110 0x3D 681 * 0 104 0x3D 682 * 1 98 0x3D 683 * 2 110 0x3C 684 * 3 104 0x3C 685 * 4 98 0x3C 686 * 5 110 0x3B 687 * 6 104 0x3B 688 * 7 98 0x3B 689 * 8 110 0x3A 690 * 9 104 0x3A 691 * 10 98 0x3A 692 * 11 110 0x39 693 * 12 104 0x39 694 * 13 98 0x39 695 * 14 110 0x38 696 * 15 104 0x38 697 * 16 98 0x38 698 * 17 110 0x37 699 * 18 104 0x37 700 * 19 98 0x37 701 * 20 110 0x36 702 * 21 104 0x36 703 * 22 98 0x36 704 * 23 110 0x35 705 * 24 104 0x35 706 * 25 98 0x35 707 * 26 110 0x34 708 * 27 104 0x34 709 * 28 98 0x34 710 * 29 110 0x33 711 * 30 104 0x33 712 * 31 98 0x33 713 * 32 110 0x32 714 * 33 104 0x32 715 * 34 98 0x32 716 * 35 110 0x31 717 * 36 104 0x31 718 * 37 98 0x31 719 * 38 110 0x30 720 * 39 104 0x30 721 * 40 98 0x30 722 * 41 110 0x25 723 * 42 104 0x25 724 * 43 98 0x25 725 * 44 110 0x24 726 * 45 104 0x24 727 * 46 98 0x24 728 * 47 110 0x23 729 * 48 104 0x23 730 * 49 98 0x23 731 * 50 110 0x22 732 * 51 104 0x18 733 * 52 98 0x18 734 * 53 110 0x17 735 * 54 104 0x17 736 * 55 98 0x17 737 * 56 110 0x16 738 * 57 104 0x16 739 * 58 98 0x16 740 * 59 110 0x15 741 * 60 104 0x15 742 * 61 98 0x15 743 * 62 110 0x14 744 * 63 104 0x14 745 * 64 98 0x14 746 * 65 110 0x13 747 * 66 104 0x13 748 * 67 98 0x13 749 * 68 110 0x12 750 * 69 104 0x08 751 * 70 98 0x08 752 * 71 110 0x07 753 * 72 104 0x07 754 * 73 98 0x07 755 * 74 110 0x06 756 * 75 104 0x06 757 * 76 98 0x06 758 * 77 110 0x05 759 * 78 104 0x05 760 * 79 98 0x05 761 * 80 110 0x04 762 * 81 104 0x04 763 * 82 98 0x04 764 * 83 110 0x03 765 * 84 104 0x03 766 * 85 98 0x03 767 * 86 110 0x02 768 * 87 104 0x02 769 * 88 98 0x02 770 * 89 110 0x01 771 * 90 104 0x01 772 * 91 98 0x01 773 * 92 110 0x00 774 * 93 104 0x00 775 * 94 98 0x00 776 * 95 93 0x00 777 * 96 88 0x00 778 * 97 83 0x00 779 * 98 78 0x00 780 */ 781 782/** 783 * Sanity checks and default values for EEPROM regulatory levels. 784 * If EEPROM values fall outside MIN/MAX range, use default values. 785 * 786 * Regulatory limits refer to the maximum average txpower allowed by 787 * regulatory agencies in the geographies in which the device is meant 788 * to be operated. These limits are SKU-specific (i.e. geography-specific), 789 * and channel-specific; each channel has an individual regulatory limit 790 * listed in the EEPROM. 791 * 792 * Units are in half-dBm (i.e. "34" means 17 dBm). 793 */ 794#define IL_TX_POWER_DEFAULT_REGULATORY_24 (34) 795#define IL_TX_POWER_DEFAULT_REGULATORY_52 (34) 796#define IL_TX_POWER_REGULATORY_MIN (0) 797#define IL_TX_POWER_REGULATORY_MAX (34) 798 799/** 800 * Sanity checks and default values for EEPROM saturation levels. 801 * If EEPROM values fall outside MIN/MAX range, use default values. 802 * 803 * Saturation is the highest level that the output power amplifier can produce 804 * without significant clipping distortion. This is a "peak" power level. 805 * Different types of modulation (i.e. various "rates", and OFDM vs. CCK) 806 * require differing amounts of backoff, relative to their average power output, 807 * in order to avoid clipping distortion. 808 * 809 * Driver must make sure that it is violating neither the saturation limit, 810 * nor the regulatory limit, when calculating Tx power settings for various 811 * rates. 812 * 813 * Units are in half-dBm (i.e. "38" means 19 dBm). 814 */ 815#define IL_TX_POWER_DEFAULT_SATURATION_24 (38) 816#define IL_TX_POWER_DEFAULT_SATURATION_52 (38) 817#define IL_TX_POWER_SATURATION_MIN (20) 818#define IL_TX_POWER_SATURATION_MAX (50) 819 820/** 821 * Channel groups used for Tx Attenuation calibration (MIMO tx channel balance) 822 * and thermal Txpower calibration. 823 * 824 * When calculating txpower, driver must compensate for current device 825 * temperature; higher temperature requires higher gain. Driver must calculate 826 * current temperature (see "4965 temperature calculation"), then compare vs. 827 * factory calibration temperature in EEPROM; if current temperature is higher 828 * than factory temperature, driver must *increase* gain by proportions shown 829 * in table below. If current temperature is lower than factory, driver must 830 * *decrease* gain. 831 * 832 * Different frequency ranges require different compensation, as shown below. 833 */ 834/* Group 0, 5.2 GHz ch 34-43: 4.5 degrees per 1/2 dB. */ 835#define CALIB_IL_TX_ATTEN_GR1_FCH 34 836#define CALIB_IL_TX_ATTEN_GR1_LCH 43 837 838/* Group 1, 5.3 GHz ch 44-70: 4.0 degrees per 1/2 dB. */ 839#define CALIB_IL_TX_ATTEN_GR2_FCH 44 840#define CALIB_IL_TX_ATTEN_GR2_LCH 70 841 842/* Group 2, 5.5 GHz ch 71-124: 4.0 degrees per 1/2 dB. */ 843#define CALIB_IL_TX_ATTEN_GR3_FCH 71 844#define CALIB_IL_TX_ATTEN_GR3_LCH 124 845 846/* Group 3, 5.7 GHz ch 125-200: 4.0 degrees per 1/2 dB. */ 847#define CALIB_IL_TX_ATTEN_GR4_FCH 125 848#define CALIB_IL_TX_ATTEN_GR4_LCH 200 849 850/* Group 4, 2.4 GHz all channels: 3.5 degrees per 1/2 dB. */ 851#define CALIB_IL_TX_ATTEN_GR5_FCH 1 852#define CALIB_IL_TX_ATTEN_GR5_LCH 20 853 854enum { 855 CALIB_CH_GROUP_1 = 0, 856 CALIB_CH_GROUP_2 = 1, 857 CALIB_CH_GROUP_3 = 2, 858 CALIB_CH_GROUP_4 = 3, 859 CALIB_CH_GROUP_5 = 4, 860 CALIB_CH_GROUP_MAX 861}; 862 863/********************* END TXPOWER *****************************************/ 864 865/** 866 * Tx/Rx Queues 867 * 868 * Most communication between driver and 4965 is via queues of data buffers. 869 * For example, all commands that the driver issues to device's embedded 870 * controller (uCode) are via the command queue (one of the Tx queues). All 871 * uCode command responses/replies/notifications, including Rx frames, are 872 * conveyed from uCode to driver via the Rx queue. 873 * 874 * Most support for these queues, including handshake support, resides in 875 * structures in host DRAM, shared between the driver and the device. When 876 * allocating this memory, the driver must make sure that data written by 877 * the host CPU updates DRAM immediately (and does not get "stuck" in CPU's 878 * cache memory), so DRAM and cache are consistent, and the device can 879 * immediately see changes made by the driver. 880 * 881 * 4965 supports up to 16 DRAM-based Tx queues, and services these queues via 882 * up to 7 DMA channels (FIFOs). Each Tx queue is supported by a circular array 883 * in DRAM containing 256 Transmit Frame Descriptors (TFDs). 884 */ 885#define IL49_NUM_FIFOS 7 886#define IL49_CMD_FIFO_NUM 4 887#define IL49_NUM_QUEUES 16 888#define IL49_NUM_AMPDU_QUEUES 8 889 890/** 891 * struct il4965_schedq_bc_tbl 892 * 893 * Byte Count table 894 * 895 * Each Tx queue uses a byte-count table containing 320 entries: 896 * one 16-bit entry for each of 256 TFDs, plus an additional 64 entries that 897 * duplicate the first 64 entries (to avoid wrap-around within a Tx win; 898 * max Tx win is 64 TFDs). 899 * 900 * When driver sets up a new TFD, it must also enter the total byte count 901 * of the frame to be transmitted into the corresponding entry in the byte 902 * count table for the chosen Tx queue. If the TFD idx is 0-63, the driver 903 * must duplicate the byte count entry in corresponding idx 256-319. 904 * 905 * padding puts each byte count table on a 1024-byte boundary; 906 * 4965 assumes tables are separated by 1024 bytes. 907 */ 908struct il4965_scd_bc_tbl { 909 __le16 tfd_offset[TFD_QUEUE_BC_SIZE]; 910 u8 pad[1024 - (TFD_QUEUE_BC_SIZE) * sizeof(__le16)]; 911} __packed; 912 913#define IL4965_RTC_INST_LOWER_BOUND (0x000000) 914 915/* RSSI to dBm */ 916#define IL4965_RSSI_OFFSET 44 917 918/* PCI registers */ 919#define PCI_CFG_RETRY_TIMEOUT 0x041 920 921#define IL4965_DEFAULT_TX_RETRY 15 922 923/* EEPROM */ 924#define IL4965_FIRST_AMPDU_QUEUE 10 925 926/* Calibration */ 927void il4965_chain_noise_calibration(struct il_priv *il, void *stat_resp); 928void il4965_sensitivity_calibration(struct il_priv *il, void *resp); 929void il4965_init_sensitivity(struct il_priv *il); 930void il4965_reset_run_time_calib(struct il_priv *il); 931 932/* Debug */ 933#ifdef CONFIG_IWLEGACY_DEBUGFS 934extern const struct il_debugfs_ops il4965_debugfs_ops; 935#endif 936 937/****************************/ 938/* Flow Handler Definitions */ 939/****************************/ 940 941/** 942 * This I/O area is directly read/writable by driver (e.g. Linux uses writel()) 943 * Addresses are offsets from device's PCI hardware base address. 944 */ 945#define FH49_MEM_LOWER_BOUND (0x1000) 946#define FH49_MEM_UPPER_BOUND (0x2000) 947 948/** 949 * Keep-Warm (KW) buffer base address. 950 * 951 * Driver must allocate a 4KByte buffer that is used by 4965 for keeping the 952 * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency 953 * DRAM access when 4965 is Txing or Rxing. The dummy accesses prevent host 954 * from going into a power-savings mode that would cause higher DRAM latency, 955 * and possible data over/under-runs, before all Tx/Rx is complete. 956 * 957 * Driver loads FH49_KW_MEM_ADDR_REG with the physical address (bits 35:4) 958 * of the buffer, which must be 4K aligned. Once this is set up, the 4965 959 * automatically invokes keep-warm accesses when normal accesses might not 960 * be sufficient to maintain fast DRAM response. 961 * 962 * Bit fields: 963 * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned 964 */ 965#define FH49_KW_MEM_ADDR_REG (FH49_MEM_LOWER_BOUND + 0x97C) 966 967/** 968 * TFD Circular Buffers Base (CBBC) addresses 969 * 970 * 4965 has 16 base pointer registers, one for each of 16 host-DRAM-resident 971 * circular buffers (CBs/queues) containing Transmit Frame Descriptors (TFDs) 972 * (see struct il_tfd_frame). These 16 pointer registers are offset by 0x04 973 * bytes from one another. Each TFD circular buffer in DRAM must be 256-byte 974 * aligned (address bits 0-7 must be 0). 975 * 976 * Bit fields in each pointer register: 977 * 27-0: TFD CB physical base address [35:8], must be 256-byte aligned 978 */ 979#define FH49_MEM_CBBC_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0x9D0) 980#define FH49_MEM_CBBC_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0xA10) 981 982/* Find TFD CB base pointer for given queue (range 0-15). */ 983#define FH49_MEM_CBBC_QUEUE(x) (FH49_MEM_CBBC_LOWER_BOUND + (x) * 0x4) 984 985/** 986 * Rx SRAM Control and Status Registers (RSCSR) 987 * 988 * These registers provide handshake between driver and 4965 for the Rx queue 989 * (this queue handles *all* command responses, notifications, Rx data, etc. 990 * sent from 4965 uCode to host driver). Unlike Tx, there is only one Rx 991 * queue, and only one Rx DMA/FIFO channel. Also unlike Tx, which can 992 * concatenate up to 20 DRAM buffers to form a Tx frame, each Receive Buffer 993 * Descriptor (RBD) points to only one Rx Buffer (RB); there is a 1:1 994 * mapping between RBDs and RBs. 995 * 996 * Driver must allocate host DRAM memory for the following, and set the 997 * physical address of each into 4965 registers: 998 * 999 * 1) Receive Buffer Descriptor (RBD) circular buffer (CB), typically with 256 1000 * entries (although any power of 2, up to 4096, is selectable by driver). 1001 * Each entry (1 dword) points to a receive buffer (RB) of consistent size 1002 * (typically 4K, although 8K or 16K are also selectable by driver). 1003 * Driver sets up RB size and number of RBDs in the CB via Rx config 1004 * register FH49_MEM_RCSR_CHNL0_CONFIG_REG. 1005 * 1006 * Bit fields within one RBD: 1007 * 27-0: Receive Buffer physical address bits [35:8], 256-byte aligned 1008 * 1009 * Driver sets physical address [35:8] of base of RBD circular buffer 1010 * into FH49_RSCSR_CHNL0_RBDCB_BASE_REG [27:0]. 1011 * 1012 * 2) Rx status buffer, 8 bytes, in which 4965 indicates which Rx Buffers 1013 * (RBs) have been filled, via a "write pointer", actually the idx of 1014 * the RB's corresponding RBD within the circular buffer. Driver sets 1015 * physical address [35:4] into FH49_RSCSR_CHNL0_STTS_WPTR_REG [31:0]. 1016 * 1017 * Bit fields in lower dword of Rx status buffer (upper dword not used 1018 * by driver; see struct il4965_shared, val0): 1019 * 31-12: Not used by driver 1020 * 11- 0: Index of last filled Rx buffer descriptor 1021 * (4965 writes, driver reads this value) 1022 * 1023 * As the driver prepares Receive Buffers (RBs) for 4965 to fill, driver must 1024 * enter pointers to these RBs into contiguous RBD circular buffer entries, 1025 * and update the 4965's "write" idx register, 1026 * FH49_RSCSR_CHNL0_RBDCB_WPTR_REG. 1027 * 1028 * This "write" idx corresponds to the *next* RBD that the driver will make 1029 * available, i.e. one RBD past the tail of the ready-to-fill RBDs within 1030 * the circular buffer. This value should initially be 0 (before preparing any 1031 * RBs), should be 8 after preparing the first 8 RBs (for example), and must 1032 * wrap back to 0 at the end of the circular buffer (but don't wrap before 1033 * "read" idx has advanced past 1! See below). 1034 * NOTE: 4965 EXPECTS THE WRITE IDX TO BE INCREMENTED IN MULTIPLES OF 8. 1035 * 1036 * As the 4965 fills RBs (referenced from contiguous RBDs within the circular 1037 * buffer), it updates the Rx status buffer in host DRAM, 2) described above, 1038 * to tell the driver the idx of the latest filled RBD. The driver must 1039 * read this "read" idx from DRAM after receiving an Rx interrupt from 4965. 1040 * 1041 * The driver must also internally keep track of a third idx, which is the 1042 * next RBD to process. When receiving an Rx interrupt, driver should process 1043 * all filled but unprocessed RBs up to, but not including, the RB 1044 * corresponding to the "read" idx. For example, if "read" idx becomes "1", 1045 * driver may process the RB pointed to by RBD 0. Depending on volume of 1046 * traffic, there may be many RBs to process. 1047 * 1048 * If read idx == write idx, 4965 thinks there is no room to put new data. 1049 * Due to this, the maximum number of filled RBs is 255, instead of 256. To 1050 * be safe, make sure that there is a gap of at least 2 RBDs between "write" 1051 * and "read" idxes; that is, make sure that there are no more than 254 1052 * buffers waiting to be filled. 1053 */ 1054#define FH49_MEM_RSCSR_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0xBC0) 1055#define FH49_MEM_RSCSR_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0xC00) 1056#define FH49_MEM_RSCSR_CHNL0 (FH49_MEM_RSCSR_LOWER_BOUND) 1057 1058/** 1059 * Physical base address of 8-byte Rx Status buffer. 1060 * Bit fields: 1061 * 31-0: Rx status buffer physical base address [35:4], must 16-byte aligned. 1062 */ 1063#define FH49_RSCSR_CHNL0_STTS_WPTR_REG (FH49_MEM_RSCSR_CHNL0) 1064 1065/** 1066 * Physical base address of Rx Buffer Descriptor Circular Buffer. 1067 * Bit fields: 1068 * 27-0: RBD CD physical base address [35:8], must be 256-byte aligned. 1069 */ 1070#define FH49_RSCSR_CHNL0_RBDCB_BASE_REG (FH49_MEM_RSCSR_CHNL0 + 0x004) 1071 1072/** 1073 * Rx write pointer (idx, really!). 1074 * Bit fields: 1075 * 11-0: Index of driver's most recent prepared-to-be-filled RBD, + 1. 1076 * NOTE: For 256-entry circular buffer, use only bits [7:0]. 1077 */ 1078#define FH49_RSCSR_CHNL0_RBDCB_WPTR_REG (FH49_MEM_RSCSR_CHNL0 + 0x008) 1079#define FH49_RSCSR_CHNL0_WPTR (FH49_RSCSR_CHNL0_RBDCB_WPTR_REG) 1080 1081/** 1082 * Rx Config/Status Registers (RCSR) 1083 * Rx Config Reg for channel 0 (only channel used) 1084 * 1085 * Driver must initialize FH49_MEM_RCSR_CHNL0_CONFIG_REG as follows for 1086 * normal operation (see bit fields). 1087 * 1088 * Clearing FH49_MEM_RCSR_CHNL0_CONFIG_REG to 0 turns off Rx DMA. 1089 * Driver should poll FH49_MEM_RSSR_RX_STATUS_REG for 1090 * FH49_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (bit 24) before continuing. 1091 * 1092 * Bit fields: 1093 * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame, 1094 * '10' operate normally 1095 * 29-24: reserved 1096 * 23-20: # RBDs in circular buffer = 2^value; use "8" for 256 RBDs (normal), 1097 * min "5" for 32 RBDs, max "12" for 4096 RBDs. 1098 * 19-18: reserved 1099 * 17-16: size of each receive buffer; '00' 4K (normal), '01' 8K, 1100 * '10' 12K, '11' 16K. 1101 * 15-14: reserved 1102 * 13-12: IRQ destination; '00' none, '01' host driver (normal operation) 1103 * 11- 4: timeout for closing Rx buffer and interrupting host (units 32 usec) 1104 * typical value 0x10 (about 1/2 msec) 1105 * 3- 0: reserved 1106 */ 1107#define FH49_MEM_RCSR_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0xC00) 1108#define FH49_MEM_RCSR_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0xCC0) 1109#define FH49_MEM_RCSR_CHNL0 (FH49_MEM_RCSR_LOWER_BOUND) 1110 1111#define FH49_MEM_RCSR_CHNL0_CONFIG_REG (FH49_MEM_RCSR_CHNL0) 1112 1113#define FH49_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MSK (0x00000FF0) /* bits 4-11 */ 1114#define FH49_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MSK (0x00001000) /* bits 12 */ 1115#define FH49_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK (0x00008000) /* bit 15 */ 1116#define FH49_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MSK (0x00030000) /* bits 16-17 */ 1117#define FH49_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MSK (0x00F00000) /* bits 20-23 */ 1118#define FH49_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MSK (0xC0000000) /* bits 30-31 */ 1119 1120#define FH49_RCSR_RX_CONFIG_RBDCB_SIZE_POS (20) 1121#define FH49_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS (4) 1122#define RX_RB_TIMEOUT (0x10) 1123 1124#define FH49_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000) 1125#define FH49_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000) 1126#define FH49_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000) 1127 1128#define FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000) 1129#define FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K (0x00010000) 1130#define FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K (0x00020000) 1131#define FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K (0x00030000) 1132 1133#define FH49_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY (0x00000004) 1134#define FH49_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000) 1135#define FH49_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000) 1136 1137/** 1138 * Rx Shared Status Registers (RSSR) 1139 * 1140 * After stopping Rx DMA channel (writing 0 to 1141 * FH49_MEM_RCSR_CHNL0_CONFIG_REG), driver must poll 1142 * FH49_MEM_RSSR_RX_STATUS_REG until Rx channel is idle. 1143 * 1144 * Bit fields: 1145 * 24: 1 = Channel 0 is idle 1146 * 1147 * FH49_MEM_RSSR_SHARED_CTRL_REG and FH49_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV 1148 * contain default values that should not be altered by the driver. 1149 */ 1150#define FH49_MEM_RSSR_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0xC40) 1151#define FH49_MEM_RSSR_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0xD00) 1152 1153#define FH49_MEM_RSSR_SHARED_CTRL_REG (FH49_MEM_RSSR_LOWER_BOUND) 1154#define FH49_MEM_RSSR_RX_STATUS_REG (FH49_MEM_RSSR_LOWER_BOUND + 0x004) 1155#define FH49_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV\ 1156 (FH49_MEM_RSSR_LOWER_BOUND + 0x008) 1157 1158#define FH49_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000) 1159 1160#define FH49_MEM_TFDIB_REG1_ADDR_BITSHIFT 28 1161 1162/* TFDB Area - TFDs buffer table */ 1163#define FH49_MEM_TFDIB_DRAM_ADDR_LSB_MSK (0xFFFFFFFF) 1164#define FH49_TFDIB_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0x900) 1165#define FH49_TFDIB_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0x958) 1166#define FH49_TFDIB_CTRL0_REG(_chnl) (FH49_TFDIB_LOWER_BOUND + 0x8 * (_chnl)) 1167#define FH49_TFDIB_CTRL1_REG(_chnl) (FH49_TFDIB_LOWER_BOUND + 0x8 * (_chnl) + 0x4) 1168 1169/** 1170 * Transmit DMA Channel Control/Status Registers (TCSR) 1171 * 1172 * 4965 has one configuration register for each of 8 Tx DMA/FIFO channels 1173 * supported in hardware (don't confuse these with the 16 Tx queues in DRAM, 1174 * which feed the DMA/FIFO channels); config regs are separated by 0x20 bytes. 1175 * 1176 * To use a Tx DMA channel, driver must initialize its 1177 * FH49_TCSR_CHNL_TX_CONFIG_REG(chnl) with: 1178 * 1179 * FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 1180 * FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL 1181 * 1182 * All other bits should be 0. 1183 * 1184 * Bit fields: 1185 * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame, 1186 * '10' operate normally 1187 * 29- 4: Reserved, set to "0" 1188 * 3: Enable internal DMA requests (1, normal operation), disable (0) 1189 * 2- 0: Reserved, set to "0" 1190 */ 1191#define FH49_TCSR_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0xD00) 1192#define FH49_TCSR_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0xE60) 1193 1194/* Find Control/Status reg for given Tx DMA/FIFO channel */ 1195#define FH49_TCSR_CHNL_NUM (7) 1196#define FH50_TCSR_CHNL_NUM (8) 1197 1198/* TCSR: tx_config register values */ 1199#define FH49_TCSR_CHNL_TX_CONFIG_REG(_chnl) \ 1200 (FH49_TCSR_LOWER_BOUND + 0x20 * (_chnl)) 1201#define FH49_TCSR_CHNL_TX_CREDIT_REG(_chnl) \ 1202 (FH49_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x4) 1203#define FH49_TCSR_CHNL_TX_BUF_STS_REG(_chnl) \ 1204 (FH49_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x8) 1205 1206#define FH49_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000) 1207#define FH49_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRV (0x00000001) 1208 1209#define FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE (0x00000000) 1210#define FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE (0x00000008) 1211 1212#define FH49_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT (0x00000000) 1213#define FH49_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD (0x00100000) 1214#define FH49_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000) 1215 1216#define FH49_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000) 1217#define FH49_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_ENDTFD (0x00400000) 1218#define FH49_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_IFTFD (0x00800000) 1219 1220#define FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000) 1221#define FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000) 1222#define FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000) 1223 1224#define FH49_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY (0x00000000) 1225#define FH49_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT (0x00002000) 1226#define FH49_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00000003) 1227 1228#define FH49_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM (20) 1229#define FH49_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX (12) 1230 1231/** 1232 * Tx Shared Status Registers (TSSR) 1233 * 1234 * After stopping Tx DMA channel (writing 0 to 1235 * FH49_TCSR_CHNL_TX_CONFIG_REG(chnl)), driver must poll 1236 * FH49_TSSR_TX_STATUS_REG until selected Tx channel is idle 1237 * (channel's buffers empty | no pending requests). 1238 * 1239 * Bit fields: 1240 * 31-24: 1 = Channel buffers empty (channel 7:0) 1241 * 23-16: 1 = No pending requests (channel 7:0) 1242 */ 1243#define FH49_TSSR_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0xEA0) 1244#define FH49_TSSR_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0xEC0) 1245 1246#define FH49_TSSR_TX_STATUS_REG (FH49_TSSR_LOWER_BOUND + 0x010) 1247 1248/** 1249 * Bit fields for TSSR(Tx Shared Status & Control) error status register: 1250 * 31: Indicates an address error when accessed to internal memory 1251 * uCode/driver must write "1" in order to clear this flag 1252 * 30: Indicates that Host did not send the expected number of dwords to FH 1253 * uCode/driver must write "1" in order to clear this flag 1254 * 16-9:Each status bit is for one channel. Indicates that an (Error) ActDMA 1255 * command was received from the scheduler while the TRB was already full 1256 * with previous command 1257 * uCode/driver must write "1" in order to clear this flag 1258 * 7-0: Each status bit indicates a channel's TxCredit error. When an error 1259 * bit is set, it indicates that the FH has received a full indication 1260 * from the RTC TxFIFO and the current value of the TxCredit counter was 1261 * not equal to zero. This mean that the credit mechanism was not 1262 * synchronized to the TxFIFO status 1263 * uCode/driver must write "1" in order to clear this flag 1264 */ 1265#define FH49_TSSR_TX_ERROR_REG (FH49_TSSR_LOWER_BOUND + 0x018) 1266 1267#define FH49_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) ((1 << (_chnl)) << 16) 1268 1269/* Tx service channels */ 1270#define FH49_SRVC_CHNL (9) 1271#define FH49_SRVC_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0x9C8) 1272#define FH49_SRVC_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0x9D0) 1273#define FH49_SRVC_CHNL_SRAM_ADDR_REG(_chnl) \ 1274 (FH49_SRVC_LOWER_BOUND + ((_chnl) - 9) * 0x4) 1275 1276#define FH49_TX_CHICKEN_BITS_REG (FH49_MEM_LOWER_BOUND + 0xE98) 1277/* Instruct FH to increment the retry count of a packet when 1278 * it is brought from the memory to TX-FIFO 1279 */ 1280#define FH49_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN (0x00000002) 1281 1282/* Keep Warm Size */ 1283#define IL_KW_SIZE 0x1000 /* 4k */ 1284 1285#endif /* __il_4965_h__ */ 1286