1/* 2 * 3 * Broadcom B43legacy wireless driver 4 * 5 * Copyright (c) 2005 Martin Langer <martin-langer@gmx.de> 6 * Copyright (c) 2005-2008 Stefano Brivio <stefano.brivio@polimi.it> 7 * Copyright (c) 2005, 2006 Michael Buesch <m@bues.ch> 8 * Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org> 9 * Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch> 10 * Copyright (c) 2007 Larry Finger <Larry.Finger@lwfinger.net> 11 * 12 * Some parts of the code in this file are derived from the ipw2200 13 * driver Copyright(c) 2003 - 2004 Intel Corporation. 14 15 * This program is free software; you can redistribute it and/or modify 16 * it under the terms of the GNU General Public License as published by 17 * the Free Software Foundation; either version 2 of the License, or 18 * (at your option) any later version. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * You should have received a copy of the GNU General Public License 26 * along with this program; see the file COPYING. If not, write to 27 * the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor, 28 * Boston, MA 02110-1301, USA. 29 * 30 */ 31 32#include <linux/delay.h> 33#include <linux/init.h> 34#include <linux/module.h> 35#include <linux/if_arp.h> 36#include <linux/etherdevice.h> 37#include <linux/firmware.h> 38#include <linux/workqueue.h> 39#include <linux/sched.h> 40#include <linux/skbuff.h> 41#include <linux/dma-mapping.h> 42#include <linux/slab.h> 43#include <net/dst.h> 44#include <asm/unaligned.h> 45 46#include "b43legacy.h" 47#include "main.h" 48#include "debugfs.h" 49#include "phy.h" 50#include "dma.h" 51#include "pio.h" 52#include "sysfs.h" 53#include "xmit.h" 54#include "radio.h" 55 56 57MODULE_DESCRIPTION("Broadcom B43legacy wireless driver"); 58MODULE_AUTHOR("Martin Langer"); 59MODULE_AUTHOR("Stefano Brivio"); 60MODULE_AUTHOR("Michael Buesch"); 61MODULE_LICENSE("GPL"); 62 63MODULE_FIRMWARE("b43legacy/ucode2.fw"); 64MODULE_FIRMWARE("b43legacy/ucode4.fw"); 65 66#if defined(CONFIG_B43LEGACY_DMA) && defined(CONFIG_B43LEGACY_PIO) 67static int modparam_pio; 68module_param_named(pio, modparam_pio, int, 0444); 69MODULE_PARM_DESC(pio, "enable(1) / disable(0) PIO mode"); 70#elif defined(CONFIG_B43LEGACY_DMA) 71# define modparam_pio 0 72#elif defined(CONFIG_B43LEGACY_PIO) 73# define modparam_pio 1 74#endif 75 76static int modparam_bad_frames_preempt; 77module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444); 78MODULE_PARM_DESC(bad_frames_preempt, "enable(1) / disable(0) Bad Frames" 79 " Preemption"); 80 81static char modparam_fwpostfix[16]; 82module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444); 83MODULE_PARM_DESC(fwpostfix, "Postfix for the firmware files to load."); 84 85/* The following table supports BCM4301, BCM4303 and BCM4306/2 devices. */ 86static const struct ssb_device_id b43legacy_ssb_tbl[] = { 87 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 2), 88 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 4), 89 {}, 90}; 91MODULE_DEVICE_TABLE(ssb, b43legacy_ssb_tbl); 92 93 94/* Channel and ratetables are shared for all devices. 95 * They can't be const, because ieee80211 puts some precalculated 96 * data in there. This data is the same for all devices, so we don't 97 * get concurrency issues */ 98#define RATETAB_ENT(_rateid, _flags) \ 99 { \ 100 .bitrate = B43legacy_RATE_TO_100KBPS(_rateid), \ 101 .hw_value = (_rateid), \ 102 .flags = (_flags), \ 103 } 104/* 105 * NOTE: When changing this, sync with xmit.c's 106 * b43legacy_plcp_get_bitrate_idx_* functions! 107 */ 108static struct ieee80211_rate __b43legacy_ratetable[] = { 109 RATETAB_ENT(B43legacy_CCK_RATE_1MB, 0), 110 RATETAB_ENT(B43legacy_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE), 111 RATETAB_ENT(B43legacy_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE), 112 RATETAB_ENT(B43legacy_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE), 113 RATETAB_ENT(B43legacy_OFDM_RATE_6MB, 0), 114 RATETAB_ENT(B43legacy_OFDM_RATE_9MB, 0), 115 RATETAB_ENT(B43legacy_OFDM_RATE_12MB, 0), 116 RATETAB_ENT(B43legacy_OFDM_RATE_18MB, 0), 117 RATETAB_ENT(B43legacy_OFDM_RATE_24MB, 0), 118 RATETAB_ENT(B43legacy_OFDM_RATE_36MB, 0), 119 RATETAB_ENT(B43legacy_OFDM_RATE_48MB, 0), 120 RATETAB_ENT(B43legacy_OFDM_RATE_54MB, 0), 121}; 122#define b43legacy_b_ratetable (__b43legacy_ratetable + 0) 123#define b43legacy_b_ratetable_size 4 124#define b43legacy_g_ratetable (__b43legacy_ratetable + 0) 125#define b43legacy_g_ratetable_size 12 126 127#define CHANTAB_ENT(_chanid, _freq) \ 128 { \ 129 .center_freq = (_freq), \ 130 .hw_value = (_chanid), \ 131 } 132static struct ieee80211_channel b43legacy_bg_chantable[] = { 133 CHANTAB_ENT(1, 2412), 134 CHANTAB_ENT(2, 2417), 135 CHANTAB_ENT(3, 2422), 136 CHANTAB_ENT(4, 2427), 137 CHANTAB_ENT(5, 2432), 138 CHANTAB_ENT(6, 2437), 139 CHANTAB_ENT(7, 2442), 140 CHANTAB_ENT(8, 2447), 141 CHANTAB_ENT(9, 2452), 142 CHANTAB_ENT(10, 2457), 143 CHANTAB_ENT(11, 2462), 144 CHANTAB_ENT(12, 2467), 145 CHANTAB_ENT(13, 2472), 146 CHANTAB_ENT(14, 2484), 147}; 148 149static struct ieee80211_supported_band b43legacy_band_2GHz_BPHY = { 150 .channels = b43legacy_bg_chantable, 151 .n_channels = ARRAY_SIZE(b43legacy_bg_chantable), 152 .bitrates = b43legacy_b_ratetable, 153 .n_bitrates = b43legacy_b_ratetable_size, 154}; 155 156static struct ieee80211_supported_band b43legacy_band_2GHz_GPHY = { 157 .channels = b43legacy_bg_chantable, 158 .n_channels = ARRAY_SIZE(b43legacy_bg_chantable), 159 .bitrates = b43legacy_g_ratetable, 160 .n_bitrates = b43legacy_g_ratetable_size, 161}; 162 163static void b43legacy_wireless_core_exit(struct b43legacy_wldev *dev); 164static int b43legacy_wireless_core_init(struct b43legacy_wldev *dev); 165static void b43legacy_wireless_core_stop(struct b43legacy_wldev *dev); 166static int b43legacy_wireless_core_start(struct b43legacy_wldev *dev); 167 168 169static int b43legacy_ratelimit(struct b43legacy_wl *wl) 170{ 171 if (!wl || !wl->current_dev) 172 return 1; 173 if (b43legacy_status(wl->current_dev) < B43legacy_STAT_STARTED) 174 return 1; 175 /* We are up and running. 176 * Ratelimit the messages to avoid DoS over the net. */ 177 return net_ratelimit(); 178} 179 180void b43legacyinfo(struct b43legacy_wl *wl, const char *fmt, ...) 181{ 182 struct va_format vaf; 183 va_list args; 184 185 if (!b43legacy_ratelimit(wl)) 186 return; 187 188 va_start(args, fmt); 189 190 vaf.fmt = fmt; 191 vaf.va = &args; 192 193 printk(KERN_INFO "b43legacy-%s: %pV", 194 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf); 195 196 va_end(args); 197} 198 199void b43legacyerr(struct b43legacy_wl *wl, const char *fmt, ...) 200{ 201 struct va_format vaf; 202 va_list args; 203 204 if (!b43legacy_ratelimit(wl)) 205 return; 206 207 va_start(args, fmt); 208 209 vaf.fmt = fmt; 210 vaf.va = &args; 211 212 printk(KERN_ERR "b43legacy-%s ERROR: %pV", 213 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf); 214 215 va_end(args); 216} 217 218void b43legacywarn(struct b43legacy_wl *wl, const char *fmt, ...) 219{ 220 struct va_format vaf; 221 va_list args; 222 223 if (!b43legacy_ratelimit(wl)) 224 return; 225 226 va_start(args, fmt); 227 228 vaf.fmt = fmt; 229 vaf.va = &args; 230 231 printk(KERN_WARNING "b43legacy-%s warning: %pV", 232 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf); 233 234 va_end(args); 235} 236 237#if B43legacy_DEBUG 238void b43legacydbg(struct b43legacy_wl *wl, const char *fmt, ...) 239{ 240 struct va_format vaf; 241 va_list args; 242 243 va_start(args, fmt); 244 245 vaf.fmt = fmt; 246 vaf.va = &args; 247 248 printk(KERN_DEBUG "b43legacy-%s debug: %pV", 249 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf); 250 251 va_end(args); 252} 253#endif /* DEBUG */ 254 255static void b43legacy_ram_write(struct b43legacy_wldev *dev, u16 offset, 256 u32 val) 257{ 258 u32 status; 259 260 B43legacy_WARN_ON(offset % 4 != 0); 261 262 status = b43legacy_read32(dev, B43legacy_MMIO_MACCTL); 263 if (status & B43legacy_MACCTL_BE) 264 val = swab32(val); 265 266 b43legacy_write32(dev, B43legacy_MMIO_RAM_CONTROL, offset); 267 mmiowb(); 268 b43legacy_write32(dev, B43legacy_MMIO_RAM_DATA, val); 269} 270 271static inline 272void b43legacy_shm_control_word(struct b43legacy_wldev *dev, 273 u16 routing, u16 offset) 274{ 275 u32 control; 276 277 /* "offset" is the WORD offset. */ 278 279 control = routing; 280 control <<= 16; 281 control |= offset; 282 b43legacy_write32(dev, B43legacy_MMIO_SHM_CONTROL, control); 283} 284 285u32 b43legacy_shm_read32(struct b43legacy_wldev *dev, 286 u16 routing, u16 offset) 287{ 288 u32 ret; 289 290 if (routing == B43legacy_SHM_SHARED) { 291 B43legacy_WARN_ON((offset & 0x0001) != 0); 292 if (offset & 0x0003) { 293 /* Unaligned access */ 294 b43legacy_shm_control_word(dev, routing, offset >> 2); 295 ret = b43legacy_read16(dev, 296 B43legacy_MMIO_SHM_DATA_UNALIGNED); 297 ret <<= 16; 298 b43legacy_shm_control_word(dev, routing, 299 (offset >> 2) + 1); 300 ret |= b43legacy_read16(dev, B43legacy_MMIO_SHM_DATA); 301 302 return ret; 303 } 304 offset >>= 2; 305 } 306 b43legacy_shm_control_word(dev, routing, offset); 307 ret = b43legacy_read32(dev, B43legacy_MMIO_SHM_DATA); 308 309 return ret; 310} 311 312u16 b43legacy_shm_read16(struct b43legacy_wldev *dev, 313 u16 routing, u16 offset) 314{ 315 u16 ret; 316 317 if (routing == B43legacy_SHM_SHARED) { 318 B43legacy_WARN_ON((offset & 0x0001) != 0); 319 if (offset & 0x0003) { 320 /* Unaligned access */ 321 b43legacy_shm_control_word(dev, routing, offset >> 2); 322 ret = b43legacy_read16(dev, 323 B43legacy_MMIO_SHM_DATA_UNALIGNED); 324 325 return ret; 326 } 327 offset >>= 2; 328 } 329 b43legacy_shm_control_word(dev, routing, offset); 330 ret = b43legacy_read16(dev, B43legacy_MMIO_SHM_DATA); 331 332 return ret; 333} 334 335void b43legacy_shm_write32(struct b43legacy_wldev *dev, 336 u16 routing, u16 offset, 337 u32 value) 338{ 339 if (routing == B43legacy_SHM_SHARED) { 340 B43legacy_WARN_ON((offset & 0x0001) != 0); 341 if (offset & 0x0003) { 342 /* Unaligned access */ 343 b43legacy_shm_control_word(dev, routing, offset >> 2); 344 mmiowb(); 345 b43legacy_write16(dev, 346 B43legacy_MMIO_SHM_DATA_UNALIGNED, 347 (value >> 16) & 0xffff); 348 mmiowb(); 349 b43legacy_shm_control_word(dev, routing, 350 (offset >> 2) + 1); 351 mmiowb(); 352 b43legacy_write16(dev, B43legacy_MMIO_SHM_DATA, 353 value & 0xffff); 354 return; 355 } 356 offset >>= 2; 357 } 358 b43legacy_shm_control_word(dev, routing, offset); 359 mmiowb(); 360 b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA, value); 361} 362 363void b43legacy_shm_write16(struct b43legacy_wldev *dev, u16 routing, u16 offset, 364 u16 value) 365{ 366 if (routing == B43legacy_SHM_SHARED) { 367 B43legacy_WARN_ON((offset & 0x0001) != 0); 368 if (offset & 0x0003) { 369 /* Unaligned access */ 370 b43legacy_shm_control_word(dev, routing, offset >> 2); 371 mmiowb(); 372 b43legacy_write16(dev, 373 B43legacy_MMIO_SHM_DATA_UNALIGNED, 374 value); 375 return; 376 } 377 offset >>= 2; 378 } 379 b43legacy_shm_control_word(dev, routing, offset); 380 mmiowb(); 381 b43legacy_write16(dev, B43legacy_MMIO_SHM_DATA, value); 382} 383 384/* Read HostFlags */ 385u32 b43legacy_hf_read(struct b43legacy_wldev *dev) 386{ 387 u32 ret; 388 389 ret = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED, 390 B43legacy_SHM_SH_HOSTFHI); 391 ret <<= 16; 392 ret |= b43legacy_shm_read16(dev, B43legacy_SHM_SHARED, 393 B43legacy_SHM_SH_HOSTFLO); 394 395 return ret; 396} 397 398/* Write HostFlags */ 399void b43legacy_hf_write(struct b43legacy_wldev *dev, u32 value) 400{ 401 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 402 B43legacy_SHM_SH_HOSTFLO, 403 (value & 0x0000FFFF)); 404 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 405 B43legacy_SHM_SH_HOSTFHI, 406 ((value & 0xFFFF0000) >> 16)); 407} 408 409void b43legacy_tsf_read(struct b43legacy_wldev *dev, u64 *tsf) 410{ 411 /* We need to be careful. As we read the TSF from multiple 412 * registers, we should take care of register overflows. 413 * In theory, the whole tsf read process should be atomic. 414 * We try to be atomic here, by restaring the read process, 415 * if any of the high registers changed (overflew). 416 */ 417 if (dev->dev->id.revision >= 3) { 418 u32 low; 419 u32 high; 420 u32 high2; 421 422 do { 423 high = b43legacy_read32(dev, 424 B43legacy_MMIO_REV3PLUS_TSF_HIGH); 425 low = b43legacy_read32(dev, 426 B43legacy_MMIO_REV3PLUS_TSF_LOW); 427 high2 = b43legacy_read32(dev, 428 B43legacy_MMIO_REV3PLUS_TSF_HIGH); 429 } while (unlikely(high != high2)); 430 431 *tsf = high; 432 *tsf <<= 32; 433 *tsf |= low; 434 } else { 435 u64 tmp; 436 u16 v0; 437 u16 v1; 438 u16 v2; 439 u16 v3; 440 u16 test1; 441 u16 test2; 442 u16 test3; 443 444 do { 445 v3 = b43legacy_read16(dev, B43legacy_MMIO_TSF_3); 446 v2 = b43legacy_read16(dev, B43legacy_MMIO_TSF_2); 447 v1 = b43legacy_read16(dev, B43legacy_MMIO_TSF_1); 448 v0 = b43legacy_read16(dev, B43legacy_MMIO_TSF_0); 449 450 test3 = b43legacy_read16(dev, B43legacy_MMIO_TSF_3); 451 test2 = b43legacy_read16(dev, B43legacy_MMIO_TSF_2); 452 test1 = b43legacy_read16(dev, B43legacy_MMIO_TSF_1); 453 } while (v3 != test3 || v2 != test2 || v1 != test1); 454 455 *tsf = v3; 456 *tsf <<= 48; 457 tmp = v2; 458 tmp <<= 32; 459 *tsf |= tmp; 460 tmp = v1; 461 tmp <<= 16; 462 *tsf |= tmp; 463 *tsf |= v0; 464 } 465} 466 467static void b43legacy_time_lock(struct b43legacy_wldev *dev) 468{ 469 u32 status; 470 471 status = b43legacy_read32(dev, B43legacy_MMIO_MACCTL); 472 status |= B43legacy_MACCTL_TBTTHOLD; 473 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, status); 474 mmiowb(); 475} 476 477static void b43legacy_time_unlock(struct b43legacy_wldev *dev) 478{ 479 u32 status; 480 481 status = b43legacy_read32(dev, B43legacy_MMIO_MACCTL); 482 status &= ~B43legacy_MACCTL_TBTTHOLD; 483 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, status); 484} 485 486static void b43legacy_tsf_write_locked(struct b43legacy_wldev *dev, u64 tsf) 487{ 488 /* Be careful with the in-progress timer. 489 * First zero out the low register, so we have a full 490 * register-overflow duration to complete the operation. 491 */ 492 if (dev->dev->id.revision >= 3) { 493 u32 lo = (tsf & 0x00000000FFFFFFFFULL); 494 u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32; 495 496 b43legacy_write32(dev, B43legacy_MMIO_REV3PLUS_TSF_LOW, 0); 497 mmiowb(); 498 b43legacy_write32(dev, B43legacy_MMIO_REV3PLUS_TSF_HIGH, 499 hi); 500 mmiowb(); 501 b43legacy_write32(dev, B43legacy_MMIO_REV3PLUS_TSF_LOW, 502 lo); 503 } else { 504 u16 v0 = (tsf & 0x000000000000FFFFULL); 505 u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16; 506 u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32; 507 u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48; 508 509 b43legacy_write16(dev, B43legacy_MMIO_TSF_0, 0); 510 mmiowb(); 511 b43legacy_write16(dev, B43legacy_MMIO_TSF_3, v3); 512 mmiowb(); 513 b43legacy_write16(dev, B43legacy_MMIO_TSF_2, v2); 514 mmiowb(); 515 b43legacy_write16(dev, B43legacy_MMIO_TSF_1, v1); 516 mmiowb(); 517 b43legacy_write16(dev, B43legacy_MMIO_TSF_0, v0); 518 } 519} 520 521void b43legacy_tsf_write(struct b43legacy_wldev *dev, u64 tsf) 522{ 523 b43legacy_time_lock(dev); 524 b43legacy_tsf_write_locked(dev, tsf); 525 b43legacy_time_unlock(dev); 526} 527 528static 529void b43legacy_macfilter_set(struct b43legacy_wldev *dev, 530 u16 offset, const u8 *mac) 531{ 532 static const u8 zero_addr[ETH_ALEN] = { 0 }; 533 u16 data; 534 535 if (!mac) 536 mac = zero_addr; 537 538 offset |= 0x0020; 539 b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_CONTROL, offset); 540 541 data = mac[0]; 542 data |= mac[1] << 8; 543 b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_DATA, data); 544 data = mac[2]; 545 data |= mac[3] << 8; 546 b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_DATA, data); 547 data = mac[4]; 548 data |= mac[5] << 8; 549 b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_DATA, data); 550} 551 552static void b43legacy_write_mac_bssid_templates(struct b43legacy_wldev *dev) 553{ 554 static const u8 zero_addr[ETH_ALEN] = { 0 }; 555 const u8 *mac = dev->wl->mac_addr; 556 const u8 *bssid = dev->wl->bssid; 557 u8 mac_bssid[ETH_ALEN * 2]; 558 int i; 559 u32 tmp; 560 561 if (!bssid) 562 bssid = zero_addr; 563 if (!mac) 564 mac = zero_addr; 565 566 b43legacy_macfilter_set(dev, B43legacy_MACFILTER_BSSID, bssid); 567 568 memcpy(mac_bssid, mac, ETH_ALEN); 569 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN); 570 571 /* Write our MAC address and BSSID to template ram */ 572 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) { 573 tmp = (u32)(mac_bssid[i + 0]); 574 tmp |= (u32)(mac_bssid[i + 1]) << 8; 575 tmp |= (u32)(mac_bssid[i + 2]) << 16; 576 tmp |= (u32)(mac_bssid[i + 3]) << 24; 577 b43legacy_ram_write(dev, 0x20 + i, tmp); 578 b43legacy_ram_write(dev, 0x78 + i, tmp); 579 b43legacy_ram_write(dev, 0x478 + i, tmp); 580 } 581} 582 583static void b43legacy_upload_card_macaddress(struct b43legacy_wldev *dev) 584{ 585 b43legacy_write_mac_bssid_templates(dev); 586 b43legacy_macfilter_set(dev, B43legacy_MACFILTER_SELF, 587 dev->wl->mac_addr); 588} 589 590static void b43legacy_set_slot_time(struct b43legacy_wldev *dev, 591 u16 slot_time) 592{ 593 /* slot_time is in usec. */ 594 if (dev->phy.type != B43legacy_PHYTYPE_G) 595 return; 596 b43legacy_write16(dev, 0x684, 510 + slot_time); 597 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0010, 598 slot_time); 599} 600 601static void b43legacy_short_slot_timing_enable(struct b43legacy_wldev *dev) 602{ 603 b43legacy_set_slot_time(dev, 9); 604} 605 606static void b43legacy_short_slot_timing_disable(struct b43legacy_wldev *dev) 607{ 608 b43legacy_set_slot_time(dev, 20); 609} 610 611/* Synchronize IRQ top- and bottom-half. 612 * IRQs must be masked before calling this. 613 * This must not be called with the irq_lock held. 614 */ 615static void b43legacy_synchronize_irq(struct b43legacy_wldev *dev) 616{ 617 synchronize_irq(dev->dev->irq); 618 tasklet_kill(&dev->isr_tasklet); 619} 620 621/* DummyTransmission function, as documented on 622 * http://bcm-specs.sipsolutions.net/DummyTransmission 623 */ 624void b43legacy_dummy_transmission(struct b43legacy_wldev *dev) 625{ 626 struct b43legacy_phy *phy = &dev->phy; 627 unsigned int i; 628 unsigned int max_loop; 629 u16 value; 630 u32 buffer[5] = { 631 0x00000000, 632 0x00D40000, 633 0x00000000, 634 0x01000000, 635 0x00000000, 636 }; 637 638 switch (phy->type) { 639 case B43legacy_PHYTYPE_B: 640 case B43legacy_PHYTYPE_G: 641 max_loop = 0xFA; 642 buffer[0] = 0x000B846E; 643 break; 644 default: 645 B43legacy_BUG_ON(1); 646 return; 647 } 648 649 for (i = 0; i < 5; i++) 650 b43legacy_ram_write(dev, i * 4, buffer[i]); 651 652 /* dummy read follows */ 653 b43legacy_read32(dev, B43legacy_MMIO_MACCTL); 654 655 b43legacy_write16(dev, 0x0568, 0x0000); 656 b43legacy_write16(dev, 0x07C0, 0x0000); 657 b43legacy_write16(dev, 0x050C, 0x0000); 658 b43legacy_write16(dev, 0x0508, 0x0000); 659 b43legacy_write16(dev, 0x050A, 0x0000); 660 b43legacy_write16(dev, 0x054C, 0x0000); 661 b43legacy_write16(dev, 0x056A, 0x0014); 662 b43legacy_write16(dev, 0x0568, 0x0826); 663 b43legacy_write16(dev, 0x0500, 0x0000); 664 b43legacy_write16(dev, 0x0502, 0x0030); 665 666 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5) 667 b43legacy_radio_write16(dev, 0x0051, 0x0017); 668 for (i = 0x00; i < max_loop; i++) { 669 value = b43legacy_read16(dev, 0x050E); 670 if (value & 0x0080) 671 break; 672 udelay(10); 673 } 674 for (i = 0x00; i < 0x0A; i++) { 675 value = b43legacy_read16(dev, 0x050E); 676 if (value & 0x0400) 677 break; 678 udelay(10); 679 } 680 for (i = 0x00; i < 0x0A; i++) { 681 value = b43legacy_read16(dev, 0x0690); 682 if (!(value & 0x0100)) 683 break; 684 udelay(10); 685 } 686 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5) 687 b43legacy_radio_write16(dev, 0x0051, 0x0037); 688} 689 690/* Turn the Analog ON/OFF */ 691static void b43legacy_switch_analog(struct b43legacy_wldev *dev, int on) 692{ 693 b43legacy_write16(dev, B43legacy_MMIO_PHY0, on ? 0 : 0xF4); 694} 695 696void b43legacy_wireless_core_reset(struct b43legacy_wldev *dev, u32 flags) 697{ 698 u32 tmslow; 699 u32 macctl; 700 701 flags |= B43legacy_TMSLOW_PHYCLKEN; 702 flags |= B43legacy_TMSLOW_PHYRESET; 703 ssb_device_enable(dev->dev, flags); 704 msleep(2); /* Wait for the PLL to turn on. */ 705 706 /* Now take the PHY out of Reset again */ 707 tmslow = ssb_read32(dev->dev, SSB_TMSLOW); 708 tmslow |= SSB_TMSLOW_FGC; 709 tmslow &= ~B43legacy_TMSLOW_PHYRESET; 710 ssb_write32(dev->dev, SSB_TMSLOW, tmslow); 711 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */ 712 msleep(1); 713 tmslow &= ~SSB_TMSLOW_FGC; 714 ssb_write32(dev->dev, SSB_TMSLOW, tmslow); 715 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */ 716 msleep(1); 717 718 /* Turn Analog ON */ 719 b43legacy_switch_analog(dev, 1); 720 721 macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL); 722 macctl &= ~B43legacy_MACCTL_GMODE; 723 if (flags & B43legacy_TMSLOW_GMODE) { 724 macctl |= B43legacy_MACCTL_GMODE; 725 dev->phy.gmode = true; 726 } else 727 dev->phy.gmode = false; 728 macctl |= B43legacy_MACCTL_IHR_ENABLED; 729 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl); 730} 731 732static void handle_irq_transmit_status(struct b43legacy_wldev *dev) 733{ 734 u32 v0; 735 u32 v1; 736 u16 tmp; 737 struct b43legacy_txstatus stat; 738 739 while (1) { 740 v0 = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_0); 741 if (!(v0 & 0x00000001)) 742 break; 743 v1 = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_1); 744 745 stat.cookie = (v0 >> 16); 746 stat.seq = (v1 & 0x0000FFFF); 747 stat.phy_stat = ((v1 & 0x00FF0000) >> 16); 748 tmp = (v0 & 0x0000FFFF); 749 stat.frame_count = ((tmp & 0xF000) >> 12); 750 stat.rts_count = ((tmp & 0x0F00) >> 8); 751 stat.supp_reason = ((tmp & 0x001C) >> 2); 752 stat.pm_indicated = !!(tmp & 0x0080); 753 stat.intermediate = !!(tmp & 0x0040); 754 stat.for_ampdu = !!(tmp & 0x0020); 755 stat.acked = !!(tmp & 0x0002); 756 757 b43legacy_handle_txstatus(dev, &stat); 758 } 759} 760 761static void drain_txstatus_queue(struct b43legacy_wldev *dev) 762{ 763 u32 dummy; 764 765 if (dev->dev->id.revision < 5) 766 return; 767 /* Read all entries from the microcode TXstatus FIFO 768 * and throw them away. 769 */ 770 while (1) { 771 dummy = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_0); 772 if (!(dummy & 0x00000001)) 773 break; 774 dummy = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_1); 775 } 776} 777 778static u32 b43legacy_jssi_read(struct b43legacy_wldev *dev) 779{ 780 u32 val = 0; 781 782 val = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED, 0x40A); 783 val <<= 16; 784 val |= b43legacy_shm_read16(dev, B43legacy_SHM_SHARED, 0x408); 785 786 return val; 787} 788 789static void b43legacy_jssi_write(struct b43legacy_wldev *dev, u32 jssi) 790{ 791 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x408, 792 (jssi & 0x0000FFFF)); 793 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x40A, 794 (jssi & 0xFFFF0000) >> 16); 795} 796 797static void b43legacy_generate_noise_sample(struct b43legacy_wldev *dev) 798{ 799 b43legacy_jssi_write(dev, 0x7F7F7F7F); 800 b43legacy_write32(dev, B43legacy_MMIO_MACCMD, 801 b43legacy_read32(dev, B43legacy_MMIO_MACCMD) 802 | B43legacy_MACCMD_BGNOISE); 803 B43legacy_WARN_ON(dev->noisecalc.channel_at_start != 804 dev->phy.channel); 805} 806 807static void b43legacy_calculate_link_quality(struct b43legacy_wldev *dev) 808{ 809 /* Top half of Link Quality calculation. */ 810 811 if (dev->noisecalc.calculation_running) 812 return; 813 dev->noisecalc.channel_at_start = dev->phy.channel; 814 dev->noisecalc.calculation_running = true; 815 dev->noisecalc.nr_samples = 0; 816 817 b43legacy_generate_noise_sample(dev); 818} 819 820static void handle_irq_noise(struct b43legacy_wldev *dev) 821{ 822 struct b43legacy_phy *phy = &dev->phy; 823 u16 tmp; 824 u8 noise[4]; 825 u8 i; 826 u8 j; 827 s32 average; 828 829 /* Bottom half of Link Quality calculation. */ 830 831 B43legacy_WARN_ON(!dev->noisecalc.calculation_running); 832 if (dev->noisecalc.channel_at_start != phy->channel) 833 goto drop_calculation; 834 *((__le32 *)noise) = cpu_to_le32(b43legacy_jssi_read(dev)); 835 if (noise[0] == 0x7F || noise[1] == 0x7F || 836 noise[2] == 0x7F || noise[3] == 0x7F) 837 goto generate_new; 838 839 /* Get the noise samples. */ 840 B43legacy_WARN_ON(dev->noisecalc.nr_samples >= 8); 841 i = dev->noisecalc.nr_samples; 842 noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1); 843 noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1); 844 noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1); 845 noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1); 846 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]]; 847 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]]; 848 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]]; 849 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]]; 850 dev->noisecalc.nr_samples++; 851 if (dev->noisecalc.nr_samples == 8) { 852 /* Calculate the Link Quality by the noise samples. */ 853 average = 0; 854 for (i = 0; i < 8; i++) { 855 for (j = 0; j < 4; j++) 856 average += dev->noisecalc.samples[i][j]; 857 } 858 average /= (8 * 4); 859 average *= 125; 860 average += 64; 861 average /= 128; 862 tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED, 863 0x40C); 864 tmp = (tmp / 128) & 0x1F; 865 if (tmp >= 8) 866 average += 2; 867 else 868 average -= 25; 869 if (tmp == 8) 870 average -= 72; 871 else 872 average -= 48; 873 874 dev->stats.link_noise = average; 875drop_calculation: 876 dev->noisecalc.calculation_running = false; 877 return; 878 } 879generate_new: 880 b43legacy_generate_noise_sample(dev); 881} 882 883static void handle_irq_tbtt_indication(struct b43legacy_wldev *dev) 884{ 885 if (b43legacy_is_mode(dev->wl, NL80211_IFTYPE_AP)) { 886 /* TODO: PS TBTT */ 887 } else { 888 if (1/*FIXME: the last PSpoll frame was sent successfully */) 889 b43legacy_power_saving_ctl_bits(dev, -1, -1); 890 } 891 if (b43legacy_is_mode(dev->wl, NL80211_IFTYPE_ADHOC)) 892 dev->dfq_valid = true; 893} 894 895static void handle_irq_atim_end(struct b43legacy_wldev *dev) 896{ 897 if (dev->dfq_valid) { 898 b43legacy_write32(dev, B43legacy_MMIO_MACCMD, 899 b43legacy_read32(dev, B43legacy_MMIO_MACCMD) 900 | B43legacy_MACCMD_DFQ_VALID); 901 dev->dfq_valid = false; 902 } 903} 904 905static void handle_irq_pmq(struct b43legacy_wldev *dev) 906{ 907 u32 tmp; 908 909 /* TODO: AP mode. */ 910 911 while (1) { 912 tmp = b43legacy_read32(dev, B43legacy_MMIO_PS_STATUS); 913 if (!(tmp & 0x00000008)) 914 break; 915 } 916 /* 16bit write is odd, but correct. */ 917 b43legacy_write16(dev, B43legacy_MMIO_PS_STATUS, 0x0002); 918} 919 920static void b43legacy_write_template_common(struct b43legacy_wldev *dev, 921 const u8 *data, u16 size, 922 u16 ram_offset, 923 u16 shm_size_offset, u8 rate) 924{ 925 u32 i; 926 u32 tmp; 927 struct b43legacy_plcp_hdr4 plcp; 928 929 plcp.data = 0; 930 b43legacy_generate_plcp_hdr(&plcp, size + FCS_LEN, rate); 931 b43legacy_ram_write(dev, ram_offset, le32_to_cpu(plcp.data)); 932 ram_offset += sizeof(u32); 933 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet. 934 * So leave the first two bytes of the next write blank. 935 */ 936 tmp = (u32)(data[0]) << 16; 937 tmp |= (u32)(data[1]) << 24; 938 b43legacy_ram_write(dev, ram_offset, tmp); 939 ram_offset += sizeof(u32); 940 for (i = 2; i < size; i += sizeof(u32)) { 941 tmp = (u32)(data[i + 0]); 942 if (i + 1 < size) 943 tmp |= (u32)(data[i + 1]) << 8; 944 if (i + 2 < size) 945 tmp |= (u32)(data[i + 2]) << 16; 946 if (i + 3 < size) 947 tmp |= (u32)(data[i + 3]) << 24; 948 b43legacy_ram_write(dev, ram_offset + i - 2, tmp); 949 } 950 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_size_offset, 951 size + sizeof(struct b43legacy_plcp_hdr6)); 952} 953 954/* Convert a b43legacy antenna number value to the PHY TX control value. */ 955static u16 b43legacy_antenna_to_phyctl(int antenna) 956{ 957 switch (antenna) { 958 case B43legacy_ANTENNA0: 959 return B43legacy_TX4_PHY_ANT0; 960 case B43legacy_ANTENNA1: 961 return B43legacy_TX4_PHY_ANT1; 962 } 963 return B43legacy_TX4_PHY_ANTLAST; 964} 965 966static void b43legacy_write_beacon_template(struct b43legacy_wldev *dev, 967 u16 ram_offset, 968 u16 shm_size_offset) 969{ 970 971 unsigned int i, len, variable_len; 972 const struct ieee80211_mgmt *bcn; 973 const u8 *ie; 974 bool tim_found = false; 975 unsigned int rate; 976 u16 ctl; 977 int antenna; 978 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(dev->wl->current_beacon); 979 980 bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data); 981 len = min_t(size_t, dev->wl->current_beacon->len, 982 0x200 - sizeof(struct b43legacy_plcp_hdr6)); 983 rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value; 984 985 b43legacy_write_template_common(dev, (const u8 *)bcn, len, ram_offset, 986 shm_size_offset, rate); 987 988 /* Write the PHY TX control parameters. */ 989 antenna = B43legacy_ANTENNA_DEFAULT; 990 antenna = b43legacy_antenna_to_phyctl(antenna); 991 ctl = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED, 992 B43legacy_SHM_SH_BEACPHYCTL); 993 /* We can't send beacons with short preamble. Would get PHY errors. */ 994 ctl &= ~B43legacy_TX4_PHY_SHORTPRMBL; 995 ctl &= ~B43legacy_TX4_PHY_ANT; 996 ctl &= ~B43legacy_TX4_PHY_ENC; 997 ctl |= antenna; 998 ctl |= B43legacy_TX4_PHY_ENC_CCK; 999 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 1000 B43legacy_SHM_SH_BEACPHYCTL, ctl); 1001 1002 /* Find the position of the TIM and the DTIM_period value 1003 * and write them to SHM. */ 1004 ie = bcn->u.beacon.variable; 1005 variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable); 1006 for (i = 0; i < variable_len - 2; ) { 1007 uint8_t ie_id, ie_len; 1008 1009 ie_id = ie[i]; 1010 ie_len = ie[i + 1]; 1011 if (ie_id == 5) { 1012 u16 tim_position; 1013 u16 dtim_period; 1014 /* This is the TIM Information Element */ 1015 1016 /* Check whether the ie_len is in the beacon data range. */ 1017 if (variable_len < ie_len + 2 + i) 1018 break; 1019 /* A valid TIM is at least 4 bytes long. */ 1020 if (ie_len < 4) 1021 break; 1022 tim_found = true; 1023 1024 tim_position = sizeof(struct b43legacy_plcp_hdr6); 1025 tim_position += offsetof(struct ieee80211_mgmt, 1026 u.beacon.variable); 1027 tim_position += i; 1028 1029 dtim_period = ie[i + 3]; 1030 1031 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 1032 B43legacy_SHM_SH_TIMPOS, tim_position); 1033 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 1034 B43legacy_SHM_SH_DTIMP, dtim_period); 1035 break; 1036 } 1037 i += ie_len + 2; 1038 } 1039 if (!tim_found) { 1040 b43legacywarn(dev->wl, "Did not find a valid TIM IE in the " 1041 "beacon template packet. AP or IBSS operation " 1042 "may be broken.\n"); 1043 } else 1044 b43legacydbg(dev->wl, "Updated beacon template\n"); 1045} 1046 1047static void b43legacy_write_probe_resp_plcp(struct b43legacy_wldev *dev, 1048 u16 shm_offset, u16 size, 1049 struct ieee80211_rate *rate) 1050{ 1051 struct b43legacy_plcp_hdr4 plcp; 1052 u32 tmp; 1053 __le16 dur; 1054 1055 plcp.data = 0; 1056 b43legacy_generate_plcp_hdr(&plcp, size + FCS_LEN, rate->hw_value); 1057 dur = ieee80211_generic_frame_duration(dev->wl->hw, 1058 dev->wl->vif, 1059 IEEE80211_BAND_2GHZ, 1060 size, 1061 rate); 1062 /* Write PLCP in two parts and timing for packet transfer */ 1063 tmp = le32_to_cpu(plcp.data); 1064 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_offset, 1065 tmp & 0xFFFF); 1066 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_offset + 2, 1067 tmp >> 16); 1068 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_offset + 6, 1069 le16_to_cpu(dur)); 1070} 1071 1072/* Instead of using custom probe response template, this function 1073 * just patches custom beacon template by: 1074 * 1) Changing packet type 1075 * 2) Patching duration field 1076 * 3) Stripping TIM 1077 */ 1078static const u8 *b43legacy_generate_probe_resp(struct b43legacy_wldev *dev, 1079 u16 *dest_size, 1080 struct ieee80211_rate *rate) 1081{ 1082 const u8 *src_data; 1083 u8 *dest_data; 1084 u16 src_size, elem_size, src_pos, dest_pos; 1085 __le16 dur; 1086 struct ieee80211_hdr *hdr; 1087 size_t ie_start; 1088 1089 src_size = dev->wl->current_beacon->len; 1090 src_data = (const u8 *)dev->wl->current_beacon->data; 1091 1092 /* Get the start offset of the variable IEs in the packet. */ 1093 ie_start = offsetof(struct ieee80211_mgmt, u.probe_resp.variable); 1094 B43legacy_WARN_ON(ie_start != offsetof(struct ieee80211_mgmt, 1095 u.beacon.variable)); 1096 1097 if (B43legacy_WARN_ON(src_size < ie_start)) 1098 return NULL; 1099 1100 dest_data = kmalloc(src_size, GFP_ATOMIC); 1101 if (unlikely(!dest_data)) 1102 return NULL; 1103 1104 /* Copy the static data and all Information Elements, except the TIM. */ 1105 memcpy(dest_data, src_data, ie_start); 1106 src_pos = ie_start; 1107 dest_pos = ie_start; 1108 for ( ; src_pos < src_size - 2; src_pos += elem_size) { 1109 elem_size = src_data[src_pos + 1] + 2; 1110 if (src_data[src_pos] == 5) { 1111 /* This is the TIM. */ 1112 continue; 1113 } 1114 memcpy(dest_data + dest_pos, src_data + src_pos, elem_size); 1115 dest_pos += elem_size; 1116 } 1117 *dest_size = dest_pos; 1118 hdr = (struct ieee80211_hdr *)dest_data; 1119 1120 /* Set the frame control. */ 1121 hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT | 1122 IEEE80211_STYPE_PROBE_RESP); 1123 dur = ieee80211_generic_frame_duration(dev->wl->hw, 1124 dev->wl->vif, 1125 IEEE80211_BAND_2GHZ, 1126 *dest_size, 1127 rate); 1128 hdr->duration_id = dur; 1129 1130 return dest_data; 1131} 1132 1133static void b43legacy_write_probe_resp_template(struct b43legacy_wldev *dev, 1134 u16 ram_offset, 1135 u16 shm_size_offset, 1136 struct ieee80211_rate *rate) 1137{ 1138 const u8 *probe_resp_data; 1139 u16 size; 1140 1141 size = dev->wl->current_beacon->len; 1142 probe_resp_data = b43legacy_generate_probe_resp(dev, &size, rate); 1143 if (unlikely(!probe_resp_data)) 1144 return; 1145 1146 /* Looks like PLCP headers plus packet timings are stored for 1147 * all possible basic rates 1148 */ 1149 b43legacy_write_probe_resp_plcp(dev, 0x31A, size, 1150 &b43legacy_b_ratetable[0]); 1151 b43legacy_write_probe_resp_plcp(dev, 0x32C, size, 1152 &b43legacy_b_ratetable[1]); 1153 b43legacy_write_probe_resp_plcp(dev, 0x33E, size, 1154 &b43legacy_b_ratetable[2]); 1155 b43legacy_write_probe_resp_plcp(dev, 0x350, size, 1156 &b43legacy_b_ratetable[3]); 1157 1158 size = min_t(size_t, size, 1159 0x200 - sizeof(struct b43legacy_plcp_hdr6)); 1160 b43legacy_write_template_common(dev, probe_resp_data, 1161 size, ram_offset, 1162 shm_size_offset, rate->hw_value); 1163 kfree(probe_resp_data); 1164} 1165 1166static void b43legacy_upload_beacon0(struct b43legacy_wldev *dev) 1167{ 1168 struct b43legacy_wl *wl = dev->wl; 1169 1170 if (wl->beacon0_uploaded) 1171 return; 1172 b43legacy_write_beacon_template(dev, 0x68, 0x18); 1173 /* FIXME: Probe resp upload doesn't really belong here, 1174 * but we don't use that feature anyway. */ 1175 b43legacy_write_probe_resp_template(dev, 0x268, 0x4A, 1176 &__b43legacy_ratetable[3]); 1177 wl->beacon0_uploaded = true; 1178} 1179 1180static void b43legacy_upload_beacon1(struct b43legacy_wldev *dev) 1181{ 1182 struct b43legacy_wl *wl = dev->wl; 1183 1184 if (wl->beacon1_uploaded) 1185 return; 1186 b43legacy_write_beacon_template(dev, 0x468, 0x1A); 1187 wl->beacon1_uploaded = true; 1188} 1189 1190static void handle_irq_beacon(struct b43legacy_wldev *dev) 1191{ 1192 struct b43legacy_wl *wl = dev->wl; 1193 u32 cmd, beacon0_valid, beacon1_valid; 1194 1195 if (!b43legacy_is_mode(wl, NL80211_IFTYPE_AP)) 1196 return; 1197 1198 /* This is the bottom half of the asynchronous beacon update. */ 1199 1200 /* Ignore interrupt in the future. */ 1201 dev->irq_mask &= ~B43legacy_IRQ_BEACON; 1202 1203 cmd = b43legacy_read32(dev, B43legacy_MMIO_MACCMD); 1204 beacon0_valid = (cmd & B43legacy_MACCMD_BEACON0_VALID); 1205 beacon1_valid = (cmd & B43legacy_MACCMD_BEACON1_VALID); 1206 1207 /* Schedule interrupt manually, if busy. */ 1208 if (beacon0_valid && beacon1_valid) { 1209 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON, B43legacy_IRQ_BEACON); 1210 dev->irq_mask |= B43legacy_IRQ_BEACON; 1211 return; 1212 } 1213 1214 if (unlikely(wl->beacon_templates_virgin)) { 1215 /* We never uploaded a beacon before. 1216 * Upload both templates now, but only mark one valid. */ 1217 wl->beacon_templates_virgin = false; 1218 b43legacy_upload_beacon0(dev); 1219 b43legacy_upload_beacon1(dev); 1220 cmd = b43legacy_read32(dev, B43legacy_MMIO_MACCMD); 1221 cmd |= B43legacy_MACCMD_BEACON0_VALID; 1222 b43legacy_write32(dev, B43legacy_MMIO_MACCMD, cmd); 1223 } else { 1224 if (!beacon0_valid) { 1225 b43legacy_upload_beacon0(dev); 1226 cmd = b43legacy_read32(dev, B43legacy_MMIO_MACCMD); 1227 cmd |= B43legacy_MACCMD_BEACON0_VALID; 1228 b43legacy_write32(dev, B43legacy_MMIO_MACCMD, cmd); 1229 } else if (!beacon1_valid) { 1230 b43legacy_upload_beacon1(dev); 1231 cmd = b43legacy_read32(dev, B43legacy_MMIO_MACCMD); 1232 cmd |= B43legacy_MACCMD_BEACON1_VALID; 1233 b43legacy_write32(dev, B43legacy_MMIO_MACCMD, cmd); 1234 } 1235 } 1236} 1237 1238static void b43legacy_beacon_update_trigger_work(struct work_struct *work) 1239{ 1240 struct b43legacy_wl *wl = container_of(work, struct b43legacy_wl, 1241 beacon_update_trigger); 1242 struct b43legacy_wldev *dev; 1243 1244 mutex_lock(&wl->mutex); 1245 dev = wl->current_dev; 1246 if (likely(dev && (b43legacy_status(dev) >= B43legacy_STAT_INITIALIZED))) { 1247 spin_lock_irq(&wl->irq_lock); 1248 /* Update beacon right away or defer to IRQ. */ 1249 handle_irq_beacon(dev); 1250 /* The handler might have updated the IRQ mask. */ 1251 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, 1252 dev->irq_mask); 1253 mmiowb(); 1254 spin_unlock_irq(&wl->irq_lock); 1255 } 1256 mutex_unlock(&wl->mutex); 1257} 1258 1259/* Asynchronously update the packet templates in template RAM. 1260 * Locking: Requires wl->irq_lock to be locked. */ 1261static void b43legacy_update_templates(struct b43legacy_wl *wl) 1262{ 1263 struct sk_buff *beacon; 1264 /* This is the top half of the ansynchronous beacon update. The bottom 1265 * half is the beacon IRQ. Beacon update must be asynchronous to avoid 1266 * sending an invalid beacon. This can happen for example, if the 1267 * firmware transmits a beacon while we are updating it. */ 1268 1269 /* We could modify the existing beacon and set the aid bit in the TIM 1270 * field, but that would probably require resizing and moving of data 1271 * within the beacon template. Simply request a new beacon and let 1272 * mac80211 do the hard work. */ 1273 beacon = ieee80211_beacon_get(wl->hw, wl->vif); 1274 if (unlikely(!beacon)) 1275 return; 1276 1277 if (wl->current_beacon) 1278 dev_kfree_skb_any(wl->current_beacon); 1279 wl->current_beacon = beacon; 1280 wl->beacon0_uploaded = false; 1281 wl->beacon1_uploaded = false; 1282 ieee80211_queue_work(wl->hw, &wl->beacon_update_trigger); 1283} 1284 1285static void b43legacy_set_beacon_int(struct b43legacy_wldev *dev, 1286 u16 beacon_int) 1287{ 1288 b43legacy_time_lock(dev); 1289 if (dev->dev->id.revision >= 3) { 1290 b43legacy_write32(dev, B43legacy_MMIO_TSF_CFP_REP, 1291 (beacon_int << 16)); 1292 b43legacy_write32(dev, B43legacy_MMIO_TSF_CFP_START, 1293 (beacon_int << 10)); 1294 } else { 1295 b43legacy_write16(dev, 0x606, (beacon_int >> 6)); 1296 b43legacy_write16(dev, 0x610, beacon_int); 1297 } 1298 b43legacy_time_unlock(dev); 1299 b43legacydbg(dev->wl, "Set beacon interval to %u\n", beacon_int); 1300} 1301 1302static void handle_irq_ucode_debug(struct b43legacy_wldev *dev) 1303{ 1304} 1305 1306/* Interrupt handler bottom-half */ 1307static void b43legacy_interrupt_tasklet(struct b43legacy_wldev *dev) 1308{ 1309 u32 reason; 1310 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)]; 1311 u32 merged_dma_reason = 0; 1312 int i; 1313 unsigned long flags; 1314 1315 spin_lock_irqsave(&dev->wl->irq_lock, flags); 1316 1317 B43legacy_WARN_ON(b43legacy_status(dev) < 1318 B43legacy_STAT_INITIALIZED); 1319 1320 reason = dev->irq_reason; 1321 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) { 1322 dma_reason[i] = dev->dma_reason[i]; 1323 merged_dma_reason |= dma_reason[i]; 1324 } 1325 1326 if (unlikely(reason & B43legacy_IRQ_MAC_TXERR)) 1327 b43legacyerr(dev->wl, "MAC transmission error\n"); 1328 1329 if (unlikely(reason & B43legacy_IRQ_PHY_TXERR)) { 1330 b43legacyerr(dev->wl, "PHY transmission error\n"); 1331 rmb(); 1332 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) { 1333 b43legacyerr(dev->wl, "Too many PHY TX errors, " 1334 "restarting the controller\n"); 1335 b43legacy_controller_restart(dev, "PHY TX errors"); 1336 } 1337 } 1338 1339 if (unlikely(merged_dma_reason & (B43legacy_DMAIRQ_FATALMASK | 1340 B43legacy_DMAIRQ_NONFATALMASK))) { 1341 if (merged_dma_reason & B43legacy_DMAIRQ_FATALMASK) { 1342 b43legacyerr(dev->wl, "Fatal DMA error: " 1343 "0x%08X, 0x%08X, 0x%08X, " 1344 "0x%08X, 0x%08X, 0x%08X\n", 1345 dma_reason[0], dma_reason[1], 1346 dma_reason[2], dma_reason[3], 1347 dma_reason[4], dma_reason[5]); 1348 b43legacy_controller_restart(dev, "DMA error"); 1349 mmiowb(); 1350 spin_unlock_irqrestore(&dev->wl->irq_lock, flags); 1351 return; 1352 } 1353 if (merged_dma_reason & B43legacy_DMAIRQ_NONFATALMASK) 1354 b43legacyerr(dev->wl, "DMA error: " 1355 "0x%08X, 0x%08X, 0x%08X, " 1356 "0x%08X, 0x%08X, 0x%08X\n", 1357 dma_reason[0], dma_reason[1], 1358 dma_reason[2], dma_reason[3], 1359 dma_reason[4], dma_reason[5]); 1360 } 1361 1362 if (unlikely(reason & B43legacy_IRQ_UCODE_DEBUG)) 1363 handle_irq_ucode_debug(dev); 1364 if (reason & B43legacy_IRQ_TBTT_INDI) 1365 handle_irq_tbtt_indication(dev); 1366 if (reason & B43legacy_IRQ_ATIM_END) 1367 handle_irq_atim_end(dev); 1368 if (reason & B43legacy_IRQ_BEACON) 1369 handle_irq_beacon(dev); 1370 if (reason & B43legacy_IRQ_PMQ) 1371 handle_irq_pmq(dev); 1372 if (reason & B43legacy_IRQ_TXFIFO_FLUSH_OK) 1373 ;/*TODO*/ 1374 if (reason & B43legacy_IRQ_NOISESAMPLE_OK) 1375 handle_irq_noise(dev); 1376 1377 /* Check the DMA reason registers for received data. */ 1378 if (dma_reason[0] & B43legacy_DMAIRQ_RX_DONE) { 1379 if (b43legacy_using_pio(dev)) 1380 b43legacy_pio_rx(dev->pio.queue0); 1381 else 1382 b43legacy_dma_rx(dev->dma.rx_ring0); 1383 } 1384 B43legacy_WARN_ON(dma_reason[1] & B43legacy_DMAIRQ_RX_DONE); 1385 B43legacy_WARN_ON(dma_reason[2] & B43legacy_DMAIRQ_RX_DONE); 1386 if (dma_reason[3] & B43legacy_DMAIRQ_RX_DONE) { 1387 if (b43legacy_using_pio(dev)) 1388 b43legacy_pio_rx(dev->pio.queue3); 1389 else 1390 b43legacy_dma_rx(dev->dma.rx_ring3); 1391 } 1392 B43legacy_WARN_ON(dma_reason[4] & B43legacy_DMAIRQ_RX_DONE); 1393 B43legacy_WARN_ON(dma_reason[5] & B43legacy_DMAIRQ_RX_DONE); 1394 1395 if (reason & B43legacy_IRQ_TX_OK) 1396 handle_irq_transmit_status(dev); 1397 1398 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, dev->irq_mask); 1399 mmiowb(); 1400 spin_unlock_irqrestore(&dev->wl->irq_lock, flags); 1401} 1402 1403static void pio_irq_workaround(struct b43legacy_wldev *dev, 1404 u16 base, int queueidx) 1405{ 1406 u16 rxctl; 1407 1408 rxctl = b43legacy_read16(dev, base + B43legacy_PIO_RXCTL); 1409 if (rxctl & B43legacy_PIO_RXCTL_DATAAVAILABLE) 1410 dev->dma_reason[queueidx] |= B43legacy_DMAIRQ_RX_DONE; 1411 else 1412 dev->dma_reason[queueidx] &= ~B43legacy_DMAIRQ_RX_DONE; 1413} 1414 1415static void b43legacy_interrupt_ack(struct b43legacy_wldev *dev, u32 reason) 1416{ 1417 if (b43legacy_using_pio(dev) && 1418 (dev->dev->id.revision < 3) && 1419 (!(reason & B43legacy_IRQ_PIO_WORKAROUND))) { 1420 /* Apply a PIO specific workaround to the dma_reasons */ 1421 pio_irq_workaround(dev, B43legacy_MMIO_PIO1_BASE, 0); 1422 pio_irq_workaround(dev, B43legacy_MMIO_PIO2_BASE, 1); 1423 pio_irq_workaround(dev, B43legacy_MMIO_PIO3_BASE, 2); 1424 pio_irq_workaround(dev, B43legacy_MMIO_PIO4_BASE, 3); 1425 } 1426 1427 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON, reason); 1428 1429 b43legacy_write32(dev, B43legacy_MMIO_DMA0_REASON, 1430 dev->dma_reason[0]); 1431 b43legacy_write32(dev, B43legacy_MMIO_DMA1_REASON, 1432 dev->dma_reason[1]); 1433 b43legacy_write32(dev, B43legacy_MMIO_DMA2_REASON, 1434 dev->dma_reason[2]); 1435 b43legacy_write32(dev, B43legacy_MMIO_DMA3_REASON, 1436 dev->dma_reason[3]); 1437 b43legacy_write32(dev, B43legacy_MMIO_DMA4_REASON, 1438 dev->dma_reason[4]); 1439 b43legacy_write32(dev, B43legacy_MMIO_DMA5_REASON, 1440 dev->dma_reason[5]); 1441} 1442 1443/* Interrupt handler top-half */ 1444static irqreturn_t b43legacy_interrupt_handler(int irq, void *dev_id) 1445{ 1446 irqreturn_t ret = IRQ_NONE; 1447 struct b43legacy_wldev *dev = dev_id; 1448 u32 reason; 1449 1450 B43legacy_WARN_ON(!dev); 1451 1452 spin_lock(&dev->wl->irq_lock); 1453 1454 if (unlikely(b43legacy_status(dev) < B43legacy_STAT_STARTED)) 1455 /* This can only happen on shared IRQ lines. */ 1456 goto out; 1457 reason = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON); 1458 if (reason == 0xffffffff) /* shared IRQ */ 1459 goto out; 1460 ret = IRQ_HANDLED; 1461 reason &= dev->irq_mask; 1462 if (!reason) 1463 goto out; 1464 1465 dev->dma_reason[0] = b43legacy_read32(dev, 1466 B43legacy_MMIO_DMA0_REASON) 1467 & 0x0001DC00; 1468 dev->dma_reason[1] = b43legacy_read32(dev, 1469 B43legacy_MMIO_DMA1_REASON) 1470 & 0x0000DC00; 1471 dev->dma_reason[2] = b43legacy_read32(dev, 1472 B43legacy_MMIO_DMA2_REASON) 1473 & 0x0000DC00; 1474 dev->dma_reason[3] = b43legacy_read32(dev, 1475 B43legacy_MMIO_DMA3_REASON) 1476 & 0x0001DC00; 1477 dev->dma_reason[4] = b43legacy_read32(dev, 1478 B43legacy_MMIO_DMA4_REASON) 1479 & 0x0000DC00; 1480 dev->dma_reason[5] = b43legacy_read32(dev, 1481 B43legacy_MMIO_DMA5_REASON) 1482 & 0x0000DC00; 1483 1484 b43legacy_interrupt_ack(dev, reason); 1485 /* Disable all IRQs. They are enabled again in the bottom half. */ 1486 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, 0); 1487 /* Save the reason code and call our bottom half. */ 1488 dev->irq_reason = reason; 1489 tasklet_schedule(&dev->isr_tasklet); 1490out: 1491 mmiowb(); 1492 spin_unlock(&dev->wl->irq_lock); 1493 1494 return ret; 1495} 1496 1497static void b43legacy_release_firmware(struct b43legacy_wldev *dev) 1498{ 1499 release_firmware(dev->fw.ucode); 1500 dev->fw.ucode = NULL; 1501 release_firmware(dev->fw.pcm); 1502 dev->fw.pcm = NULL; 1503 release_firmware(dev->fw.initvals); 1504 dev->fw.initvals = NULL; 1505 release_firmware(dev->fw.initvals_band); 1506 dev->fw.initvals_band = NULL; 1507} 1508 1509static void b43legacy_print_fw_helptext(struct b43legacy_wl *wl) 1510{ 1511 b43legacyerr(wl, "You must go to http://wireless.kernel.org/en/users/" 1512 "Drivers/b43#devicefirmware " 1513 "and download the correct firmware (version 3).\n"); 1514} 1515 1516static void b43legacy_fw_cb(const struct firmware *firmware, void *context) 1517{ 1518 struct b43legacy_wldev *dev = context; 1519 1520 dev->fwp = firmware; 1521 complete(&dev->fw_load_complete); 1522} 1523 1524static int do_request_fw(struct b43legacy_wldev *dev, 1525 const char *name, 1526 const struct firmware **fw, bool async) 1527{ 1528 char path[sizeof(modparam_fwpostfix) + 32]; 1529 struct b43legacy_fw_header *hdr; 1530 u32 size; 1531 int err; 1532 1533 if (!name) 1534 return 0; 1535 1536 snprintf(path, ARRAY_SIZE(path), 1537 "b43legacy%s/%s.fw", 1538 modparam_fwpostfix, name); 1539 b43legacyinfo(dev->wl, "Loading firmware %s\n", path); 1540 if (async) { 1541 init_completion(&dev->fw_load_complete); 1542 err = request_firmware_nowait(THIS_MODULE, 1, path, 1543 dev->dev->dev, GFP_KERNEL, 1544 dev, b43legacy_fw_cb); 1545 if (err) { 1546 b43legacyerr(dev->wl, "Unable to load firmware\n"); 1547 return err; 1548 } 1549 /* stall here until fw ready */ 1550 wait_for_completion(&dev->fw_load_complete); 1551 if (!dev->fwp) 1552 err = -EINVAL; 1553 *fw = dev->fwp; 1554 } else { 1555 err = request_firmware(fw, path, dev->dev->dev); 1556 } 1557 if (err) { 1558 b43legacyerr(dev->wl, "Firmware file \"%s\" not found " 1559 "or load failed.\n", path); 1560 return err; 1561 } 1562 if ((*fw)->size < sizeof(struct b43legacy_fw_header)) 1563 goto err_format; 1564 hdr = (struct b43legacy_fw_header *)((*fw)->data); 1565 switch (hdr->type) { 1566 case B43legacy_FW_TYPE_UCODE: 1567 case B43legacy_FW_TYPE_PCM: 1568 size = be32_to_cpu(hdr->size); 1569 if (size != (*fw)->size - sizeof(struct b43legacy_fw_header)) 1570 goto err_format; 1571 /* fallthrough */ 1572 case B43legacy_FW_TYPE_IV: 1573 if (hdr->ver != 1) 1574 goto err_format; 1575 break; 1576 default: 1577 goto err_format; 1578 } 1579 1580 return err; 1581 1582err_format: 1583 b43legacyerr(dev->wl, "Firmware file \"%s\" format error.\n", path); 1584 return -EPROTO; 1585} 1586 1587static int b43legacy_one_core_attach(struct ssb_device *dev, 1588 struct b43legacy_wl *wl); 1589static void b43legacy_one_core_detach(struct ssb_device *dev); 1590 1591static void b43legacy_request_firmware(struct work_struct *work) 1592{ 1593 struct b43legacy_wl *wl = container_of(work, 1594 struct b43legacy_wl, firmware_load); 1595 struct b43legacy_wldev *dev = wl->current_dev; 1596 struct b43legacy_firmware *fw = &dev->fw; 1597 const u8 rev = dev->dev->id.revision; 1598 const char *filename; 1599 int err; 1600 1601 if (!fw->ucode) { 1602 if (rev == 2) 1603 filename = "ucode2"; 1604 else if (rev == 4) 1605 filename = "ucode4"; 1606 else 1607 filename = "ucode5"; 1608 err = do_request_fw(dev, filename, &fw->ucode, true); 1609 if (err) 1610 goto err_load; 1611 } 1612 if (!fw->pcm) { 1613 if (rev < 5) 1614 filename = "pcm4"; 1615 else 1616 filename = "pcm5"; 1617 err = do_request_fw(dev, filename, &fw->pcm, false); 1618 if (err) 1619 goto err_load; 1620 } 1621 if (!fw->initvals) { 1622 switch (dev->phy.type) { 1623 case B43legacy_PHYTYPE_B: 1624 case B43legacy_PHYTYPE_G: 1625 if ((rev >= 5) && (rev <= 10)) 1626 filename = "b0g0initvals5"; 1627 else if (rev == 2 || rev == 4) 1628 filename = "b0g0initvals2"; 1629 else 1630 goto err_no_initvals; 1631 break; 1632 default: 1633 goto err_no_initvals; 1634 } 1635 err = do_request_fw(dev, filename, &fw->initvals, false); 1636 if (err) 1637 goto err_load; 1638 } 1639 if (!fw->initvals_band) { 1640 switch (dev->phy.type) { 1641 case B43legacy_PHYTYPE_B: 1642 case B43legacy_PHYTYPE_G: 1643 if ((rev >= 5) && (rev <= 10)) 1644 filename = "b0g0bsinitvals5"; 1645 else if (rev >= 11) 1646 filename = NULL; 1647 else if (rev == 2 || rev == 4) 1648 filename = NULL; 1649 else 1650 goto err_no_initvals; 1651 break; 1652 default: 1653 goto err_no_initvals; 1654 } 1655 err = do_request_fw(dev, filename, &fw->initvals_band, false); 1656 if (err) 1657 goto err_load; 1658 } 1659 err = ieee80211_register_hw(wl->hw); 1660 if (err) 1661 goto err_one_core_detach; 1662 return; 1663 1664err_one_core_detach: 1665 b43legacy_one_core_detach(dev->dev); 1666 goto error; 1667 1668err_load: 1669 b43legacy_print_fw_helptext(dev->wl); 1670 goto error; 1671 1672err_no_initvals: 1673 err = -ENODEV; 1674 b43legacyerr(dev->wl, "No Initial Values firmware file for PHY %u, " 1675 "core rev %u\n", dev->phy.type, rev); 1676 goto error; 1677 1678error: 1679 b43legacy_release_firmware(dev); 1680 return; 1681} 1682 1683static int b43legacy_upload_microcode(struct b43legacy_wldev *dev) 1684{ 1685 struct wiphy *wiphy = dev->wl->hw->wiphy; 1686 const size_t hdr_len = sizeof(struct b43legacy_fw_header); 1687 const __be32 *data; 1688 unsigned int i; 1689 unsigned int len; 1690 u16 fwrev; 1691 u16 fwpatch; 1692 u16 fwdate; 1693 u16 fwtime; 1694 u32 tmp, macctl; 1695 int err = 0; 1696 1697 /* Jump the microcode PSM to offset 0 */ 1698 macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL); 1699 B43legacy_WARN_ON(macctl & B43legacy_MACCTL_PSM_RUN); 1700 macctl |= B43legacy_MACCTL_PSM_JMP0; 1701 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl); 1702 /* Zero out all microcode PSM registers and shared memory. */ 1703 for (i = 0; i < 64; i++) 1704 b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS, i, 0); 1705 for (i = 0; i < 4096; i += 2) 1706 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, i, 0); 1707 1708 /* Upload Microcode. */ 1709 data = (__be32 *) (dev->fw.ucode->data + hdr_len); 1710 len = (dev->fw.ucode->size - hdr_len) / sizeof(__be32); 1711 b43legacy_shm_control_word(dev, 1712 B43legacy_SHM_UCODE | 1713 B43legacy_SHM_AUTOINC_W, 1714 0x0000); 1715 for (i = 0; i < len; i++) { 1716 b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA, 1717 be32_to_cpu(data[i])); 1718 udelay(10); 1719 } 1720 1721 if (dev->fw.pcm) { 1722 /* Upload PCM data. */ 1723 data = (__be32 *) (dev->fw.pcm->data + hdr_len); 1724 len = (dev->fw.pcm->size - hdr_len) / sizeof(__be32); 1725 b43legacy_shm_control_word(dev, B43legacy_SHM_HW, 0x01EA); 1726 b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA, 0x00004000); 1727 /* No need for autoinc bit in SHM_HW */ 1728 b43legacy_shm_control_word(dev, B43legacy_SHM_HW, 0x01EB); 1729 for (i = 0; i < len; i++) { 1730 b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA, 1731 be32_to_cpu(data[i])); 1732 udelay(10); 1733 } 1734 } 1735 1736 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON, 1737 B43legacy_IRQ_ALL); 1738 1739 /* Start the microcode PSM */ 1740 macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL); 1741 macctl &= ~B43legacy_MACCTL_PSM_JMP0; 1742 macctl |= B43legacy_MACCTL_PSM_RUN; 1743 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl); 1744 1745 /* Wait for the microcode to load and respond */ 1746 i = 0; 1747 while (1) { 1748 tmp = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON); 1749 if (tmp == B43legacy_IRQ_MAC_SUSPENDED) 1750 break; 1751 i++; 1752 if (i >= B43legacy_IRQWAIT_MAX_RETRIES) { 1753 b43legacyerr(dev->wl, "Microcode not responding\n"); 1754 b43legacy_print_fw_helptext(dev->wl); 1755 err = -ENODEV; 1756 goto error; 1757 } 1758 msleep_interruptible(50); 1759 if (signal_pending(current)) { 1760 err = -EINTR; 1761 goto error; 1762 } 1763 } 1764 /* dummy read follows */ 1765 b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON); 1766 1767 /* Get and check the revisions. */ 1768 fwrev = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED, 1769 B43legacy_SHM_SH_UCODEREV); 1770 fwpatch = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED, 1771 B43legacy_SHM_SH_UCODEPATCH); 1772 fwdate = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED, 1773 B43legacy_SHM_SH_UCODEDATE); 1774 fwtime = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED, 1775 B43legacy_SHM_SH_UCODETIME); 1776 1777 if (fwrev > 0x128) { 1778 b43legacyerr(dev->wl, "YOU ARE TRYING TO LOAD V4 FIRMWARE." 1779 " Only firmware from binary drivers version 3.x" 1780 " is supported. You must change your firmware" 1781 " files.\n"); 1782 b43legacy_print_fw_helptext(dev->wl); 1783 err = -EOPNOTSUPP; 1784 goto error; 1785 } 1786 b43legacyinfo(dev->wl, "Loading firmware version 0x%X, patch level %u " 1787 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n", fwrev, fwpatch, 1788 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF, 1789 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, 1790 fwtime & 0x1F); 1791 1792 dev->fw.rev = fwrev; 1793 dev->fw.patch = fwpatch; 1794 1795 snprintf(wiphy->fw_version, sizeof(wiphy->fw_version), "%u.%u", 1796 dev->fw.rev, dev->fw.patch); 1797 wiphy->hw_version = dev->dev->id.coreid; 1798 1799 return 0; 1800 1801error: 1802 macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL); 1803 macctl &= ~B43legacy_MACCTL_PSM_RUN; 1804 macctl |= B43legacy_MACCTL_PSM_JMP0; 1805 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl); 1806 1807 return err; 1808} 1809 1810static int b43legacy_write_initvals(struct b43legacy_wldev *dev, 1811 const struct b43legacy_iv *ivals, 1812 size_t count, 1813 size_t array_size) 1814{ 1815 const struct b43legacy_iv *iv; 1816 u16 offset; 1817 size_t i; 1818 bool bit32; 1819 1820 BUILD_BUG_ON(sizeof(struct b43legacy_iv) != 6); 1821 iv = ivals; 1822 for (i = 0; i < count; i++) { 1823 if (array_size < sizeof(iv->offset_size)) 1824 goto err_format; 1825 array_size -= sizeof(iv->offset_size); 1826 offset = be16_to_cpu(iv->offset_size); 1827 bit32 = !!(offset & B43legacy_IV_32BIT); 1828 offset &= B43legacy_IV_OFFSET_MASK; 1829 if (offset >= 0x1000) 1830 goto err_format; 1831 if (bit32) { 1832 u32 value; 1833 1834 if (array_size < sizeof(iv->data.d32)) 1835 goto err_format; 1836 array_size -= sizeof(iv->data.d32); 1837 1838 value = get_unaligned_be32(&iv->data.d32); 1839 b43legacy_write32(dev, offset, value); 1840 1841 iv = (const struct b43legacy_iv *)((const uint8_t *)iv + 1842 sizeof(__be16) + 1843 sizeof(__be32)); 1844 } else { 1845 u16 value; 1846 1847 if (array_size < sizeof(iv->data.d16)) 1848 goto err_format; 1849 array_size -= sizeof(iv->data.d16); 1850 1851 value = be16_to_cpu(iv->data.d16); 1852 b43legacy_write16(dev, offset, value); 1853 1854 iv = (const struct b43legacy_iv *)((const uint8_t *)iv + 1855 sizeof(__be16) + 1856 sizeof(__be16)); 1857 } 1858 } 1859 if (array_size) 1860 goto err_format; 1861 1862 return 0; 1863 1864err_format: 1865 b43legacyerr(dev->wl, "Initial Values Firmware file-format error.\n"); 1866 b43legacy_print_fw_helptext(dev->wl); 1867 1868 return -EPROTO; 1869} 1870 1871static int b43legacy_upload_initvals(struct b43legacy_wldev *dev) 1872{ 1873 const size_t hdr_len = sizeof(struct b43legacy_fw_header); 1874 const struct b43legacy_fw_header *hdr; 1875 struct b43legacy_firmware *fw = &dev->fw; 1876 const struct b43legacy_iv *ivals; 1877 size_t count; 1878 int err; 1879 1880 hdr = (const struct b43legacy_fw_header *)(fw->initvals->data); 1881 ivals = (const struct b43legacy_iv *)(fw->initvals->data + hdr_len); 1882 count = be32_to_cpu(hdr->size); 1883 err = b43legacy_write_initvals(dev, ivals, count, 1884 fw->initvals->size - hdr_len); 1885 if (err) 1886 goto out; 1887 if (fw->initvals_band) { 1888 hdr = (const struct b43legacy_fw_header *) 1889 (fw->initvals_band->data); 1890 ivals = (const struct b43legacy_iv *)(fw->initvals_band->data 1891 + hdr_len); 1892 count = be32_to_cpu(hdr->size); 1893 err = b43legacy_write_initvals(dev, ivals, count, 1894 fw->initvals_band->size - hdr_len); 1895 if (err) 1896 goto out; 1897 } 1898out: 1899 1900 return err; 1901} 1902 1903/* Initialize the GPIOs 1904 * http://bcm-specs.sipsolutions.net/GPIO 1905 */ 1906static int b43legacy_gpio_init(struct b43legacy_wldev *dev) 1907{ 1908 struct ssb_bus *bus = dev->dev->bus; 1909 struct ssb_device *gpiodev, *pcidev = NULL; 1910 u32 mask; 1911 u32 set; 1912 1913 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, 1914 b43legacy_read32(dev, 1915 B43legacy_MMIO_MACCTL) 1916 & 0xFFFF3FFF); 1917 1918 b43legacy_write16(dev, B43legacy_MMIO_GPIO_MASK, 1919 b43legacy_read16(dev, 1920 B43legacy_MMIO_GPIO_MASK) 1921 | 0x000F); 1922 1923 mask = 0x0000001F; 1924 set = 0x0000000F; 1925 if (dev->dev->bus->chip_id == 0x4301) { 1926 mask |= 0x0060; 1927 set |= 0x0060; 1928 } 1929 if (dev->dev->bus->sprom.boardflags_lo & B43legacy_BFL_PACTRL) { 1930 b43legacy_write16(dev, B43legacy_MMIO_GPIO_MASK, 1931 b43legacy_read16(dev, 1932 B43legacy_MMIO_GPIO_MASK) 1933 | 0x0200); 1934 mask |= 0x0200; 1935 set |= 0x0200; 1936 } 1937 if (dev->dev->id.revision >= 2) 1938 mask |= 0x0010; /* FIXME: This is redundant. */ 1939 1940#ifdef CONFIG_SSB_DRIVER_PCICORE 1941 pcidev = bus->pcicore.dev; 1942#endif 1943 gpiodev = bus->chipco.dev ? : pcidev; 1944 if (!gpiodev) 1945 return 0; 1946 ssb_write32(gpiodev, B43legacy_GPIO_CONTROL, 1947 (ssb_read32(gpiodev, B43legacy_GPIO_CONTROL) 1948 & ~mask) | set); 1949 1950 return 0; 1951} 1952 1953/* Turn off all GPIO stuff. Call this on module unload, for example. */ 1954static void b43legacy_gpio_cleanup(struct b43legacy_wldev *dev) 1955{ 1956 struct ssb_bus *bus = dev->dev->bus; 1957 struct ssb_device *gpiodev, *pcidev = NULL; 1958 1959#ifdef CONFIG_SSB_DRIVER_PCICORE 1960 pcidev = bus->pcicore.dev; 1961#endif 1962 gpiodev = bus->chipco.dev ? : pcidev; 1963 if (!gpiodev) 1964 return; 1965 ssb_write32(gpiodev, B43legacy_GPIO_CONTROL, 0); 1966} 1967 1968/* http://bcm-specs.sipsolutions.net/EnableMac */ 1969void b43legacy_mac_enable(struct b43legacy_wldev *dev) 1970{ 1971 dev->mac_suspended--; 1972 B43legacy_WARN_ON(dev->mac_suspended < 0); 1973 B43legacy_WARN_ON(irqs_disabled()); 1974 if (dev->mac_suspended == 0) { 1975 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, 1976 b43legacy_read32(dev, 1977 B43legacy_MMIO_MACCTL) 1978 | B43legacy_MACCTL_ENABLED); 1979 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON, 1980 B43legacy_IRQ_MAC_SUSPENDED); 1981 /* the next two are dummy reads */ 1982 b43legacy_read32(dev, B43legacy_MMIO_MACCTL); 1983 b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON); 1984 b43legacy_power_saving_ctl_bits(dev, -1, -1); 1985 1986 /* Re-enable IRQs. */ 1987 spin_lock_irq(&dev->wl->irq_lock); 1988 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, 1989 dev->irq_mask); 1990 spin_unlock_irq(&dev->wl->irq_lock); 1991 } 1992} 1993 1994/* http://bcm-specs.sipsolutions.net/SuspendMAC */ 1995void b43legacy_mac_suspend(struct b43legacy_wldev *dev) 1996{ 1997 int i; 1998 u32 tmp; 1999 2000 might_sleep(); 2001 B43legacy_WARN_ON(irqs_disabled()); 2002 B43legacy_WARN_ON(dev->mac_suspended < 0); 2003 2004 if (dev->mac_suspended == 0) { 2005 /* Mask IRQs before suspending MAC. Otherwise 2006 * the MAC stays busy and won't suspend. */ 2007 spin_lock_irq(&dev->wl->irq_lock); 2008 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, 0); 2009 spin_unlock_irq(&dev->wl->irq_lock); 2010 b43legacy_synchronize_irq(dev); 2011 2012 b43legacy_power_saving_ctl_bits(dev, -1, 1); 2013 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, 2014 b43legacy_read32(dev, 2015 B43legacy_MMIO_MACCTL) 2016 & ~B43legacy_MACCTL_ENABLED); 2017 b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON); 2018 for (i = 40; i; i--) { 2019 tmp = b43legacy_read32(dev, 2020 B43legacy_MMIO_GEN_IRQ_REASON); 2021 if (tmp & B43legacy_IRQ_MAC_SUSPENDED) 2022 goto out; 2023 msleep(1); 2024 } 2025 b43legacyerr(dev->wl, "MAC suspend failed\n"); 2026 } 2027out: 2028 dev->mac_suspended++; 2029} 2030 2031static void b43legacy_adjust_opmode(struct b43legacy_wldev *dev) 2032{ 2033 struct b43legacy_wl *wl = dev->wl; 2034 u32 ctl; 2035 u16 cfp_pretbtt; 2036 2037 ctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL); 2038 /* Reset status to STA infrastructure mode. */ 2039 ctl &= ~B43legacy_MACCTL_AP; 2040 ctl &= ~B43legacy_MACCTL_KEEP_CTL; 2041 ctl &= ~B43legacy_MACCTL_KEEP_BADPLCP; 2042 ctl &= ~B43legacy_MACCTL_KEEP_BAD; 2043 ctl &= ~B43legacy_MACCTL_PROMISC; 2044 ctl &= ~B43legacy_MACCTL_BEACPROMISC; 2045 ctl |= B43legacy_MACCTL_INFRA; 2046 2047 if (b43legacy_is_mode(wl, NL80211_IFTYPE_AP)) 2048 ctl |= B43legacy_MACCTL_AP; 2049 else if (b43legacy_is_mode(wl, NL80211_IFTYPE_ADHOC)) 2050 ctl &= ~B43legacy_MACCTL_INFRA; 2051 2052 if (wl->filter_flags & FIF_CONTROL) 2053 ctl |= B43legacy_MACCTL_KEEP_CTL; 2054 if (wl->filter_flags & FIF_FCSFAIL) 2055 ctl |= B43legacy_MACCTL_KEEP_BAD; 2056 if (wl->filter_flags & FIF_PLCPFAIL) 2057 ctl |= B43legacy_MACCTL_KEEP_BADPLCP; 2058 if (wl->filter_flags & FIF_PROMISC_IN_BSS) 2059 ctl |= B43legacy_MACCTL_PROMISC; 2060 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC) 2061 ctl |= B43legacy_MACCTL_BEACPROMISC; 2062 2063 /* Workaround: On old hardware the HW-MAC-address-filter 2064 * doesn't work properly, so always run promisc in filter 2065 * it in software. */ 2066 if (dev->dev->id.revision <= 4) 2067 ctl |= B43legacy_MACCTL_PROMISC; 2068 2069 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, ctl); 2070 2071 cfp_pretbtt = 2; 2072 if ((ctl & B43legacy_MACCTL_INFRA) && 2073 !(ctl & B43legacy_MACCTL_AP)) { 2074 if (dev->dev->bus->chip_id == 0x4306 && 2075 dev->dev->bus->chip_rev == 3) 2076 cfp_pretbtt = 100; 2077 else 2078 cfp_pretbtt = 50; 2079 } 2080 b43legacy_write16(dev, 0x612, cfp_pretbtt); 2081} 2082 2083static void b43legacy_rate_memory_write(struct b43legacy_wldev *dev, 2084 u16 rate, 2085 int is_ofdm) 2086{ 2087 u16 offset; 2088 2089 if (is_ofdm) { 2090 offset = 0x480; 2091 offset += (b43legacy_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2; 2092 } else { 2093 offset = 0x4C0; 2094 offset += (b43legacy_plcp_get_ratecode_cck(rate) & 0x000F) * 2; 2095 } 2096 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, offset + 0x20, 2097 b43legacy_shm_read16(dev, 2098 B43legacy_SHM_SHARED, offset)); 2099} 2100 2101static void b43legacy_rate_memory_init(struct b43legacy_wldev *dev) 2102{ 2103 switch (dev->phy.type) { 2104 case B43legacy_PHYTYPE_G: 2105 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_6MB, 1); 2106 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_12MB, 1); 2107 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_18MB, 1); 2108 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_24MB, 1); 2109 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_36MB, 1); 2110 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_48MB, 1); 2111 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_54MB, 1); 2112 /* fallthrough */ 2113 case B43legacy_PHYTYPE_B: 2114 b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_1MB, 0); 2115 b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_2MB, 0); 2116 b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_5MB, 0); 2117 b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_11MB, 0); 2118 break; 2119 default: 2120 B43legacy_BUG_ON(1); 2121 } 2122} 2123 2124/* Set the TX-Antenna for management frames sent by firmware. */ 2125static void b43legacy_mgmtframe_txantenna(struct b43legacy_wldev *dev, 2126 int antenna) 2127{ 2128 u16 ant = 0; 2129 u16 tmp; 2130 2131 switch (antenna) { 2132 case B43legacy_ANTENNA0: 2133 ant |= B43legacy_TX4_PHY_ANT0; 2134 break; 2135 case B43legacy_ANTENNA1: 2136 ant |= B43legacy_TX4_PHY_ANT1; 2137 break; 2138 case B43legacy_ANTENNA_AUTO: 2139 ant |= B43legacy_TX4_PHY_ANTLAST; 2140 break; 2141 default: 2142 B43legacy_BUG_ON(1); 2143 } 2144 2145 /* FIXME We also need to set the other flags of the PHY control 2146 * field somewhere. */ 2147 2148 /* For Beacons */ 2149 tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED, 2150 B43legacy_SHM_SH_BEACPHYCTL); 2151 tmp = (tmp & ~B43legacy_TX4_PHY_ANT) | ant; 2152 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 2153 B43legacy_SHM_SH_BEACPHYCTL, tmp); 2154 /* For ACK/CTS */ 2155 tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED, 2156 B43legacy_SHM_SH_ACKCTSPHYCTL); 2157 tmp = (tmp & ~B43legacy_TX4_PHY_ANT) | ant; 2158 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 2159 B43legacy_SHM_SH_ACKCTSPHYCTL, tmp); 2160 /* For Probe Resposes */ 2161 tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED, 2162 B43legacy_SHM_SH_PRPHYCTL); 2163 tmp = (tmp & ~B43legacy_TX4_PHY_ANT) | ant; 2164 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 2165 B43legacy_SHM_SH_PRPHYCTL, tmp); 2166} 2167 2168/* This is the opposite of b43legacy_chip_init() */ 2169static void b43legacy_chip_exit(struct b43legacy_wldev *dev) 2170{ 2171 b43legacy_radio_turn_off(dev, 1); 2172 b43legacy_gpio_cleanup(dev); 2173 /* firmware is released later */ 2174} 2175 2176/* Initialize the chip 2177 * http://bcm-specs.sipsolutions.net/ChipInit 2178 */ 2179static int b43legacy_chip_init(struct b43legacy_wldev *dev) 2180{ 2181 struct b43legacy_phy *phy = &dev->phy; 2182 int err; 2183 int tmp; 2184 u32 value32, macctl; 2185 u16 value16; 2186 2187 /* Initialize the MAC control */ 2188 macctl = B43legacy_MACCTL_IHR_ENABLED | B43legacy_MACCTL_SHM_ENABLED; 2189 if (dev->phy.gmode) 2190 macctl |= B43legacy_MACCTL_GMODE; 2191 macctl |= B43legacy_MACCTL_INFRA; 2192 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl); 2193 2194 err = b43legacy_upload_microcode(dev); 2195 if (err) 2196 goto out; /* firmware is released later */ 2197 2198 err = b43legacy_gpio_init(dev); 2199 if (err) 2200 goto out; /* firmware is released later */ 2201 2202 err = b43legacy_upload_initvals(dev); 2203 if (err) 2204 goto err_gpio_clean; 2205 b43legacy_radio_turn_on(dev); 2206 2207 b43legacy_write16(dev, 0x03E6, 0x0000); 2208 err = b43legacy_phy_init(dev); 2209 if (err) 2210 goto err_radio_off; 2211 2212 /* Select initial Interference Mitigation. */ 2213 tmp = phy->interfmode; 2214 phy->interfmode = B43legacy_INTERFMODE_NONE; 2215 b43legacy_radio_set_interference_mitigation(dev, tmp); 2216 2217 b43legacy_phy_set_antenna_diversity(dev); 2218 b43legacy_mgmtframe_txantenna(dev, B43legacy_ANTENNA_DEFAULT); 2219 2220 if (phy->type == B43legacy_PHYTYPE_B) { 2221 value16 = b43legacy_read16(dev, 0x005E); 2222 value16 |= 0x0004; 2223 b43legacy_write16(dev, 0x005E, value16); 2224 } 2225 b43legacy_write32(dev, 0x0100, 0x01000000); 2226 if (dev->dev->id.revision < 5) 2227 b43legacy_write32(dev, 0x010C, 0x01000000); 2228 2229 value32 = b43legacy_read32(dev, B43legacy_MMIO_MACCTL); 2230 value32 &= ~B43legacy_MACCTL_INFRA; 2231 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, value32); 2232 value32 = b43legacy_read32(dev, B43legacy_MMIO_MACCTL); 2233 value32 |= B43legacy_MACCTL_INFRA; 2234 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, value32); 2235 2236 if (b43legacy_using_pio(dev)) { 2237 b43legacy_write32(dev, 0x0210, 0x00000100); 2238 b43legacy_write32(dev, 0x0230, 0x00000100); 2239 b43legacy_write32(dev, 0x0250, 0x00000100); 2240 b43legacy_write32(dev, 0x0270, 0x00000100); 2241 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0034, 2242 0x0000); 2243 } 2244 2245 /* Probe Response Timeout value */ 2246 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */ 2247 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0074, 0x0000); 2248 2249 /* Initially set the wireless operation mode. */ 2250 b43legacy_adjust_opmode(dev); 2251 2252 if (dev->dev->id.revision < 3) { 2253 b43legacy_write16(dev, 0x060E, 0x0000); 2254 b43legacy_write16(dev, 0x0610, 0x8000); 2255 b43legacy_write16(dev, 0x0604, 0x0000); 2256 b43legacy_write16(dev, 0x0606, 0x0200); 2257 } else { 2258 b43legacy_write32(dev, 0x0188, 0x80000000); 2259 b43legacy_write32(dev, 0x018C, 0x02000000); 2260 } 2261 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON, 0x00004000); 2262 b43legacy_write32(dev, B43legacy_MMIO_DMA0_IRQ_MASK, 0x0001DC00); 2263 b43legacy_write32(dev, B43legacy_MMIO_DMA1_IRQ_MASK, 0x0000DC00); 2264 b43legacy_write32(dev, B43legacy_MMIO_DMA2_IRQ_MASK, 0x0000DC00); 2265 b43legacy_write32(dev, B43legacy_MMIO_DMA3_IRQ_MASK, 0x0001DC00); 2266 b43legacy_write32(dev, B43legacy_MMIO_DMA4_IRQ_MASK, 0x0000DC00); 2267 b43legacy_write32(dev, B43legacy_MMIO_DMA5_IRQ_MASK, 0x0000DC00); 2268 2269 value32 = ssb_read32(dev->dev, SSB_TMSLOW); 2270 value32 |= B43legacy_TMSLOW_MACPHYCLKEN; 2271 ssb_write32(dev->dev, SSB_TMSLOW, value32); 2272 2273 b43legacy_write16(dev, B43legacy_MMIO_POWERUP_DELAY, 2274 dev->dev->bus->chipco.fast_pwrup_delay); 2275 2276 /* PHY TX errors counter. */ 2277 atomic_set(&phy->txerr_cnt, B43legacy_PHY_TX_BADNESS_LIMIT); 2278 2279 B43legacy_WARN_ON(err != 0); 2280 b43legacydbg(dev->wl, "Chip initialized\n"); 2281out: 2282 return err; 2283 2284err_radio_off: 2285 b43legacy_radio_turn_off(dev, 1); 2286err_gpio_clean: 2287 b43legacy_gpio_cleanup(dev); 2288 goto out; 2289} 2290 2291static void b43legacy_periodic_every120sec(struct b43legacy_wldev *dev) 2292{ 2293 struct b43legacy_phy *phy = &dev->phy; 2294 2295 if (phy->type != B43legacy_PHYTYPE_G || phy->rev < 2) 2296 return; 2297 2298 b43legacy_mac_suspend(dev); 2299 b43legacy_phy_lo_g_measure(dev); 2300 b43legacy_mac_enable(dev); 2301} 2302 2303static void b43legacy_periodic_every60sec(struct b43legacy_wldev *dev) 2304{ 2305 b43legacy_phy_lo_mark_all_unused(dev); 2306 if (dev->dev->bus->sprom.boardflags_lo & B43legacy_BFL_RSSI) { 2307 b43legacy_mac_suspend(dev); 2308 b43legacy_calc_nrssi_slope(dev); 2309 b43legacy_mac_enable(dev); 2310 } 2311} 2312 2313static void b43legacy_periodic_every30sec(struct b43legacy_wldev *dev) 2314{ 2315 /* Update device statistics. */ 2316 b43legacy_calculate_link_quality(dev); 2317} 2318 2319static void b43legacy_periodic_every15sec(struct b43legacy_wldev *dev) 2320{ 2321 b43legacy_phy_xmitpower(dev); /* FIXME: unless scanning? */ 2322 2323 atomic_set(&dev->phy.txerr_cnt, B43legacy_PHY_TX_BADNESS_LIMIT); 2324 wmb(); 2325} 2326 2327static void do_periodic_work(struct b43legacy_wldev *dev) 2328{ 2329 unsigned int state; 2330 2331 state = dev->periodic_state; 2332 if (state % 8 == 0) 2333 b43legacy_periodic_every120sec(dev); 2334 if (state % 4 == 0) 2335 b43legacy_periodic_every60sec(dev); 2336 if (state % 2 == 0) 2337 b43legacy_periodic_every30sec(dev); 2338 b43legacy_periodic_every15sec(dev); 2339} 2340 2341/* Periodic work locking policy: 2342 * The whole periodic work handler is protected by 2343 * wl->mutex. If another lock is needed somewhere in the 2344 * pwork callchain, it's acquired in-place, where it's needed. 2345 */ 2346static void b43legacy_periodic_work_handler(struct work_struct *work) 2347{ 2348 struct b43legacy_wldev *dev = container_of(work, struct b43legacy_wldev, 2349 periodic_work.work); 2350 struct b43legacy_wl *wl = dev->wl; 2351 unsigned long delay; 2352 2353 mutex_lock(&wl->mutex); 2354 2355 if (unlikely(b43legacy_status(dev) != B43legacy_STAT_STARTED)) 2356 goto out; 2357 if (b43legacy_debug(dev, B43legacy_DBG_PWORK_STOP)) 2358 goto out_requeue; 2359 2360 do_periodic_work(dev); 2361 2362 dev->periodic_state++; 2363out_requeue: 2364 if (b43legacy_debug(dev, B43legacy_DBG_PWORK_FAST)) 2365 delay = msecs_to_jiffies(50); 2366 else 2367 delay = round_jiffies_relative(HZ * 15); 2368 ieee80211_queue_delayed_work(wl->hw, &dev->periodic_work, delay); 2369out: 2370 mutex_unlock(&wl->mutex); 2371} 2372 2373static void b43legacy_periodic_tasks_setup(struct b43legacy_wldev *dev) 2374{ 2375 struct delayed_work *work = &dev->periodic_work; 2376 2377 dev->periodic_state = 0; 2378 INIT_DELAYED_WORK(work, b43legacy_periodic_work_handler); 2379 ieee80211_queue_delayed_work(dev->wl->hw, work, 0); 2380} 2381 2382/* Validate access to the chip (SHM) */ 2383static int b43legacy_validate_chipaccess(struct b43legacy_wldev *dev) 2384{ 2385 u32 value; 2386 u32 shm_backup; 2387 2388 shm_backup = b43legacy_shm_read32(dev, B43legacy_SHM_SHARED, 0); 2389 b43legacy_shm_write32(dev, B43legacy_SHM_SHARED, 0, 0xAA5555AA); 2390 if (b43legacy_shm_read32(dev, B43legacy_SHM_SHARED, 0) != 2391 0xAA5555AA) 2392 goto error; 2393 b43legacy_shm_write32(dev, B43legacy_SHM_SHARED, 0, 0x55AAAA55); 2394 if (b43legacy_shm_read32(dev, B43legacy_SHM_SHARED, 0) != 2395 0x55AAAA55) 2396 goto error; 2397 b43legacy_shm_write32(dev, B43legacy_SHM_SHARED, 0, shm_backup); 2398 2399 value = b43legacy_read32(dev, B43legacy_MMIO_MACCTL); 2400 if ((value | B43legacy_MACCTL_GMODE) != 2401 (B43legacy_MACCTL_GMODE | B43legacy_MACCTL_IHR_ENABLED)) 2402 goto error; 2403 2404 value = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON); 2405 if (value) 2406 goto error; 2407 2408 return 0; 2409error: 2410 b43legacyerr(dev->wl, "Failed to validate the chipaccess\n"); 2411 return -ENODEV; 2412} 2413 2414static void b43legacy_security_init(struct b43legacy_wldev *dev) 2415{ 2416 dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20; 2417 B43legacy_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key)); 2418 dev->ktp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED, 2419 0x0056); 2420 /* KTP is a word address, but we address SHM bytewise. 2421 * So multiply by two. 2422 */ 2423 dev->ktp *= 2; 2424 if (dev->dev->id.revision >= 5) 2425 /* Number of RCMTA address slots */ 2426 b43legacy_write16(dev, B43legacy_MMIO_RCMTA_COUNT, 2427 dev->max_nr_keys - 8); 2428} 2429 2430#ifdef CONFIG_B43LEGACY_HWRNG 2431static int b43legacy_rng_read(struct hwrng *rng, u32 *data) 2432{ 2433 struct b43legacy_wl *wl = (struct b43legacy_wl *)rng->priv; 2434 unsigned long flags; 2435 2436 /* Don't take wl->mutex here, as it could deadlock with 2437 * hwrng internal locking. It's not needed to take 2438 * wl->mutex here, anyway. */ 2439 2440 spin_lock_irqsave(&wl->irq_lock, flags); 2441 *data = b43legacy_read16(wl->current_dev, B43legacy_MMIO_RNG); 2442 spin_unlock_irqrestore(&wl->irq_lock, flags); 2443 2444 return (sizeof(u16)); 2445} 2446#endif 2447 2448static void b43legacy_rng_exit(struct b43legacy_wl *wl) 2449{ 2450#ifdef CONFIG_B43LEGACY_HWRNG 2451 if (wl->rng_initialized) 2452 hwrng_unregister(&wl->rng); 2453#endif 2454} 2455 2456static int b43legacy_rng_init(struct b43legacy_wl *wl) 2457{ 2458 int err = 0; 2459 2460#ifdef CONFIG_B43LEGACY_HWRNG 2461 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name), 2462 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy)); 2463 wl->rng.name = wl->rng_name; 2464 wl->rng.data_read = b43legacy_rng_read; 2465 wl->rng.priv = (unsigned long)wl; 2466 wl->rng_initialized = 1; 2467 err = hwrng_register(&wl->rng); 2468 if (err) { 2469 wl->rng_initialized = 0; 2470 b43legacyerr(wl, "Failed to register the random " 2471 "number generator (%d)\n", err); 2472 } 2473 2474#endif 2475 return err; 2476} 2477 2478static void b43legacy_tx_work(struct work_struct *work) 2479{ 2480 struct b43legacy_wl *wl = container_of(work, struct b43legacy_wl, 2481 tx_work); 2482 struct b43legacy_wldev *dev; 2483 struct sk_buff *skb; 2484 int queue_num; 2485 int err = 0; 2486 2487 mutex_lock(&wl->mutex); 2488 dev = wl->current_dev; 2489 if (unlikely(!dev || b43legacy_status(dev) < B43legacy_STAT_STARTED)) { 2490 mutex_unlock(&wl->mutex); 2491 return; 2492 } 2493 2494 for (queue_num = 0; queue_num < B43legacy_QOS_QUEUE_NUM; queue_num++) { 2495 while (skb_queue_len(&wl->tx_queue[queue_num])) { 2496 skb = skb_dequeue(&wl->tx_queue[queue_num]); 2497 if (b43legacy_using_pio(dev)) 2498 err = b43legacy_pio_tx(dev, skb); 2499 else 2500 err = b43legacy_dma_tx(dev, skb); 2501 if (err == -ENOSPC) { 2502 wl->tx_queue_stopped[queue_num] = 1; 2503 ieee80211_stop_queue(wl->hw, queue_num); 2504 skb_queue_head(&wl->tx_queue[queue_num], skb); 2505 break; 2506 } 2507 if (unlikely(err)) 2508 dev_kfree_skb(skb); /* Drop it */ 2509 err = 0; 2510 } 2511 2512 if (!err) 2513 wl->tx_queue_stopped[queue_num] = 0; 2514 } 2515 2516 mutex_unlock(&wl->mutex); 2517} 2518 2519static void b43legacy_op_tx(struct ieee80211_hw *hw, 2520 struct ieee80211_tx_control *control, 2521 struct sk_buff *skb) 2522{ 2523 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw); 2524 2525 if (unlikely(skb->len < 2 + 2 + 6)) { 2526 /* Too short, this can't be a valid frame. */ 2527 dev_kfree_skb_any(skb); 2528 return; 2529 } 2530 B43legacy_WARN_ON(skb_shinfo(skb)->nr_frags); 2531 2532 skb_queue_tail(&wl->tx_queue[skb->queue_mapping], skb); 2533 if (!wl->tx_queue_stopped[skb->queue_mapping]) 2534 ieee80211_queue_work(wl->hw, &wl->tx_work); 2535 else 2536 ieee80211_stop_queue(wl->hw, skb->queue_mapping); 2537} 2538 2539static int b43legacy_op_conf_tx(struct ieee80211_hw *hw, 2540 struct ieee80211_vif *vif, u16 queue, 2541 const struct ieee80211_tx_queue_params *params) 2542{ 2543 return 0; 2544} 2545 2546static int b43legacy_op_get_stats(struct ieee80211_hw *hw, 2547 struct ieee80211_low_level_stats *stats) 2548{ 2549 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw); 2550 unsigned long flags; 2551 2552 spin_lock_irqsave(&wl->irq_lock, flags); 2553 memcpy(stats, &wl->ieee_stats, sizeof(*stats)); 2554 spin_unlock_irqrestore(&wl->irq_lock, flags); 2555 2556 return 0; 2557} 2558 2559static const char *phymode_to_string(unsigned int phymode) 2560{ 2561 switch (phymode) { 2562 case B43legacy_PHYMODE_B: 2563 return "B"; 2564 case B43legacy_PHYMODE_G: 2565 return "G"; 2566 default: 2567 B43legacy_BUG_ON(1); 2568 } 2569 return ""; 2570} 2571 2572static int find_wldev_for_phymode(struct b43legacy_wl *wl, 2573 unsigned int phymode, 2574 struct b43legacy_wldev **dev, 2575 bool *gmode) 2576{ 2577 struct b43legacy_wldev *d; 2578 2579 list_for_each_entry(d, &wl->devlist, list) { 2580 if (d->phy.possible_phymodes & phymode) { 2581 /* Ok, this device supports the PHY-mode. 2582 * Set the gmode bit. */ 2583 *gmode = true; 2584 *dev = d; 2585 2586 return 0; 2587 } 2588 } 2589 2590 return -ESRCH; 2591} 2592 2593static void b43legacy_put_phy_into_reset(struct b43legacy_wldev *dev) 2594{ 2595 struct ssb_device *sdev = dev->dev; 2596 u32 tmslow; 2597 2598 tmslow = ssb_read32(sdev, SSB_TMSLOW); 2599 tmslow &= ~B43legacy_TMSLOW_GMODE; 2600 tmslow |= B43legacy_TMSLOW_PHYRESET; 2601 tmslow |= SSB_TMSLOW_FGC; 2602 ssb_write32(sdev, SSB_TMSLOW, tmslow); 2603 msleep(1); 2604 2605 tmslow = ssb_read32(sdev, SSB_TMSLOW); 2606 tmslow &= ~SSB_TMSLOW_FGC; 2607 tmslow |= B43legacy_TMSLOW_PHYRESET; 2608 ssb_write32(sdev, SSB_TMSLOW, tmslow); 2609 msleep(1); 2610} 2611 2612/* Expects wl->mutex locked */ 2613static int b43legacy_switch_phymode(struct b43legacy_wl *wl, 2614 unsigned int new_mode) 2615{ 2616 struct b43legacy_wldev *uninitialized_var(up_dev); 2617 struct b43legacy_wldev *down_dev; 2618 int err; 2619 bool gmode = false; 2620 int prev_status; 2621 2622 err = find_wldev_for_phymode(wl, new_mode, &up_dev, &gmode); 2623 if (err) { 2624 b43legacyerr(wl, "Could not find a device for %s-PHY mode\n", 2625 phymode_to_string(new_mode)); 2626 return err; 2627 } 2628 if ((up_dev == wl->current_dev) && 2629 (!!wl->current_dev->phy.gmode == !!gmode)) 2630 /* This device is already running. */ 2631 return 0; 2632 b43legacydbg(wl, "Reconfiguring PHYmode to %s-PHY\n", 2633 phymode_to_string(new_mode)); 2634 down_dev = wl->current_dev; 2635 2636 prev_status = b43legacy_status(down_dev); 2637 /* Shutdown the currently running core. */ 2638 if (prev_status >= B43legacy_STAT_STARTED) 2639 b43legacy_wireless_core_stop(down_dev); 2640 if (prev_status >= B43legacy_STAT_INITIALIZED) 2641 b43legacy_wireless_core_exit(down_dev); 2642 2643 if (down_dev != up_dev) 2644 /* We switch to a different core, so we put PHY into 2645 * RESET on the old core. */ 2646 b43legacy_put_phy_into_reset(down_dev); 2647 2648 /* Now start the new core. */ 2649 up_dev->phy.gmode = gmode; 2650 if (prev_status >= B43legacy_STAT_INITIALIZED) { 2651 err = b43legacy_wireless_core_init(up_dev); 2652 if (err) { 2653 b43legacyerr(wl, "Fatal: Could not initialize device" 2654 " for newly selected %s-PHY mode\n", 2655 phymode_to_string(new_mode)); 2656 goto init_failure; 2657 } 2658 } 2659 if (prev_status >= B43legacy_STAT_STARTED) { 2660 err = b43legacy_wireless_core_start(up_dev); 2661 if (err) { 2662 b43legacyerr(wl, "Fatal: Could not start device for " 2663 "newly selected %s-PHY mode\n", 2664 phymode_to_string(new_mode)); 2665 b43legacy_wireless_core_exit(up_dev); 2666 goto init_failure; 2667 } 2668 } 2669 B43legacy_WARN_ON(b43legacy_status(up_dev) != prev_status); 2670 2671 b43legacy_shm_write32(up_dev, B43legacy_SHM_SHARED, 0x003E, 0); 2672 2673 wl->current_dev = up_dev; 2674 2675 return 0; 2676init_failure: 2677 /* Whoops, failed to init the new core. No core is operating now. */ 2678 wl->current_dev = NULL; 2679 return err; 2680} 2681 2682/* Write the short and long frame retry limit values. */ 2683static void b43legacy_set_retry_limits(struct b43legacy_wldev *dev, 2684 unsigned int short_retry, 2685 unsigned int long_retry) 2686{ 2687 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing 2688 * the chip-internal counter. */ 2689 short_retry = min(short_retry, (unsigned int)0xF); 2690 long_retry = min(long_retry, (unsigned int)0xF); 2691 2692 b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS, 0x0006, short_retry); 2693 b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS, 0x0007, long_retry); 2694} 2695 2696static int b43legacy_op_dev_config(struct ieee80211_hw *hw, 2697 u32 changed) 2698{ 2699 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw); 2700 struct b43legacy_wldev *dev; 2701 struct b43legacy_phy *phy; 2702 struct ieee80211_conf *conf = &hw->conf; 2703 unsigned long flags; 2704 unsigned int new_phymode = 0xFFFF; 2705 int antenna_tx; 2706 int err = 0; 2707 2708 antenna_tx = B43legacy_ANTENNA_DEFAULT; 2709 2710 mutex_lock(&wl->mutex); 2711 dev = wl->current_dev; 2712 phy = &dev->phy; 2713 2714 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS) 2715 b43legacy_set_retry_limits(dev, 2716 conf->short_frame_max_tx_count, 2717 conf->long_frame_max_tx_count); 2718 changed &= ~IEEE80211_CONF_CHANGE_RETRY_LIMITS; 2719 if (!changed) 2720 goto out_unlock_mutex; 2721 2722 /* Switch the PHY mode (if necessary). */ 2723 switch (conf->chandef.chan->band) { 2724 case IEEE80211_BAND_2GHZ: 2725 if (phy->type == B43legacy_PHYTYPE_B) 2726 new_phymode = B43legacy_PHYMODE_B; 2727 else 2728 new_phymode = B43legacy_PHYMODE_G; 2729 break; 2730 default: 2731 B43legacy_WARN_ON(1); 2732 } 2733 err = b43legacy_switch_phymode(wl, new_phymode); 2734 if (err) 2735 goto out_unlock_mutex; 2736 2737 /* Disable IRQs while reconfiguring the device. 2738 * This makes it possible to drop the spinlock throughout 2739 * the reconfiguration process. */ 2740 spin_lock_irqsave(&wl->irq_lock, flags); 2741 if (b43legacy_status(dev) < B43legacy_STAT_STARTED) { 2742 spin_unlock_irqrestore(&wl->irq_lock, flags); 2743 goto out_unlock_mutex; 2744 } 2745 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, 0); 2746 spin_unlock_irqrestore(&wl->irq_lock, flags); 2747 b43legacy_synchronize_irq(dev); 2748 2749 /* Switch to the requested channel. 2750 * The firmware takes care of races with the TX handler. */ 2751 if (conf->chandef.chan->hw_value != phy->channel) 2752 b43legacy_radio_selectchannel(dev, conf->chandef.chan->hw_value, 2753 0); 2754 2755 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_MONITOR); 2756 2757 /* Adjust the desired TX power level. */ 2758 if (conf->power_level != 0) { 2759 if (conf->power_level != phy->power_level) { 2760 phy->power_level = conf->power_level; 2761 b43legacy_phy_xmitpower(dev); 2762 } 2763 } 2764 2765 /* Antennas for RX and management frame TX. */ 2766 b43legacy_mgmtframe_txantenna(dev, antenna_tx); 2767 2768 if (wl->radio_enabled != phy->radio_on) { 2769 if (wl->radio_enabled) { 2770 b43legacy_radio_turn_on(dev); 2771 b43legacyinfo(dev->wl, "Radio turned on by software\n"); 2772 if (!dev->radio_hw_enable) 2773 b43legacyinfo(dev->wl, "The hardware RF-kill" 2774 " button still turns the radio" 2775 " physically off. Press the" 2776 " button to turn it on.\n"); 2777 } else { 2778 b43legacy_radio_turn_off(dev, 0); 2779 b43legacyinfo(dev->wl, "Radio turned off by" 2780 " software\n"); 2781 } 2782 } 2783 2784 spin_lock_irqsave(&wl->irq_lock, flags); 2785 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, dev->irq_mask); 2786 mmiowb(); 2787 spin_unlock_irqrestore(&wl->irq_lock, flags); 2788out_unlock_mutex: 2789 mutex_unlock(&wl->mutex); 2790 2791 return err; 2792} 2793 2794static void b43legacy_update_basic_rates(struct b43legacy_wldev *dev, u32 brates) 2795{ 2796 struct ieee80211_supported_band *sband = 2797 dev->wl->hw->wiphy->bands[IEEE80211_BAND_2GHZ]; 2798 struct ieee80211_rate *rate; 2799 int i; 2800 u16 basic, direct, offset, basic_offset, rateptr; 2801 2802 for (i = 0; i < sband->n_bitrates; i++) { 2803 rate = &sband->bitrates[i]; 2804 2805 if (b43legacy_is_cck_rate(rate->hw_value)) { 2806 direct = B43legacy_SHM_SH_CCKDIRECT; 2807 basic = B43legacy_SHM_SH_CCKBASIC; 2808 offset = b43legacy_plcp_get_ratecode_cck(rate->hw_value); 2809 offset &= 0xF; 2810 } else { 2811 direct = B43legacy_SHM_SH_OFDMDIRECT; 2812 basic = B43legacy_SHM_SH_OFDMBASIC; 2813 offset = b43legacy_plcp_get_ratecode_ofdm(rate->hw_value); 2814 offset &= 0xF; 2815 } 2816 2817 rate = ieee80211_get_response_rate(sband, brates, rate->bitrate); 2818 2819 if (b43legacy_is_cck_rate(rate->hw_value)) { 2820 basic_offset = b43legacy_plcp_get_ratecode_cck(rate->hw_value); 2821 basic_offset &= 0xF; 2822 } else { 2823 basic_offset = b43legacy_plcp_get_ratecode_ofdm(rate->hw_value); 2824 basic_offset &= 0xF; 2825 } 2826 2827 /* 2828 * Get the pointer that we need to point to 2829 * from the direct map 2830 */ 2831 rateptr = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED, 2832 direct + 2 * basic_offset); 2833 /* and write it to the basic map */ 2834 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 2835 basic + 2 * offset, rateptr); 2836 } 2837} 2838 2839static void b43legacy_op_bss_info_changed(struct ieee80211_hw *hw, 2840 struct ieee80211_vif *vif, 2841 struct ieee80211_bss_conf *conf, 2842 u32 changed) 2843{ 2844 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw); 2845 struct b43legacy_wldev *dev; 2846 unsigned long flags; 2847 2848 mutex_lock(&wl->mutex); 2849 B43legacy_WARN_ON(wl->vif != vif); 2850 2851 dev = wl->current_dev; 2852 2853 /* Disable IRQs while reconfiguring the device. 2854 * This makes it possible to drop the spinlock throughout 2855 * the reconfiguration process. */ 2856 spin_lock_irqsave(&wl->irq_lock, flags); 2857 if (b43legacy_status(dev) < B43legacy_STAT_STARTED) { 2858 spin_unlock_irqrestore(&wl->irq_lock, flags); 2859 goto out_unlock_mutex; 2860 } 2861 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, 0); 2862 2863 if (changed & BSS_CHANGED_BSSID) { 2864 b43legacy_synchronize_irq(dev); 2865 2866 if (conf->bssid) 2867 memcpy(wl->bssid, conf->bssid, ETH_ALEN); 2868 else 2869 eth_zero_addr(wl->bssid); 2870 } 2871 2872 if (b43legacy_status(dev) >= B43legacy_STAT_INITIALIZED) { 2873 if (changed & BSS_CHANGED_BEACON && 2874 (b43legacy_is_mode(wl, NL80211_IFTYPE_AP) || 2875 b43legacy_is_mode(wl, NL80211_IFTYPE_ADHOC))) 2876 b43legacy_update_templates(wl); 2877 2878 if (changed & BSS_CHANGED_BSSID) 2879 b43legacy_write_mac_bssid_templates(dev); 2880 } 2881 spin_unlock_irqrestore(&wl->irq_lock, flags); 2882 2883 b43legacy_mac_suspend(dev); 2884 2885 if (changed & BSS_CHANGED_BEACON_INT && 2886 (b43legacy_is_mode(wl, NL80211_IFTYPE_AP) || 2887 b43legacy_is_mode(wl, NL80211_IFTYPE_ADHOC))) 2888 b43legacy_set_beacon_int(dev, conf->beacon_int); 2889 2890 if (changed & BSS_CHANGED_BASIC_RATES) 2891 b43legacy_update_basic_rates(dev, conf->basic_rates); 2892 2893 if (changed & BSS_CHANGED_ERP_SLOT) { 2894 if (conf->use_short_slot) 2895 b43legacy_short_slot_timing_enable(dev); 2896 else 2897 b43legacy_short_slot_timing_disable(dev); 2898 } 2899 2900 b43legacy_mac_enable(dev); 2901 2902 spin_lock_irqsave(&wl->irq_lock, flags); 2903 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, dev->irq_mask); 2904 /* XXX: why? */ 2905 mmiowb(); 2906 spin_unlock_irqrestore(&wl->irq_lock, flags); 2907 out_unlock_mutex: 2908 mutex_unlock(&wl->mutex); 2909} 2910 2911static void b43legacy_op_configure_filter(struct ieee80211_hw *hw, 2912 unsigned int changed, 2913 unsigned int *fflags,u64 multicast) 2914{ 2915 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw); 2916 struct b43legacy_wldev *dev = wl->current_dev; 2917 unsigned long flags; 2918 2919 if (!dev) { 2920 *fflags = 0; 2921 return; 2922 } 2923 2924 spin_lock_irqsave(&wl->irq_lock, flags); 2925 *fflags &= FIF_PROMISC_IN_BSS | 2926 FIF_ALLMULTI | 2927 FIF_FCSFAIL | 2928 FIF_PLCPFAIL | 2929 FIF_CONTROL | 2930 FIF_OTHER_BSS | 2931 FIF_BCN_PRBRESP_PROMISC; 2932 2933 changed &= FIF_PROMISC_IN_BSS | 2934 FIF_ALLMULTI | 2935 FIF_FCSFAIL | 2936 FIF_PLCPFAIL | 2937 FIF_CONTROL | 2938 FIF_OTHER_BSS | 2939 FIF_BCN_PRBRESP_PROMISC; 2940 2941 wl->filter_flags = *fflags; 2942 2943 if (changed && b43legacy_status(dev) >= B43legacy_STAT_INITIALIZED) 2944 b43legacy_adjust_opmode(dev); 2945 spin_unlock_irqrestore(&wl->irq_lock, flags); 2946} 2947 2948/* Locking: wl->mutex */ 2949static void b43legacy_wireless_core_stop(struct b43legacy_wldev *dev) 2950{ 2951 struct b43legacy_wl *wl = dev->wl; 2952 unsigned long flags; 2953 int queue_num; 2954 2955 if (b43legacy_status(dev) < B43legacy_STAT_STARTED) 2956 return; 2957 2958 /* Disable and sync interrupts. We must do this before than 2959 * setting the status to INITIALIZED, as the interrupt handler 2960 * won't care about IRQs then. */ 2961 spin_lock_irqsave(&wl->irq_lock, flags); 2962 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, 0); 2963 b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_MASK); /* flush */ 2964 spin_unlock_irqrestore(&wl->irq_lock, flags); 2965 b43legacy_synchronize_irq(dev); 2966 2967 b43legacy_set_status(dev, B43legacy_STAT_INITIALIZED); 2968 2969 mutex_unlock(&wl->mutex); 2970 /* Must unlock as it would otherwise deadlock. No races here. 2971 * Cancel the possibly running self-rearming periodic work. */ 2972 cancel_delayed_work_sync(&dev->periodic_work); 2973 cancel_work_sync(&wl->tx_work); 2974 mutex_lock(&wl->mutex); 2975 2976 /* Drain all TX queues. */ 2977 for (queue_num = 0; queue_num < B43legacy_QOS_QUEUE_NUM; queue_num++) { 2978 while (skb_queue_len(&wl->tx_queue[queue_num])) 2979 dev_kfree_skb(skb_dequeue(&wl->tx_queue[queue_num])); 2980 } 2981 2982b43legacy_mac_suspend(dev); 2983 free_irq(dev->dev->irq, dev); 2984 b43legacydbg(wl, "Wireless interface stopped\n"); 2985} 2986 2987/* Locking: wl->mutex */ 2988static int b43legacy_wireless_core_start(struct b43legacy_wldev *dev) 2989{ 2990 int err; 2991 2992 B43legacy_WARN_ON(b43legacy_status(dev) != B43legacy_STAT_INITIALIZED); 2993 2994 drain_txstatus_queue(dev); 2995 err = request_irq(dev->dev->irq, b43legacy_interrupt_handler, 2996 IRQF_SHARED, KBUILD_MODNAME, dev); 2997 if (err) { 2998 b43legacyerr(dev->wl, "Cannot request IRQ-%d\n", 2999 dev->dev->irq); 3000 goto out; 3001 } 3002 /* We are ready to run. */ 3003 ieee80211_wake_queues(dev->wl->hw); 3004 b43legacy_set_status(dev, B43legacy_STAT_STARTED); 3005 3006 /* Start data flow (TX/RX) */ 3007 b43legacy_mac_enable(dev); 3008 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, dev->irq_mask); 3009 3010 /* Start maintenance work */ 3011 b43legacy_periodic_tasks_setup(dev); 3012 3013 b43legacydbg(dev->wl, "Wireless interface started\n"); 3014out: 3015 return err; 3016} 3017 3018/* Get PHY and RADIO versioning numbers */ 3019static int b43legacy_phy_versioning(struct b43legacy_wldev *dev) 3020{ 3021 struct b43legacy_phy *phy = &dev->phy; 3022 u32 tmp; 3023 u8 analog_type; 3024 u8 phy_type; 3025 u8 phy_rev; 3026 u16 radio_manuf; 3027 u16 radio_ver; 3028 u16 radio_rev; 3029 int unsupported = 0; 3030 3031 /* Get PHY versioning */ 3032 tmp = b43legacy_read16(dev, B43legacy_MMIO_PHY_VER); 3033 analog_type = (tmp & B43legacy_PHYVER_ANALOG) 3034 >> B43legacy_PHYVER_ANALOG_SHIFT; 3035 phy_type = (tmp & B43legacy_PHYVER_TYPE) >> B43legacy_PHYVER_TYPE_SHIFT; 3036 phy_rev = (tmp & B43legacy_PHYVER_VERSION); 3037 switch (phy_type) { 3038 case B43legacy_PHYTYPE_B: 3039 if (phy_rev != 2 && phy_rev != 4 3040 && phy_rev != 6 && phy_rev != 7) 3041 unsupported = 1; 3042 break; 3043 case B43legacy_PHYTYPE_G: 3044 if (phy_rev > 8) 3045 unsupported = 1; 3046 break; 3047 default: 3048 unsupported = 1; 3049 } 3050 if (unsupported) { 3051 b43legacyerr(dev->wl, "FOUND UNSUPPORTED PHY " 3052 "(Analog %u, Type %u, Revision %u)\n", 3053 analog_type, phy_type, phy_rev); 3054 return -EOPNOTSUPP; 3055 } 3056 b43legacydbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n", 3057 analog_type, phy_type, phy_rev); 3058 3059 3060 /* Get RADIO versioning */ 3061 if (dev->dev->bus->chip_id == 0x4317) { 3062 if (dev->dev->bus->chip_rev == 0) 3063 tmp = 0x3205017F; 3064 else if (dev->dev->bus->chip_rev == 1) 3065 tmp = 0x4205017F; 3066 else 3067 tmp = 0x5205017F; 3068 } else { 3069 b43legacy_write16(dev, B43legacy_MMIO_RADIO_CONTROL, 3070 B43legacy_RADIOCTL_ID); 3071 tmp = b43legacy_read16(dev, B43legacy_MMIO_RADIO_DATA_HIGH); 3072 tmp <<= 16; 3073 b43legacy_write16(dev, B43legacy_MMIO_RADIO_CONTROL, 3074 B43legacy_RADIOCTL_ID); 3075 tmp |= b43legacy_read16(dev, B43legacy_MMIO_RADIO_DATA_LOW); 3076 } 3077 radio_manuf = (tmp & 0x00000FFF); 3078 radio_ver = (tmp & 0x0FFFF000) >> 12; 3079 radio_rev = (tmp & 0xF0000000) >> 28; 3080 switch (phy_type) { 3081 case B43legacy_PHYTYPE_B: 3082 if ((radio_ver & 0xFFF0) != 0x2050) 3083 unsupported = 1; 3084 break; 3085 case B43legacy_PHYTYPE_G: 3086 if (radio_ver != 0x2050) 3087 unsupported = 1; 3088 break; 3089 default: 3090 B43legacy_BUG_ON(1); 3091 } 3092 if (unsupported) { 3093 b43legacyerr(dev->wl, "FOUND UNSUPPORTED RADIO " 3094 "(Manuf 0x%X, Version 0x%X, Revision %u)\n", 3095 radio_manuf, radio_ver, radio_rev); 3096 return -EOPNOTSUPP; 3097 } 3098 b43legacydbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X," 3099 " Revision %u\n", radio_manuf, radio_ver, radio_rev); 3100 3101 3102 phy->radio_manuf = radio_manuf; 3103 phy->radio_ver = radio_ver; 3104 phy->radio_rev = radio_rev; 3105 3106 phy->analog = analog_type; 3107 phy->type = phy_type; 3108 phy->rev = phy_rev; 3109 3110 return 0; 3111} 3112 3113static void setup_struct_phy_for_init(struct b43legacy_wldev *dev, 3114 struct b43legacy_phy *phy) 3115{ 3116 struct b43legacy_lopair *lo; 3117 int i; 3118 3119 memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig)); 3120 memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos)); 3121 3122 /* Assume the radio is enabled. If it's not enabled, the state will 3123 * immediately get fixed on the first periodic work run. */ 3124 dev->radio_hw_enable = true; 3125 3126 phy->savedpctlreg = 0xFFFF; 3127 phy->aci_enable = false; 3128 phy->aci_wlan_automatic = false; 3129 phy->aci_hw_rssi = false; 3130 3131 lo = phy->_lo_pairs; 3132 if (lo) 3133 memset(lo, 0, sizeof(struct b43legacy_lopair) * 3134 B43legacy_LO_COUNT); 3135 phy->max_lb_gain = 0; 3136 phy->trsw_rx_gain = 0; 3137 3138 /* Set default attenuation values. */ 3139 phy->bbatt = b43legacy_default_baseband_attenuation(dev); 3140 phy->rfatt = b43legacy_default_radio_attenuation(dev); 3141 phy->txctl1 = b43legacy_default_txctl1(dev); 3142 phy->txpwr_offset = 0; 3143 3144 /* NRSSI */ 3145 phy->nrssislope = 0; 3146 for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++) 3147 phy->nrssi[i] = -1000; 3148 for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++) 3149 phy->nrssi_lt[i] = i; 3150 3151 phy->lofcal = 0xFFFF; 3152 phy->initval = 0xFFFF; 3153 3154 phy->interfmode = B43legacy_INTERFMODE_NONE; 3155 phy->channel = 0xFF; 3156} 3157 3158static void setup_struct_wldev_for_init(struct b43legacy_wldev *dev) 3159{ 3160 /* Flags */ 3161 dev->dfq_valid = false; 3162 3163 /* Stats */ 3164 memset(&dev->stats, 0, sizeof(dev->stats)); 3165 3166 setup_struct_phy_for_init(dev, &dev->phy); 3167 3168 /* IRQ related flags */ 3169 dev->irq_reason = 0; 3170 memset(dev->dma_reason, 0, sizeof(dev->dma_reason)); 3171 dev->irq_mask = B43legacy_IRQ_MASKTEMPLATE; 3172 3173 dev->mac_suspended = 1; 3174 3175 /* Noise calculation context */ 3176 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc)); 3177} 3178 3179static void b43legacy_set_synth_pu_delay(struct b43legacy_wldev *dev, 3180 bool idle) { 3181 u16 pu_delay = 1050; 3182 3183 if (b43legacy_is_mode(dev->wl, NL80211_IFTYPE_ADHOC) || idle) 3184 pu_delay = 500; 3185 if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8)) 3186 pu_delay = max(pu_delay, (u16)2400); 3187 3188 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 3189 B43legacy_SHM_SH_SPUWKUP, pu_delay); 3190} 3191 3192/* Set the TSF CFP pre-TargetBeaconTransmissionTime. */ 3193static void b43legacy_set_pretbtt(struct b43legacy_wldev *dev) 3194{ 3195 u16 pretbtt; 3196 3197 /* The time value is in microseconds. */ 3198 if (b43legacy_is_mode(dev->wl, NL80211_IFTYPE_ADHOC)) 3199 pretbtt = 2; 3200 else 3201 pretbtt = 250; 3202 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 3203 B43legacy_SHM_SH_PRETBTT, pretbtt); 3204 b43legacy_write16(dev, B43legacy_MMIO_TSF_CFP_PRETBTT, pretbtt); 3205} 3206 3207/* Shutdown a wireless core */ 3208/* Locking: wl->mutex */ 3209static void b43legacy_wireless_core_exit(struct b43legacy_wldev *dev) 3210{ 3211 struct b43legacy_phy *phy = &dev->phy; 3212 u32 macctl; 3213 3214 B43legacy_WARN_ON(b43legacy_status(dev) > B43legacy_STAT_INITIALIZED); 3215 if (b43legacy_status(dev) != B43legacy_STAT_INITIALIZED) 3216 return; 3217 b43legacy_set_status(dev, B43legacy_STAT_UNINIT); 3218 3219 /* Stop the microcode PSM. */ 3220 macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL); 3221 macctl &= ~B43legacy_MACCTL_PSM_RUN; 3222 macctl |= B43legacy_MACCTL_PSM_JMP0; 3223 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl); 3224 3225 b43legacy_leds_exit(dev); 3226 b43legacy_rng_exit(dev->wl); 3227 b43legacy_pio_free(dev); 3228 b43legacy_dma_free(dev); 3229 b43legacy_chip_exit(dev); 3230 b43legacy_radio_turn_off(dev, 1); 3231 b43legacy_switch_analog(dev, 0); 3232 if (phy->dyn_tssi_tbl) 3233 kfree(phy->tssi2dbm); 3234 kfree(phy->lo_control); 3235 phy->lo_control = NULL; 3236 if (dev->wl->current_beacon) { 3237 dev_kfree_skb_any(dev->wl->current_beacon); 3238 dev->wl->current_beacon = NULL; 3239 } 3240 3241 ssb_device_disable(dev->dev, 0); 3242 ssb_bus_may_powerdown(dev->dev->bus); 3243} 3244 3245static void prepare_phy_data_for_init(struct b43legacy_wldev *dev) 3246{ 3247 struct b43legacy_phy *phy = &dev->phy; 3248 int i; 3249 3250 /* Set default attenuation values. */ 3251 phy->bbatt = b43legacy_default_baseband_attenuation(dev); 3252 phy->rfatt = b43legacy_default_radio_attenuation(dev); 3253 phy->txctl1 = b43legacy_default_txctl1(dev); 3254 phy->txctl2 = 0xFFFF; 3255 phy->txpwr_offset = 0; 3256 3257 /* NRSSI */ 3258 phy->nrssislope = 0; 3259 for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++) 3260 phy->nrssi[i] = -1000; 3261 for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++) 3262 phy->nrssi_lt[i] = i; 3263 3264 phy->lofcal = 0xFFFF; 3265 phy->initval = 0xFFFF; 3266 3267 phy->aci_enable = false; 3268 phy->aci_wlan_automatic = false; 3269 phy->aci_hw_rssi = false; 3270 3271 phy->antenna_diversity = 0xFFFF; 3272 memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig)); 3273 memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos)); 3274 3275 /* Flags */ 3276 phy->calibrated = 0; 3277 3278 if (phy->_lo_pairs) 3279 memset(phy->_lo_pairs, 0, 3280 sizeof(struct b43legacy_lopair) * B43legacy_LO_COUNT); 3281 memset(phy->loopback_gain, 0, sizeof(phy->loopback_gain)); 3282} 3283 3284/* Initialize a wireless core */ 3285static int b43legacy_wireless_core_init(struct b43legacy_wldev *dev) 3286{ 3287 struct b43legacy_wl *wl = dev->wl; 3288 struct ssb_bus *bus = dev->dev->bus; 3289 struct b43legacy_phy *phy = &dev->phy; 3290 struct ssb_sprom *sprom = &dev->dev->bus->sprom; 3291 int err; 3292 u32 hf; 3293 u32 tmp; 3294 3295 B43legacy_WARN_ON(b43legacy_status(dev) != B43legacy_STAT_UNINIT); 3296 3297 err = ssb_bus_powerup(bus, 0); 3298 if (err) 3299 goto out; 3300 if (!ssb_device_is_enabled(dev->dev)) { 3301 tmp = phy->gmode ? B43legacy_TMSLOW_GMODE : 0; 3302 b43legacy_wireless_core_reset(dev, tmp); 3303 } 3304 3305 if ((phy->type == B43legacy_PHYTYPE_B) || 3306 (phy->type == B43legacy_PHYTYPE_G)) { 3307 phy->_lo_pairs = kzalloc(sizeof(struct b43legacy_lopair) 3308 * B43legacy_LO_COUNT, 3309 GFP_KERNEL); 3310 if (!phy->_lo_pairs) 3311 return -ENOMEM; 3312 } 3313 setup_struct_wldev_for_init(dev); 3314 3315 err = b43legacy_phy_init_tssi2dbm_table(dev); 3316 if (err) 3317 goto err_kfree_lo_control; 3318 3319 /* Enable IRQ routing to this device. */ 3320 ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev); 3321 3322 prepare_phy_data_for_init(dev); 3323 b43legacy_phy_calibrate(dev); 3324 err = b43legacy_chip_init(dev); 3325 if (err) 3326 goto err_kfree_tssitbl; 3327 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 3328 B43legacy_SHM_SH_WLCOREREV, 3329 dev->dev->id.revision); 3330 hf = b43legacy_hf_read(dev); 3331 if (phy->type == B43legacy_PHYTYPE_G) { 3332 hf |= B43legacy_HF_SYMW; 3333 if (phy->rev == 1) 3334 hf |= B43legacy_HF_GDCW; 3335 if (sprom->boardflags_lo & B43legacy_BFL_PACTRL) 3336 hf |= B43legacy_HF_OFDMPABOOST; 3337 } else if (phy->type == B43legacy_PHYTYPE_B) { 3338 hf |= B43legacy_HF_SYMW; 3339 if (phy->rev >= 2 && phy->radio_ver == 0x2050) 3340 hf &= ~B43legacy_HF_GDCW; 3341 } 3342 b43legacy_hf_write(dev, hf); 3343 3344 b43legacy_set_retry_limits(dev, 3345 B43legacy_DEFAULT_SHORT_RETRY_LIMIT, 3346 B43legacy_DEFAULT_LONG_RETRY_LIMIT); 3347 3348 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 3349 0x0044, 3); 3350 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 3351 0x0046, 2); 3352 3353 /* Disable sending probe responses from firmware. 3354 * Setting the MaxTime to one usec will always trigger 3355 * a timeout, so we never send any probe resp. 3356 * A timeout of zero is infinite. */ 3357 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 3358 B43legacy_SHM_SH_PRMAXTIME, 1); 3359 3360 b43legacy_rate_memory_init(dev); 3361 3362 /* Minimum Contention Window */ 3363 if (phy->type == B43legacy_PHYTYPE_B) 3364 b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS, 3365 0x0003, 31); 3366 else 3367 b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS, 3368 0x0003, 15); 3369 /* Maximum Contention Window */ 3370 b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS, 3371 0x0004, 1023); 3372 3373 do { 3374 if (b43legacy_using_pio(dev)) 3375 err = b43legacy_pio_init(dev); 3376 else { 3377 err = b43legacy_dma_init(dev); 3378 if (!err) 3379 b43legacy_qos_init(dev); 3380 } 3381 } while (err == -EAGAIN); 3382 if (err) 3383 goto err_chip_exit; 3384 3385 b43legacy_set_synth_pu_delay(dev, 1); 3386 3387 ssb_bus_powerup(bus, 1); /* Enable dynamic PCTL */ 3388 b43legacy_upload_card_macaddress(dev); 3389 b43legacy_security_init(dev); 3390 b43legacy_rng_init(wl); 3391 3392 ieee80211_wake_queues(dev->wl->hw); 3393 b43legacy_set_status(dev, B43legacy_STAT_INITIALIZED); 3394 3395 b43legacy_leds_init(dev); 3396out: 3397 return err; 3398 3399err_chip_exit: 3400 b43legacy_chip_exit(dev); 3401err_kfree_tssitbl: 3402 if (phy->dyn_tssi_tbl) 3403 kfree(phy->tssi2dbm); 3404err_kfree_lo_control: 3405 kfree(phy->lo_control); 3406 phy->lo_control = NULL; 3407 ssb_bus_may_powerdown(bus); 3408 B43legacy_WARN_ON(b43legacy_status(dev) != B43legacy_STAT_UNINIT); 3409 return err; 3410} 3411 3412static int b43legacy_op_add_interface(struct ieee80211_hw *hw, 3413 struct ieee80211_vif *vif) 3414{ 3415 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw); 3416 struct b43legacy_wldev *dev; 3417 unsigned long flags; 3418 int err = -EOPNOTSUPP; 3419 3420 /* TODO: allow WDS/AP devices to coexist */ 3421 3422 if (vif->type != NL80211_IFTYPE_AP && 3423 vif->type != NL80211_IFTYPE_STATION && 3424 vif->type != NL80211_IFTYPE_WDS && 3425 vif->type != NL80211_IFTYPE_ADHOC) 3426 return -EOPNOTSUPP; 3427 3428 mutex_lock(&wl->mutex); 3429 if (wl->operating) 3430 goto out_mutex_unlock; 3431 3432 b43legacydbg(wl, "Adding Interface type %d\n", vif->type); 3433 3434 dev = wl->current_dev; 3435 wl->operating = true; 3436 wl->vif = vif; 3437 wl->if_type = vif->type; 3438 memcpy(wl->mac_addr, vif->addr, ETH_ALEN); 3439 3440 spin_lock_irqsave(&wl->irq_lock, flags); 3441 b43legacy_adjust_opmode(dev); 3442 b43legacy_set_pretbtt(dev); 3443 b43legacy_set_synth_pu_delay(dev, 0); 3444 b43legacy_upload_card_macaddress(dev); 3445 spin_unlock_irqrestore(&wl->irq_lock, flags); 3446 3447 err = 0; 3448 out_mutex_unlock: 3449 mutex_unlock(&wl->mutex); 3450 3451 return err; 3452} 3453 3454static void b43legacy_op_remove_interface(struct ieee80211_hw *hw, 3455 struct ieee80211_vif *vif) 3456{ 3457 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw); 3458 struct b43legacy_wldev *dev = wl->current_dev; 3459 unsigned long flags; 3460 3461 b43legacydbg(wl, "Removing Interface type %d\n", vif->type); 3462 3463 mutex_lock(&wl->mutex); 3464 3465 B43legacy_WARN_ON(!wl->operating); 3466 B43legacy_WARN_ON(wl->vif != vif); 3467 wl->vif = NULL; 3468 3469 wl->operating = false; 3470 3471 spin_lock_irqsave(&wl->irq_lock, flags); 3472 b43legacy_adjust_opmode(dev); 3473 eth_zero_addr(wl->mac_addr); 3474 b43legacy_upload_card_macaddress(dev); 3475 spin_unlock_irqrestore(&wl->irq_lock, flags); 3476 3477 mutex_unlock(&wl->mutex); 3478} 3479 3480static int b43legacy_op_start(struct ieee80211_hw *hw) 3481{ 3482 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw); 3483 struct b43legacy_wldev *dev = wl->current_dev; 3484 int did_init = 0; 3485 int err = 0; 3486 3487 /* Kill all old instance specific information to make sure 3488 * the card won't use it in the short timeframe between start 3489 * and mac80211 reconfiguring it. */ 3490 eth_zero_addr(wl->bssid); 3491 eth_zero_addr(wl->mac_addr); 3492 wl->filter_flags = 0; 3493 wl->beacon0_uploaded = false; 3494 wl->beacon1_uploaded = false; 3495 wl->beacon_templates_virgin = true; 3496 wl->radio_enabled = true; 3497 3498 mutex_lock(&wl->mutex); 3499 3500 if (b43legacy_status(dev) < B43legacy_STAT_INITIALIZED) { 3501 err = b43legacy_wireless_core_init(dev); 3502 if (err) 3503 goto out_mutex_unlock; 3504 did_init = 1; 3505 } 3506 3507 if (b43legacy_status(dev) < B43legacy_STAT_STARTED) { 3508 err = b43legacy_wireless_core_start(dev); 3509 if (err) { 3510 if (did_init) 3511 b43legacy_wireless_core_exit(dev); 3512 goto out_mutex_unlock; 3513 } 3514 } 3515 3516 wiphy_rfkill_start_polling(hw->wiphy); 3517 3518out_mutex_unlock: 3519 mutex_unlock(&wl->mutex); 3520 3521 return err; 3522} 3523 3524static void b43legacy_op_stop(struct ieee80211_hw *hw) 3525{ 3526 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw); 3527 struct b43legacy_wldev *dev = wl->current_dev; 3528 3529 cancel_work_sync(&(wl->beacon_update_trigger)); 3530 3531 mutex_lock(&wl->mutex); 3532 if (b43legacy_status(dev) >= B43legacy_STAT_STARTED) 3533 b43legacy_wireless_core_stop(dev); 3534 b43legacy_wireless_core_exit(dev); 3535 wl->radio_enabled = false; 3536 mutex_unlock(&wl->mutex); 3537} 3538 3539static int b43legacy_op_beacon_set_tim(struct ieee80211_hw *hw, 3540 struct ieee80211_sta *sta, bool set) 3541{ 3542 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw); 3543 unsigned long flags; 3544 3545 spin_lock_irqsave(&wl->irq_lock, flags); 3546 b43legacy_update_templates(wl); 3547 spin_unlock_irqrestore(&wl->irq_lock, flags); 3548 3549 return 0; 3550} 3551 3552static int b43legacy_op_get_survey(struct ieee80211_hw *hw, int idx, 3553 struct survey_info *survey) 3554{ 3555 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw); 3556 struct b43legacy_wldev *dev = wl->current_dev; 3557 struct ieee80211_conf *conf = &hw->conf; 3558 3559 if (idx != 0) 3560 return -ENOENT; 3561 3562 survey->channel = conf->chandef.chan; 3563 survey->filled = SURVEY_INFO_NOISE_DBM; 3564 survey->noise = dev->stats.link_noise; 3565 3566 return 0; 3567} 3568 3569static const struct ieee80211_ops b43legacy_hw_ops = { 3570 .tx = b43legacy_op_tx, 3571 .conf_tx = b43legacy_op_conf_tx, 3572 .add_interface = b43legacy_op_add_interface, 3573 .remove_interface = b43legacy_op_remove_interface, 3574 .config = b43legacy_op_dev_config, 3575 .bss_info_changed = b43legacy_op_bss_info_changed, 3576 .configure_filter = b43legacy_op_configure_filter, 3577 .get_stats = b43legacy_op_get_stats, 3578 .start = b43legacy_op_start, 3579 .stop = b43legacy_op_stop, 3580 .set_tim = b43legacy_op_beacon_set_tim, 3581 .get_survey = b43legacy_op_get_survey, 3582 .rfkill_poll = b43legacy_rfkill_poll, 3583}; 3584 3585/* Hard-reset the chip. Do not call this directly. 3586 * Use b43legacy_controller_restart() 3587 */ 3588static void b43legacy_chip_reset(struct work_struct *work) 3589{ 3590 struct b43legacy_wldev *dev = 3591 container_of(work, struct b43legacy_wldev, restart_work); 3592 struct b43legacy_wl *wl = dev->wl; 3593 int err = 0; 3594 int prev_status; 3595 3596 mutex_lock(&wl->mutex); 3597 3598 prev_status = b43legacy_status(dev); 3599 /* Bring the device down... */ 3600 if (prev_status >= B43legacy_STAT_STARTED) 3601 b43legacy_wireless_core_stop(dev); 3602 if (prev_status >= B43legacy_STAT_INITIALIZED) 3603 b43legacy_wireless_core_exit(dev); 3604 3605 /* ...and up again. */ 3606 if (prev_status >= B43legacy_STAT_INITIALIZED) { 3607 err = b43legacy_wireless_core_init(dev); 3608 if (err) 3609 goto out; 3610 } 3611 if (prev_status >= B43legacy_STAT_STARTED) { 3612 err = b43legacy_wireless_core_start(dev); 3613 if (err) { 3614 b43legacy_wireless_core_exit(dev); 3615 goto out; 3616 } 3617 } 3618out: 3619 if (err) 3620 wl->current_dev = NULL; /* Failed to init the dev. */ 3621 mutex_unlock(&wl->mutex); 3622 if (err) 3623 b43legacyerr(wl, "Controller restart FAILED\n"); 3624 else 3625 b43legacyinfo(wl, "Controller restarted\n"); 3626} 3627 3628static int b43legacy_setup_modes(struct b43legacy_wldev *dev, 3629 int have_bphy, 3630 int have_gphy) 3631{ 3632 struct ieee80211_hw *hw = dev->wl->hw; 3633 struct b43legacy_phy *phy = &dev->phy; 3634 3635 phy->possible_phymodes = 0; 3636 if (have_bphy) { 3637 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = 3638 &b43legacy_band_2GHz_BPHY; 3639 phy->possible_phymodes |= B43legacy_PHYMODE_B; 3640 } 3641 3642 if (have_gphy) { 3643 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = 3644 &b43legacy_band_2GHz_GPHY; 3645 phy->possible_phymodes |= B43legacy_PHYMODE_G; 3646 } 3647 3648 return 0; 3649} 3650 3651static void b43legacy_wireless_core_detach(struct b43legacy_wldev *dev) 3652{ 3653 /* We release firmware that late to not be required to re-request 3654 * is all the time when we reinit the core. */ 3655 b43legacy_release_firmware(dev); 3656} 3657 3658static int b43legacy_wireless_core_attach(struct b43legacy_wldev *dev) 3659{ 3660 struct b43legacy_wl *wl = dev->wl; 3661 struct ssb_bus *bus = dev->dev->bus; 3662 struct pci_dev *pdev = (bus->bustype == SSB_BUSTYPE_PCI) ? bus->host_pci : NULL; 3663 int err; 3664 int have_bphy = 0; 3665 int have_gphy = 0; 3666 u32 tmp; 3667 3668 /* Do NOT do any device initialization here. 3669 * Do it in wireless_core_init() instead. 3670 * This function is for gathering basic information about the HW, only. 3671 * Also some structs may be set up here. But most likely you want to 3672 * have that in core_init(), too. 3673 */ 3674 3675 err = ssb_bus_powerup(bus, 0); 3676 if (err) { 3677 b43legacyerr(wl, "Bus powerup failed\n"); 3678 goto out; 3679 } 3680 /* Get the PHY type. */ 3681 if (dev->dev->id.revision >= 5) { 3682 u32 tmshigh; 3683 3684 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH); 3685 have_gphy = !!(tmshigh & B43legacy_TMSHIGH_GPHY); 3686 if (!have_gphy) 3687 have_bphy = 1; 3688 } else if (dev->dev->id.revision == 4) 3689 have_gphy = 1; 3690 else 3691 have_bphy = 1; 3692 3693 dev->phy.gmode = (have_gphy || have_bphy); 3694 dev->phy.radio_on = true; 3695 tmp = dev->phy.gmode ? B43legacy_TMSLOW_GMODE : 0; 3696 b43legacy_wireless_core_reset(dev, tmp); 3697 3698 err = b43legacy_phy_versioning(dev); 3699 if (err) 3700 goto err_powerdown; 3701 /* Check if this device supports multiband. */ 3702 if (!pdev || 3703 (pdev->device != 0x4312 && 3704 pdev->device != 0x4319 && 3705 pdev->device != 0x4324)) { 3706 /* No multiband support. */ 3707 have_bphy = 0; 3708 have_gphy = 0; 3709 switch (dev->phy.type) { 3710 case B43legacy_PHYTYPE_B: 3711 have_bphy = 1; 3712 break; 3713 case B43legacy_PHYTYPE_G: 3714 have_gphy = 1; 3715 break; 3716 default: 3717 B43legacy_BUG_ON(1); 3718 } 3719 } 3720 dev->phy.gmode = (have_gphy || have_bphy); 3721 tmp = dev->phy.gmode ? B43legacy_TMSLOW_GMODE : 0; 3722 b43legacy_wireless_core_reset(dev, tmp); 3723 3724 err = b43legacy_validate_chipaccess(dev); 3725 if (err) 3726 goto err_powerdown; 3727 err = b43legacy_setup_modes(dev, have_bphy, have_gphy); 3728 if (err) 3729 goto err_powerdown; 3730 3731 /* Now set some default "current_dev" */ 3732 if (!wl->current_dev) 3733 wl->current_dev = dev; 3734 INIT_WORK(&dev->restart_work, b43legacy_chip_reset); 3735 3736 b43legacy_radio_turn_off(dev, 1); 3737 b43legacy_switch_analog(dev, 0); 3738 ssb_device_disable(dev->dev, 0); 3739 ssb_bus_may_powerdown(bus); 3740 3741out: 3742 return err; 3743 3744err_powerdown: 3745 ssb_bus_may_powerdown(bus); 3746 return err; 3747} 3748 3749static void b43legacy_one_core_detach(struct ssb_device *dev) 3750{ 3751 struct b43legacy_wldev *wldev; 3752 struct b43legacy_wl *wl; 3753 3754 /* Do not cancel ieee80211-workqueue based work here. 3755 * See comment in b43legacy_remove(). */ 3756 3757 wldev = ssb_get_drvdata(dev); 3758 wl = wldev->wl; 3759 b43legacy_debugfs_remove_device(wldev); 3760 b43legacy_wireless_core_detach(wldev); 3761 list_del(&wldev->list); 3762 wl->nr_devs--; 3763 ssb_set_drvdata(dev, NULL); 3764 kfree(wldev); 3765} 3766 3767static int b43legacy_one_core_attach(struct ssb_device *dev, 3768 struct b43legacy_wl *wl) 3769{ 3770 struct b43legacy_wldev *wldev; 3771 int err = -ENOMEM; 3772 3773 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL); 3774 if (!wldev) 3775 goto out; 3776 3777 wldev->dev = dev; 3778 wldev->wl = wl; 3779 b43legacy_set_status(wldev, B43legacy_STAT_UNINIT); 3780 wldev->bad_frames_preempt = modparam_bad_frames_preempt; 3781 tasklet_init(&wldev->isr_tasklet, 3782 (void (*)(unsigned long))b43legacy_interrupt_tasklet, 3783 (unsigned long)wldev); 3784 if (modparam_pio) 3785 wldev->__using_pio = true; 3786 INIT_LIST_HEAD(&wldev->list); 3787 3788 err = b43legacy_wireless_core_attach(wldev); 3789 if (err) 3790 goto err_kfree_wldev; 3791 3792 list_add(&wldev->list, &wl->devlist); 3793 wl->nr_devs++; 3794 ssb_set_drvdata(dev, wldev); 3795 b43legacy_debugfs_add_device(wldev); 3796out: 3797 return err; 3798 3799err_kfree_wldev: 3800 kfree(wldev); 3801 return err; 3802} 3803 3804static void b43legacy_sprom_fixup(struct ssb_bus *bus) 3805{ 3806 /* boardflags workarounds */ 3807 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE && 3808 bus->boardinfo.type == 0x4E && 3809 bus->sprom.board_rev > 0x40) 3810 bus->sprom.boardflags_lo |= B43legacy_BFL_PACTRL; 3811} 3812 3813static void b43legacy_wireless_exit(struct ssb_device *dev, 3814 struct b43legacy_wl *wl) 3815{ 3816 struct ieee80211_hw *hw = wl->hw; 3817 3818 ssb_set_devtypedata(dev, NULL); 3819 ieee80211_free_hw(hw); 3820} 3821 3822static int b43legacy_wireless_init(struct ssb_device *dev) 3823{ 3824 struct ssb_sprom *sprom = &dev->bus->sprom; 3825 struct ieee80211_hw *hw; 3826 struct b43legacy_wl *wl; 3827 int err = -ENOMEM; 3828 int queue_num; 3829 3830 b43legacy_sprom_fixup(dev->bus); 3831 3832 hw = ieee80211_alloc_hw(sizeof(*wl), &b43legacy_hw_ops); 3833 if (!hw) { 3834 b43legacyerr(NULL, "Could not allocate ieee80211 device\n"); 3835 goto out; 3836 } 3837 3838 /* fill hw info */ 3839 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS | 3840 IEEE80211_HW_SIGNAL_DBM; 3841 hw->wiphy->interface_modes = 3842 BIT(NL80211_IFTYPE_AP) | 3843 BIT(NL80211_IFTYPE_STATION) | 3844 BIT(NL80211_IFTYPE_WDS) | 3845 BIT(NL80211_IFTYPE_ADHOC); 3846 hw->queues = 1; /* FIXME: hardware has more queues */ 3847 hw->max_rates = 2; 3848 SET_IEEE80211_DEV(hw, dev->dev); 3849 if (is_valid_ether_addr(sprom->et1mac)) 3850 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac); 3851 else 3852 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac); 3853 3854 /* Get and initialize struct b43legacy_wl */ 3855 wl = hw_to_b43legacy_wl(hw); 3856 memset(wl, 0, sizeof(*wl)); 3857 wl->hw = hw; 3858 spin_lock_init(&wl->irq_lock); 3859 spin_lock_init(&wl->leds_lock); 3860 mutex_init(&wl->mutex); 3861 INIT_LIST_HEAD(&wl->devlist); 3862 INIT_WORK(&wl->beacon_update_trigger, b43legacy_beacon_update_trigger_work); 3863 INIT_WORK(&wl->tx_work, b43legacy_tx_work); 3864 3865 /* Initialize queues and flags. */ 3866 for (queue_num = 0; queue_num < B43legacy_QOS_QUEUE_NUM; queue_num++) { 3867 skb_queue_head_init(&wl->tx_queue[queue_num]); 3868 wl->tx_queue_stopped[queue_num] = 0; 3869 } 3870 3871 ssb_set_devtypedata(dev, wl); 3872 b43legacyinfo(wl, "Broadcom %04X WLAN found (core revision %u)\n", 3873 dev->bus->chip_id, dev->id.revision); 3874 err = 0; 3875out: 3876 return err; 3877} 3878 3879static int b43legacy_probe(struct ssb_device *dev, 3880 const struct ssb_device_id *id) 3881{ 3882 struct b43legacy_wl *wl; 3883 int err; 3884 int first = 0; 3885 3886 wl = ssb_get_devtypedata(dev); 3887 if (!wl) { 3888 /* Probing the first core - setup common struct b43legacy_wl */ 3889 first = 1; 3890 err = b43legacy_wireless_init(dev); 3891 if (err) 3892 goto out; 3893 wl = ssb_get_devtypedata(dev); 3894 B43legacy_WARN_ON(!wl); 3895 } 3896 err = b43legacy_one_core_attach(dev, wl); 3897 if (err) 3898 goto err_wireless_exit; 3899 3900 /* setup and start work to load firmware */ 3901 INIT_WORK(&wl->firmware_load, b43legacy_request_firmware); 3902 schedule_work(&wl->firmware_load); 3903 3904out: 3905 return err; 3906 3907err_wireless_exit: 3908 if (first) 3909 b43legacy_wireless_exit(dev, wl); 3910 return err; 3911} 3912 3913static void b43legacy_remove(struct ssb_device *dev) 3914{ 3915 struct b43legacy_wl *wl = ssb_get_devtypedata(dev); 3916 struct b43legacy_wldev *wldev = ssb_get_drvdata(dev); 3917 3918 /* We must cancel any work here before unregistering from ieee80211, 3919 * as the ieee80211 unreg will destroy the workqueue. */ 3920 cancel_work_sync(&wldev->restart_work); 3921 cancel_work_sync(&wl->firmware_load); 3922 complete(&wldev->fw_load_complete); 3923 3924 B43legacy_WARN_ON(!wl); 3925 if (!wldev->fw.ucode) 3926 return; /* NULL if fw never loaded */ 3927 if (wl->current_dev == wldev) 3928 ieee80211_unregister_hw(wl->hw); 3929 3930 b43legacy_one_core_detach(dev); 3931 3932 if (list_empty(&wl->devlist)) 3933 /* Last core on the chip unregistered. 3934 * We can destroy common struct b43legacy_wl. 3935 */ 3936 b43legacy_wireless_exit(dev, wl); 3937} 3938 3939/* Perform a hardware reset. This can be called from any context. */ 3940void b43legacy_controller_restart(struct b43legacy_wldev *dev, 3941 const char *reason) 3942{ 3943 /* Must avoid requeueing, if we are in shutdown. */ 3944 if (b43legacy_status(dev) < B43legacy_STAT_INITIALIZED) 3945 return; 3946 b43legacyinfo(dev->wl, "Controller RESET (%s) ...\n", reason); 3947 ieee80211_queue_work(dev->wl->hw, &dev->restart_work); 3948} 3949 3950#ifdef CONFIG_PM 3951 3952static int b43legacy_suspend(struct ssb_device *dev, pm_message_t state) 3953{ 3954 struct b43legacy_wldev *wldev = ssb_get_drvdata(dev); 3955 struct b43legacy_wl *wl = wldev->wl; 3956 3957 b43legacydbg(wl, "Suspending...\n"); 3958 3959 mutex_lock(&wl->mutex); 3960 wldev->suspend_init_status = b43legacy_status(wldev); 3961 if (wldev->suspend_init_status >= B43legacy_STAT_STARTED) 3962 b43legacy_wireless_core_stop(wldev); 3963 if (wldev->suspend_init_status >= B43legacy_STAT_INITIALIZED) 3964 b43legacy_wireless_core_exit(wldev); 3965 mutex_unlock(&wl->mutex); 3966 3967 b43legacydbg(wl, "Device suspended.\n"); 3968 3969 return 0; 3970} 3971 3972static int b43legacy_resume(struct ssb_device *dev) 3973{ 3974 struct b43legacy_wldev *wldev = ssb_get_drvdata(dev); 3975 struct b43legacy_wl *wl = wldev->wl; 3976 int err = 0; 3977 3978 b43legacydbg(wl, "Resuming...\n"); 3979 3980 mutex_lock(&wl->mutex); 3981 if (wldev->suspend_init_status >= B43legacy_STAT_INITIALIZED) { 3982 err = b43legacy_wireless_core_init(wldev); 3983 if (err) { 3984 b43legacyerr(wl, "Resume failed at core init\n"); 3985 goto out; 3986 } 3987 } 3988 if (wldev->suspend_init_status >= B43legacy_STAT_STARTED) { 3989 err = b43legacy_wireless_core_start(wldev); 3990 if (err) { 3991 b43legacy_wireless_core_exit(wldev); 3992 b43legacyerr(wl, "Resume failed at core start\n"); 3993 goto out; 3994 } 3995 } 3996 3997 b43legacydbg(wl, "Device resumed.\n"); 3998out: 3999 mutex_unlock(&wl->mutex); 4000 return err; 4001} 4002 4003#else /* CONFIG_PM */ 4004# define b43legacy_suspend NULL 4005# define b43legacy_resume NULL 4006#endif /* CONFIG_PM */ 4007 4008static struct ssb_driver b43legacy_ssb_driver = { 4009 .name = KBUILD_MODNAME, 4010 .id_table = b43legacy_ssb_tbl, 4011 .probe = b43legacy_probe, 4012 .remove = b43legacy_remove, 4013 .suspend = b43legacy_suspend, 4014 .resume = b43legacy_resume, 4015}; 4016 4017static void b43legacy_print_driverinfo(void) 4018{ 4019 const char *feat_pci = "", *feat_leds = "", 4020 *feat_pio = "", *feat_dma = ""; 4021 4022#ifdef CONFIG_B43LEGACY_PCI_AUTOSELECT 4023 feat_pci = "P"; 4024#endif 4025#ifdef CONFIG_B43LEGACY_LEDS 4026 feat_leds = "L"; 4027#endif 4028#ifdef CONFIG_B43LEGACY_PIO 4029 feat_pio = "I"; 4030#endif 4031#ifdef CONFIG_B43LEGACY_DMA 4032 feat_dma = "D"; 4033#endif 4034 printk(KERN_INFO "Broadcom 43xx-legacy driver loaded " 4035 "[ Features: %s%s%s%s ]\n", 4036 feat_pci, feat_leds, feat_pio, feat_dma); 4037} 4038 4039static int __init b43legacy_init(void) 4040{ 4041 int err; 4042 4043 b43legacy_debugfs_init(); 4044 4045 err = ssb_driver_register(&b43legacy_ssb_driver); 4046 if (err) 4047 goto err_dfs_exit; 4048 4049 b43legacy_print_driverinfo(); 4050 4051 return err; 4052 4053err_dfs_exit: 4054 b43legacy_debugfs_exit(); 4055 return err; 4056} 4057 4058static void __exit b43legacy_exit(void) 4059{ 4060 ssb_driver_unregister(&b43legacy_ssb_driver); 4061 b43legacy_debugfs_exit(); 4062} 4063 4064module_init(b43legacy_init) 4065module_exit(b43legacy_exit) 4066