1/* 2 * Copyright (c) 2010-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17#ifndef AR9003_EEPROM_H 18#define AR9003_EEPROM_H 19 20#include <linux/types.h> 21 22#define AR9300_EEP_VER 0xD000 23#define AR9300_EEP_VER_MINOR_MASK 0xFFF 24#define AR9300_EEP_MINOR_VER_1 0x1 25#define AR9300_EEP_MINOR_VER AR9300_EEP_MINOR_VER_1 26 27/* 16-bit offset location start of calibration struct */ 28#define AR9300_EEP_START_LOC 256 29#define AR9300_NUM_5G_CAL_PIERS 8 30#define AR9300_NUM_2G_CAL_PIERS 3 31#define AR9300_NUM_5G_20_TARGET_POWERS 8 32#define AR9300_NUM_5G_40_TARGET_POWERS 8 33#define AR9300_NUM_2G_CCK_TARGET_POWERS 2 34#define AR9300_NUM_2G_20_TARGET_POWERS 3 35#define AR9300_NUM_2G_40_TARGET_POWERS 3 36/* #define AR9300_NUM_CTLS 21 */ 37#define AR9300_NUM_CTLS_5G 9 38#define AR9300_NUM_CTLS_2G 12 39#define AR9300_NUM_BAND_EDGES_5G 8 40#define AR9300_NUM_BAND_EDGES_2G 4 41#define AR9300_EEPMISC_BIG_ENDIAN 0x01 42#define AR9300_EEPMISC_WOW 0x02 43#define AR9300_CUSTOMER_DATA_SIZE 20 44 45#define AR9300_MAX_CHAINS 3 46#define AR9300_ANT_16S 25 47#define AR9300_FUTURE_MODAL_SZ 6 48 49#define AR9300_PAPRD_RATE_MASK 0x01ffffff 50#define AR9300_PAPRD_SCALE_1 0x0e000000 51#define AR9300_PAPRD_SCALE_1_S 25 52#define AR9300_PAPRD_SCALE_2 0x70000000 53#define AR9300_PAPRD_SCALE_2_S 28 54 55#define AR9300_EEP_ANTDIV_CONTROL_DEFAULT_VALUE 0xc9 56 57/* Delta from which to start power to pdadc table */ 58/* This offset is used in both open loop and closed loop power control 59 * schemes. In open loop power control, it is not really needed, but for 60 * the "sake of consistency" it was kept. For certain AP designs, this 61 * value is overwritten by the value in the flag "pwrTableOffset" just 62 * before writing the pdadc vs pwr into the chip registers. 63 */ 64#define AR9300_PWR_TABLE_OFFSET 0 65 66/* byte addressable */ 67#define AR9300_EEPROM_SIZE (16*1024) 68 69#define AR9300_BASE_ADDR_4K 0xfff 70#define AR9300_BASE_ADDR 0x3ff 71#define AR9300_BASE_ADDR_512 0x1ff 72 73#define AR9300_OTP_BASE \ 74 ((AR_SREV_9340(ah) || AR_SREV_9550(ah)) ? 0x30000 : 0x14000) 75#define AR9300_OTP_STATUS \ 76 ((AR_SREV_9340(ah) || AR_SREV_9550(ah)) ? 0x30018 : 0x15f18) 77#define AR9300_OTP_STATUS_TYPE 0x7 78#define AR9300_OTP_STATUS_VALID 0x4 79#define AR9300_OTP_STATUS_ACCESS_BUSY 0x2 80#define AR9300_OTP_STATUS_SM_BUSY 0x1 81#define AR9300_OTP_READ_DATA \ 82 ((AR_SREV_9340(ah) || AR_SREV_9550(ah)) ? 0x3001c : 0x15f1c) 83 84enum targetPowerHTRates { 85 HT_TARGET_RATE_0_8_16, 86 HT_TARGET_RATE_1_3_9_11_17_19, 87 HT_TARGET_RATE_4, 88 HT_TARGET_RATE_5, 89 HT_TARGET_RATE_6, 90 HT_TARGET_RATE_7, 91 HT_TARGET_RATE_12, 92 HT_TARGET_RATE_13, 93 HT_TARGET_RATE_14, 94 HT_TARGET_RATE_15, 95 HT_TARGET_RATE_20, 96 HT_TARGET_RATE_21, 97 HT_TARGET_RATE_22, 98 HT_TARGET_RATE_23 99}; 100 101enum targetPowerLegacyRates { 102 LEGACY_TARGET_RATE_6_24, 103 LEGACY_TARGET_RATE_36, 104 LEGACY_TARGET_RATE_48, 105 LEGACY_TARGET_RATE_54 106}; 107 108enum targetPowerCckRates { 109 LEGACY_TARGET_RATE_1L_5L, 110 LEGACY_TARGET_RATE_5S, 111 LEGACY_TARGET_RATE_11L, 112 LEGACY_TARGET_RATE_11S 113}; 114 115enum ar9300_Rates { 116 ALL_TARGET_LEGACY_6_24, 117 ALL_TARGET_LEGACY_36, 118 ALL_TARGET_LEGACY_48, 119 ALL_TARGET_LEGACY_54, 120 ALL_TARGET_LEGACY_1L_5L, 121 ALL_TARGET_LEGACY_5S, 122 ALL_TARGET_LEGACY_11L, 123 ALL_TARGET_LEGACY_11S, 124 ALL_TARGET_HT20_0_8_16, 125 ALL_TARGET_HT20_1_3_9_11_17_19, 126 ALL_TARGET_HT20_4, 127 ALL_TARGET_HT20_5, 128 ALL_TARGET_HT20_6, 129 ALL_TARGET_HT20_7, 130 ALL_TARGET_HT20_12, 131 ALL_TARGET_HT20_13, 132 ALL_TARGET_HT20_14, 133 ALL_TARGET_HT20_15, 134 ALL_TARGET_HT20_20, 135 ALL_TARGET_HT20_21, 136 ALL_TARGET_HT20_22, 137 ALL_TARGET_HT20_23, 138 ALL_TARGET_HT40_0_8_16, 139 ALL_TARGET_HT40_1_3_9_11_17_19, 140 ALL_TARGET_HT40_4, 141 ALL_TARGET_HT40_5, 142 ALL_TARGET_HT40_6, 143 ALL_TARGET_HT40_7, 144 ALL_TARGET_HT40_12, 145 ALL_TARGET_HT40_13, 146 ALL_TARGET_HT40_14, 147 ALL_TARGET_HT40_15, 148 ALL_TARGET_HT40_20, 149 ALL_TARGET_HT40_21, 150 ALL_TARGET_HT40_22, 151 ALL_TARGET_HT40_23, 152 ar9300RateSize, 153}; 154 155 156struct eepFlags { 157 u8 opFlags; 158 u8 eepMisc; 159} __packed; 160 161enum CompressAlgorithm { 162 _CompressNone = 0, 163 _CompressLzma, 164 _CompressPairs, 165 _CompressBlock, 166 _Compress4, 167 _Compress5, 168 _Compress6, 169 _Compress7, 170}; 171 172struct ar9300_base_eep_hdr { 173 __le16 regDmn[2]; 174 /* 4 bits tx and 4 bits rx */ 175 u8 txrxMask; 176 struct eepFlags opCapFlags; 177 u8 rfSilent; 178 u8 blueToothOptions; 179 u8 deviceCap; 180 /* takes lower byte in eeprom location */ 181 u8 deviceType; 182 /* offset in dB to be added to beginning 183 * of pdadc table in calibration 184 */ 185 int8_t pwrTableOffset; 186 u8 params_for_tuning_caps[2]; 187 /* 188 * bit0 - enable tx temp comp 189 * bit1 - enable tx volt comp 190 * bit2 - enable fastClock - default to 1 191 * bit3 - enable doubling - default to 1 192 * bit4 - enable internal regulator - default to 1 193 */ 194 u8 featureEnable; 195 /* misc flags: bit0 - turn down drivestrength */ 196 u8 miscConfiguration; 197 u8 eepromWriteEnableGpio; 198 u8 wlanDisableGpio; 199 u8 wlanLedGpio; 200 u8 rxBandSelectGpio; 201 u8 txrxgain; 202 /* SW controlled internal regulator fields */ 203 __le32 swreg; 204} __packed; 205 206struct ar9300_modal_eep_header { 207 /* 4 idle, t1, t2, b (4 bits per setting) */ 208 __le32 antCtrlCommon; 209 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */ 210 __le32 antCtrlCommon2; 211 /* 6 idle, t, r, rx1, rx12, b (2 bits each) */ 212 __le16 antCtrlChain[AR9300_MAX_CHAINS]; 213 /* 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */ 214 u8 xatten1DB[AR9300_MAX_CHAINS]; 215 /* 3 xatten1_margin for merlin (0xa20c/b20c 16:12 */ 216 u8 xatten1Margin[AR9300_MAX_CHAINS]; 217 int8_t tempSlope; 218 int8_t voltSlope; 219 /* spur channels in usual fbin coding format */ 220 u8 spurChans[AR_EEPROM_MODAL_SPURS]; 221 /* 3 Check if the register is per chain */ 222 int8_t noiseFloorThreshCh[AR9300_MAX_CHAINS]; 223 u8 reserved[11]; 224 int8_t quick_drop; 225 u8 xpaBiasLvl; 226 u8 txFrameToDataStart; 227 u8 txFrameToPaOn; 228 u8 txClip; 229 int8_t antennaGain; 230 u8 switchSettling; 231 int8_t adcDesiredSize; 232 u8 txEndToXpaOff; 233 u8 txEndToRxOn; 234 u8 txFrameToXpaOn; 235 u8 thresh62; 236 __le32 papdRateMaskHt20; 237 __le32 papdRateMaskHt40; 238 __le16 switchcomspdt; 239 u8 xlna_bias_strength; 240 u8 futureModal[7]; 241} __packed; 242 243struct ar9300_cal_data_per_freq_op_loop { 244 int8_t refPower; 245 /* pdadc voltage at power measurement */ 246 u8 voltMeas; 247 /* pcdac used for power measurement */ 248 u8 tempMeas; 249 /* range is -60 to -127 create a mapping equation 1db resolution */ 250 int8_t rxNoisefloorCal; 251 /*range is same as noisefloor */ 252 int8_t rxNoisefloorPower; 253 /* temp measured when noisefloor cal was performed */ 254 u8 rxTempMeas; 255} __packed; 256 257struct cal_tgt_pow_legacy { 258 u8 tPow2x[4]; 259} __packed; 260 261struct cal_tgt_pow_ht { 262 u8 tPow2x[14]; 263} __packed; 264 265struct cal_ctl_data_2g { 266 u8 ctlEdges[AR9300_NUM_BAND_EDGES_2G]; 267} __packed; 268 269struct cal_ctl_data_5g { 270 u8 ctlEdges[AR9300_NUM_BAND_EDGES_5G]; 271} __packed; 272 273#define MAX_BASE_EXTENSION_FUTURE 2 274 275struct ar9300_BaseExtension_1 { 276 u8 ant_div_control; 277 u8 future[MAX_BASE_EXTENSION_FUTURE]; 278 /* 279 * misc_enable: 280 * 281 * BIT 0 - TX Gain Cap enable. 282 * BIT 1 - Uncompressed Checksum enable. 283 * BIT 2/3 - MinCCApwr enable 2g/5g. 284 */ 285 u8 misc_enable; 286 int8_t tempslopextension[8]; 287 int8_t quick_drop_low; 288 int8_t quick_drop_high; 289} __packed; 290 291struct ar9300_BaseExtension_2 { 292 int8_t tempSlopeLow; 293 int8_t tempSlopeHigh; 294 u8 xatten1DBLow[AR9300_MAX_CHAINS]; 295 u8 xatten1MarginLow[AR9300_MAX_CHAINS]; 296 u8 xatten1DBHigh[AR9300_MAX_CHAINS]; 297 u8 xatten1MarginHigh[AR9300_MAX_CHAINS]; 298} __packed; 299 300struct ar9300_eeprom { 301 u8 eepromVersion; 302 u8 templateVersion; 303 u8 macAddr[6]; 304 u8 custData[AR9300_CUSTOMER_DATA_SIZE]; 305 306 struct ar9300_base_eep_hdr baseEepHeader; 307 308 struct ar9300_modal_eep_header modalHeader2G; 309 struct ar9300_BaseExtension_1 base_ext1; 310 u8 calFreqPier2G[AR9300_NUM_2G_CAL_PIERS]; 311 struct ar9300_cal_data_per_freq_op_loop 312 calPierData2G[AR9300_MAX_CHAINS][AR9300_NUM_2G_CAL_PIERS]; 313 u8 calTarget_freqbin_Cck[AR9300_NUM_2G_CCK_TARGET_POWERS]; 314 u8 calTarget_freqbin_2G[AR9300_NUM_2G_20_TARGET_POWERS]; 315 u8 calTarget_freqbin_2GHT20[AR9300_NUM_2G_20_TARGET_POWERS]; 316 u8 calTarget_freqbin_2GHT40[AR9300_NUM_2G_40_TARGET_POWERS]; 317 struct cal_tgt_pow_legacy 318 calTargetPowerCck[AR9300_NUM_2G_CCK_TARGET_POWERS]; 319 struct cal_tgt_pow_legacy 320 calTargetPower2G[AR9300_NUM_2G_20_TARGET_POWERS]; 321 struct cal_tgt_pow_ht 322 calTargetPower2GHT20[AR9300_NUM_2G_20_TARGET_POWERS]; 323 struct cal_tgt_pow_ht 324 calTargetPower2GHT40[AR9300_NUM_2G_40_TARGET_POWERS]; 325 u8 ctlIndex_2G[AR9300_NUM_CTLS_2G]; 326 u8 ctl_freqbin_2G[AR9300_NUM_CTLS_2G][AR9300_NUM_BAND_EDGES_2G]; 327 struct cal_ctl_data_2g ctlPowerData_2G[AR9300_NUM_CTLS_2G]; 328 struct ar9300_modal_eep_header modalHeader5G; 329 struct ar9300_BaseExtension_2 base_ext2; 330 u8 calFreqPier5G[AR9300_NUM_5G_CAL_PIERS]; 331 struct ar9300_cal_data_per_freq_op_loop 332 calPierData5G[AR9300_MAX_CHAINS][AR9300_NUM_5G_CAL_PIERS]; 333 u8 calTarget_freqbin_5G[AR9300_NUM_5G_20_TARGET_POWERS]; 334 u8 calTarget_freqbin_5GHT20[AR9300_NUM_5G_20_TARGET_POWERS]; 335 u8 calTarget_freqbin_5GHT40[AR9300_NUM_5G_40_TARGET_POWERS]; 336 struct cal_tgt_pow_legacy 337 calTargetPower5G[AR9300_NUM_5G_20_TARGET_POWERS]; 338 struct cal_tgt_pow_ht 339 calTargetPower5GHT20[AR9300_NUM_5G_20_TARGET_POWERS]; 340 struct cal_tgt_pow_ht 341 calTargetPower5GHT40[AR9300_NUM_5G_40_TARGET_POWERS]; 342 u8 ctlIndex_5G[AR9300_NUM_CTLS_5G]; 343 u8 ctl_freqbin_5G[AR9300_NUM_CTLS_5G][AR9300_NUM_BAND_EDGES_5G]; 344 struct cal_ctl_data_5g ctlPowerData_5G[AR9300_NUM_CTLS_5G]; 345} __packed; 346 347s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah); 348s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah); 349u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, bool is2ghz); 350u32 ar9003_hw_ant_ctrl_common_2_get(struct ath_hw *ah, bool is2ghz); 351 352u8 *ar9003_get_spur_chan_ptr(struct ath_hw *ah, bool is_2ghz); 353 354unsigned int ar9003_get_paprd_scale_factor(struct ath_hw *ah, 355 struct ath9k_channel *chan); 356 357void ar9003_hw_internal_regulator_apply(struct ath_hw *ah); 358 359#endif 360