1/* 2 * Copyright (c) 2005-2011 Atheros Communications Inc. 3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18#include <linux/pci.h> 19#include <linux/module.h> 20#include <linux/interrupt.h> 21#include <linux/spinlock.h> 22#include <linux/bitops.h> 23 24#include "core.h" 25#include "debug.h" 26 27#include "targaddrs.h" 28#include "bmi.h" 29 30#include "hif.h" 31#include "htc.h" 32 33#include "ce.h" 34#include "pci.h" 35 36enum ath10k_pci_irq_mode { 37 ATH10K_PCI_IRQ_AUTO = 0, 38 ATH10K_PCI_IRQ_LEGACY = 1, 39 ATH10K_PCI_IRQ_MSI = 2, 40}; 41 42enum ath10k_pci_reset_mode { 43 ATH10K_PCI_RESET_AUTO = 0, 44 ATH10K_PCI_RESET_WARM_ONLY = 1, 45}; 46 47static unsigned int ath10k_pci_irq_mode = ATH10K_PCI_IRQ_AUTO; 48static unsigned int ath10k_pci_reset_mode = ATH10K_PCI_RESET_AUTO; 49 50module_param_named(irq_mode, ath10k_pci_irq_mode, uint, 0644); 51MODULE_PARM_DESC(irq_mode, "0: auto, 1: legacy, 2: msi (default: 0)"); 52 53module_param_named(reset_mode, ath10k_pci_reset_mode, uint, 0644); 54MODULE_PARM_DESC(reset_mode, "0: auto, 1: warm only (default: 0)"); 55 56/* how long wait to wait for target to initialise, in ms */ 57#define ATH10K_PCI_TARGET_WAIT 3000 58#define ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS 3 59 60#define QCA988X_2_0_DEVICE_ID (0x003c) 61#define QCA6174_2_1_DEVICE_ID (0x003e) 62 63static const struct pci_device_id ath10k_pci_id_table[] = { 64 { PCI_VDEVICE(ATHEROS, QCA988X_2_0_DEVICE_ID) }, /* PCI-E QCA988X V2 */ 65 { PCI_VDEVICE(ATHEROS, QCA6174_2_1_DEVICE_ID) }, /* PCI-E QCA6174 V2.1 */ 66 {0} 67}; 68 69static const struct ath10k_pci_supp_chip ath10k_pci_supp_chips[] = { 70 /* QCA988X pre 2.0 chips are not supported because they need some nasty 71 * hacks. ath10k doesn't have them and these devices crash horribly 72 * because of that. 73 */ 74 { QCA988X_2_0_DEVICE_ID, QCA988X_HW_2_0_CHIP_ID_REV }, 75 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_2_1_CHIP_ID_REV }, 76 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_2_2_CHIP_ID_REV }, 77 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_0_CHIP_ID_REV }, 78 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_1_CHIP_ID_REV }, 79 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_2_CHIP_ID_REV }, 80}; 81 82static void ath10k_pci_buffer_cleanup(struct ath10k *ar); 83static int ath10k_pci_cold_reset(struct ath10k *ar); 84static int ath10k_pci_warm_reset(struct ath10k *ar); 85static int ath10k_pci_wait_for_target_init(struct ath10k *ar); 86static int ath10k_pci_init_irq(struct ath10k *ar); 87static int ath10k_pci_deinit_irq(struct ath10k *ar); 88static int ath10k_pci_request_irq(struct ath10k *ar); 89static void ath10k_pci_free_irq(struct ath10k *ar); 90static int ath10k_pci_bmi_wait(struct ath10k_ce_pipe *tx_pipe, 91 struct ath10k_ce_pipe *rx_pipe, 92 struct bmi_xfer *xfer); 93 94static const struct ce_attr host_ce_config_wlan[] = { 95 /* CE0: host->target HTC control and raw streams */ 96 { 97 .flags = CE_ATTR_FLAGS, 98 .src_nentries = 16, 99 .src_sz_max = 256, 100 .dest_nentries = 0, 101 }, 102 103 /* CE1: target->host HTT + HTC control */ 104 { 105 .flags = CE_ATTR_FLAGS, 106 .src_nentries = 0, 107 .src_sz_max = 2048, 108 .dest_nentries = 512, 109 }, 110 111 /* CE2: target->host WMI */ 112 { 113 .flags = CE_ATTR_FLAGS, 114 .src_nentries = 0, 115 .src_sz_max = 2048, 116 .dest_nentries = 32, 117 }, 118 119 /* CE3: host->target WMI */ 120 { 121 .flags = CE_ATTR_FLAGS, 122 .src_nentries = 32, 123 .src_sz_max = 2048, 124 .dest_nentries = 0, 125 }, 126 127 /* CE4: host->target HTT */ 128 { 129 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR, 130 .src_nentries = CE_HTT_H2T_MSG_SRC_NENTRIES, 131 .src_sz_max = 256, 132 .dest_nentries = 0, 133 }, 134 135 /* CE5: unused */ 136 { 137 .flags = CE_ATTR_FLAGS, 138 .src_nentries = 0, 139 .src_sz_max = 0, 140 .dest_nentries = 0, 141 }, 142 143 /* CE6: target autonomous hif_memcpy */ 144 { 145 .flags = CE_ATTR_FLAGS, 146 .src_nentries = 0, 147 .src_sz_max = 0, 148 .dest_nentries = 0, 149 }, 150 151 /* CE7: ce_diag, the Diagnostic Window */ 152 { 153 .flags = CE_ATTR_FLAGS, 154 .src_nentries = 2, 155 .src_sz_max = DIAG_TRANSFER_LIMIT, 156 .dest_nentries = 2, 157 }, 158}; 159 160/* Target firmware's Copy Engine configuration. */ 161static const struct ce_pipe_config target_ce_config_wlan[] = { 162 /* CE0: host->target HTC control and raw streams */ 163 { 164 .pipenum = __cpu_to_le32(0), 165 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 166 .nentries = __cpu_to_le32(32), 167 .nbytes_max = __cpu_to_le32(256), 168 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 169 .reserved = __cpu_to_le32(0), 170 }, 171 172 /* CE1: target->host HTT + HTC control */ 173 { 174 .pipenum = __cpu_to_le32(1), 175 .pipedir = __cpu_to_le32(PIPEDIR_IN), 176 .nentries = __cpu_to_le32(32), 177 .nbytes_max = __cpu_to_le32(2048), 178 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 179 .reserved = __cpu_to_le32(0), 180 }, 181 182 /* CE2: target->host WMI */ 183 { 184 .pipenum = __cpu_to_le32(2), 185 .pipedir = __cpu_to_le32(PIPEDIR_IN), 186 .nentries = __cpu_to_le32(32), 187 .nbytes_max = __cpu_to_le32(2048), 188 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 189 .reserved = __cpu_to_le32(0), 190 }, 191 192 /* CE3: host->target WMI */ 193 { 194 .pipenum = __cpu_to_le32(3), 195 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 196 .nentries = __cpu_to_le32(32), 197 .nbytes_max = __cpu_to_le32(2048), 198 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 199 .reserved = __cpu_to_le32(0), 200 }, 201 202 /* CE4: host->target HTT */ 203 { 204 .pipenum = __cpu_to_le32(4), 205 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 206 .nentries = __cpu_to_le32(256), 207 .nbytes_max = __cpu_to_le32(256), 208 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 209 .reserved = __cpu_to_le32(0), 210 }, 211 212 /* NB: 50% of src nentries, since tx has 2 frags */ 213 214 /* CE5: unused */ 215 { 216 .pipenum = __cpu_to_le32(5), 217 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 218 .nentries = __cpu_to_le32(32), 219 .nbytes_max = __cpu_to_le32(2048), 220 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 221 .reserved = __cpu_to_le32(0), 222 }, 223 224 /* CE6: Reserved for target autonomous hif_memcpy */ 225 { 226 .pipenum = __cpu_to_le32(6), 227 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 228 .nentries = __cpu_to_le32(32), 229 .nbytes_max = __cpu_to_le32(4096), 230 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 231 .reserved = __cpu_to_le32(0), 232 }, 233 234 /* CE7 used only by Host */ 235}; 236 237/* 238 * Map from service/endpoint to Copy Engine. 239 * This table is derived from the CE_PCI TABLE, above. 240 * It is passed to the Target at startup for use by firmware. 241 */ 242static const struct service_to_pipe target_service_to_ce_map_wlan[] = { 243 { 244 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO), 245 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 246 __cpu_to_le32(3), 247 }, 248 { 249 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO), 250 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 251 __cpu_to_le32(2), 252 }, 253 { 254 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK), 255 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 256 __cpu_to_le32(3), 257 }, 258 { 259 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK), 260 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 261 __cpu_to_le32(2), 262 }, 263 { 264 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE), 265 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 266 __cpu_to_le32(3), 267 }, 268 { 269 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE), 270 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 271 __cpu_to_le32(2), 272 }, 273 { 274 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI), 275 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 276 __cpu_to_le32(3), 277 }, 278 { 279 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI), 280 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 281 __cpu_to_le32(2), 282 }, 283 { 284 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL), 285 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 286 __cpu_to_le32(3), 287 }, 288 { 289 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL), 290 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 291 __cpu_to_le32(2), 292 }, 293 { 294 __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL), 295 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 296 __cpu_to_le32(0), 297 }, 298 { 299 __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL), 300 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 301 __cpu_to_le32(1), 302 }, 303 { /* not used */ 304 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS), 305 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 306 __cpu_to_le32(0), 307 }, 308 { /* not used */ 309 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS), 310 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 311 __cpu_to_le32(1), 312 }, 313 { 314 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG), 315 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 316 __cpu_to_le32(4), 317 }, 318 { 319 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG), 320 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 321 __cpu_to_le32(1), 322 }, 323 324 /* (Additions here) */ 325 326 { /* must be last */ 327 __cpu_to_le32(0), 328 __cpu_to_le32(0), 329 __cpu_to_le32(0), 330 }, 331}; 332 333static bool ath10k_pci_irq_pending(struct ath10k *ar) 334{ 335 u32 cause; 336 337 /* Check if the shared legacy irq is for us */ 338 cause = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + 339 PCIE_INTR_CAUSE_ADDRESS); 340 if (cause & (PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL)) 341 return true; 342 343 return false; 344} 345 346static void ath10k_pci_disable_and_clear_legacy_irq(struct ath10k *ar) 347{ 348 /* IMPORTANT: INTR_CLR register has to be set after 349 * INTR_ENABLE is set to 0, otherwise interrupt can not be 350 * really cleared. */ 351 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS, 352 0); 353 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_CLR_ADDRESS, 354 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL); 355 356 /* IMPORTANT: this extra read transaction is required to 357 * flush the posted write buffer. */ 358 (void)ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + 359 PCIE_INTR_ENABLE_ADDRESS); 360} 361 362static void ath10k_pci_enable_legacy_irq(struct ath10k *ar) 363{ 364 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + 365 PCIE_INTR_ENABLE_ADDRESS, 366 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL); 367 368 /* IMPORTANT: this extra read transaction is required to 369 * flush the posted write buffer. */ 370 (void)ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + 371 PCIE_INTR_ENABLE_ADDRESS); 372} 373 374static inline const char *ath10k_pci_get_irq_method(struct ath10k *ar) 375{ 376 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 377 378 if (ar_pci->num_msi_intrs > 1) 379 return "msi-x"; 380 381 if (ar_pci->num_msi_intrs == 1) 382 return "msi"; 383 384 return "legacy"; 385} 386 387static int __ath10k_pci_rx_post_buf(struct ath10k_pci_pipe *pipe) 388{ 389 struct ath10k *ar = pipe->hif_ce_state; 390 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 391 struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl; 392 struct sk_buff *skb; 393 dma_addr_t paddr; 394 int ret; 395 396 lockdep_assert_held(&ar_pci->ce_lock); 397 398 skb = dev_alloc_skb(pipe->buf_sz); 399 if (!skb) 400 return -ENOMEM; 401 402 WARN_ONCE((unsigned long)skb->data & 3, "unaligned skb"); 403 404 paddr = dma_map_single(ar->dev, skb->data, 405 skb->len + skb_tailroom(skb), 406 DMA_FROM_DEVICE); 407 if (unlikely(dma_mapping_error(ar->dev, paddr))) { 408 ath10k_warn(ar, "failed to dma map pci rx buf\n"); 409 dev_kfree_skb_any(skb); 410 return -EIO; 411 } 412 413 ATH10K_SKB_RXCB(skb)->paddr = paddr; 414 415 ret = __ath10k_ce_rx_post_buf(ce_pipe, skb, paddr); 416 if (ret) { 417 ath10k_warn(ar, "failed to post pci rx buf: %d\n", ret); 418 dma_unmap_single(ar->dev, paddr, skb->len + skb_tailroom(skb), 419 DMA_FROM_DEVICE); 420 dev_kfree_skb_any(skb); 421 return ret; 422 } 423 424 return 0; 425} 426 427static void __ath10k_pci_rx_post_pipe(struct ath10k_pci_pipe *pipe) 428{ 429 struct ath10k *ar = pipe->hif_ce_state; 430 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 431 struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl; 432 int ret, num; 433 434 lockdep_assert_held(&ar_pci->ce_lock); 435 436 if (pipe->buf_sz == 0) 437 return; 438 439 if (!ce_pipe->dest_ring) 440 return; 441 442 num = __ath10k_ce_rx_num_free_bufs(ce_pipe); 443 while (num--) { 444 ret = __ath10k_pci_rx_post_buf(pipe); 445 if (ret) { 446 ath10k_warn(ar, "failed to post pci rx buf: %d\n", ret); 447 mod_timer(&ar_pci->rx_post_retry, jiffies + 448 ATH10K_PCI_RX_POST_RETRY_MS); 449 break; 450 } 451 } 452} 453 454static void ath10k_pci_rx_post_pipe(struct ath10k_pci_pipe *pipe) 455{ 456 struct ath10k *ar = pipe->hif_ce_state; 457 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 458 459 spin_lock_bh(&ar_pci->ce_lock); 460 __ath10k_pci_rx_post_pipe(pipe); 461 spin_unlock_bh(&ar_pci->ce_lock); 462} 463 464static void ath10k_pci_rx_post(struct ath10k *ar) 465{ 466 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 467 int i; 468 469 spin_lock_bh(&ar_pci->ce_lock); 470 for (i = 0; i < CE_COUNT; i++) 471 __ath10k_pci_rx_post_pipe(&ar_pci->pipe_info[i]); 472 spin_unlock_bh(&ar_pci->ce_lock); 473} 474 475static void ath10k_pci_rx_replenish_retry(unsigned long ptr) 476{ 477 struct ath10k *ar = (void *)ptr; 478 479 ath10k_pci_rx_post(ar); 480} 481 482/* 483 * Diagnostic read/write access is provided for startup/config/debug usage. 484 * Caller must guarantee proper alignment, when applicable, and single user 485 * at any moment. 486 */ 487static int ath10k_pci_diag_read_mem(struct ath10k *ar, u32 address, void *data, 488 int nbytes) 489{ 490 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 491 int ret = 0; 492 u32 buf; 493 unsigned int completed_nbytes, orig_nbytes, remaining_bytes; 494 unsigned int id; 495 unsigned int flags; 496 struct ath10k_ce_pipe *ce_diag; 497 /* Host buffer address in CE space */ 498 u32 ce_data; 499 dma_addr_t ce_data_base = 0; 500 void *data_buf = NULL; 501 int i; 502 503 spin_lock_bh(&ar_pci->ce_lock); 504 505 ce_diag = ar_pci->ce_diag; 506 507 /* 508 * Allocate a temporary bounce buffer to hold caller's data 509 * to be DMA'ed from Target. This guarantees 510 * 1) 4-byte alignment 511 * 2) Buffer in DMA-able space 512 */ 513 orig_nbytes = nbytes; 514 data_buf = (unsigned char *)dma_alloc_coherent(ar->dev, 515 orig_nbytes, 516 &ce_data_base, 517 GFP_ATOMIC); 518 519 if (!data_buf) { 520 ret = -ENOMEM; 521 goto done; 522 } 523 memset(data_buf, 0, orig_nbytes); 524 525 remaining_bytes = orig_nbytes; 526 ce_data = ce_data_base; 527 while (remaining_bytes) { 528 nbytes = min_t(unsigned int, remaining_bytes, 529 DIAG_TRANSFER_LIMIT); 530 531 ret = __ath10k_ce_rx_post_buf(ce_diag, NULL, ce_data); 532 if (ret != 0) 533 goto done; 534 535 /* Request CE to send from Target(!) address to Host buffer */ 536 /* 537 * The address supplied by the caller is in the 538 * Target CPU virtual address space. 539 * 540 * In order to use this address with the diagnostic CE, 541 * convert it from Target CPU virtual address space 542 * to CE address space 543 */ 544 address = TARG_CPU_SPACE_TO_CE_SPACE(ar, ar_pci->mem, 545 address); 546 547 ret = ath10k_ce_send_nolock(ce_diag, NULL, (u32)address, nbytes, 0, 548 0); 549 if (ret) 550 goto done; 551 552 i = 0; 553 while (ath10k_ce_completed_send_next_nolock(ce_diag, NULL, &buf, 554 &completed_nbytes, 555 &id) != 0) { 556 mdelay(1); 557 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) { 558 ret = -EBUSY; 559 goto done; 560 } 561 } 562 563 if (nbytes != completed_nbytes) { 564 ret = -EIO; 565 goto done; 566 } 567 568 if (buf != (u32)address) { 569 ret = -EIO; 570 goto done; 571 } 572 573 i = 0; 574 while (ath10k_ce_completed_recv_next_nolock(ce_diag, NULL, &buf, 575 &completed_nbytes, 576 &id, &flags) != 0) { 577 mdelay(1); 578 579 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) { 580 ret = -EBUSY; 581 goto done; 582 } 583 } 584 585 if (nbytes != completed_nbytes) { 586 ret = -EIO; 587 goto done; 588 } 589 590 if (buf != ce_data) { 591 ret = -EIO; 592 goto done; 593 } 594 595 remaining_bytes -= nbytes; 596 address += nbytes; 597 ce_data += nbytes; 598 } 599 600done: 601 if (ret == 0) 602 memcpy(data, data_buf, orig_nbytes); 603 else 604 ath10k_warn(ar, "failed to read diag value at 0x%x: %d\n", 605 address, ret); 606 607 if (data_buf) 608 dma_free_coherent(ar->dev, orig_nbytes, data_buf, 609 ce_data_base); 610 611 spin_unlock_bh(&ar_pci->ce_lock); 612 613 return ret; 614} 615 616static int ath10k_pci_diag_read32(struct ath10k *ar, u32 address, u32 *value) 617{ 618 __le32 val = 0; 619 int ret; 620 621 ret = ath10k_pci_diag_read_mem(ar, address, &val, sizeof(val)); 622 *value = __le32_to_cpu(val); 623 624 return ret; 625} 626 627static int __ath10k_pci_diag_read_hi(struct ath10k *ar, void *dest, 628 u32 src, u32 len) 629{ 630 u32 host_addr, addr; 631 int ret; 632 633 host_addr = host_interest_item_address(src); 634 635 ret = ath10k_pci_diag_read32(ar, host_addr, &addr); 636 if (ret != 0) { 637 ath10k_warn(ar, "failed to get memcpy hi address for firmware address %d: %d\n", 638 src, ret); 639 return ret; 640 } 641 642 ret = ath10k_pci_diag_read_mem(ar, addr, dest, len); 643 if (ret != 0) { 644 ath10k_warn(ar, "failed to memcpy firmware memory from %d (%d B): %d\n", 645 addr, len, ret); 646 return ret; 647 } 648 649 return 0; 650} 651 652#define ath10k_pci_diag_read_hi(ar, dest, src, len) \ 653 __ath10k_pci_diag_read_hi(ar, dest, HI_ITEM(src), len) 654 655static int ath10k_pci_diag_write_mem(struct ath10k *ar, u32 address, 656 const void *data, int nbytes) 657{ 658 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 659 int ret = 0; 660 u32 buf; 661 unsigned int completed_nbytes, orig_nbytes, remaining_bytes; 662 unsigned int id; 663 unsigned int flags; 664 struct ath10k_ce_pipe *ce_diag; 665 void *data_buf = NULL; 666 u32 ce_data; /* Host buffer address in CE space */ 667 dma_addr_t ce_data_base = 0; 668 int i; 669 670 spin_lock_bh(&ar_pci->ce_lock); 671 672 ce_diag = ar_pci->ce_diag; 673 674 /* 675 * Allocate a temporary bounce buffer to hold caller's data 676 * to be DMA'ed to Target. This guarantees 677 * 1) 4-byte alignment 678 * 2) Buffer in DMA-able space 679 */ 680 orig_nbytes = nbytes; 681 data_buf = (unsigned char *)dma_alloc_coherent(ar->dev, 682 orig_nbytes, 683 &ce_data_base, 684 GFP_ATOMIC); 685 if (!data_buf) { 686 ret = -ENOMEM; 687 goto done; 688 } 689 690 /* Copy caller's data to allocated DMA buf */ 691 memcpy(data_buf, data, orig_nbytes); 692 693 /* 694 * The address supplied by the caller is in the 695 * Target CPU virtual address space. 696 * 697 * In order to use this address with the diagnostic CE, 698 * convert it from 699 * Target CPU virtual address space 700 * to 701 * CE address space 702 */ 703 address = TARG_CPU_SPACE_TO_CE_SPACE(ar, ar_pci->mem, address); 704 705 remaining_bytes = orig_nbytes; 706 ce_data = ce_data_base; 707 while (remaining_bytes) { 708 /* FIXME: check cast */ 709 nbytes = min_t(int, remaining_bytes, DIAG_TRANSFER_LIMIT); 710 711 /* Set up to receive directly into Target(!) address */ 712 ret = __ath10k_ce_rx_post_buf(ce_diag, NULL, address); 713 if (ret != 0) 714 goto done; 715 716 /* 717 * Request CE to send caller-supplied data that 718 * was copied to bounce buffer to Target(!) address. 719 */ 720 ret = ath10k_ce_send_nolock(ce_diag, NULL, (u32)ce_data, 721 nbytes, 0, 0); 722 if (ret != 0) 723 goto done; 724 725 i = 0; 726 while (ath10k_ce_completed_send_next_nolock(ce_diag, NULL, &buf, 727 &completed_nbytes, 728 &id) != 0) { 729 mdelay(1); 730 731 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) { 732 ret = -EBUSY; 733 goto done; 734 } 735 } 736 737 if (nbytes != completed_nbytes) { 738 ret = -EIO; 739 goto done; 740 } 741 742 if (buf != ce_data) { 743 ret = -EIO; 744 goto done; 745 } 746 747 i = 0; 748 while (ath10k_ce_completed_recv_next_nolock(ce_diag, NULL, &buf, 749 &completed_nbytes, 750 &id, &flags) != 0) { 751 mdelay(1); 752 753 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) { 754 ret = -EBUSY; 755 goto done; 756 } 757 } 758 759 if (nbytes != completed_nbytes) { 760 ret = -EIO; 761 goto done; 762 } 763 764 if (buf != address) { 765 ret = -EIO; 766 goto done; 767 } 768 769 remaining_bytes -= nbytes; 770 address += nbytes; 771 ce_data += nbytes; 772 } 773 774done: 775 if (data_buf) { 776 dma_free_coherent(ar->dev, orig_nbytes, data_buf, 777 ce_data_base); 778 } 779 780 if (ret != 0) 781 ath10k_warn(ar, "failed to write diag value at 0x%x: %d\n", 782 address, ret); 783 784 spin_unlock_bh(&ar_pci->ce_lock); 785 786 return ret; 787} 788 789static int ath10k_pci_diag_write32(struct ath10k *ar, u32 address, u32 value) 790{ 791 __le32 val = __cpu_to_le32(value); 792 793 return ath10k_pci_diag_write_mem(ar, address, &val, sizeof(val)); 794} 795 796static bool ath10k_pci_is_awake(struct ath10k *ar) 797{ 798 u32 val = ath10k_pci_reg_read32(ar, RTC_STATE_ADDRESS); 799 800 return RTC_STATE_V_GET(val) == RTC_STATE_V_ON; 801} 802 803static int ath10k_pci_wake_wait(struct ath10k *ar) 804{ 805 int tot_delay = 0; 806 int curr_delay = 5; 807 808 while (tot_delay < PCIE_WAKE_TIMEOUT) { 809 if (ath10k_pci_is_awake(ar)) 810 return 0; 811 812 udelay(curr_delay); 813 tot_delay += curr_delay; 814 815 if (curr_delay < 50) 816 curr_delay += 5; 817 } 818 819 return -ETIMEDOUT; 820} 821 822static int ath10k_pci_wake(struct ath10k *ar) 823{ 824 ath10k_pci_reg_write32(ar, PCIE_SOC_WAKE_ADDRESS, 825 PCIE_SOC_WAKE_V_MASK); 826 return ath10k_pci_wake_wait(ar); 827} 828 829static void ath10k_pci_sleep(struct ath10k *ar) 830{ 831 ath10k_pci_reg_write32(ar, PCIE_SOC_WAKE_ADDRESS, 832 PCIE_SOC_WAKE_RESET); 833} 834 835/* Called by lower (CE) layer when a send to Target completes. */ 836static void ath10k_pci_ce_send_done(struct ath10k_ce_pipe *ce_state) 837{ 838 struct ath10k *ar = ce_state->ar; 839 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 840 struct ath10k_hif_cb *cb = &ar_pci->msg_callbacks_current; 841 struct sk_buff_head list; 842 struct sk_buff *skb; 843 u32 ce_data; 844 unsigned int nbytes; 845 unsigned int transfer_id; 846 847 __skb_queue_head_init(&list); 848 while (ath10k_ce_completed_send_next(ce_state, (void **)&skb, &ce_data, 849 &nbytes, &transfer_id) == 0) { 850 /* no need to call tx completion for NULL pointers */ 851 if (skb == NULL) 852 continue; 853 854 __skb_queue_tail(&list, skb); 855 } 856 857 while ((skb = __skb_dequeue(&list))) 858 cb->tx_completion(ar, skb); 859} 860 861/* Called by lower (CE) layer when data is received from the Target. */ 862static void ath10k_pci_ce_recv_data(struct ath10k_ce_pipe *ce_state) 863{ 864 struct ath10k *ar = ce_state->ar; 865 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 866 struct ath10k_pci_pipe *pipe_info = &ar_pci->pipe_info[ce_state->id]; 867 struct ath10k_hif_cb *cb = &ar_pci->msg_callbacks_current; 868 struct sk_buff *skb; 869 struct sk_buff_head list; 870 void *transfer_context; 871 u32 ce_data; 872 unsigned int nbytes, max_nbytes; 873 unsigned int transfer_id; 874 unsigned int flags; 875 876 __skb_queue_head_init(&list); 877 while (ath10k_ce_completed_recv_next(ce_state, &transfer_context, 878 &ce_data, &nbytes, &transfer_id, 879 &flags) == 0) { 880 skb = transfer_context; 881 max_nbytes = skb->len + skb_tailroom(skb); 882 dma_unmap_single(ar->dev, ATH10K_SKB_RXCB(skb)->paddr, 883 max_nbytes, DMA_FROM_DEVICE); 884 885 if (unlikely(max_nbytes < nbytes)) { 886 ath10k_warn(ar, "rxed more than expected (nbytes %d, max %d)", 887 nbytes, max_nbytes); 888 dev_kfree_skb_any(skb); 889 continue; 890 } 891 892 skb_put(skb, nbytes); 893 __skb_queue_tail(&list, skb); 894 } 895 896 while ((skb = __skb_dequeue(&list))) { 897 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci rx ce pipe %d len %d\n", 898 ce_state->id, skb->len); 899 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci rx: ", 900 skb->data, skb->len); 901 902 cb->rx_completion(ar, skb); 903 } 904 905 ath10k_pci_rx_post_pipe(pipe_info); 906} 907 908static int ath10k_pci_hif_tx_sg(struct ath10k *ar, u8 pipe_id, 909 struct ath10k_hif_sg_item *items, int n_items) 910{ 911 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 912 struct ath10k_pci_pipe *pci_pipe = &ar_pci->pipe_info[pipe_id]; 913 struct ath10k_ce_pipe *ce_pipe = pci_pipe->ce_hdl; 914 struct ath10k_ce_ring *src_ring = ce_pipe->src_ring; 915 unsigned int nentries_mask; 916 unsigned int sw_index; 917 unsigned int write_index; 918 int err, i = 0; 919 920 spin_lock_bh(&ar_pci->ce_lock); 921 922 nentries_mask = src_ring->nentries_mask; 923 sw_index = src_ring->sw_index; 924 write_index = src_ring->write_index; 925 926 if (unlikely(CE_RING_DELTA(nentries_mask, 927 write_index, sw_index - 1) < n_items)) { 928 err = -ENOBUFS; 929 goto err; 930 } 931 932 for (i = 0; i < n_items - 1; i++) { 933 ath10k_dbg(ar, ATH10K_DBG_PCI, 934 "pci tx item %d paddr 0x%08x len %d n_items %d\n", 935 i, items[i].paddr, items[i].len, n_items); 936 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci tx data: ", 937 items[i].vaddr, items[i].len); 938 939 err = ath10k_ce_send_nolock(ce_pipe, 940 items[i].transfer_context, 941 items[i].paddr, 942 items[i].len, 943 items[i].transfer_id, 944 CE_SEND_FLAG_GATHER); 945 if (err) 946 goto err; 947 } 948 949 /* `i` is equal to `n_items -1` after for() */ 950 951 ath10k_dbg(ar, ATH10K_DBG_PCI, 952 "pci tx item %d paddr 0x%08x len %d n_items %d\n", 953 i, items[i].paddr, items[i].len, n_items); 954 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci tx data: ", 955 items[i].vaddr, items[i].len); 956 957 err = ath10k_ce_send_nolock(ce_pipe, 958 items[i].transfer_context, 959 items[i].paddr, 960 items[i].len, 961 items[i].transfer_id, 962 0); 963 if (err) 964 goto err; 965 966 spin_unlock_bh(&ar_pci->ce_lock); 967 return 0; 968 969err: 970 for (; i > 0; i--) 971 __ath10k_ce_send_revert(ce_pipe); 972 973 spin_unlock_bh(&ar_pci->ce_lock); 974 return err; 975} 976 977static int ath10k_pci_hif_diag_read(struct ath10k *ar, u32 address, void *buf, 978 size_t buf_len) 979{ 980 return ath10k_pci_diag_read_mem(ar, address, buf, buf_len); 981} 982 983static u16 ath10k_pci_hif_get_free_queue_number(struct ath10k *ar, u8 pipe) 984{ 985 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 986 987 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif get free queue number\n"); 988 989 return ath10k_ce_num_free_src_entries(ar_pci->pipe_info[pipe].ce_hdl); 990} 991 992static void ath10k_pci_dump_registers(struct ath10k *ar, 993 struct ath10k_fw_crash_data *crash_data) 994{ 995 __le32 reg_dump_values[REG_DUMP_COUNT_QCA988X] = {}; 996 int i, ret; 997 998 lockdep_assert_held(&ar->data_lock); 999 1000 ret = ath10k_pci_diag_read_hi(ar, ®_dump_values[0], 1001 hi_failure_state, 1002 REG_DUMP_COUNT_QCA988X * sizeof(__le32)); 1003 if (ret) { 1004 ath10k_err(ar, "failed to read firmware dump area: %d\n", ret); 1005 return; 1006 } 1007 1008 BUILD_BUG_ON(REG_DUMP_COUNT_QCA988X % 4); 1009 1010 ath10k_err(ar, "firmware register dump:\n"); 1011 for (i = 0; i < REG_DUMP_COUNT_QCA988X; i += 4) 1012 ath10k_err(ar, "[%02d]: 0x%08X 0x%08X 0x%08X 0x%08X\n", 1013 i, 1014 __le32_to_cpu(reg_dump_values[i]), 1015 __le32_to_cpu(reg_dump_values[i + 1]), 1016 __le32_to_cpu(reg_dump_values[i + 2]), 1017 __le32_to_cpu(reg_dump_values[i + 3])); 1018 1019 if (!crash_data) 1020 return; 1021 1022 for (i = 0; i < REG_DUMP_COUNT_QCA988X; i++) 1023 crash_data->registers[i] = reg_dump_values[i]; 1024} 1025 1026static void ath10k_pci_fw_crashed_dump(struct ath10k *ar) 1027{ 1028 struct ath10k_fw_crash_data *crash_data; 1029 char uuid[50]; 1030 1031 spin_lock_bh(&ar->data_lock); 1032 1033 ar->stats.fw_crash_counter++; 1034 1035 crash_data = ath10k_debug_get_new_fw_crash_data(ar); 1036 1037 if (crash_data) 1038 scnprintf(uuid, sizeof(uuid), "%pUl", &crash_data->uuid); 1039 else 1040 scnprintf(uuid, sizeof(uuid), "n/a"); 1041 1042 ath10k_err(ar, "firmware crashed! (uuid %s)\n", uuid); 1043 ath10k_print_driver_info(ar); 1044 ath10k_pci_dump_registers(ar, crash_data); 1045 1046 spin_unlock_bh(&ar->data_lock); 1047 1048 queue_work(ar->workqueue, &ar->restart_work); 1049} 1050 1051static void ath10k_pci_hif_send_complete_check(struct ath10k *ar, u8 pipe, 1052 int force) 1053{ 1054 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif send complete check\n"); 1055 1056 if (!force) { 1057 int resources; 1058 /* 1059 * Decide whether to actually poll for completions, or just 1060 * wait for a later chance. 1061 * If there seem to be plenty of resources left, then just wait 1062 * since checking involves reading a CE register, which is a 1063 * relatively expensive operation. 1064 */ 1065 resources = ath10k_pci_hif_get_free_queue_number(ar, pipe); 1066 1067 /* 1068 * If at least 50% of the total resources are still available, 1069 * don't bother checking again yet. 1070 */ 1071 if (resources > (host_ce_config_wlan[pipe].src_nentries >> 1)) 1072 return; 1073 } 1074 ath10k_ce_per_engine_service(ar, pipe); 1075} 1076 1077static void ath10k_pci_hif_set_callbacks(struct ath10k *ar, 1078 struct ath10k_hif_cb *callbacks) 1079{ 1080 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1081 1082 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif set callbacks\n"); 1083 1084 memcpy(&ar_pci->msg_callbacks_current, callbacks, 1085 sizeof(ar_pci->msg_callbacks_current)); 1086} 1087 1088static void ath10k_pci_kill_tasklet(struct ath10k *ar) 1089{ 1090 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1091 int i; 1092 1093 tasklet_kill(&ar_pci->intr_tq); 1094 tasklet_kill(&ar_pci->msi_fw_err); 1095 1096 for (i = 0; i < CE_COUNT; i++) 1097 tasklet_kill(&ar_pci->pipe_info[i].intr); 1098 1099 del_timer_sync(&ar_pci->rx_post_retry); 1100} 1101 1102static int ath10k_pci_hif_map_service_to_pipe(struct ath10k *ar, 1103 u16 service_id, u8 *ul_pipe, 1104 u8 *dl_pipe, int *ul_is_polled, 1105 int *dl_is_polled) 1106{ 1107 const struct service_to_pipe *entry; 1108 bool ul_set = false, dl_set = false; 1109 int i; 1110 1111 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif map service\n"); 1112 1113 /* polling for received messages not supported */ 1114 *dl_is_polled = 0; 1115 1116 for (i = 0; i < ARRAY_SIZE(target_service_to_ce_map_wlan); i++) { 1117 entry = &target_service_to_ce_map_wlan[i]; 1118 1119 if (__le32_to_cpu(entry->service_id) != service_id) 1120 continue; 1121 1122 switch (__le32_to_cpu(entry->pipedir)) { 1123 case PIPEDIR_NONE: 1124 break; 1125 case PIPEDIR_IN: 1126 WARN_ON(dl_set); 1127 *dl_pipe = __le32_to_cpu(entry->pipenum); 1128 dl_set = true; 1129 break; 1130 case PIPEDIR_OUT: 1131 WARN_ON(ul_set); 1132 *ul_pipe = __le32_to_cpu(entry->pipenum); 1133 ul_set = true; 1134 break; 1135 case PIPEDIR_INOUT: 1136 WARN_ON(dl_set); 1137 WARN_ON(ul_set); 1138 *dl_pipe = __le32_to_cpu(entry->pipenum); 1139 *ul_pipe = __le32_to_cpu(entry->pipenum); 1140 dl_set = true; 1141 ul_set = true; 1142 break; 1143 } 1144 } 1145 1146 if (WARN_ON(!ul_set || !dl_set)) 1147 return -ENOENT; 1148 1149 *ul_is_polled = 1150 (host_ce_config_wlan[*ul_pipe].flags & CE_ATTR_DIS_INTR) != 0; 1151 1152 return 0; 1153} 1154 1155static void ath10k_pci_hif_get_default_pipe(struct ath10k *ar, 1156 u8 *ul_pipe, u8 *dl_pipe) 1157{ 1158 int ul_is_polled, dl_is_polled; 1159 1160 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif get default pipe\n"); 1161 1162 (void)ath10k_pci_hif_map_service_to_pipe(ar, 1163 ATH10K_HTC_SVC_ID_RSVD_CTRL, 1164 ul_pipe, 1165 dl_pipe, 1166 &ul_is_polled, 1167 &dl_is_polled); 1168} 1169 1170static void ath10k_pci_irq_msi_fw_mask(struct ath10k *ar) 1171{ 1172 u32 val; 1173 1174 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + CORE_CTRL_ADDRESS); 1175 val &= ~CORE_CTRL_PCIE_REG_31_MASK; 1176 1177 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + CORE_CTRL_ADDRESS, val); 1178} 1179 1180static void ath10k_pci_irq_msi_fw_unmask(struct ath10k *ar) 1181{ 1182 u32 val; 1183 1184 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + CORE_CTRL_ADDRESS); 1185 val |= CORE_CTRL_PCIE_REG_31_MASK; 1186 1187 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + CORE_CTRL_ADDRESS, val); 1188} 1189 1190static void ath10k_pci_irq_disable(struct ath10k *ar) 1191{ 1192 ath10k_ce_disable_interrupts(ar); 1193 ath10k_pci_disable_and_clear_legacy_irq(ar); 1194 ath10k_pci_irq_msi_fw_mask(ar); 1195} 1196 1197static void ath10k_pci_irq_sync(struct ath10k *ar) 1198{ 1199 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1200 int i; 1201 1202 for (i = 0; i < max(1, ar_pci->num_msi_intrs); i++) 1203 synchronize_irq(ar_pci->pdev->irq + i); 1204} 1205 1206static void ath10k_pci_irq_enable(struct ath10k *ar) 1207{ 1208 ath10k_ce_enable_interrupts(ar); 1209 ath10k_pci_enable_legacy_irq(ar); 1210 ath10k_pci_irq_msi_fw_unmask(ar); 1211} 1212 1213static int ath10k_pci_hif_start(struct ath10k *ar) 1214{ 1215 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif start\n"); 1216 1217 ath10k_pci_irq_enable(ar); 1218 ath10k_pci_rx_post(ar); 1219 1220 return 0; 1221} 1222 1223static void ath10k_pci_rx_pipe_cleanup(struct ath10k_pci_pipe *pci_pipe) 1224{ 1225 struct ath10k *ar; 1226 struct ath10k_ce_pipe *ce_pipe; 1227 struct ath10k_ce_ring *ce_ring; 1228 struct sk_buff *skb; 1229 int i; 1230 1231 ar = pci_pipe->hif_ce_state; 1232 ce_pipe = pci_pipe->ce_hdl; 1233 ce_ring = ce_pipe->dest_ring; 1234 1235 if (!ce_ring) 1236 return; 1237 1238 if (!pci_pipe->buf_sz) 1239 return; 1240 1241 for (i = 0; i < ce_ring->nentries; i++) { 1242 skb = ce_ring->per_transfer_context[i]; 1243 if (!skb) 1244 continue; 1245 1246 ce_ring->per_transfer_context[i] = NULL; 1247 1248 dma_unmap_single(ar->dev, ATH10K_SKB_RXCB(skb)->paddr, 1249 skb->len + skb_tailroom(skb), 1250 DMA_FROM_DEVICE); 1251 dev_kfree_skb_any(skb); 1252 } 1253} 1254 1255static void ath10k_pci_tx_pipe_cleanup(struct ath10k_pci_pipe *pci_pipe) 1256{ 1257 struct ath10k *ar; 1258 struct ath10k_pci *ar_pci; 1259 struct ath10k_ce_pipe *ce_pipe; 1260 struct ath10k_ce_ring *ce_ring; 1261 struct ce_desc *ce_desc; 1262 struct sk_buff *skb; 1263 unsigned int id; 1264 int i; 1265 1266 ar = pci_pipe->hif_ce_state; 1267 ar_pci = ath10k_pci_priv(ar); 1268 ce_pipe = pci_pipe->ce_hdl; 1269 ce_ring = ce_pipe->src_ring; 1270 1271 if (!ce_ring) 1272 return; 1273 1274 if (!pci_pipe->buf_sz) 1275 return; 1276 1277 ce_desc = ce_ring->shadow_base; 1278 if (WARN_ON(!ce_desc)) 1279 return; 1280 1281 for (i = 0; i < ce_ring->nentries; i++) { 1282 skb = ce_ring->per_transfer_context[i]; 1283 if (!skb) 1284 continue; 1285 1286 ce_ring->per_transfer_context[i] = NULL; 1287 id = MS(__le16_to_cpu(ce_desc[i].flags), 1288 CE_DESC_FLAGS_META_DATA); 1289 1290 ar_pci->msg_callbacks_current.tx_completion(ar, skb); 1291 } 1292} 1293 1294/* 1295 * Cleanup residual buffers for device shutdown: 1296 * buffers that were enqueued for receive 1297 * buffers that were to be sent 1298 * Note: Buffers that had completed but which were 1299 * not yet processed are on a completion queue. They 1300 * are handled when the completion thread shuts down. 1301 */ 1302static void ath10k_pci_buffer_cleanup(struct ath10k *ar) 1303{ 1304 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1305 int pipe_num; 1306 1307 for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) { 1308 struct ath10k_pci_pipe *pipe_info; 1309 1310 pipe_info = &ar_pci->pipe_info[pipe_num]; 1311 ath10k_pci_rx_pipe_cleanup(pipe_info); 1312 ath10k_pci_tx_pipe_cleanup(pipe_info); 1313 } 1314} 1315 1316static void ath10k_pci_ce_deinit(struct ath10k *ar) 1317{ 1318 int i; 1319 1320 for (i = 0; i < CE_COUNT; i++) 1321 ath10k_ce_deinit_pipe(ar, i); 1322} 1323 1324static void ath10k_pci_flush(struct ath10k *ar) 1325{ 1326 ath10k_pci_kill_tasklet(ar); 1327 ath10k_pci_buffer_cleanup(ar); 1328} 1329 1330static void ath10k_pci_hif_stop(struct ath10k *ar) 1331{ 1332 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif stop\n"); 1333 1334 /* Most likely the device has HTT Rx ring configured. The only way to 1335 * prevent the device from accessing (and possible corrupting) host 1336 * memory is to reset the chip now. 1337 * 1338 * There's also no known way of masking MSI interrupts on the device. 1339 * For ranged MSI the CE-related interrupts can be masked. However 1340 * regardless how many MSI interrupts are assigned the first one 1341 * is always used for firmware indications (crashes) and cannot be 1342 * masked. To prevent the device from asserting the interrupt reset it 1343 * before proceeding with cleanup. 1344 */ 1345 ath10k_pci_warm_reset(ar); 1346 1347 ath10k_pci_irq_disable(ar); 1348 ath10k_pci_irq_sync(ar); 1349 ath10k_pci_flush(ar); 1350} 1351 1352static int ath10k_pci_hif_exchange_bmi_msg(struct ath10k *ar, 1353 void *req, u32 req_len, 1354 void *resp, u32 *resp_len) 1355{ 1356 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1357 struct ath10k_pci_pipe *pci_tx = &ar_pci->pipe_info[BMI_CE_NUM_TO_TARG]; 1358 struct ath10k_pci_pipe *pci_rx = &ar_pci->pipe_info[BMI_CE_NUM_TO_HOST]; 1359 struct ath10k_ce_pipe *ce_tx = pci_tx->ce_hdl; 1360 struct ath10k_ce_pipe *ce_rx = pci_rx->ce_hdl; 1361 dma_addr_t req_paddr = 0; 1362 dma_addr_t resp_paddr = 0; 1363 struct bmi_xfer xfer = {}; 1364 void *treq, *tresp = NULL; 1365 int ret = 0; 1366 1367 might_sleep(); 1368 1369 if (resp && !resp_len) 1370 return -EINVAL; 1371 1372 if (resp && resp_len && *resp_len == 0) 1373 return -EINVAL; 1374 1375 treq = kmemdup(req, req_len, GFP_KERNEL); 1376 if (!treq) 1377 return -ENOMEM; 1378 1379 req_paddr = dma_map_single(ar->dev, treq, req_len, DMA_TO_DEVICE); 1380 ret = dma_mapping_error(ar->dev, req_paddr); 1381 if (ret) { 1382 ret = -EIO; 1383 goto err_dma; 1384 } 1385 1386 if (resp && resp_len) { 1387 tresp = kzalloc(*resp_len, GFP_KERNEL); 1388 if (!tresp) { 1389 ret = -ENOMEM; 1390 goto err_req; 1391 } 1392 1393 resp_paddr = dma_map_single(ar->dev, tresp, *resp_len, 1394 DMA_FROM_DEVICE); 1395 ret = dma_mapping_error(ar->dev, resp_paddr); 1396 if (ret) { 1397 ret = EIO; 1398 goto err_req; 1399 } 1400 1401 xfer.wait_for_resp = true; 1402 xfer.resp_len = 0; 1403 1404 ath10k_ce_rx_post_buf(ce_rx, &xfer, resp_paddr); 1405 } 1406 1407 ret = ath10k_ce_send(ce_tx, &xfer, req_paddr, req_len, -1, 0); 1408 if (ret) 1409 goto err_resp; 1410 1411 ret = ath10k_pci_bmi_wait(ce_tx, ce_rx, &xfer); 1412 if (ret) { 1413 u32 unused_buffer; 1414 unsigned int unused_nbytes; 1415 unsigned int unused_id; 1416 1417 ath10k_ce_cancel_send_next(ce_tx, NULL, &unused_buffer, 1418 &unused_nbytes, &unused_id); 1419 } else { 1420 /* non-zero means we did not time out */ 1421 ret = 0; 1422 } 1423 1424err_resp: 1425 if (resp) { 1426 u32 unused_buffer; 1427 1428 ath10k_ce_revoke_recv_next(ce_rx, NULL, &unused_buffer); 1429 dma_unmap_single(ar->dev, resp_paddr, 1430 *resp_len, DMA_FROM_DEVICE); 1431 } 1432err_req: 1433 dma_unmap_single(ar->dev, req_paddr, req_len, DMA_TO_DEVICE); 1434 1435 if (ret == 0 && resp_len) { 1436 *resp_len = min(*resp_len, xfer.resp_len); 1437 memcpy(resp, tresp, xfer.resp_len); 1438 } 1439err_dma: 1440 kfree(treq); 1441 kfree(tresp); 1442 1443 return ret; 1444} 1445 1446static void ath10k_pci_bmi_send_done(struct ath10k_ce_pipe *ce_state) 1447{ 1448 struct bmi_xfer *xfer; 1449 u32 ce_data; 1450 unsigned int nbytes; 1451 unsigned int transfer_id; 1452 1453 if (ath10k_ce_completed_send_next(ce_state, (void **)&xfer, &ce_data, 1454 &nbytes, &transfer_id)) 1455 return; 1456 1457 xfer->tx_done = true; 1458} 1459 1460static void ath10k_pci_bmi_recv_data(struct ath10k_ce_pipe *ce_state) 1461{ 1462 struct ath10k *ar = ce_state->ar; 1463 struct bmi_xfer *xfer; 1464 u32 ce_data; 1465 unsigned int nbytes; 1466 unsigned int transfer_id; 1467 unsigned int flags; 1468 1469 if (ath10k_ce_completed_recv_next(ce_state, (void **)&xfer, &ce_data, 1470 &nbytes, &transfer_id, &flags)) 1471 return; 1472 1473 if (WARN_ON_ONCE(!xfer)) 1474 return; 1475 1476 if (!xfer->wait_for_resp) { 1477 ath10k_warn(ar, "unexpected: BMI data received; ignoring\n"); 1478 return; 1479 } 1480 1481 xfer->resp_len = nbytes; 1482 xfer->rx_done = true; 1483} 1484 1485static int ath10k_pci_bmi_wait(struct ath10k_ce_pipe *tx_pipe, 1486 struct ath10k_ce_pipe *rx_pipe, 1487 struct bmi_xfer *xfer) 1488{ 1489 unsigned long timeout = jiffies + BMI_COMMUNICATION_TIMEOUT_HZ; 1490 1491 while (time_before_eq(jiffies, timeout)) { 1492 ath10k_pci_bmi_send_done(tx_pipe); 1493 ath10k_pci_bmi_recv_data(rx_pipe); 1494 1495 if (xfer->tx_done && (xfer->rx_done == xfer->wait_for_resp)) 1496 return 0; 1497 1498 schedule(); 1499 } 1500 1501 return -ETIMEDOUT; 1502} 1503 1504/* 1505 * Send an interrupt to the device to wake up the Target CPU 1506 * so it has an opportunity to notice any changed state. 1507 */ 1508static int ath10k_pci_wake_target_cpu(struct ath10k *ar) 1509{ 1510 u32 addr, val; 1511 1512 addr = SOC_CORE_BASE_ADDRESS | CORE_CTRL_ADDRESS; 1513 val = ath10k_pci_read32(ar, addr); 1514 val |= CORE_CTRL_CPU_INTR_MASK; 1515 ath10k_pci_write32(ar, addr, val); 1516 1517 return 0; 1518} 1519 1520static int ath10k_pci_get_num_banks(struct ath10k *ar) 1521{ 1522 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1523 1524 switch (ar_pci->pdev->device) { 1525 case QCA988X_2_0_DEVICE_ID: 1526 return 1; 1527 case QCA6174_2_1_DEVICE_ID: 1528 switch (MS(ar->chip_id, SOC_CHIP_ID_REV)) { 1529 case QCA6174_HW_1_0_CHIP_ID_REV: 1530 case QCA6174_HW_1_1_CHIP_ID_REV: 1531 case QCA6174_HW_2_1_CHIP_ID_REV: 1532 case QCA6174_HW_2_2_CHIP_ID_REV: 1533 return 3; 1534 case QCA6174_HW_1_3_CHIP_ID_REV: 1535 return 2; 1536 case QCA6174_HW_3_0_CHIP_ID_REV: 1537 case QCA6174_HW_3_1_CHIP_ID_REV: 1538 case QCA6174_HW_3_2_CHIP_ID_REV: 1539 return 9; 1540 } 1541 break; 1542 } 1543 1544 ath10k_warn(ar, "unknown number of banks, assuming 1\n"); 1545 return 1; 1546} 1547 1548static int ath10k_pci_init_config(struct ath10k *ar) 1549{ 1550 u32 interconnect_targ_addr; 1551 u32 pcie_state_targ_addr = 0; 1552 u32 pipe_cfg_targ_addr = 0; 1553 u32 svc_to_pipe_map = 0; 1554 u32 pcie_config_flags = 0; 1555 u32 ealloc_value; 1556 u32 ealloc_targ_addr; 1557 u32 flag2_value; 1558 u32 flag2_targ_addr; 1559 int ret = 0; 1560 1561 /* Download to Target the CE Config and the service-to-CE map */ 1562 interconnect_targ_addr = 1563 host_interest_item_address(HI_ITEM(hi_interconnect_state)); 1564 1565 /* Supply Target-side CE configuration */ 1566 ret = ath10k_pci_diag_read32(ar, interconnect_targ_addr, 1567 &pcie_state_targ_addr); 1568 if (ret != 0) { 1569 ath10k_err(ar, "Failed to get pcie state addr: %d\n", ret); 1570 return ret; 1571 } 1572 1573 if (pcie_state_targ_addr == 0) { 1574 ret = -EIO; 1575 ath10k_err(ar, "Invalid pcie state addr\n"); 1576 return ret; 1577 } 1578 1579 ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr + 1580 offsetof(struct pcie_state, 1581 pipe_cfg_addr)), 1582 &pipe_cfg_targ_addr); 1583 if (ret != 0) { 1584 ath10k_err(ar, "Failed to get pipe cfg addr: %d\n", ret); 1585 return ret; 1586 } 1587 1588 if (pipe_cfg_targ_addr == 0) { 1589 ret = -EIO; 1590 ath10k_err(ar, "Invalid pipe cfg addr\n"); 1591 return ret; 1592 } 1593 1594 ret = ath10k_pci_diag_write_mem(ar, pipe_cfg_targ_addr, 1595 target_ce_config_wlan, 1596 sizeof(target_ce_config_wlan)); 1597 1598 if (ret != 0) { 1599 ath10k_err(ar, "Failed to write pipe cfg: %d\n", ret); 1600 return ret; 1601 } 1602 1603 ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr + 1604 offsetof(struct pcie_state, 1605 svc_to_pipe_map)), 1606 &svc_to_pipe_map); 1607 if (ret != 0) { 1608 ath10k_err(ar, "Failed to get svc/pipe map: %d\n", ret); 1609 return ret; 1610 } 1611 1612 if (svc_to_pipe_map == 0) { 1613 ret = -EIO; 1614 ath10k_err(ar, "Invalid svc_to_pipe map\n"); 1615 return ret; 1616 } 1617 1618 ret = ath10k_pci_diag_write_mem(ar, svc_to_pipe_map, 1619 target_service_to_ce_map_wlan, 1620 sizeof(target_service_to_ce_map_wlan)); 1621 if (ret != 0) { 1622 ath10k_err(ar, "Failed to write svc/pipe map: %d\n", ret); 1623 return ret; 1624 } 1625 1626 ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr + 1627 offsetof(struct pcie_state, 1628 config_flags)), 1629 &pcie_config_flags); 1630 if (ret != 0) { 1631 ath10k_err(ar, "Failed to get pcie config_flags: %d\n", ret); 1632 return ret; 1633 } 1634 1635 pcie_config_flags &= ~PCIE_CONFIG_FLAG_ENABLE_L1; 1636 1637 ret = ath10k_pci_diag_write32(ar, (pcie_state_targ_addr + 1638 offsetof(struct pcie_state, 1639 config_flags)), 1640 pcie_config_flags); 1641 if (ret != 0) { 1642 ath10k_err(ar, "Failed to write pcie config_flags: %d\n", ret); 1643 return ret; 1644 } 1645 1646 /* configure early allocation */ 1647 ealloc_targ_addr = host_interest_item_address(HI_ITEM(hi_early_alloc)); 1648 1649 ret = ath10k_pci_diag_read32(ar, ealloc_targ_addr, &ealloc_value); 1650 if (ret != 0) { 1651 ath10k_err(ar, "Faile to get early alloc val: %d\n", ret); 1652 return ret; 1653 } 1654 1655 /* first bank is switched to IRAM */ 1656 ealloc_value |= ((HI_EARLY_ALLOC_MAGIC << HI_EARLY_ALLOC_MAGIC_SHIFT) & 1657 HI_EARLY_ALLOC_MAGIC_MASK); 1658 ealloc_value |= ((ath10k_pci_get_num_banks(ar) << 1659 HI_EARLY_ALLOC_IRAM_BANKS_SHIFT) & 1660 HI_EARLY_ALLOC_IRAM_BANKS_MASK); 1661 1662 ret = ath10k_pci_diag_write32(ar, ealloc_targ_addr, ealloc_value); 1663 if (ret != 0) { 1664 ath10k_err(ar, "Failed to set early alloc val: %d\n", ret); 1665 return ret; 1666 } 1667 1668 /* Tell Target to proceed with initialization */ 1669 flag2_targ_addr = host_interest_item_address(HI_ITEM(hi_option_flag2)); 1670 1671 ret = ath10k_pci_diag_read32(ar, flag2_targ_addr, &flag2_value); 1672 if (ret != 0) { 1673 ath10k_err(ar, "Failed to get option val: %d\n", ret); 1674 return ret; 1675 } 1676 1677 flag2_value |= HI_OPTION_EARLY_CFG_DONE; 1678 1679 ret = ath10k_pci_diag_write32(ar, flag2_targ_addr, flag2_value); 1680 if (ret != 0) { 1681 ath10k_err(ar, "Failed to set option val: %d\n", ret); 1682 return ret; 1683 } 1684 1685 return 0; 1686} 1687 1688static int ath10k_pci_alloc_pipes(struct ath10k *ar) 1689{ 1690 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1691 struct ath10k_pci_pipe *pipe; 1692 int i, ret; 1693 1694 for (i = 0; i < CE_COUNT; i++) { 1695 pipe = &ar_pci->pipe_info[i]; 1696 pipe->ce_hdl = &ar_pci->ce_states[i]; 1697 pipe->pipe_num = i; 1698 pipe->hif_ce_state = ar; 1699 1700 ret = ath10k_ce_alloc_pipe(ar, i, &host_ce_config_wlan[i], 1701 ath10k_pci_ce_send_done, 1702 ath10k_pci_ce_recv_data); 1703 if (ret) { 1704 ath10k_err(ar, "failed to allocate copy engine pipe %d: %d\n", 1705 i, ret); 1706 return ret; 1707 } 1708 1709 /* Last CE is Diagnostic Window */ 1710 if (i == CE_COUNT - 1) { 1711 ar_pci->ce_diag = pipe->ce_hdl; 1712 continue; 1713 } 1714 1715 pipe->buf_sz = (size_t)(host_ce_config_wlan[i].src_sz_max); 1716 } 1717 1718 return 0; 1719} 1720 1721static void ath10k_pci_free_pipes(struct ath10k *ar) 1722{ 1723 int i; 1724 1725 for (i = 0; i < CE_COUNT; i++) 1726 ath10k_ce_free_pipe(ar, i); 1727} 1728 1729static int ath10k_pci_init_pipes(struct ath10k *ar) 1730{ 1731 int i, ret; 1732 1733 for (i = 0; i < CE_COUNT; i++) { 1734 ret = ath10k_ce_init_pipe(ar, i, &host_ce_config_wlan[i]); 1735 if (ret) { 1736 ath10k_err(ar, "failed to initialize copy engine pipe %d: %d\n", 1737 i, ret); 1738 return ret; 1739 } 1740 } 1741 1742 return 0; 1743} 1744 1745static bool ath10k_pci_has_fw_crashed(struct ath10k *ar) 1746{ 1747 return ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS) & 1748 FW_IND_EVENT_PENDING; 1749} 1750 1751static void ath10k_pci_fw_crashed_clear(struct ath10k *ar) 1752{ 1753 u32 val; 1754 1755 val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS); 1756 val &= ~FW_IND_EVENT_PENDING; 1757 ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS, val); 1758} 1759 1760/* this function effectively clears target memory controller assert line */ 1761static void ath10k_pci_warm_reset_si0(struct ath10k *ar) 1762{ 1763 u32 val; 1764 1765 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS); 1766 ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS, 1767 val | SOC_RESET_CONTROL_SI0_RST_MASK); 1768 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS); 1769 1770 msleep(10); 1771 1772 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS); 1773 ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS, 1774 val & ~SOC_RESET_CONTROL_SI0_RST_MASK); 1775 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS); 1776 1777 msleep(10); 1778} 1779 1780static void ath10k_pci_warm_reset_cpu(struct ath10k *ar) 1781{ 1782 u32 val; 1783 1784 ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS, 0); 1785 1786 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS + 1787 SOC_RESET_CONTROL_ADDRESS); 1788 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS, 1789 val | SOC_RESET_CONTROL_CPU_WARM_RST_MASK); 1790} 1791 1792static void ath10k_pci_warm_reset_ce(struct ath10k *ar) 1793{ 1794 u32 val; 1795 1796 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS + 1797 SOC_RESET_CONTROL_ADDRESS); 1798 1799 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS, 1800 val | SOC_RESET_CONTROL_CE_RST_MASK); 1801 msleep(10); 1802 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS, 1803 val & ~SOC_RESET_CONTROL_CE_RST_MASK); 1804} 1805 1806static void ath10k_pci_warm_reset_clear_lf(struct ath10k *ar) 1807{ 1808 u32 val; 1809 1810 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS + 1811 SOC_LF_TIMER_CONTROL0_ADDRESS); 1812 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + 1813 SOC_LF_TIMER_CONTROL0_ADDRESS, 1814 val & ~SOC_LF_TIMER_CONTROL0_ENABLE_MASK); 1815} 1816 1817static int ath10k_pci_warm_reset(struct ath10k *ar) 1818{ 1819 int ret; 1820 1821 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot warm reset\n"); 1822 1823 spin_lock_bh(&ar->data_lock); 1824 ar->stats.fw_warm_reset_counter++; 1825 spin_unlock_bh(&ar->data_lock); 1826 1827 ath10k_pci_irq_disable(ar); 1828 1829 /* Make sure the target CPU is not doing anything dangerous, e.g. if it 1830 * were to access copy engine while host performs copy engine reset 1831 * then it is possible for the device to confuse pci-e controller to 1832 * the point of bringing host system to a complete stop (i.e. hang). 1833 */ 1834 ath10k_pci_warm_reset_si0(ar); 1835 ath10k_pci_warm_reset_cpu(ar); 1836 ath10k_pci_init_pipes(ar); 1837 ath10k_pci_wait_for_target_init(ar); 1838 1839 ath10k_pci_warm_reset_clear_lf(ar); 1840 ath10k_pci_warm_reset_ce(ar); 1841 ath10k_pci_warm_reset_cpu(ar); 1842 ath10k_pci_init_pipes(ar); 1843 1844 ret = ath10k_pci_wait_for_target_init(ar); 1845 if (ret) { 1846 ath10k_warn(ar, "failed to wait for target init: %d\n", ret); 1847 return ret; 1848 } 1849 1850 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot warm reset complete\n"); 1851 1852 return 0; 1853} 1854 1855static int ath10k_pci_qca988x_chip_reset(struct ath10k *ar) 1856{ 1857 int i, ret; 1858 u32 val; 1859 1860 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot 988x chip reset\n"); 1861 1862 /* Some hardware revisions (e.g. CUS223v2) has issues with cold reset. 1863 * It is thus preferred to use warm reset which is safer but may not be 1864 * able to recover the device from all possible fail scenarios. 1865 * 1866 * Warm reset doesn't always work on first try so attempt it a few 1867 * times before giving up. 1868 */ 1869 for (i = 0; i < ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS; i++) { 1870 ret = ath10k_pci_warm_reset(ar); 1871 if (ret) { 1872 ath10k_warn(ar, "failed to warm reset attempt %d of %d: %d\n", 1873 i + 1, ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS, 1874 ret); 1875 continue; 1876 } 1877 1878 /* FIXME: Sometimes copy engine doesn't recover after warm 1879 * reset. In most cases this needs cold reset. In some of these 1880 * cases the device is in such a state that a cold reset may 1881 * lock up the host. 1882 * 1883 * Reading any host interest register via copy engine is 1884 * sufficient to verify if device is capable of booting 1885 * firmware blob. 1886 */ 1887 ret = ath10k_pci_init_pipes(ar); 1888 if (ret) { 1889 ath10k_warn(ar, "failed to init copy engine: %d\n", 1890 ret); 1891 continue; 1892 } 1893 1894 ret = ath10k_pci_diag_read32(ar, QCA988X_HOST_INTEREST_ADDRESS, 1895 &val); 1896 if (ret) { 1897 ath10k_warn(ar, "failed to poke copy engine: %d\n", 1898 ret); 1899 continue; 1900 } 1901 1902 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot chip reset complete (warm)\n"); 1903 return 0; 1904 } 1905 1906 if (ath10k_pci_reset_mode == ATH10K_PCI_RESET_WARM_ONLY) { 1907 ath10k_warn(ar, "refusing cold reset as requested\n"); 1908 return -EPERM; 1909 } 1910 1911 ret = ath10k_pci_cold_reset(ar); 1912 if (ret) { 1913 ath10k_warn(ar, "failed to cold reset: %d\n", ret); 1914 return ret; 1915 } 1916 1917 ret = ath10k_pci_wait_for_target_init(ar); 1918 if (ret) { 1919 ath10k_warn(ar, "failed to wait for target after cold reset: %d\n", 1920 ret); 1921 return ret; 1922 } 1923 1924 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca988x chip reset complete (cold)\n"); 1925 1926 return 0; 1927} 1928 1929static int ath10k_pci_qca6174_chip_reset(struct ath10k *ar) 1930{ 1931 int ret; 1932 1933 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca6174 chip reset\n"); 1934 1935 /* FIXME: QCA6174 requires cold + warm reset to work. */ 1936 1937 ret = ath10k_pci_cold_reset(ar); 1938 if (ret) { 1939 ath10k_warn(ar, "failed to cold reset: %d\n", ret); 1940 return ret; 1941 } 1942 1943 ret = ath10k_pci_wait_for_target_init(ar); 1944 if (ret) { 1945 ath10k_warn(ar, "failed to wait for target after cold reset: %d\n", 1946 ret); 1947 return ret; 1948 } 1949 1950 ret = ath10k_pci_warm_reset(ar); 1951 if (ret) { 1952 ath10k_warn(ar, "failed to warm reset: %d\n", ret); 1953 return ret; 1954 } 1955 1956 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca6174 chip reset complete (cold)\n"); 1957 1958 return 0; 1959} 1960 1961static int ath10k_pci_chip_reset(struct ath10k *ar) 1962{ 1963 if (QCA_REV_988X(ar)) 1964 return ath10k_pci_qca988x_chip_reset(ar); 1965 else if (QCA_REV_6174(ar)) 1966 return ath10k_pci_qca6174_chip_reset(ar); 1967 else 1968 return -ENOTSUPP; 1969} 1970 1971static int ath10k_pci_hif_power_up(struct ath10k *ar) 1972{ 1973 int ret; 1974 1975 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif power up\n"); 1976 1977 ret = ath10k_pci_wake(ar); 1978 if (ret) { 1979 ath10k_err(ar, "failed to wake up target: %d\n", ret); 1980 return ret; 1981 } 1982 1983 /* 1984 * Bring the target up cleanly. 1985 * 1986 * The target may be in an undefined state with an AUX-powered Target 1987 * and a Host in WoW mode. If the Host crashes, loses power, or is 1988 * restarted (without unloading the driver) then the Target is left 1989 * (aux) powered and running. On a subsequent driver load, the Target 1990 * is in an unexpected state. We try to catch that here in order to 1991 * reset the Target and retry the probe. 1992 */ 1993 ret = ath10k_pci_chip_reset(ar); 1994 if (ret) { 1995 if (ath10k_pci_has_fw_crashed(ar)) { 1996 ath10k_warn(ar, "firmware crashed during chip reset\n"); 1997 ath10k_pci_fw_crashed_clear(ar); 1998 ath10k_pci_fw_crashed_dump(ar); 1999 } 2000 2001 ath10k_err(ar, "failed to reset chip: %d\n", ret); 2002 goto err_sleep; 2003 } 2004 2005 ret = ath10k_pci_init_pipes(ar); 2006 if (ret) { 2007 ath10k_err(ar, "failed to initialize CE: %d\n", ret); 2008 goto err_sleep; 2009 } 2010 2011 ret = ath10k_pci_init_config(ar); 2012 if (ret) { 2013 ath10k_err(ar, "failed to setup init config: %d\n", ret); 2014 goto err_ce; 2015 } 2016 2017 ret = ath10k_pci_wake_target_cpu(ar); 2018 if (ret) { 2019 ath10k_err(ar, "could not wake up target CPU: %d\n", ret); 2020 goto err_ce; 2021 } 2022 2023 return 0; 2024 2025err_ce: 2026 ath10k_pci_ce_deinit(ar); 2027 2028err_sleep: 2029 ath10k_pci_sleep(ar); 2030 return ret; 2031} 2032 2033static void ath10k_pci_hif_power_down(struct ath10k *ar) 2034{ 2035 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif power down\n"); 2036 2037 /* Currently hif_power_up performs effectively a reset and hif_stop 2038 * resets the chip as well so there's no point in resetting here. 2039 */ 2040 2041 ath10k_pci_sleep(ar); 2042} 2043 2044#ifdef CONFIG_PM 2045 2046#define ATH10K_PCI_PM_CONTROL 0x44 2047 2048static int ath10k_pci_hif_suspend(struct ath10k *ar) 2049{ 2050 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2051 struct pci_dev *pdev = ar_pci->pdev; 2052 u32 val; 2053 2054 pci_read_config_dword(pdev, ATH10K_PCI_PM_CONTROL, &val); 2055 2056 if ((val & 0x000000ff) != 0x3) { 2057 pci_save_state(pdev); 2058 pci_disable_device(pdev); 2059 pci_write_config_dword(pdev, ATH10K_PCI_PM_CONTROL, 2060 (val & 0xffffff00) | 0x03); 2061 } 2062 2063 return 0; 2064} 2065 2066static int ath10k_pci_hif_resume(struct ath10k *ar) 2067{ 2068 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2069 struct pci_dev *pdev = ar_pci->pdev; 2070 u32 val; 2071 2072 pci_read_config_dword(pdev, ATH10K_PCI_PM_CONTROL, &val); 2073 2074 if ((val & 0x000000ff) != 0) { 2075 pci_restore_state(pdev); 2076 pci_write_config_dword(pdev, ATH10K_PCI_PM_CONTROL, 2077 val & 0xffffff00); 2078 /* 2079 * Suspend/Resume resets the PCI configuration space, 2080 * so we have to re-disable the RETRY_TIMEOUT register (0x41) 2081 * to keep PCI Tx retries from interfering with C3 CPU state 2082 */ 2083 pci_read_config_dword(pdev, 0x40, &val); 2084 2085 if ((val & 0x0000ff00) != 0) 2086 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff); 2087 } 2088 2089 return 0; 2090} 2091#endif 2092 2093static const struct ath10k_hif_ops ath10k_pci_hif_ops = { 2094 .tx_sg = ath10k_pci_hif_tx_sg, 2095 .diag_read = ath10k_pci_hif_diag_read, 2096 .diag_write = ath10k_pci_diag_write_mem, 2097 .exchange_bmi_msg = ath10k_pci_hif_exchange_bmi_msg, 2098 .start = ath10k_pci_hif_start, 2099 .stop = ath10k_pci_hif_stop, 2100 .map_service_to_pipe = ath10k_pci_hif_map_service_to_pipe, 2101 .get_default_pipe = ath10k_pci_hif_get_default_pipe, 2102 .send_complete_check = ath10k_pci_hif_send_complete_check, 2103 .set_callbacks = ath10k_pci_hif_set_callbacks, 2104 .get_free_queue_number = ath10k_pci_hif_get_free_queue_number, 2105 .power_up = ath10k_pci_hif_power_up, 2106 .power_down = ath10k_pci_hif_power_down, 2107 .read32 = ath10k_pci_read32, 2108 .write32 = ath10k_pci_write32, 2109#ifdef CONFIG_PM 2110 .suspend = ath10k_pci_hif_suspend, 2111 .resume = ath10k_pci_hif_resume, 2112#endif 2113}; 2114 2115static void ath10k_pci_ce_tasklet(unsigned long ptr) 2116{ 2117 struct ath10k_pci_pipe *pipe = (struct ath10k_pci_pipe *)ptr; 2118 struct ath10k_pci *ar_pci = pipe->ar_pci; 2119 2120 ath10k_ce_per_engine_service(ar_pci->ar, pipe->pipe_num); 2121} 2122 2123static void ath10k_msi_err_tasklet(unsigned long data) 2124{ 2125 struct ath10k *ar = (struct ath10k *)data; 2126 2127 if (!ath10k_pci_has_fw_crashed(ar)) { 2128 ath10k_warn(ar, "received unsolicited fw crash interrupt\n"); 2129 return; 2130 } 2131 2132 ath10k_pci_irq_disable(ar); 2133 ath10k_pci_fw_crashed_clear(ar); 2134 ath10k_pci_fw_crashed_dump(ar); 2135} 2136 2137/* 2138 * Handler for a per-engine interrupt on a PARTICULAR CE. 2139 * This is used in cases where each CE has a private MSI interrupt. 2140 */ 2141static irqreturn_t ath10k_pci_per_engine_handler(int irq, void *arg) 2142{ 2143 struct ath10k *ar = arg; 2144 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2145 int ce_id = irq - ar_pci->pdev->irq - MSI_ASSIGN_CE_INITIAL; 2146 2147 if (ce_id < 0 || ce_id >= ARRAY_SIZE(ar_pci->pipe_info)) { 2148 ath10k_warn(ar, "unexpected/invalid irq %d ce_id %d\n", irq, 2149 ce_id); 2150 return IRQ_HANDLED; 2151 } 2152 2153 /* 2154 * NOTE: We are able to derive ce_id from irq because we 2155 * use a one-to-one mapping for CE's 0..5. 2156 * CE's 6 & 7 do not use interrupts at all. 2157 * 2158 * This mapping must be kept in sync with the mapping 2159 * used by firmware. 2160 */ 2161 tasklet_schedule(&ar_pci->pipe_info[ce_id].intr); 2162 return IRQ_HANDLED; 2163} 2164 2165static irqreturn_t ath10k_pci_msi_fw_handler(int irq, void *arg) 2166{ 2167 struct ath10k *ar = arg; 2168 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2169 2170 tasklet_schedule(&ar_pci->msi_fw_err); 2171 return IRQ_HANDLED; 2172} 2173 2174/* 2175 * Top-level interrupt handler for all PCI interrupts from a Target. 2176 * When a block of MSI interrupts is allocated, this top-level handler 2177 * is not used; instead, we directly call the correct sub-handler. 2178 */ 2179static irqreturn_t ath10k_pci_interrupt_handler(int irq, void *arg) 2180{ 2181 struct ath10k *ar = arg; 2182 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2183 2184 if (ar_pci->num_msi_intrs == 0) { 2185 if (!ath10k_pci_irq_pending(ar)) 2186 return IRQ_NONE; 2187 2188 ath10k_pci_disable_and_clear_legacy_irq(ar); 2189 } 2190 2191 tasklet_schedule(&ar_pci->intr_tq); 2192 2193 return IRQ_HANDLED; 2194} 2195 2196static void ath10k_pci_tasklet(unsigned long data) 2197{ 2198 struct ath10k *ar = (struct ath10k *)data; 2199 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2200 2201 if (ath10k_pci_has_fw_crashed(ar)) { 2202 ath10k_pci_irq_disable(ar); 2203 ath10k_pci_fw_crashed_clear(ar); 2204 ath10k_pci_fw_crashed_dump(ar); 2205 return; 2206 } 2207 2208 ath10k_ce_per_engine_service_any(ar); 2209 2210 /* Re-enable legacy irq that was disabled in the irq handler */ 2211 if (ar_pci->num_msi_intrs == 0) 2212 ath10k_pci_enable_legacy_irq(ar); 2213} 2214 2215static int ath10k_pci_request_irq_msix(struct ath10k *ar) 2216{ 2217 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2218 int ret, i; 2219 2220 ret = request_irq(ar_pci->pdev->irq + MSI_ASSIGN_FW, 2221 ath10k_pci_msi_fw_handler, 2222 IRQF_SHARED, "ath10k_pci", ar); 2223 if (ret) { 2224 ath10k_warn(ar, "failed to request MSI-X fw irq %d: %d\n", 2225 ar_pci->pdev->irq + MSI_ASSIGN_FW, ret); 2226 return ret; 2227 } 2228 2229 for (i = MSI_ASSIGN_CE_INITIAL; i <= MSI_ASSIGN_CE_MAX; i++) { 2230 ret = request_irq(ar_pci->pdev->irq + i, 2231 ath10k_pci_per_engine_handler, 2232 IRQF_SHARED, "ath10k_pci", ar); 2233 if (ret) { 2234 ath10k_warn(ar, "failed to request MSI-X ce irq %d: %d\n", 2235 ar_pci->pdev->irq + i, ret); 2236 2237 for (i--; i >= MSI_ASSIGN_CE_INITIAL; i--) 2238 free_irq(ar_pci->pdev->irq + i, ar); 2239 2240 free_irq(ar_pci->pdev->irq + MSI_ASSIGN_FW, ar); 2241 return ret; 2242 } 2243 } 2244 2245 return 0; 2246} 2247 2248static int ath10k_pci_request_irq_msi(struct ath10k *ar) 2249{ 2250 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2251 int ret; 2252 2253 ret = request_irq(ar_pci->pdev->irq, 2254 ath10k_pci_interrupt_handler, 2255 IRQF_SHARED, "ath10k_pci", ar); 2256 if (ret) { 2257 ath10k_warn(ar, "failed to request MSI irq %d: %d\n", 2258 ar_pci->pdev->irq, ret); 2259 return ret; 2260 } 2261 2262 return 0; 2263} 2264 2265static int ath10k_pci_request_irq_legacy(struct ath10k *ar) 2266{ 2267 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2268 int ret; 2269 2270 ret = request_irq(ar_pci->pdev->irq, 2271 ath10k_pci_interrupt_handler, 2272 IRQF_SHARED, "ath10k_pci", ar); 2273 if (ret) { 2274 ath10k_warn(ar, "failed to request legacy irq %d: %d\n", 2275 ar_pci->pdev->irq, ret); 2276 return ret; 2277 } 2278 2279 return 0; 2280} 2281 2282static int ath10k_pci_request_irq(struct ath10k *ar) 2283{ 2284 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2285 2286 switch (ar_pci->num_msi_intrs) { 2287 case 0: 2288 return ath10k_pci_request_irq_legacy(ar); 2289 case 1: 2290 return ath10k_pci_request_irq_msi(ar); 2291 case MSI_NUM_REQUEST: 2292 return ath10k_pci_request_irq_msix(ar); 2293 } 2294 2295 ath10k_warn(ar, "unknown irq configuration upon request\n"); 2296 return -EINVAL; 2297} 2298 2299static void ath10k_pci_free_irq(struct ath10k *ar) 2300{ 2301 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2302 int i; 2303 2304 /* There's at least one interrupt irregardless whether its legacy INTR 2305 * or MSI or MSI-X */ 2306 for (i = 0; i < max(1, ar_pci->num_msi_intrs); i++) 2307 free_irq(ar_pci->pdev->irq + i, ar); 2308} 2309 2310static void ath10k_pci_init_irq_tasklets(struct ath10k *ar) 2311{ 2312 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2313 int i; 2314 2315 tasklet_init(&ar_pci->intr_tq, ath10k_pci_tasklet, (unsigned long)ar); 2316 tasklet_init(&ar_pci->msi_fw_err, ath10k_msi_err_tasklet, 2317 (unsigned long)ar); 2318 2319 for (i = 0; i < CE_COUNT; i++) { 2320 ar_pci->pipe_info[i].ar_pci = ar_pci; 2321 tasklet_init(&ar_pci->pipe_info[i].intr, ath10k_pci_ce_tasklet, 2322 (unsigned long)&ar_pci->pipe_info[i]); 2323 } 2324} 2325 2326static int ath10k_pci_init_irq(struct ath10k *ar) 2327{ 2328 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2329 int ret; 2330 2331 ath10k_pci_init_irq_tasklets(ar); 2332 2333 if (ath10k_pci_irq_mode != ATH10K_PCI_IRQ_AUTO) 2334 ath10k_info(ar, "limiting irq mode to: %d\n", 2335 ath10k_pci_irq_mode); 2336 2337 /* Try MSI-X */ 2338 if (ath10k_pci_irq_mode == ATH10K_PCI_IRQ_AUTO) { 2339 ar_pci->num_msi_intrs = MSI_NUM_REQUEST; 2340 ret = pci_enable_msi_range(ar_pci->pdev, ar_pci->num_msi_intrs, 2341 ar_pci->num_msi_intrs); 2342 if (ret > 0) 2343 return 0; 2344 2345 /* fall-through */ 2346 } 2347 2348 /* Try MSI */ 2349 if (ath10k_pci_irq_mode != ATH10K_PCI_IRQ_LEGACY) { 2350 ar_pci->num_msi_intrs = 1; 2351 ret = pci_enable_msi(ar_pci->pdev); 2352 if (ret == 0) 2353 return 0; 2354 2355 /* fall-through */ 2356 } 2357 2358 /* Try legacy irq 2359 * 2360 * A potential race occurs here: The CORE_BASE write 2361 * depends on target correctly decoding AXI address but 2362 * host won't know when target writes BAR to CORE_CTRL. 2363 * This write might get lost if target has NOT written BAR. 2364 * For now, fix the race by repeating the write in below 2365 * synchronization checking. */ 2366 ar_pci->num_msi_intrs = 0; 2367 2368 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS, 2369 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL); 2370 2371 return 0; 2372} 2373 2374static void ath10k_pci_deinit_irq_legacy(struct ath10k *ar) 2375{ 2376 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS, 2377 0); 2378} 2379 2380static int ath10k_pci_deinit_irq(struct ath10k *ar) 2381{ 2382 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2383 2384 switch (ar_pci->num_msi_intrs) { 2385 case 0: 2386 ath10k_pci_deinit_irq_legacy(ar); 2387 return 0; 2388 case 1: 2389 /* fall-through */ 2390 case MSI_NUM_REQUEST: 2391 pci_disable_msi(ar_pci->pdev); 2392 return 0; 2393 default: 2394 pci_disable_msi(ar_pci->pdev); 2395 } 2396 2397 ath10k_warn(ar, "unknown irq configuration upon deinit\n"); 2398 return -EINVAL; 2399} 2400 2401static int ath10k_pci_wait_for_target_init(struct ath10k *ar) 2402{ 2403 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2404 unsigned long timeout; 2405 u32 val; 2406 2407 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot waiting target to initialise\n"); 2408 2409 timeout = jiffies + msecs_to_jiffies(ATH10K_PCI_TARGET_WAIT); 2410 2411 do { 2412 val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS); 2413 2414 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot target indicator %x\n", 2415 val); 2416 2417 /* target should never return this */ 2418 if (val == 0xffffffff) 2419 continue; 2420 2421 /* the device has crashed so don't bother trying anymore */ 2422 if (val & FW_IND_EVENT_PENDING) 2423 break; 2424 2425 if (val & FW_IND_INITIALIZED) 2426 break; 2427 2428 if (ar_pci->num_msi_intrs == 0) 2429 /* Fix potential race by repeating CORE_BASE writes */ 2430 ath10k_pci_enable_legacy_irq(ar); 2431 2432 mdelay(10); 2433 } while (time_before(jiffies, timeout)); 2434 2435 ath10k_pci_disable_and_clear_legacy_irq(ar); 2436 ath10k_pci_irq_msi_fw_mask(ar); 2437 2438 if (val == 0xffffffff) { 2439 ath10k_err(ar, "failed to read device register, device is gone\n"); 2440 return -EIO; 2441 } 2442 2443 if (val & FW_IND_EVENT_PENDING) { 2444 ath10k_warn(ar, "device has crashed during init\n"); 2445 return -ECOMM; 2446 } 2447 2448 if (!(val & FW_IND_INITIALIZED)) { 2449 ath10k_err(ar, "failed to receive initialized event from target: %08x\n", 2450 val); 2451 return -ETIMEDOUT; 2452 } 2453 2454 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot target initialised\n"); 2455 return 0; 2456} 2457 2458static int ath10k_pci_cold_reset(struct ath10k *ar) 2459{ 2460 int i; 2461 u32 val; 2462 2463 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cold reset\n"); 2464 2465 spin_lock_bh(&ar->data_lock); 2466 2467 ar->stats.fw_cold_reset_counter++; 2468 2469 spin_unlock_bh(&ar->data_lock); 2470 2471 /* Put Target, including PCIe, into RESET. */ 2472 val = ath10k_pci_reg_read32(ar, SOC_GLOBAL_RESET_ADDRESS); 2473 val |= 1; 2474 ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val); 2475 2476 for (i = 0; i < ATH_PCI_RESET_WAIT_MAX; i++) { 2477 if (ath10k_pci_reg_read32(ar, RTC_STATE_ADDRESS) & 2478 RTC_STATE_COLD_RESET_MASK) 2479 break; 2480 msleep(1); 2481 } 2482 2483 /* Pull Target, including PCIe, out of RESET. */ 2484 val &= ~1; 2485 ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val); 2486 2487 for (i = 0; i < ATH_PCI_RESET_WAIT_MAX; i++) { 2488 if (!(ath10k_pci_reg_read32(ar, RTC_STATE_ADDRESS) & 2489 RTC_STATE_COLD_RESET_MASK)) 2490 break; 2491 msleep(1); 2492 } 2493 2494 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cold reset complete\n"); 2495 2496 return 0; 2497} 2498 2499static int ath10k_pci_claim(struct ath10k *ar) 2500{ 2501 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2502 struct pci_dev *pdev = ar_pci->pdev; 2503 u32 lcr_val; 2504 int ret; 2505 2506 pci_set_drvdata(pdev, ar); 2507 2508 ret = pci_enable_device(pdev); 2509 if (ret) { 2510 ath10k_err(ar, "failed to enable pci device: %d\n", ret); 2511 return ret; 2512 } 2513 2514 ret = pci_request_region(pdev, BAR_NUM, "ath"); 2515 if (ret) { 2516 ath10k_err(ar, "failed to request region BAR%d: %d\n", BAR_NUM, 2517 ret); 2518 goto err_device; 2519 } 2520 2521 /* Target expects 32 bit DMA. Enforce it. */ 2522 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 2523 if (ret) { 2524 ath10k_err(ar, "failed to set dma mask to 32-bit: %d\n", ret); 2525 goto err_region; 2526 } 2527 2528 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 2529 if (ret) { 2530 ath10k_err(ar, "failed to set consistent dma mask to 32-bit: %d\n", 2531 ret); 2532 goto err_region; 2533 } 2534 2535 pci_set_master(pdev); 2536 2537 /* Workaround: Disable ASPM */ 2538 pci_read_config_dword(pdev, 0x80, &lcr_val); 2539 pci_write_config_dword(pdev, 0x80, (lcr_val & 0xffffff00)); 2540 2541 /* Arrange for access to Target SoC registers. */ 2542 ar_pci->mem = pci_iomap(pdev, BAR_NUM, 0); 2543 if (!ar_pci->mem) { 2544 ath10k_err(ar, "failed to iomap BAR%d\n", BAR_NUM); 2545 ret = -EIO; 2546 goto err_master; 2547 } 2548 2549 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot pci_mem 0x%p\n", ar_pci->mem); 2550 return 0; 2551 2552err_master: 2553 pci_clear_master(pdev); 2554 2555err_region: 2556 pci_release_region(pdev, BAR_NUM); 2557 2558err_device: 2559 pci_disable_device(pdev); 2560 2561 return ret; 2562} 2563 2564static void ath10k_pci_release(struct ath10k *ar) 2565{ 2566 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2567 struct pci_dev *pdev = ar_pci->pdev; 2568 2569 pci_iounmap(pdev, ar_pci->mem); 2570 pci_release_region(pdev, BAR_NUM); 2571 pci_clear_master(pdev); 2572 pci_disable_device(pdev); 2573} 2574 2575static bool ath10k_pci_chip_is_supported(u32 dev_id, u32 chip_id) 2576{ 2577 const struct ath10k_pci_supp_chip *supp_chip; 2578 int i; 2579 u32 rev_id = MS(chip_id, SOC_CHIP_ID_REV); 2580 2581 for (i = 0; i < ARRAY_SIZE(ath10k_pci_supp_chips); i++) { 2582 supp_chip = &ath10k_pci_supp_chips[i]; 2583 2584 if (supp_chip->dev_id == dev_id && 2585 supp_chip->rev_id == rev_id) 2586 return true; 2587 } 2588 2589 return false; 2590} 2591 2592static int ath10k_pci_probe(struct pci_dev *pdev, 2593 const struct pci_device_id *pci_dev) 2594{ 2595 int ret = 0; 2596 struct ath10k *ar; 2597 struct ath10k_pci *ar_pci; 2598 enum ath10k_hw_rev hw_rev; 2599 u32 chip_id; 2600 2601 switch (pci_dev->device) { 2602 case QCA988X_2_0_DEVICE_ID: 2603 hw_rev = ATH10K_HW_QCA988X; 2604 break; 2605 case QCA6174_2_1_DEVICE_ID: 2606 hw_rev = ATH10K_HW_QCA6174; 2607 break; 2608 default: 2609 WARN_ON(1); 2610 return -ENOTSUPP; 2611 } 2612 2613 ar = ath10k_core_create(sizeof(*ar_pci), &pdev->dev, ATH10K_BUS_PCI, 2614 hw_rev, &ath10k_pci_hif_ops); 2615 if (!ar) { 2616 dev_err(&pdev->dev, "failed to allocate core\n"); 2617 return -ENOMEM; 2618 } 2619 2620 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci probe\n"); 2621 2622 ar_pci = ath10k_pci_priv(ar); 2623 ar_pci->pdev = pdev; 2624 ar_pci->dev = &pdev->dev; 2625 ar_pci->ar = ar; 2626 2627 spin_lock_init(&ar_pci->ce_lock); 2628 setup_timer(&ar_pci->rx_post_retry, ath10k_pci_rx_replenish_retry, 2629 (unsigned long)ar); 2630 2631 ret = ath10k_pci_claim(ar); 2632 if (ret) { 2633 ath10k_err(ar, "failed to claim device: %d\n", ret); 2634 goto err_core_destroy; 2635 } 2636 2637 ret = ath10k_pci_wake(ar); 2638 if (ret) { 2639 ath10k_err(ar, "failed to wake up: %d\n", ret); 2640 goto err_release; 2641 } 2642 2643 ret = ath10k_pci_alloc_pipes(ar); 2644 if (ret) { 2645 ath10k_err(ar, "failed to allocate copy engine pipes: %d\n", 2646 ret); 2647 goto err_sleep; 2648 } 2649 2650 ath10k_pci_ce_deinit(ar); 2651 ath10k_pci_irq_disable(ar); 2652 2653 ret = ath10k_pci_init_irq(ar); 2654 if (ret) { 2655 ath10k_err(ar, "failed to init irqs: %d\n", ret); 2656 goto err_free_pipes; 2657 } 2658 2659 ath10k_info(ar, "pci irq %s interrupts %d irq_mode %d reset_mode %d\n", 2660 ath10k_pci_get_irq_method(ar), ar_pci->num_msi_intrs, 2661 ath10k_pci_irq_mode, ath10k_pci_reset_mode); 2662 2663 ret = ath10k_pci_request_irq(ar); 2664 if (ret) { 2665 ath10k_warn(ar, "failed to request irqs: %d\n", ret); 2666 goto err_deinit_irq; 2667 } 2668 2669 ret = ath10k_pci_chip_reset(ar); 2670 if (ret) { 2671 ath10k_err(ar, "failed to reset chip: %d\n", ret); 2672 goto err_free_irq; 2673 } 2674 2675 chip_id = ath10k_pci_soc_read32(ar, SOC_CHIP_ID_ADDRESS); 2676 if (chip_id == 0xffffffff) { 2677 ath10k_err(ar, "failed to get chip id\n"); 2678 goto err_free_irq; 2679 } 2680 2681 if (!ath10k_pci_chip_is_supported(pdev->device, chip_id)) { 2682 ath10k_err(ar, "device %04x with chip_id %08x isn't supported\n", 2683 pdev->device, chip_id); 2684 goto err_sleep; 2685 } 2686 2687 ath10k_pci_sleep(ar); 2688 2689 ret = ath10k_core_register(ar, chip_id); 2690 if (ret) { 2691 ath10k_err(ar, "failed to register driver core: %d\n", ret); 2692 goto err_free_irq; 2693 } 2694 2695 return 0; 2696 2697err_free_irq: 2698 ath10k_pci_free_irq(ar); 2699 ath10k_pci_kill_tasklet(ar); 2700 2701err_deinit_irq: 2702 ath10k_pci_deinit_irq(ar); 2703 2704err_free_pipes: 2705 ath10k_pci_free_pipes(ar); 2706 2707err_sleep: 2708 ath10k_pci_sleep(ar); 2709 2710err_release: 2711 ath10k_pci_release(ar); 2712 2713err_core_destroy: 2714 ath10k_core_destroy(ar); 2715 2716 return ret; 2717} 2718 2719static void ath10k_pci_remove(struct pci_dev *pdev) 2720{ 2721 struct ath10k *ar = pci_get_drvdata(pdev); 2722 struct ath10k_pci *ar_pci; 2723 2724 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci remove\n"); 2725 2726 if (!ar) 2727 return; 2728 2729 ar_pci = ath10k_pci_priv(ar); 2730 2731 if (!ar_pci) 2732 return; 2733 2734 ath10k_core_unregister(ar); 2735 ath10k_pci_free_irq(ar); 2736 ath10k_pci_kill_tasklet(ar); 2737 ath10k_pci_deinit_irq(ar); 2738 ath10k_pci_ce_deinit(ar); 2739 ath10k_pci_free_pipes(ar); 2740 ath10k_pci_release(ar); 2741 ath10k_core_destroy(ar); 2742} 2743 2744MODULE_DEVICE_TABLE(pci, ath10k_pci_id_table); 2745 2746static struct pci_driver ath10k_pci_driver = { 2747 .name = "ath10k_pci", 2748 .id_table = ath10k_pci_id_table, 2749 .probe = ath10k_pci_probe, 2750 .remove = ath10k_pci_remove, 2751}; 2752 2753static int __init ath10k_pci_init(void) 2754{ 2755 int ret; 2756 2757 ret = pci_register_driver(&ath10k_pci_driver); 2758 if (ret) 2759 printk(KERN_ERR "failed to register ath10k pci driver: %d\n", 2760 ret); 2761 2762 return ret; 2763} 2764module_init(ath10k_pci_init); 2765 2766static void __exit ath10k_pci_exit(void) 2767{ 2768 pci_unregister_driver(&ath10k_pci_driver); 2769} 2770 2771module_exit(ath10k_pci_exit); 2772 2773MODULE_AUTHOR("Qualcomm Atheros"); 2774MODULE_DESCRIPTION("Driver support for Atheros QCA988X PCIe devices"); 2775MODULE_LICENSE("Dual BSD/GPL"); 2776MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" QCA988X_HW_2_0_FW_FILE); 2777MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API2_FILE); 2778MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API3_FILE); 2779MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" QCA988X_HW_2_0_BOARD_DATA_FILE); 2780