1/*
2 *      FarSync WAN driver for Linux (2.6.x kernel version)
3 *
4 *      Actually sync driver for X.21, V.35 and V.24 on FarSync T-series cards
5 *
6 *      Copyright (C) 2001-2004 FarSite Communications Ltd.
7 *      www.farsite.co.uk
8 *
9 *      This program is free software; you can redistribute it and/or
10 *      modify it under the terms of the GNU General Public License
11 *      as published by the Free Software Foundation; either version
12 *      2 of the License, or (at your option) any later version.
13 *
14 *      Author:      R.J.Dunlop    <bob.dunlop@farsite.co.uk>
15 *      Maintainer:  Kevin Curtis  <kevin.curtis@farsite.co.uk>
16 */
17
18#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19
20#include <linux/module.h>
21#include <linux/kernel.h>
22#include <linux/version.h>
23#include <linux/pci.h>
24#include <linux/sched.h>
25#include <linux/slab.h>
26#include <linux/ioport.h>
27#include <linux/init.h>
28#include <linux/interrupt.h>
29#include <linux/delay.h>
30#include <linux/if.h>
31#include <linux/hdlc.h>
32#include <asm/io.h>
33#include <asm/uaccess.h>
34
35#include "farsync.h"
36
37/*
38 *      Module info
39 */
40MODULE_AUTHOR("R.J.Dunlop <bob.dunlop@farsite.co.uk>");
41MODULE_DESCRIPTION("FarSync T-Series WAN driver. FarSite Communications Ltd.");
42MODULE_LICENSE("GPL");
43
44/*      Driver configuration and global parameters
45 *      ==========================================
46 */
47
48/*      Number of ports (per card) and cards supported
49 */
50#define FST_MAX_PORTS           4
51#define FST_MAX_CARDS           32
52
53/*      Default parameters for the link
54 */
55#define FST_TX_QUEUE_LEN        100	/* At 8Mbps a longer queue length is
56					 * useful */
57#define FST_TXQ_DEPTH           16	/* This one is for the buffering
58					 * of frames on the way down to the card
59					 * so that we can keep the card busy
60					 * and maximise throughput
61					 */
62#define FST_HIGH_WATER_MARK     12	/* Point at which we flow control
63					 * network layer */
64#define FST_LOW_WATER_MARK      8	/* Point at which we remove flow
65					 * control from network layer */
66#define FST_MAX_MTU             8000	/* Huge but possible */
67#define FST_DEF_MTU             1500	/* Common sane value */
68
69#define FST_TX_TIMEOUT          (2*HZ)
70
71#ifdef ARPHRD_RAWHDLC
72#define ARPHRD_MYTYPE   ARPHRD_RAWHDLC	/* Raw frames */
73#else
74#define ARPHRD_MYTYPE   ARPHRD_HDLC	/* Cisco-HDLC (keepalives etc) */
75#endif
76
77/*
78 * Modules parameters and associated variables
79 */
80static int fst_txq_low = FST_LOW_WATER_MARK;
81static int fst_txq_high = FST_HIGH_WATER_MARK;
82static int fst_max_reads = 7;
83static int fst_excluded_cards = 0;
84static int fst_excluded_list[FST_MAX_CARDS];
85
86module_param(fst_txq_low, int, 0);
87module_param(fst_txq_high, int, 0);
88module_param(fst_max_reads, int, 0);
89module_param(fst_excluded_cards, int, 0);
90module_param_array(fst_excluded_list, int, NULL, 0);
91
92/*      Card shared memory layout
93 *      =========================
94 */
95#pragma pack(1)
96
97/*      This information is derived in part from the FarSite FarSync Smc.h
98 *      file. Unfortunately various name clashes and the non-portability of the
99 *      bit field declarations in that file have meant that I have chosen to
100 *      recreate the information here.
101 *
102 *      The SMC (Shared Memory Configuration) has a version number that is
103 *      incremented every time there is a significant change. This number can
104 *      be used to check that we have not got out of step with the firmware
105 *      contained in the .CDE files.
106 */
107#define SMC_VERSION 24
108
109#define FST_MEMSIZE 0x100000	/* Size of card memory (1Mb) */
110
111#define SMC_BASE 0x00002000L	/* Base offset of the shared memory window main
112				 * configuration structure */
113#define BFM_BASE 0x00010000L	/* Base offset of the shared memory window DMA
114				 * buffers */
115
116#define LEN_TX_BUFFER 8192	/* Size of packet buffers */
117#define LEN_RX_BUFFER 8192
118
119#define LEN_SMALL_TX_BUFFER 256	/* Size of obsolete buffs used for DOS diags */
120#define LEN_SMALL_RX_BUFFER 256
121
122#define NUM_TX_BUFFER 2		/* Must be power of 2. Fixed by firmware */
123#define NUM_RX_BUFFER 8
124
125/* Interrupt retry time in milliseconds */
126#define INT_RETRY_TIME 2
127
128/*      The Am186CH/CC processors support a SmartDMA mode using circular pools
129 *      of buffer descriptors. The structure is almost identical to that used
130 *      in the LANCE Ethernet controllers. Details available as PDF from the
131 *      AMD web site: http://www.amd.com/products/epd/processors/\
132 *                    2.16bitcont/3.am186cxfa/a21914/21914.pdf
133 */
134struct txdesc {			/* Transmit descriptor */
135	volatile u16 ladr;	/* Low order address of packet. This is a
136				 * linear address in the Am186 memory space
137				 */
138	volatile u8 hadr;	/* High order address. Low 4 bits only, high 4
139				 * bits must be zero
140				 */
141	volatile u8 bits;	/* Status and config */
142	volatile u16 bcnt;	/* 2s complement of packet size in low 15 bits.
143				 * Transmit terminal count interrupt enable in
144				 * top bit.
145				 */
146	u16 unused;		/* Not used in Tx */
147};
148
149struct rxdesc {			/* Receive descriptor */
150	volatile u16 ladr;	/* Low order address of packet */
151	volatile u8 hadr;	/* High order address */
152	volatile u8 bits;	/* Status and config */
153	volatile u16 bcnt;	/* 2s complement of buffer size in low 15 bits.
154				 * Receive terminal count interrupt enable in
155				 * top bit.
156				 */
157	volatile u16 mcnt;	/* Message byte count (15 bits) */
158};
159
160/* Convert a length into the 15 bit 2's complement */
161/* #define cnv_bcnt(len)   (( ~(len) + 1 ) & 0x7FFF ) */
162/* Since we need to set the high bit to enable the completion interrupt this
163 * can be made a lot simpler
164 */
165#define cnv_bcnt(len)   (-(len))
166
167/* Status and config bits for the above */
168#define DMA_OWN         0x80	/* SmartDMA owns the descriptor */
169#define TX_STP          0x02	/* Tx: start of packet */
170#define TX_ENP          0x01	/* Tx: end of packet */
171#define RX_ERR          0x40	/* Rx: error (OR of next 4 bits) */
172#define RX_FRAM         0x20	/* Rx: framing error */
173#define RX_OFLO         0x10	/* Rx: overflow error */
174#define RX_CRC          0x08	/* Rx: CRC error */
175#define RX_HBUF         0x04	/* Rx: buffer error */
176#define RX_STP          0x02	/* Rx: start of packet */
177#define RX_ENP          0x01	/* Rx: end of packet */
178
179/* Interrupts from the card are caused by various events which are presented
180 * in a circular buffer as several events may be processed on one physical int
181 */
182#define MAX_CIRBUFF     32
183
184struct cirbuff {
185	u8 rdindex;		/* read, then increment and wrap */
186	u8 wrindex;		/* write, then increment and wrap */
187	u8 evntbuff[MAX_CIRBUFF];
188};
189
190/* Interrupt event codes.
191 * Where appropriate the two low order bits indicate the port number
192 */
193#define CTLA_CHG        0x18	/* Control signal changed */
194#define CTLB_CHG        0x19
195#define CTLC_CHG        0x1A
196#define CTLD_CHG        0x1B
197
198#define INIT_CPLT       0x20	/* Initialisation complete */
199#define INIT_FAIL       0x21	/* Initialisation failed */
200
201#define ABTA_SENT       0x24	/* Abort sent */
202#define ABTB_SENT       0x25
203#define ABTC_SENT       0x26
204#define ABTD_SENT       0x27
205
206#define TXA_UNDF        0x28	/* Transmission underflow */
207#define TXB_UNDF        0x29
208#define TXC_UNDF        0x2A
209#define TXD_UNDF        0x2B
210
211#define F56_INT         0x2C
212#define M32_INT         0x2D
213
214#define TE1_ALMA        0x30
215
216/* Port physical configuration. See farsync.h for field values */
217struct port_cfg {
218	u16 lineInterface;	/* Physical interface type */
219	u8 x25op;		/* Unused at present */
220	u8 internalClock;	/* 1 => internal clock, 0 => external */
221	u8 transparentMode;	/* 1 => on, 0 => off */
222	u8 invertClock;		/* 0 => normal, 1 => inverted */
223	u8 padBytes[6];		/* Padding */
224	u32 lineSpeed;		/* Speed in bps */
225};
226
227/* TE1 port physical configuration */
228struct su_config {
229	u32 dataRate;
230	u8 clocking;
231	u8 framing;
232	u8 structure;
233	u8 interface;
234	u8 coding;
235	u8 lineBuildOut;
236	u8 equalizer;
237	u8 transparentMode;
238	u8 loopMode;
239	u8 range;
240	u8 txBufferMode;
241	u8 rxBufferMode;
242	u8 startingSlot;
243	u8 losThreshold;
244	u8 enableIdleCode;
245	u8 idleCode;
246	u8 spare[44];
247};
248
249/* TE1 Status */
250struct su_status {
251	u32 receiveBufferDelay;
252	u32 framingErrorCount;
253	u32 codeViolationCount;
254	u32 crcErrorCount;
255	u32 lineAttenuation;
256	u8 portStarted;
257	u8 lossOfSignal;
258	u8 receiveRemoteAlarm;
259	u8 alarmIndicationSignal;
260	u8 spare[40];
261};
262
263/* Finally sling all the above together into the shared memory structure.
264 * Sorry it's a hodge podge of arrays, structures and unused bits, it's been
265 * evolving under NT for some time so I guess we're stuck with it.
266 * The structure starts at offset SMC_BASE.
267 * See farsync.h for some field values.
268 */
269struct fst_shared {
270	/* DMA descriptor rings */
271	struct rxdesc rxDescrRing[FST_MAX_PORTS][NUM_RX_BUFFER];
272	struct txdesc txDescrRing[FST_MAX_PORTS][NUM_TX_BUFFER];
273
274	/* Obsolete small buffers */
275	u8 smallRxBuffer[FST_MAX_PORTS][NUM_RX_BUFFER][LEN_SMALL_RX_BUFFER];
276	u8 smallTxBuffer[FST_MAX_PORTS][NUM_TX_BUFFER][LEN_SMALL_TX_BUFFER];
277
278	u8 taskStatus;		/* 0x00 => initialising, 0x01 => running,
279				 * 0xFF => halted
280				 */
281
282	u8 interruptHandshake;	/* Set to 0x01 by adapter to signal interrupt,
283				 * set to 0xEE by host to acknowledge interrupt
284				 */
285
286	u16 smcVersion;		/* Must match SMC_VERSION */
287
288	u32 smcFirmwareVersion;	/* 0xIIVVRRBB where II = product ID, VV = major
289				 * version, RR = revision and BB = build
290				 */
291
292	u16 txa_done;		/* Obsolete completion flags */
293	u16 rxa_done;
294	u16 txb_done;
295	u16 rxb_done;
296	u16 txc_done;
297	u16 rxc_done;
298	u16 txd_done;
299	u16 rxd_done;
300
301	u16 mailbox[4];		/* Diagnostics mailbox. Not used */
302
303	struct cirbuff interruptEvent;	/* interrupt causes */
304
305	u32 v24IpSts[FST_MAX_PORTS];	/* V.24 control input status */
306	u32 v24OpSts[FST_MAX_PORTS];	/* V.24 control output status */
307
308	struct port_cfg portConfig[FST_MAX_PORTS];
309
310	u16 clockStatus[FST_MAX_PORTS];	/* lsb: 0=> present, 1=> absent */
311
312	u16 cableStatus;	/* lsb: 0=> present, 1=> absent */
313
314	u16 txDescrIndex[FST_MAX_PORTS];	/* transmit descriptor ring index */
315	u16 rxDescrIndex[FST_MAX_PORTS];	/* receive descriptor ring index */
316
317	u16 portMailbox[FST_MAX_PORTS][2];	/* command, modifier */
318	u16 cardMailbox[4];	/* Not used */
319
320	/* Number of times the card thinks the host has
321	 * missed an interrupt by not acknowledging
322	 * within 2mS (I guess NT has problems)
323	 */
324	u32 interruptRetryCount;
325
326	/* Driver private data used as an ID. We'll not
327	 * use this as I'd rather keep such things
328	 * in main memory rather than on the PCI bus
329	 */
330	u32 portHandle[FST_MAX_PORTS];
331
332	/* Count of Tx underflows for stats */
333	u32 transmitBufferUnderflow[FST_MAX_PORTS];
334
335	/* Debounced V.24 control input status */
336	u32 v24DebouncedSts[FST_MAX_PORTS];
337
338	/* Adapter debounce timers. Don't touch */
339	u32 ctsTimer[FST_MAX_PORTS];
340	u32 ctsTimerRun[FST_MAX_PORTS];
341	u32 dcdTimer[FST_MAX_PORTS];
342	u32 dcdTimerRun[FST_MAX_PORTS];
343
344	u32 numberOfPorts;	/* Number of ports detected at startup */
345
346	u16 _reserved[64];
347
348	u16 cardMode;		/* Bit-mask to enable features:
349				 * Bit 0: 1 enables LED identify mode
350				 */
351
352	u16 portScheduleOffset;
353
354	struct su_config suConfig;	/* TE1 Bits */
355	struct su_status suStatus;
356
357	u32 endOfSmcSignature;	/* endOfSmcSignature MUST be the last member of
358				 * the structure and marks the end of shared
359				 * memory. Adapter code initializes it as
360				 * END_SIG.
361				 */
362};
363
364/* endOfSmcSignature value */
365#define END_SIG                 0x12345678
366
367/* Mailbox values. (portMailbox) */
368#define NOP             0	/* No operation */
369#define ACK             1	/* Positive acknowledgement to PC driver */
370#define NAK             2	/* Negative acknowledgement to PC driver */
371#define STARTPORT       3	/* Start an HDLC port */
372#define STOPPORT        4	/* Stop an HDLC port */
373#define ABORTTX         5	/* Abort the transmitter for a port */
374#define SETV24O         6	/* Set V24 outputs */
375
376/* PLX Chip Register Offsets */
377#define CNTRL_9052      0x50	/* Control Register */
378#define CNTRL_9054      0x6c	/* Control Register */
379
380#define INTCSR_9052     0x4c	/* Interrupt control/status register */
381#define INTCSR_9054     0x68	/* Interrupt control/status register */
382
383/* 9054 DMA Registers */
384/*
385 * Note that we will be using DMA Channel 0 for copying rx data
386 * and Channel 1 for copying tx data
387 */
388#define DMAMODE0        0x80
389#define DMAPADR0        0x84
390#define DMALADR0        0x88
391#define DMASIZ0         0x8c
392#define DMADPR0         0x90
393#define DMAMODE1        0x94
394#define DMAPADR1        0x98
395#define DMALADR1        0x9c
396#define DMASIZ1         0xa0
397#define DMADPR1         0xa4
398#define DMACSR0         0xa8
399#define DMACSR1         0xa9
400#define DMAARB          0xac
401#define DMATHR          0xb0
402#define DMADAC0         0xb4
403#define DMADAC1         0xb8
404#define DMAMARBR        0xac
405
406#define FST_MIN_DMA_LEN 64
407#define FST_RX_DMA_INT  0x01
408#define FST_TX_DMA_INT  0x02
409#define FST_CARD_INT    0x04
410
411/* Larger buffers are positioned in memory at offset BFM_BASE */
412struct buf_window {
413	u8 txBuffer[FST_MAX_PORTS][NUM_TX_BUFFER][LEN_TX_BUFFER];
414	u8 rxBuffer[FST_MAX_PORTS][NUM_RX_BUFFER][LEN_RX_BUFFER];
415};
416
417/* Calculate offset of a buffer object within the shared memory window */
418#define BUF_OFFSET(X)   (BFM_BASE + offsetof(struct buf_window, X))
419
420#pragma pack()
421
422/*      Device driver private information
423 *      =================================
424 */
425/*      Per port (line or channel) information
426 */
427struct fst_port_info {
428        struct net_device *dev; /* Device struct - must be first */
429	struct fst_card_info *card;	/* Card we're associated with */
430	int index;		/* Port index on the card */
431	int hwif;		/* Line hardware (lineInterface copy) */
432	int run;		/* Port is running */
433	int mode;		/* Normal or FarSync raw */
434	int rxpos;		/* Next Rx buffer to use */
435	int txpos;		/* Next Tx buffer to use */
436	int txipos;		/* Next Tx buffer to check for free */
437	int start;		/* Indication of start/stop to network */
438	/*
439	 * A sixteen entry transmit queue
440	 */
441	int txqs;		/* index to get next buffer to tx */
442	int txqe;		/* index to queue next packet */
443	struct sk_buff *txq[FST_TXQ_DEPTH];	/* The queue */
444	int rxqdepth;
445};
446
447/*      Per card information
448 */
449struct fst_card_info {
450	char __iomem *mem;	/* Card memory mapped to kernel space */
451	char __iomem *ctlmem;	/* Control memory for PCI cards */
452	unsigned int phys_mem;	/* Physical memory window address */
453	unsigned int phys_ctlmem;	/* Physical control memory address */
454	unsigned int irq;	/* Interrupt request line number */
455	unsigned int nports;	/* Number of serial ports */
456	unsigned int type;	/* Type index of card */
457	unsigned int state;	/* State of card */
458	spinlock_t card_lock;	/* Lock for SMP access */
459	unsigned short pci_conf;	/* PCI card config in I/O space */
460	/* Per port info */
461	struct fst_port_info ports[FST_MAX_PORTS];
462	struct pci_dev *device;	/* Information about the pci device */
463	int card_no;		/* Inst of the card on the system */
464	int family;		/* TxP or TxU */
465	int dmarx_in_progress;
466	int dmatx_in_progress;
467	unsigned long int_count;
468	unsigned long int_time_ave;
469	void *rx_dma_handle_host;
470	dma_addr_t rx_dma_handle_card;
471	void *tx_dma_handle_host;
472	dma_addr_t tx_dma_handle_card;
473	struct sk_buff *dma_skb_rx;
474	struct fst_port_info *dma_port_rx;
475	struct fst_port_info *dma_port_tx;
476	int dma_len_rx;
477	int dma_len_tx;
478	int dma_txpos;
479	int dma_rxpos;
480};
481
482/* Convert an HDLC device pointer into a port info pointer and similar */
483#define dev_to_port(D)  (dev_to_hdlc(D)->priv)
484#define port_to_dev(P)  ((P)->dev)
485
486
487/*
488 *      Shared memory window access macros
489 *
490 *      We have a nice memory based structure above, which could be directly
491 *      mapped on i386 but might not work on other architectures unless we use
492 *      the readb,w,l and writeb,w,l macros. Unfortunately these macros take
493 *      physical offsets so we have to convert. The only saving grace is that
494 *      this should all collapse back to a simple indirection eventually.
495 */
496#define WIN_OFFSET(X)   ((long)&(((struct fst_shared *)SMC_BASE)->X))
497
498#define FST_RDB(C,E)    readb ((C)->mem + WIN_OFFSET(E))
499#define FST_RDW(C,E)    readw ((C)->mem + WIN_OFFSET(E))
500#define FST_RDL(C,E)    readl ((C)->mem + WIN_OFFSET(E))
501
502#define FST_WRB(C,E,B)  writeb ((B), (C)->mem + WIN_OFFSET(E))
503#define FST_WRW(C,E,W)  writew ((W), (C)->mem + WIN_OFFSET(E))
504#define FST_WRL(C,E,L)  writel ((L), (C)->mem + WIN_OFFSET(E))
505
506/*
507 *      Debug support
508 */
509#if FST_DEBUG
510
511static int fst_debug_mask = { FST_DEBUG };
512
513/* Most common debug activity is to print something if the corresponding bit
514 * is set in the debug mask. Note: this uses a non-ANSI extension in GCC to
515 * support variable numbers of macro parameters. The inverted if prevents us
516 * eating someone else's else clause.
517 */
518#define dbg(F, fmt, args...)					\
519do {								\
520	if (fst_debug_mask & (F))				\
521		printk(KERN_DEBUG pr_fmt(fmt), ##args);		\
522} while (0)
523#else
524#define dbg(F, fmt, args...)					\
525do {								\
526	if (0)							\
527		printk(KERN_DEBUG pr_fmt(fmt), ##args);		\
528} while (0)
529#endif
530
531/*
532 *      PCI ID lookup table
533 */
534static const struct pci_device_id fst_pci_dev_id[] = {
535	{PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T2P, PCI_ANY_ID,
536	 PCI_ANY_ID, 0, 0, FST_TYPE_T2P},
537
538	{PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T4P, PCI_ANY_ID,
539	 PCI_ANY_ID, 0, 0, FST_TYPE_T4P},
540
541	{PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T1U, PCI_ANY_ID,
542	 PCI_ANY_ID, 0, 0, FST_TYPE_T1U},
543
544	{PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T2U, PCI_ANY_ID,
545	 PCI_ANY_ID, 0, 0, FST_TYPE_T2U},
546
547	{PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T4U, PCI_ANY_ID,
548	 PCI_ANY_ID, 0, 0, FST_TYPE_T4U},
549
550	{PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_TE1, PCI_ANY_ID,
551	 PCI_ANY_ID, 0, 0, FST_TYPE_TE1},
552
553	{PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_TE1C, PCI_ANY_ID,
554	 PCI_ANY_ID, 0, 0, FST_TYPE_TE1},
555	{0,}			/* End */
556};
557
558MODULE_DEVICE_TABLE(pci, fst_pci_dev_id);
559
560/*
561 *      Device Driver Work Queues
562 *
563 *      So that we don't spend too much time processing events in the
564 *      Interrupt Service routine, we will declare a work queue per Card
565 *      and make the ISR schedule a task in the queue for later execution.
566 *      In the 2.4 Kernel we used to use the immediate queue for BH's
567 *      Now that they are gone, tasklets seem to be much better than work
568 *      queues.
569 */
570
571static void do_bottom_half_tx(struct fst_card_info *card);
572static void do_bottom_half_rx(struct fst_card_info *card);
573static void fst_process_tx_work_q(unsigned long work_q);
574static void fst_process_int_work_q(unsigned long work_q);
575
576static DECLARE_TASKLET(fst_tx_task, fst_process_tx_work_q, 0);
577static DECLARE_TASKLET(fst_int_task, fst_process_int_work_q, 0);
578
579static struct fst_card_info *fst_card_array[FST_MAX_CARDS];
580static spinlock_t fst_work_q_lock;
581static u64 fst_work_txq;
582static u64 fst_work_intq;
583
584static void
585fst_q_work_item(u64 * queue, int card_index)
586{
587	unsigned long flags;
588	u64 mask;
589
590	/*
591	 * Grab the queue exclusively
592	 */
593	spin_lock_irqsave(&fst_work_q_lock, flags);
594
595	/*
596	 * Making an entry in the queue is simply a matter of setting
597	 * a bit for the card indicating that there is work to do in the
598	 * bottom half for the card.  Note the limitation of 64 cards.
599	 * That ought to be enough
600	 */
601	mask = (u64)1 << card_index;
602	*queue |= mask;
603	spin_unlock_irqrestore(&fst_work_q_lock, flags);
604}
605
606static void
607fst_process_tx_work_q(unsigned long /*void **/work_q)
608{
609	unsigned long flags;
610	u64 work_txq;
611	int i;
612
613	/*
614	 * Grab the queue exclusively
615	 */
616	dbg(DBG_TX, "fst_process_tx_work_q\n");
617	spin_lock_irqsave(&fst_work_q_lock, flags);
618	work_txq = fst_work_txq;
619	fst_work_txq = 0;
620	spin_unlock_irqrestore(&fst_work_q_lock, flags);
621
622	/*
623	 * Call the bottom half for each card with work waiting
624	 */
625	for (i = 0; i < FST_MAX_CARDS; i++) {
626		if (work_txq & 0x01) {
627			if (fst_card_array[i] != NULL) {
628				dbg(DBG_TX, "Calling tx bh for card %d\n", i);
629				do_bottom_half_tx(fst_card_array[i]);
630			}
631		}
632		work_txq = work_txq >> 1;
633	}
634}
635
636static void
637fst_process_int_work_q(unsigned long /*void **/work_q)
638{
639	unsigned long flags;
640	u64 work_intq;
641	int i;
642
643	/*
644	 * Grab the queue exclusively
645	 */
646	dbg(DBG_INTR, "fst_process_int_work_q\n");
647	spin_lock_irqsave(&fst_work_q_lock, flags);
648	work_intq = fst_work_intq;
649	fst_work_intq = 0;
650	spin_unlock_irqrestore(&fst_work_q_lock, flags);
651
652	/*
653	 * Call the bottom half for each card with work waiting
654	 */
655	for (i = 0; i < FST_MAX_CARDS; i++) {
656		if (work_intq & 0x01) {
657			if (fst_card_array[i] != NULL) {
658				dbg(DBG_INTR,
659				    "Calling rx & tx bh for card %d\n", i);
660				do_bottom_half_rx(fst_card_array[i]);
661				do_bottom_half_tx(fst_card_array[i]);
662			}
663		}
664		work_intq = work_intq >> 1;
665	}
666}
667
668/*      Card control functions
669 *      ======================
670 */
671/*      Place the processor in reset state
672 *
673 * Used to be a simple write to card control space but a glitch in the latest
674 * AMD Am186CH processor means that we now have to do it by asserting and de-
675 * asserting the PLX chip PCI Adapter Software Reset. Bit 30 in CNTRL register
676 * at offset 9052_CNTRL.  Note the updates for the TXU.
677 */
678static inline void
679fst_cpureset(struct fst_card_info *card)
680{
681	unsigned char interrupt_line_register;
682	unsigned int regval;
683
684	if (card->family == FST_FAMILY_TXU) {
685		if (pci_read_config_byte
686		    (card->device, PCI_INTERRUPT_LINE, &interrupt_line_register)) {
687			dbg(DBG_ASS,
688			    "Error in reading interrupt line register\n");
689		}
690		/*
691		 * Assert PLX software reset and Am186 hardware reset
692		 * and then deassert the PLX software reset but 186 still in reset
693		 */
694		outw(0x440f, card->pci_conf + CNTRL_9054 + 2);
695		outw(0x040f, card->pci_conf + CNTRL_9054 + 2);
696		/*
697		 * We are delaying here to allow the 9054 to reset itself
698		 */
699		usleep_range(10, 20);
700		outw(0x240f, card->pci_conf + CNTRL_9054 + 2);
701		/*
702		 * We are delaying here to allow the 9054 to reload its eeprom
703		 */
704		usleep_range(10, 20);
705		outw(0x040f, card->pci_conf + CNTRL_9054 + 2);
706
707		if (pci_write_config_byte
708		    (card->device, PCI_INTERRUPT_LINE, interrupt_line_register)) {
709			dbg(DBG_ASS,
710			    "Error in writing interrupt line register\n");
711		}
712
713	} else {
714		regval = inl(card->pci_conf + CNTRL_9052);
715
716		outl(regval | 0x40000000, card->pci_conf + CNTRL_9052);
717		outl(regval & ~0x40000000, card->pci_conf + CNTRL_9052);
718	}
719}
720
721/*      Release the processor from reset
722 */
723static inline void
724fst_cpurelease(struct fst_card_info *card)
725{
726	if (card->family == FST_FAMILY_TXU) {
727		/*
728		 * Force posted writes to complete
729		 */
730		(void) readb(card->mem);
731
732		/*
733		 * Release LRESET DO = 1
734		 * Then release Local Hold, DO = 1
735		 */
736		outw(0x040e, card->pci_conf + CNTRL_9054 + 2);
737		outw(0x040f, card->pci_conf + CNTRL_9054 + 2);
738	} else {
739		(void) readb(card->ctlmem);
740	}
741}
742
743/*      Clear the cards interrupt flag
744 */
745static inline void
746fst_clear_intr(struct fst_card_info *card)
747{
748	if (card->family == FST_FAMILY_TXU) {
749		(void) readb(card->ctlmem);
750	} else {
751		/* Poke the appropriate PLX chip register (same as enabling interrupts)
752		 */
753		outw(0x0543, card->pci_conf + INTCSR_9052);
754	}
755}
756
757/*      Enable card interrupts
758 */
759static inline void
760fst_enable_intr(struct fst_card_info *card)
761{
762	if (card->family == FST_FAMILY_TXU) {
763		outl(0x0f0c0900, card->pci_conf + INTCSR_9054);
764	} else {
765		outw(0x0543, card->pci_conf + INTCSR_9052);
766	}
767}
768
769/*      Disable card interrupts
770 */
771static inline void
772fst_disable_intr(struct fst_card_info *card)
773{
774	if (card->family == FST_FAMILY_TXU) {
775		outl(0x00000000, card->pci_conf + INTCSR_9054);
776	} else {
777		outw(0x0000, card->pci_conf + INTCSR_9052);
778	}
779}
780
781/*      Process the result of trying to pass a received frame up the stack
782 */
783static void
784fst_process_rx_status(int rx_status, char *name)
785{
786	switch (rx_status) {
787	case NET_RX_SUCCESS:
788		{
789			/*
790			 * Nothing to do here
791			 */
792			break;
793		}
794	case NET_RX_DROP:
795		{
796			dbg(DBG_ASS, "%s: Received packet dropped\n", name);
797			break;
798		}
799	}
800}
801
802/*      Initilaise DMA for PLX 9054
803 */
804static inline void
805fst_init_dma(struct fst_card_info *card)
806{
807	/*
808	 * This is only required for the PLX 9054
809	 */
810	if (card->family == FST_FAMILY_TXU) {
811	        pci_set_master(card->device);
812		outl(0x00020441, card->pci_conf + DMAMODE0);
813		outl(0x00020441, card->pci_conf + DMAMODE1);
814		outl(0x0, card->pci_conf + DMATHR);
815	}
816}
817
818/*      Tx dma complete interrupt
819 */
820static void
821fst_tx_dma_complete(struct fst_card_info *card, struct fst_port_info *port,
822		    int len, int txpos)
823{
824	struct net_device *dev = port_to_dev(port);
825
826	/*
827	 * Everything is now set, just tell the card to go
828	 */
829	dbg(DBG_TX, "fst_tx_dma_complete\n");
830	FST_WRB(card, txDescrRing[port->index][txpos].bits,
831		DMA_OWN | TX_STP | TX_ENP);
832	dev->stats.tx_packets++;
833	dev->stats.tx_bytes += len;
834	dev->trans_start = jiffies;
835}
836
837/*
838 * Mark it for our own raw sockets interface
839 */
840static __be16 farsync_type_trans(struct sk_buff *skb, struct net_device *dev)
841{
842	skb->dev = dev;
843	skb_reset_mac_header(skb);
844	skb->pkt_type = PACKET_HOST;
845	return htons(ETH_P_CUST);
846}
847
848/*      Rx dma complete interrupt
849 */
850static void
851fst_rx_dma_complete(struct fst_card_info *card, struct fst_port_info *port,
852		    int len, struct sk_buff *skb, int rxp)
853{
854	struct net_device *dev = port_to_dev(port);
855	int pi;
856	int rx_status;
857
858	dbg(DBG_TX, "fst_rx_dma_complete\n");
859	pi = port->index;
860	memcpy(skb_put(skb, len), card->rx_dma_handle_host, len);
861
862	/* Reset buffer descriptor */
863	FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);
864
865	/* Update stats */
866	dev->stats.rx_packets++;
867	dev->stats.rx_bytes += len;
868
869	/* Push upstream */
870	dbg(DBG_RX, "Pushing the frame up the stack\n");
871	if (port->mode == FST_RAW)
872		skb->protocol = farsync_type_trans(skb, dev);
873	else
874		skb->protocol = hdlc_type_trans(skb, dev);
875	rx_status = netif_rx(skb);
876	fst_process_rx_status(rx_status, port_to_dev(port)->name);
877	if (rx_status == NET_RX_DROP)
878		dev->stats.rx_dropped++;
879}
880
881/*
882 *      Receive a frame through the DMA
883 */
884static inline void
885fst_rx_dma(struct fst_card_info *card, dma_addr_t dma, u32 mem, int len)
886{
887	/*
888	 * This routine will setup the DMA and start it
889	 */
890
891	dbg(DBG_RX, "In fst_rx_dma %x %x %d\n", (u32)dma, mem, len);
892	if (card->dmarx_in_progress) {
893		dbg(DBG_ASS, "In fst_rx_dma while dma in progress\n");
894	}
895
896	outl(dma, card->pci_conf + DMAPADR0);	/* Copy to here */
897	outl(mem, card->pci_conf + DMALADR0);	/* from here */
898	outl(len, card->pci_conf + DMASIZ0);	/* for this length */
899	outl(0x00000000c, card->pci_conf + DMADPR0);	/* In this direction */
900
901	/*
902	 * We use the dmarx_in_progress flag to flag the channel as busy
903	 */
904	card->dmarx_in_progress = 1;
905	outb(0x03, card->pci_conf + DMACSR0);	/* Start the transfer */
906}
907
908/*
909 *      Send a frame through the DMA
910 */
911static inline void
912fst_tx_dma(struct fst_card_info *card, dma_addr_t dma, u32 mem, int len)
913{
914	/*
915	 * This routine will setup the DMA and start it.
916	 */
917
918	dbg(DBG_TX, "In fst_tx_dma %x %x %d\n", (u32)dma, mem, len);
919	if (card->dmatx_in_progress) {
920		dbg(DBG_ASS, "In fst_tx_dma while dma in progress\n");
921	}
922
923	outl(dma, card->pci_conf + DMAPADR1);	/* Copy from here */
924	outl(mem, card->pci_conf + DMALADR1);	/* to here */
925	outl(len, card->pci_conf + DMASIZ1);	/* for this length */
926	outl(0x000000004, card->pci_conf + DMADPR1);	/* In this direction */
927
928	/*
929	 * We use the dmatx_in_progress to flag the channel as busy
930	 */
931	card->dmatx_in_progress = 1;
932	outb(0x03, card->pci_conf + DMACSR1);	/* Start the transfer */
933}
934
935/*      Issue a Mailbox command for a port.
936 *      Note we issue them on a fire and forget basis, not expecting to see an
937 *      error and not waiting for completion.
938 */
939static void
940fst_issue_cmd(struct fst_port_info *port, unsigned short cmd)
941{
942	struct fst_card_info *card;
943	unsigned short mbval;
944	unsigned long flags;
945	int safety;
946
947	card = port->card;
948	spin_lock_irqsave(&card->card_lock, flags);
949	mbval = FST_RDW(card, portMailbox[port->index][0]);
950
951	safety = 0;
952	/* Wait for any previous command to complete */
953	while (mbval > NAK) {
954		spin_unlock_irqrestore(&card->card_lock, flags);
955		schedule_timeout_uninterruptible(1);
956		spin_lock_irqsave(&card->card_lock, flags);
957
958		if (++safety > 2000) {
959			pr_err("Mailbox safety timeout\n");
960			break;
961		}
962
963		mbval = FST_RDW(card, portMailbox[port->index][0]);
964	}
965	if (safety > 0) {
966		dbg(DBG_CMD, "Mailbox clear after %d jiffies\n", safety);
967	}
968	if (mbval == NAK) {
969		dbg(DBG_CMD, "issue_cmd: previous command was NAK'd\n");
970	}
971
972	FST_WRW(card, portMailbox[port->index][0], cmd);
973
974	if (cmd == ABORTTX || cmd == STARTPORT) {
975		port->txpos = 0;
976		port->txipos = 0;
977		port->start = 0;
978	}
979
980	spin_unlock_irqrestore(&card->card_lock, flags);
981}
982
983/*      Port output signals control
984 */
985static inline void
986fst_op_raise(struct fst_port_info *port, unsigned int outputs)
987{
988	outputs |= FST_RDL(port->card, v24OpSts[port->index]);
989	FST_WRL(port->card, v24OpSts[port->index], outputs);
990
991	if (port->run)
992		fst_issue_cmd(port, SETV24O);
993}
994
995static inline void
996fst_op_lower(struct fst_port_info *port, unsigned int outputs)
997{
998	outputs = ~outputs & FST_RDL(port->card, v24OpSts[port->index]);
999	FST_WRL(port->card, v24OpSts[port->index], outputs);
1000
1001	if (port->run)
1002		fst_issue_cmd(port, SETV24O);
1003}
1004
1005/*
1006 *      Setup port Rx buffers
1007 */
1008static void
1009fst_rx_config(struct fst_port_info *port)
1010{
1011	int i;
1012	int pi;
1013	unsigned int offset;
1014	unsigned long flags;
1015	struct fst_card_info *card;
1016
1017	pi = port->index;
1018	card = port->card;
1019	spin_lock_irqsave(&card->card_lock, flags);
1020	for (i = 0; i < NUM_RX_BUFFER; i++) {
1021		offset = BUF_OFFSET(rxBuffer[pi][i][0]);
1022
1023		FST_WRW(card, rxDescrRing[pi][i].ladr, (u16) offset);
1024		FST_WRB(card, rxDescrRing[pi][i].hadr, (u8) (offset >> 16));
1025		FST_WRW(card, rxDescrRing[pi][i].bcnt, cnv_bcnt(LEN_RX_BUFFER));
1026		FST_WRW(card, rxDescrRing[pi][i].mcnt, LEN_RX_BUFFER);
1027		FST_WRB(card, rxDescrRing[pi][i].bits, DMA_OWN);
1028	}
1029	port->rxpos = 0;
1030	spin_unlock_irqrestore(&card->card_lock, flags);
1031}
1032
1033/*
1034 *      Setup port Tx buffers
1035 */
1036static void
1037fst_tx_config(struct fst_port_info *port)
1038{
1039	int i;
1040	int pi;
1041	unsigned int offset;
1042	unsigned long flags;
1043	struct fst_card_info *card;
1044
1045	pi = port->index;
1046	card = port->card;
1047	spin_lock_irqsave(&card->card_lock, flags);
1048	for (i = 0; i < NUM_TX_BUFFER; i++) {
1049		offset = BUF_OFFSET(txBuffer[pi][i][0]);
1050
1051		FST_WRW(card, txDescrRing[pi][i].ladr, (u16) offset);
1052		FST_WRB(card, txDescrRing[pi][i].hadr, (u8) (offset >> 16));
1053		FST_WRW(card, txDescrRing[pi][i].bcnt, 0);
1054		FST_WRB(card, txDescrRing[pi][i].bits, 0);
1055	}
1056	port->txpos = 0;
1057	port->txipos = 0;
1058	port->start = 0;
1059	spin_unlock_irqrestore(&card->card_lock, flags);
1060}
1061
1062/*      TE1 Alarm change interrupt event
1063 */
1064static void
1065fst_intr_te1_alarm(struct fst_card_info *card, struct fst_port_info *port)
1066{
1067	u8 los;
1068	u8 rra;
1069	u8 ais;
1070
1071	los = FST_RDB(card, suStatus.lossOfSignal);
1072	rra = FST_RDB(card, suStatus.receiveRemoteAlarm);
1073	ais = FST_RDB(card, suStatus.alarmIndicationSignal);
1074
1075	if (los) {
1076		/*
1077		 * Lost the link
1078		 */
1079		if (netif_carrier_ok(port_to_dev(port))) {
1080			dbg(DBG_INTR, "Net carrier off\n");
1081			netif_carrier_off(port_to_dev(port));
1082		}
1083	} else {
1084		/*
1085		 * Link available
1086		 */
1087		if (!netif_carrier_ok(port_to_dev(port))) {
1088			dbg(DBG_INTR, "Net carrier on\n");
1089			netif_carrier_on(port_to_dev(port));
1090		}
1091	}
1092
1093	if (los)
1094		dbg(DBG_INTR, "Assert LOS Alarm\n");
1095	else
1096		dbg(DBG_INTR, "De-assert LOS Alarm\n");
1097	if (rra)
1098		dbg(DBG_INTR, "Assert RRA Alarm\n");
1099	else
1100		dbg(DBG_INTR, "De-assert RRA Alarm\n");
1101
1102	if (ais)
1103		dbg(DBG_INTR, "Assert AIS Alarm\n");
1104	else
1105		dbg(DBG_INTR, "De-assert AIS Alarm\n");
1106}
1107
1108/*      Control signal change interrupt event
1109 */
1110static void
1111fst_intr_ctlchg(struct fst_card_info *card, struct fst_port_info *port)
1112{
1113	int signals;
1114
1115	signals = FST_RDL(card, v24DebouncedSts[port->index]);
1116
1117	if (signals & (((port->hwif == X21) || (port->hwif == X21D))
1118		       ? IPSTS_INDICATE : IPSTS_DCD)) {
1119		if (!netif_carrier_ok(port_to_dev(port))) {
1120			dbg(DBG_INTR, "DCD active\n");
1121			netif_carrier_on(port_to_dev(port));
1122		}
1123	} else {
1124		if (netif_carrier_ok(port_to_dev(port))) {
1125			dbg(DBG_INTR, "DCD lost\n");
1126			netif_carrier_off(port_to_dev(port));
1127		}
1128	}
1129}
1130
1131/*      Log Rx Errors
1132 */
1133static void
1134fst_log_rx_error(struct fst_card_info *card, struct fst_port_info *port,
1135		 unsigned char dmabits, int rxp, unsigned short len)
1136{
1137	struct net_device *dev = port_to_dev(port);
1138
1139	/*
1140	 * Increment the appropriate error counter
1141	 */
1142	dev->stats.rx_errors++;
1143	if (dmabits & RX_OFLO) {
1144		dev->stats.rx_fifo_errors++;
1145		dbg(DBG_ASS, "Rx fifo error on card %d port %d buffer %d\n",
1146		    card->card_no, port->index, rxp);
1147	}
1148	if (dmabits & RX_CRC) {
1149		dev->stats.rx_crc_errors++;
1150		dbg(DBG_ASS, "Rx crc error on card %d port %d\n",
1151		    card->card_no, port->index);
1152	}
1153	if (dmabits & RX_FRAM) {
1154		dev->stats.rx_frame_errors++;
1155		dbg(DBG_ASS, "Rx frame error on card %d port %d\n",
1156		    card->card_no, port->index);
1157	}
1158	if (dmabits == (RX_STP | RX_ENP)) {
1159		dev->stats.rx_length_errors++;
1160		dbg(DBG_ASS, "Rx length error (%d) on card %d port %d\n",
1161		    len, card->card_no, port->index);
1162	}
1163}
1164
1165/*      Rx Error Recovery
1166 */
1167static void
1168fst_recover_rx_error(struct fst_card_info *card, struct fst_port_info *port,
1169		     unsigned char dmabits, int rxp, unsigned short len)
1170{
1171	int i;
1172	int pi;
1173
1174	pi = port->index;
1175	/*
1176	 * Discard buffer descriptors until we see the start of the
1177	 * next frame.  Note that for long frames this could be in
1178	 * a subsequent interrupt.
1179	 */
1180	i = 0;
1181	while ((dmabits & (DMA_OWN | RX_STP)) == 0) {
1182		FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);
1183		rxp = (rxp+1) % NUM_RX_BUFFER;
1184		if (++i > NUM_RX_BUFFER) {
1185			dbg(DBG_ASS, "intr_rx: Discarding more bufs"
1186			    " than we have\n");
1187			break;
1188		}
1189		dmabits = FST_RDB(card, rxDescrRing[pi][rxp].bits);
1190		dbg(DBG_ASS, "DMA Bits of next buffer was %x\n", dmabits);
1191	}
1192	dbg(DBG_ASS, "There were %d subsequent buffers in error\n", i);
1193
1194	/* Discard the terminal buffer */
1195	if (!(dmabits & DMA_OWN)) {
1196		FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);
1197		rxp = (rxp+1) % NUM_RX_BUFFER;
1198	}
1199	port->rxpos = rxp;
1200	return;
1201
1202}
1203
1204/*      Rx complete interrupt
1205 */
1206static void
1207fst_intr_rx(struct fst_card_info *card, struct fst_port_info *port)
1208{
1209	unsigned char dmabits;
1210	int pi;
1211	int rxp;
1212	int rx_status;
1213	unsigned short len;
1214	struct sk_buff *skb;
1215	struct net_device *dev = port_to_dev(port);
1216
1217	/* Check we have a buffer to process */
1218	pi = port->index;
1219	rxp = port->rxpos;
1220	dmabits = FST_RDB(card, rxDescrRing[pi][rxp].bits);
1221	if (dmabits & DMA_OWN) {
1222		dbg(DBG_RX | DBG_INTR, "intr_rx: No buffer port %d pos %d\n",
1223		    pi, rxp);
1224		return;
1225	}
1226	if (card->dmarx_in_progress) {
1227		return;
1228	}
1229
1230	/* Get buffer length */
1231	len = FST_RDW(card, rxDescrRing[pi][rxp].mcnt);
1232	/* Discard the CRC */
1233	len -= 2;
1234	if (len == 0) {
1235		/*
1236		 * This seems to happen on the TE1 interface sometimes
1237		 * so throw the frame away and log the event.
1238		 */
1239		pr_err("Frame received with 0 length. Card %d Port %d\n",
1240		       card->card_no, port->index);
1241		/* Return descriptor to card */
1242		FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);
1243
1244		rxp = (rxp+1) % NUM_RX_BUFFER;
1245		port->rxpos = rxp;
1246		return;
1247	}
1248
1249	/* Check buffer length and for other errors. We insist on one packet
1250	 * in one buffer. This simplifies things greatly and since we've
1251	 * allocated 8K it shouldn't be a real world limitation
1252	 */
1253	dbg(DBG_RX, "intr_rx: %d,%d: flags %x len %d\n", pi, rxp, dmabits, len);
1254	if (dmabits != (RX_STP | RX_ENP) || len > LEN_RX_BUFFER - 2) {
1255		fst_log_rx_error(card, port, dmabits, rxp, len);
1256		fst_recover_rx_error(card, port, dmabits, rxp, len);
1257		return;
1258	}
1259
1260	/* Allocate SKB */
1261	if ((skb = dev_alloc_skb(len)) == NULL) {
1262		dbg(DBG_RX, "intr_rx: can't allocate buffer\n");
1263
1264		dev->stats.rx_dropped++;
1265
1266		/* Return descriptor to card */
1267		FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);
1268
1269		rxp = (rxp+1) % NUM_RX_BUFFER;
1270		port->rxpos = rxp;
1271		return;
1272	}
1273
1274	/*
1275	 * We know the length we need to receive, len.
1276	 * It's not worth using the DMA for reads of less than
1277	 * FST_MIN_DMA_LEN
1278	 */
1279
1280	if ((len < FST_MIN_DMA_LEN) || (card->family == FST_FAMILY_TXP)) {
1281		memcpy_fromio(skb_put(skb, len),
1282			      card->mem + BUF_OFFSET(rxBuffer[pi][rxp][0]),
1283			      len);
1284
1285		/* Reset buffer descriptor */
1286		FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);
1287
1288		/* Update stats */
1289		dev->stats.rx_packets++;
1290		dev->stats.rx_bytes += len;
1291
1292		/* Push upstream */
1293		dbg(DBG_RX, "Pushing frame up the stack\n");
1294		if (port->mode == FST_RAW)
1295			skb->protocol = farsync_type_trans(skb, dev);
1296		else
1297			skb->protocol = hdlc_type_trans(skb, dev);
1298		rx_status = netif_rx(skb);
1299		fst_process_rx_status(rx_status, port_to_dev(port)->name);
1300		if (rx_status == NET_RX_DROP)
1301			dev->stats.rx_dropped++;
1302	} else {
1303		card->dma_skb_rx = skb;
1304		card->dma_port_rx = port;
1305		card->dma_len_rx = len;
1306		card->dma_rxpos = rxp;
1307		fst_rx_dma(card, card->rx_dma_handle_card,
1308			   BUF_OFFSET(rxBuffer[pi][rxp][0]), len);
1309	}
1310	if (rxp != port->rxpos) {
1311		dbg(DBG_ASS, "About to increment rxpos by more than 1\n");
1312		dbg(DBG_ASS, "rxp = %d rxpos = %d\n", rxp, port->rxpos);
1313	}
1314	rxp = (rxp+1) % NUM_RX_BUFFER;
1315	port->rxpos = rxp;
1316}
1317
1318/*
1319 *      The bottom halfs to the ISR
1320 *
1321 */
1322
1323static void
1324do_bottom_half_tx(struct fst_card_info *card)
1325{
1326	struct fst_port_info *port;
1327	int pi;
1328	int txq_length;
1329	struct sk_buff *skb;
1330	unsigned long flags;
1331	struct net_device *dev;
1332
1333	/*
1334	 *  Find a free buffer for the transmit
1335	 *  Step through each port on this card
1336	 */
1337
1338	dbg(DBG_TX, "do_bottom_half_tx\n");
1339	for (pi = 0, port = card->ports; pi < card->nports; pi++, port++) {
1340		if (!port->run)
1341			continue;
1342
1343		dev = port_to_dev(port);
1344		while (!(FST_RDB(card, txDescrRing[pi][port->txpos].bits) &
1345			 DMA_OWN) &&
1346		       !(card->dmatx_in_progress)) {
1347			/*
1348			 * There doesn't seem to be a txdone event per-se
1349			 * We seem to have to deduce it, by checking the DMA_OWN
1350			 * bit on the next buffer we think we can use
1351			 */
1352			spin_lock_irqsave(&card->card_lock, flags);
1353			if ((txq_length = port->txqe - port->txqs) < 0) {
1354				/*
1355				 * This is the case where one has wrapped and the
1356				 * maths gives us a negative number
1357				 */
1358				txq_length = txq_length + FST_TXQ_DEPTH;
1359			}
1360			spin_unlock_irqrestore(&card->card_lock, flags);
1361			if (txq_length > 0) {
1362				/*
1363				 * There is something to send
1364				 */
1365				spin_lock_irqsave(&card->card_lock, flags);
1366				skb = port->txq[port->txqs];
1367				port->txqs++;
1368				if (port->txqs == FST_TXQ_DEPTH) {
1369					port->txqs = 0;
1370				}
1371				spin_unlock_irqrestore(&card->card_lock, flags);
1372				/*
1373				 * copy the data and set the required indicators on the
1374				 * card.
1375				 */
1376				FST_WRW(card, txDescrRing[pi][port->txpos].bcnt,
1377					cnv_bcnt(skb->len));
1378				if ((skb->len < FST_MIN_DMA_LEN) ||
1379				    (card->family == FST_FAMILY_TXP)) {
1380					/* Enqueue the packet with normal io */
1381					memcpy_toio(card->mem +
1382						    BUF_OFFSET(txBuffer[pi]
1383							       [port->
1384								txpos][0]),
1385						    skb->data, skb->len);
1386					FST_WRB(card,
1387						txDescrRing[pi][port->txpos].
1388						bits,
1389						DMA_OWN | TX_STP | TX_ENP);
1390					dev->stats.tx_packets++;
1391					dev->stats.tx_bytes += skb->len;
1392					dev->trans_start = jiffies;
1393				} else {
1394					/* Or do it through dma */
1395					memcpy(card->tx_dma_handle_host,
1396					       skb->data, skb->len);
1397					card->dma_port_tx = port;
1398					card->dma_len_tx = skb->len;
1399					card->dma_txpos = port->txpos;
1400					fst_tx_dma(card,
1401						   card->tx_dma_handle_card,
1402						   BUF_OFFSET(txBuffer[pi]
1403							      [port->txpos][0]),
1404						   skb->len);
1405				}
1406				if (++port->txpos >= NUM_TX_BUFFER)
1407					port->txpos = 0;
1408				/*
1409				 * If we have flow control on, can we now release it?
1410				 */
1411				if (port->start) {
1412					if (txq_length < fst_txq_low) {
1413						netif_wake_queue(port_to_dev
1414								 (port));
1415						port->start = 0;
1416					}
1417				}
1418				dev_kfree_skb(skb);
1419			} else {
1420				/*
1421				 * Nothing to send so break out of the while loop
1422				 */
1423				break;
1424			}
1425		}
1426	}
1427}
1428
1429static void
1430do_bottom_half_rx(struct fst_card_info *card)
1431{
1432	struct fst_port_info *port;
1433	int pi;
1434	int rx_count = 0;
1435
1436	/* Check for rx completions on all ports on this card */
1437	dbg(DBG_RX, "do_bottom_half_rx\n");
1438	for (pi = 0, port = card->ports; pi < card->nports; pi++, port++) {
1439		if (!port->run)
1440			continue;
1441
1442		while (!(FST_RDB(card, rxDescrRing[pi][port->rxpos].bits)
1443			 & DMA_OWN) && !(card->dmarx_in_progress)) {
1444			if (rx_count > fst_max_reads) {
1445				/*
1446				 * Don't spend forever in receive processing
1447				 * Schedule another event
1448				 */
1449				fst_q_work_item(&fst_work_intq, card->card_no);
1450				tasklet_schedule(&fst_int_task);
1451				break;	/* Leave the loop */
1452			}
1453			fst_intr_rx(card, port);
1454			rx_count++;
1455		}
1456	}
1457}
1458
1459/*
1460 *      The interrupt service routine
1461 *      Dev_id is our fst_card_info pointer
1462 */
1463static irqreturn_t
1464fst_intr(int dummy, void *dev_id)
1465{
1466	struct fst_card_info *card = dev_id;
1467	struct fst_port_info *port;
1468	int rdidx;		/* Event buffer indices */
1469	int wridx;
1470	int event;		/* Actual event for processing */
1471	unsigned int dma_intcsr = 0;
1472	unsigned int do_card_interrupt;
1473	unsigned int int_retry_count;
1474
1475	/*
1476	 * Check to see if the interrupt was for this card
1477	 * return if not
1478	 * Note that the call to clear the interrupt is important
1479	 */
1480	dbg(DBG_INTR, "intr: %d %p\n", card->irq, card);
1481	if (card->state != FST_RUNNING) {
1482		pr_err("Interrupt received for card %d in a non running state (%d)\n",
1483		       card->card_no, card->state);
1484
1485		/*
1486		 * It is possible to really be running, i.e. we have re-loaded
1487		 * a running card
1488		 * Clear and reprime the interrupt source
1489		 */
1490		fst_clear_intr(card);
1491		return IRQ_HANDLED;
1492	}
1493
1494	/* Clear and reprime the interrupt source */
1495	fst_clear_intr(card);
1496
1497	/*
1498	 * Is the interrupt for this card (handshake == 1)
1499	 */
1500	do_card_interrupt = 0;
1501	if (FST_RDB(card, interruptHandshake) == 1) {
1502		do_card_interrupt += FST_CARD_INT;
1503		/* Set the software acknowledge */
1504		FST_WRB(card, interruptHandshake, 0xEE);
1505	}
1506	if (card->family == FST_FAMILY_TXU) {
1507		/*
1508		 * Is it a DMA Interrupt
1509		 */
1510		dma_intcsr = inl(card->pci_conf + INTCSR_9054);
1511		if (dma_intcsr & 0x00200000) {
1512			/*
1513			 * DMA Channel 0 (Rx transfer complete)
1514			 */
1515			dbg(DBG_RX, "DMA Rx xfer complete\n");
1516			outb(0x8, card->pci_conf + DMACSR0);
1517			fst_rx_dma_complete(card, card->dma_port_rx,
1518					    card->dma_len_rx, card->dma_skb_rx,
1519					    card->dma_rxpos);
1520			card->dmarx_in_progress = 0;
1521			do_card_interrupt += FST_RX_DMA_INT;
1522		}
1523		if (dma_intcsr & 0x00400000) {
1524			/*
1525			 * DMA Channel 1 (Tx transfer complete)
1526			 */
1527			dbg(DBG_TX, "DMA Tx xfer complete\n");
1528			outb(0x8, card->pci_conf + DMACSR1);
1529			fst_tx_dma_complete(card, card->dma_port_tx,
1530					    card->dma_len_tx, card->dma_txpos);
1531			card->dmatx_in_progress = 0;
1532			do_card_interrupt += FST_TX_DMA_INT;
1533		}
1534	}
1535
1536	/*
1537	 * Have we been missing Interrupts
1538	 */
1539	int_retry_count = FST_RDL(card, interruptRetryCount);
1540	if (int_retry_count) {
1541		dbg(DBG_ASS, "Card %d int_retry_count is  %d\n",
1542		    card->card_no, int_retry_count);
1543		FST_WRL(card, interruptRetryCount, 0);
1544	}
1545
1546	if (!do_card_interrupt) {
1547		return IRQ_HANDLED;
1548	}
1549
1550	/* Scehdule the bottom half of the ISR */
1551	fst_q_work_item(&fst_work_intq, card->card_no);
1552	tasklet_schedule(&fst_int_task);
1553
1554	/* Drain the event queue */
1555	rdidx = FST_RDB(card, interruptEvent.rdindex) & 0x1f;
1556	wridx = FST_RDB(card, interruptEvent.wrindex) & 0x1f;
1557	while (rdidx != wridx) {
1558		event = FST_RDB(card, interruptEvent.evntbuff[rdidx]);
1559		port = &card->ports[event & 0x03];
1560
1561		dbg(DBG_INTR, "Processing Interrupt event: %x\n", event);
1562
1563		switch (event) {
1564		case TE1_ALMA:
1565			dbg(DBG_INTR, "TE1 Alarm intr\n");
1566			if (port->run)
1567				fst_intr_te1_alarm(card, port);
1568			break;
1569
1570		case CTLA_CHG:
1571		case CTLB_CHG:
1572		case CTLC_CHG:
1573		case CTLD_CHG:
1574			if (port->run)
1575				fst_intr_ctlchg(card, port);
1576			break;
1577
1578		case ABTA_SENT:
1579		case ABTB_SENT:
1580		case ABTC_SENT:
1581		case ABTD_SENT:
1582			dbg(DBG_TX, "Abort complete port %d\n", port->index);
1583			break;
1584
1585		case TXA_UNDF:
1586		case TXB_UNDF:
1587		case TXC_UNDF:
1588		case TXD_UNDF:
1589			/* Difficult to see how we'd get this given that we
1590			 * always load up the entire packet for DMA.
1591			 */
1592			dbg(DBG_TX, "Tx underflow port %d\n", port->index);
1593			port_to_dev(port)->stats.tx_errors++;
1594			port_to_dev(port)->stats.tx_fifo_errors++;
1595			dbg(DBG_ASS, "Tx underflow on card %d port %d\n",
1596			    card->card_no, port->index);
1597			break;
1598
1599		case INIT_CPLT:
1600			dbg(DBG_INIT, "Card init OK intr\n");
1601			break;
1602
1603		case INIT_FAIL:
1604			dbg(DBG_INIT, "Card init FAILED intr\n");
1605			card->state = FST_IFAILED;
1606			break;
1607
1608		default:
1609			pr_err("intr: unknown card event %d. ignored\n", event);
1610			break;
1611		}
1612
1613		/* Bump and wrap the index */
1614		if (++rdidx >= MAX_CIRBUFF)
1615			rdidx = 0;
1616	}
1617	FST_WRB(card, interruptEvent.rdindex, rdidx);
1618        return IRQ_HANDLED;
1619}
1620
1621/*      Check that the shared memory configuration is one that we can handle
1622 *      and that some basic parameters are correct
1623 */
1624static void
1625check_started_ok(struct fst_card_info *card)
1626{
1627	int i;
1628
1629	/* Check structure version and end marker */
1630	if (FST_RDW(card, smcVersion) != SMC_VERSION) {
1631		pr_err("Bad shared memory version %d expected %d\n",
1632		       FST_RDW(card, smcVersion), SMC_VERSION);
1633		card->state = FST_BADVERSION;
1634		return;
1635	}
1636	if (FST_RDL(card, endOfSmcSignature) != END_SIG) {
1637		pr_err("Missing shared memory signature\n");
1638		card->state = FST_BADVERSION;
1639		return;
1640	}
1641	/* Firmware status flag, 0x00 = initialising, 0x01 = OK, 0xFF = fail */
1642	if ((i = FST_RDB(card, taskStatus)) == 0x01) {
1643		card->state = FST_RUNNING;
1644	} else if (i == 0xFF) {
1645		pr_err("Firmware initialisation failed. Card halted\n");
1646		card->state = FST_HALTED;
1647		return;
1648	} else if (i != 0x00) {
1649		pr_err("Unknown firmware status 0x%x\n", i);
1650		card->state = FST_HALTED;
1651		return;
1652	}
1653
1654	/* Finally check the number of ports reported by firmware against the
1655	 * number we assumed at card detection. Should never happen with
1656	 * existing firmware etc so we just report it for the moment.
1657	 */
1658	if (FST_RDL(card, numberOfPorts) != card->nports) {
1659		pr_warn("Port count mismatch on card %d.  Firmware thinks %d we say %d\n",
1660			card->card_no,
1661			FST_RDL(card, numberOfPorts), card->nports);
1662	}
1663}
1664
1665static int
1666set_conf_from_info(struct fst_card_info *card, struct fst_port_info *port,
1667		   struct fstioc_info *info)
1668{
1669	int err;
1670	unsigned char my_framing;
1671
1672	/* Set things according to the user set valid flags
1673	 * Several of the old options have been invalidated/replaced by the
1674	 * generic hdlc package.
1675	 */
1676	err = 0;
1677	if (info->valid & FSTVAL_PROTO) {
1678		if (info->proto == FST_RAW)
1679			port->mode = FST_RAW;
1680		else
1681			port->mode = FST_GEN_HDLC;
1682	}
1683
1684	if (info->valid & FSTVAL_CABLE)
1685		err = -EINVAL;
1686
1687	if (info->valid & FSTVAL_SPEED)
1688		err = -EINVAL;
1689
1690	if (info->valid & FSTVAL_PHASE)
1691		FST_WRB(card, portConfig[port->index].invertClock,
1692			info->invertClock);
1693	if (info->valid & FSTVAL_MODE)
1694		FST_WRW(card, cardMode, info->cardMode);
1695	if (info->valid & FSTVAL_TE1) {
1696		FST_WRL(card, suConfig.dataRate, info->lineSpeed);
1697		FST_WRB(card, suConfig.clocking, info->clockSource);
1698		my_framing = FRAMING_E1;
1699		if (info->framing == E1)
1700			my_framing = FRAMING_E1;
1701		if (info->framing == T1)
1702			my_framing = FRAMING_T1;
1703		if (info->framing == J1)
1704			my_framing = FRAMING_J1;
1705		FST_WRB(card, suConfig.framing, my_framing);
1706		FST_WRB(card, suConfig.structure, info->structure);
1707		FST_WRB(card, suConfig.interface, info->interface);
1708		FST_WRB(card, suConfig.coding, info->coding);
1709		FST_WRB(card, suConfig.lineBuildOut, info->lineBuildOut);
1710		FST_WRB(card, suConfig.equalizer, info->equalizer);
1711		FST_WRB(card, suConfig.transparentMode, info->transparentMode);
1712		FST_WRB(card, suConfig.loopMode, info->loopMode);
1713		FST_WRB(card, suConfig.range, info->range);
1714		FST_WRB(card, suConfig.txBufferMode, info->txBufferMode);
1715		FST_WRB(card, suConfig.rxBufferMode, info->rxBufferMode);
1716		FST_WRB(card, suConfig.startingSlot, info->startingSlot);
1717		FST_WRB(card, suConfig.losThreshold, info->losThreshold);
1718		if (info->idleCode)
1719			FST_WRB(card, suConfig.enableIdleCode, 1);
1720		else
1721			FST_WRB(card, suConfig.enableIdleCode, 0);
1722		FST_WRB(card, suConfig.idleCode, info->idleCode);
1723#if FST_DEBUG
1724		if (info->valid & FSTVAL_TE1) {
1725			printk("Setting TE1 data\n");
1726			printk("Line Speed = %d\n", info->lineSpeed);
1727			printk("Start slot = %d\n", info->startingSlot);
1728			printk("Clock source = %d\n", info->clockSource);
1729			printk("Framing = %d\n", my_framing);
1730			printk("Structure = %d\n", info->structure);
1731			printk("interface = %d\n", info->interface);
1732			printk("Coding = %d\n", info->coding);
1733			printk("Line build out = %d\n", info->lineBuildOut);
1734			printk("Equaliser = %d\n", info->equalizer);
1735			printk("Transparent mode = %d\n",
1736			       info->transparentMode);
1737			printk("Loop mode = %d\n", info->loopMode);
1738			printk("Range = %d\n", info->range);
1739			printk("Tx Buffer mode = %d\n", info->txBufferMode);
1740			printk("Rx Buffer mode = %d\n", info->rxBufferMode);
1741			printk("LOS Threshold = %d\n", info->losThreshold);
1742			printk("Idle Code = %d\n", info->idleCode);
1743		}
1744#endif
1745	}
1746#if FST_DEBUG
1747	if (info->valid & FSTVAL_DEBUG) {
1748		fst_debug_mask = info->debug;
1749	}
1750#endif
1751
1752	return err;
1753}
1754
1755static void
1756gather_conf_info(struct fst_card_info *card, struct fst_port_info *port,
1757		 struct fstioc_info *info)
1758{
1759	int i;
1760
1761	memset(info, 0, sizeof (struct fstioc_info));
1762
1763	i = port->index;
1764	info->kernelVersion = LINUX_VERSION_CODE;
1765	info->nports = card->nports;
1766	info->type = card->type;
1767	info->state = card->state;
1768	info->proto = FST_GEN_HDLC;
1769	info->index = i;
1770#if FST_DEBUG
1771	info->debug = fst_debug_mask;
1772#endif
1773
1774	/* Only mark information as valid if card is running.
1775	 * Copy the data anyway in case it is useful for diagnostics
1776	 */
1777	info->valid = ((card->state == FST_RUNNING) ? FSTVAL_ALL : FSTVAL_CARD)
1778#if FST_DEBUG
1779	    | FSTVAL_DEBUG
1780#endif
1781	    ;
1782
1783	info->lineInterface = FST_RDW(card, portConfig[i].lineInterface);
1784	info->internalClock = FST_RDB(card, portConfig[i].internalClock);
1785	info->lineSpeed = FST_RDL(card, portConfig[i].lineSpeed);
1786	info->invertClock = FST_RDB(card, portConfig[i].invertClock);
1787	info->v24IpSts = FST_RDL(card, v24IpSts[i]);
1788	info->v24OpSts = FST_RDL(card, v24OpSts[i]);
1789	info->clockStatus = FST_RDW(card, clockStatus[i]);
1790	info->cableStatus = FST_RDW(card, cableStatus);
1791	info->cardMode = FST_RDW(card, cardMode);
1792	info->smcFirmwareVersion = FST_RDL(card, smcFirmwareVersion);
1793
1794	/*
1795	 * The T2U can report cable presence for both A or B
1796	 * in bits 0 and 1 of cableStatus.  See which port we are and
1797	 * do the mapping.
1798	 */
1799	if (card->family == FST_FAMILY_TXU) {
1800		if (port->index == 0) {
1801			/*
1802			 * Port A
1803			 */
1804			info->cableStatus = info->cableStatus & 1;
1805		} else {
1806			/*
1807			 * Port B
1808			 */
1809			info->cableStatus = info->cableStatus >> 1;
1810			info->cableStatus = info->cableStatus & 1;
1811		}
1812	}
1813	/*
1814	 * Some additional bits if we are TE1
1815	 */
1816	if (card->type == FST_TYPE_TE1) {
1817		info->lineSpeed = FST_RDL(card, suConfig.dataRate);
1818		info->clockSource = FST_RDB(card, suConfig.clocking);
1819		info->framing = FST_RDB(card, suConfig.framing);
1820		info->structure = FST_RDB(card, suConfig.structure);
1821		info->interface = FST_RDB(card, suConfig.interface);
1822		info->coding = FST_RDB(card, suConfig.coding);
1823		info->lineBuildOut = FST_RDB(card, suConfig.lineBuildOut);
1824		info->equalizer = FST_RDB(card, suConfig.equalizer);
1825		info->loopMode = FST_RDB(card, suConfig.loopMode);
1826		info->range = FST_RDB(card, suConfig.range);
1827		info->txBufferMode = FST_RDB(card, suConfig.txBufferMode);
1828		info->rxBufferMode = FST_RDB(card, suConfig.rxBufferMode);
1829		info->startingSlot = FST_RDB(card, suConfig.startingSlot);
1830		info->losThreshold = FST_RDB(card, suConfig.losThreshold);
1831		if (FST_RDB(card, suConfig.enableIdleCode))
1832			info->idleCode = FST_RDB(card, suConfig.idleCode);
1833		else
1834			info->idleCode = 0;
1835		info->receiveBufferDelay =
1836		    FST_RDL(card, suStatus.receiveBufferDelay);
1837		info->framingErrorCount =
1838		    FST_RDL(card, suStatus.framingErrorCount);
1839		info->codeViolationCount =
1840		    FST_RDL(card, suStatus.codeViolationCount);
1841		info->crcErrorCount = FST_RDL(card, suStatus.crcErrorCount);
1842		info->lineAttenuation = FST_RDL(card, suStatus.lineAttenuation);
1843		info->lossOfSignal = FST_RDB(card, suStatus.lossOfSignal);
1844		info->receiveRemoteAlarm =
1845		    FST_RDB(card, suStatus.receiveRemoteAlarm);
1846		info->alarmIndicationSignal =
1847		    FST_RDB(card, suStatus.alarmIndicationSignal);
1848	}
1849}
1850
1851static int
1852fst_set_iface(struct fst_card_info *card, struct fst_port_info *port,
1853	      struct ifreq *ifr)
1854{
1855	sync_serial_settings sync;
1856	int i;
1857
1858	if (ifr->ifr_settings.size != sizeof (sync)) {
1859		return -ENOMEM;
1860	}
1861
1862	if (copy_from_user
1863	    (&sync, ifr->ifr_settings.ifs_ifsu.sync, sizeof (sync))) {
1864		return -EFAULT;
1865	}
1866
1867	if (sync.loopback)
1868		return -EINVAL;
1869
1870	i = port->index;
1871
1872	switch (ifr->ifr_settings.type) {
1873	case IF_IFACE_V35:
1874		FST_WRW(card, portConfig[i].lineInterface, V35);
1875		port->hwif = V35;
1876		break;
1877
1878	case IF_IFACE_V24:
1879		FST_WRW(card, portConfig[i].lineInterface, V24);
1880		port->hwif = V24;
1881		break;
1882
1883	case IF_IFACE_X21:
1884		FST_WRW(card, portConfig[i].lineInterface, X21);
1885		port->hwif = X21;
1886		break;
1887
1888	case IF_IFACE_X21D:
1889		FST_WRW(card, portConfig[i].lineInterface, X21D);
1890		port->hwif = X21D;
1891		break;
1892
1893	case IF_IFACE_T1:
1894		FST_WRW(card, portConfig[i].lineInterface, T1);
1895		port->hwif = T1;
1896		break;
1897
1898	case IF_IFACE_E1:
1899		FST_WRW(card, portConfig[i].lineInterface, E1);
1900		port->hwif = E1;
1901		break;
1902
1903	case IF_IFACE_SYNC_SERIAL:
1904		break;
1905
1906	default:
1907		return -EINVAL;
1908	}
1909
1910	switch (sync.clock_type) {
1911	case CLOCK_EXT:
1912		FST_WRB(card, portConfig[i].internalClock, EXTCLK);
1913		break;
1914
1915	case CLOCK_INT:
1916		FST_WRB(card, portConfig[i].internalClock, INTCLK);
1917		break;
1918
1919	default:
1920		return -EINVAL;
1921	}
1922	FST_WRL(card, portConfig[i].lineSpeed, sync.clock_rate);
1923	return 0;
1924}
1925
1926static int
1927fst_get_iface(struct fst_card_info *card, struct fst_port_info *port,
1928	      struct ifreq *ifr)
1929{
1930	sync_serial_settings sync;
1931	int i;
1932
1933	/* First check what line type is set, we'll default to reporting X.21
1934	 * if nothing is set as IF_IFACE_SYNC_SERIAL implies it can't be
1935	 * changed
1936	 */
1937	switch (port->hwif) {
1938	case E1:
1939		ifr->ifr_settings.type = IF_IFACE_E1;
1940		break;
1941	case T1:
1942		ifr->ifr_settings.type = IF_IFACE_T1;
1943		break;
1944	case V35:
1945		ifr->ifr_settings.type = IF_IFACE_V35;
1946		break;
1947	case V24:
1948		ifr->ifr_settings.type = IF_IFACE_V24;
1949		break;
1950	case X21D:
1951		ifr->ifr_settings.type = IF_IFACE_X21D;
1952		break;
1953	case X21:
1954	default:
1955		ifr->ifr_settings.type = IF_IFACE_X21;
1956		break;
1957	}
1958	if (ifr->ifr_settings.size == 0) {
1959		return 0;	/* only type requested */
1960	}
1961	if (ifr->ifr_settings.size < sizeof (sync)) {
1962		return -ENOMEM;
1963	}
1964
1965	i = port->index;
1966	memset(&sync, 0, sizeof(sync));
1967	sync.clock_rate = FST_RDL(card, portConfig[i].lineSpeed);
1968	/* Lucky card and linux use same encoding here */
1969	sync.clock_type = FST_RDB(card, portConfig[i].internalClock) ==
1970	    INTCLK ? CLOCK_INT : CLOCK_EXT;
1971	sync.loopback = 0;
1972
1973	if (copy_to_user(ifr->ifr_settings.ifs_ifsu.sync, &sync, sizeof (sync))) {
1974		return -EFAULT;
1975	}
1976
1977	ifr->ifr_settings.size = sizeof (sync);
1978	return 0;
1979}
1980
1981static int
1982fst_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1983{
1984	struct fst_card_info *card;
1985	struct fst_port_info *port;
1986	struct fstioc_write wrthdr;
1987	struct fstioc_info info;
1988	unsigned long flags;
1989	void *buf;
1990
1991	dbg(DBG_IOCTL, "ioctl: %x, %p\n", cmd, ifr->ifr_data);
1992
1993	port = dev_to_port(dev);
1994	card = port->card;
1995
1996	if (!capable(CAP_NET_ADMIN))
1997		return -EPERM;
1998
1999	switch (cmd) {
2000	case FSTCPURESET:
2001		fst_cpureset(card);
2002		card->state = FST_RESET;
2003		return 0;
2004
2005	case FSTCPURELEASE:
2006		fst_cpurelease(card);
2007		card->state = FST_STARTING;
2008		return 0;
2009
2010	case FSTWRITE:		/* Code write (download) */
2011
2012		/* First copy in the header with the length and offset of data
2013		 * to write
2014		 */
2015		if (ifr->ifr_data == NULL) {
2016			return -EINVAL;
2017		}
2018		if (copy_from_user(&wrthdr, ifr->ifr_data,
2019				   sizeof (struct fstioc_write))) {
2020			return -EFAULT;
2021		}
2022
2023		/* Sanity check the parameters. We don't support partial writes
2024		 * when going over the top
2025		 */
2026		if (wrthdr.size > FST_MEMSIZE || wrthdr.offset > FST_MEMSIZE ||
2027		    wrthdr.size + wrthdr.offset > FST_MEMSIZE) {
2028			return -ENXIO;
2029		}
2030
2031		/* Now copy the data to the card. */
2032
2033		buf = memdup_user(ifr->ifr_data + sizeof(struct fstioc_write),
2034				  wrthdr.size);
2035		if (IS_ERR(buf))
2036			return PTR_ERR(buf);
2037
2038		memcpy_toio(card->mem + wrthdr.offset, buf, wrthdr.size);
2039		kfree(buf);
2040
2041		/* Writes to the memory of a card in the reset state constitute
2042		 * a download
2043		 */
2044		if (card->state == FST_RESET) {
2045			card->state = FST_DOWNLOAD;
2046		}
2047		return 0;
2048
2049	case FSTGETCONF:
2050
2051		/* If card has just been started check the shared memory config
2052		 * version and marker
2053		 */
2054		if (card->state == FST_STARTING) {
2055			check_started_ok(card);
2056
2057			/* If everything checked out enable card interrupts */
2058			if (card->state == FST_RUNNING) {
2059				spin_lock_irqsave(&card->card_lock, flags);
2060				fst_enable_intr(card);
2061				FST_WRB(card, interruptHandshake, 0xEE);
2062				spin_unlock_irqrestore(&card->card_lock, flags);
2063			}
2064		}
2065
2066		if (ifr->ifr_data == NULL) {
2067			return -EINVAL;
2068		}
2069
2070		gather_conf_info(card, port, &info);
2071
2072		if (copy_to_user(ifr->ifr_data, &info, sizeof (info))) {
2073			return -EFAULT;
2074		}
2075		return 0;
2076
2077	case FSTSETCONF:
2078
2079		/*
2080		 * Most of the settings have been moved to the generic ioctls
2081		 * this just covers debug and board ident now
2082		 */
2083
2084		if (card->state != FST_RUNNING) {
2085			pr_err("Attempt to configure card %d in non-running state (%d)\n",
2086			       card->card_no, card->state);
2087			return -EIO;
2088		}
2089		if (copy_from_user(&info, ifr->ifr_data, sizeof (info))) {
2090			return -EFAULT;
2091		}
2092
2093		return set_conf_from_info(card, port, &info);
2094
2095	case SIOCWANDEV:
2096		switch (ifr->ifr_settings.type) {
2097		case IF_GET_IFACE:
2098			return fst_get_iface(card, port, ifr);
2099
2100		case IF_IFACE_SYNC_SERIAL:
2101		case IF_IFACE_V35:
2102		case IF_IFACE_V24:
2103		case IF_IFACE_X21:
2104		case IF_IFACE_X21D:
2105		case IF_IFACE_T1:
2106		case IF_IFACE_E1:
2107			return fst_set_iface(card, port, ifr);
2108
2109		case IF_PROTO_RAW:
2110			port->mode = FST_RAW;
2111			return 0;
2112
2113		case IF_GET_PROTO:
2114			if (port->mode == FST_RAW) {
2115				ifr->ifr_settings.type = IF_PROTO_RAW;
2116				return 0;
2117			}
2118			return hdlc_ioctl(dev, ifr, cmd);
2119
2120		default:
2121			port->mode = FST_GEN_HDLC;
2122			dbg(DBG_IOCTL, "Passing this type to hdlc %x\n",
2123			    ifr->ifr_settings.type);
2124			return hdlc_ioctl(dev, ifr, cmd);
2125		}
2126
2127	default:
2128		/* Not one of ours. Pass through to HDLC package */
2129		return hdlc_ioctl(dev, ifr, cmd);
2130	}
2131}
2132
2133static void
2134fst_openport(struct fst_port_info *port)
2135{
2136	int signals;
2137	int txq_length;
2138
2139	/* Only init things if card is actually running. This allows open to
2140	 * succeed for downloads etc.
2141	 */
2142	if (port->card->state == FST_RUNNING) {
2143		if (port->run) {
2144			dbg(DBG_OPEN, "open: found port already running\n");
2145
2146			fst_issue_cmd(port, STOPPORT);
2147			port->run = 0;
2148		}
2149
2150		fst_rx_config(port);
2151		fst_tx_config(port);
2152		fst_op_raise(port, OPSTS_RTS | OPSTS_DTR);
2153
2154		fst_issue_cmd(port, STARTPORT);
2155		port->run = 1;
2156
2157		signals = FST_RDL(port->card, v24DebouncedSts[port->index]);
2158		if (signals & (((port->hwif == X21) || (port->hwif == X21D))
2159			       ? IPSTS_INDICATE : IPSTS_DCD))
2160			netif_carrier_on(port_to_dev(port));
2161		else
2162			netif_carrier_off(port_to_dev(port));
2163
2164		txq_length = port->txqe - port->txqs;
2165		port->txqe = 0;
2166		port->txqs = 0;
2167	}
2168
2169}
2170
2171static void
2172fst_closeport(struct fst_port_info *port)
2173{
2174	if (port->card->state == FST_RUNNING) {
2175		if (port->run) {
2176			port->run = 0;
2177			fst_op_lower(port, OPSTS_RTS | OPSTS_DTR);
2178
2179			fst_issue_cmd(port, STOPPORT);
2180		} else {
2181			dbg(DBG_OPEN, "close: port not running\n");
2182		}
2183	}
2184}
2185
2186static int
2187fst_open(struct net_device *dev)
2188{
2189	int err;
2190	struct fst_port_info *port;
2191
2192	port = dev_to_port(dev);
2193	if (!try_module_get(THIS_MODULE))
2194          return -EBUSY;
2195
2196	if (port->mode != FST_RAW) {
2197		err = hdlc_open(dev);
2198		if (err) {
2199			module_put(THIS_MODULE);
2200			return err;
2201		}
2202	}
2203
2204	fst_openport(port);
2205	netif_wake_queue(dev);
2206	return 0;
2207}
2208
2209static int
2210fst_close(struct net_device *dev)
2211{
2212	struct fst_port_info *port;
2213	struct fst_card_info *card;
2214	unsigned char tx_dma_done;
2215	unsigned char rx_dma_done;
2216
2217	port = dev_to_port(dev);
2218	card = port->card;
2219
2220	tx_dma_done = inb(card->pci_conf + DMACSR1);
2221	rx_dma_done = inb(card->pci_conf + DMACSR0);
2222	dbg(DBG_OPEN,
2223	    "Port Close: tx_dma_in_progress = %d (%x) rx_dma_in_progress = %d (%x)\n",
2224	    card->dmatx_in_progress, tx_dma_done, card->dmarx_in_progress,
2225	    rx_dma_done);
2226
2227	netif_stop_queue(dev);
2228	fst_closeport(dev_to_port(dev));
2229	if (port->mode != FST_RAW) {
2230		hdlc_close(dev);
2231	}
2232	module_put(THIS_MODULE);
2233	return 0;
2234}
2235
2236static int
2237fst_attach(struct net_device *dev, unsigned short encoding, unsigned short parity)
2238{
2239	/*
2240	 * Setting currently fixed in FarSync card so we check and forget
2241	 */
2242	if (encoding != ENCODING_NRZ || parity != PARITY_CRC16_PR1_CCITT)
2243		return -EINVAL;
2244	return 0;
2245}
2246
2247static void
2248fst_tx_timeout(struct net_device *dev)
2249{
2250	struct fst_port_info *port;
2251	struct fst_card_info *card;
2252
2253	port = dev_to_port(dev);
2254	card = port->card;
2255	dev->stats.tx_errors++;
2256	dev->stats.tx_aborted_errors++;
2257	dbg(DBG_ASS, "Tx timeout card %d port %d\n",
2258	    card->card_no, port->index);
2259	fst_issue_cmd(port, ABORTTX);
2260
2261	dev->trans_start = jiffies;
2262	netif_wake_queue(dev);
2263	port->start = 0;
2264}
2265
2266static netdev_tx_t
2267fst_start_xmit(struct sk_buff *skb, struct net_device *dev)
2268{
2269	struct fst_card_info *card;
2270	struct fst_port_info *port;
2271	unsigned long flags;
2272	int txq_length;
2273
2274	port = dev_to_port(dev);
2275	card = port->card;
2276	dbg(DBG_TX, "fst_start_xmit: length = %d\n", skb->len);
2277
2278	/* Drop packet with error if we don't have carrier */
2279	if (!netif_carrier_ok(dev)) {
2280		dev_kfree_skb(skb);
2281		dev->stats.tx_errors++;
2282		dev->stats.tx_carrier_errors++;
2283		dbg(DBG_ASS,
2284		    "Tried to transmit but no carrier on card %d port %d\n",
2285		    card->card_no, port->index);
2286		return NETDEV_TX_OK;
2287	}
2288
2289	/* Drop it if it's too big! MTU failure ? */
2290	if (skb->len > LEN_TX_BUFFER) {
2291		dbg(DBG_ASS, "Packet too large %d vs %d\n", skb->len,
2292		    LEN_TX_BUFFER);
2293		dev_kfree_skb(skb);
2294		dev->stats.tx_errors++;
2295		return NETDEV_TX_OK;
2296	}
2297
2298	/*
2299	 * We are always going to queue the packet
2300	 * so that the bottom half is the only place we tx from
2301	 * Check there is room in the port txq
2302	 */
2303	spin_lock_irqsave(&card->card_lock, flags);
2304	if ((txq_length = port->txqe - port->txqs) < 0) {
2305		/*
2306		 * This is the case where the next free has wrapped but the
2307		 * last used hasn't
2308		 */
2309		txq_length = txq_length + FST_TXQ_DEPTH;
2310	}
2311	spin_unlock_irqrestore(&card->card_lock, flags);
2312	if (txq_length > fst_txq_high) {
2313		/*
2314		 * We have got enough buffers in the pipeline.  Ask the network
2315		 * layer to stop sending frames down
2316		 */
2317		netif_stop_queue(dev);
2318		port->start = 1;	/* I'm using this to signal stop sent up */
2319	}
2320
2321	if (txq_length == FST_TXQ_DEPTH - 1) {
2322		/*
2323		 * This shouldn't have happened but such is life
2324		 */
2325		dev_kfree_skb(skb);
2326		dev->stats.tx_errors++;
2327		dbg(DBG_ASS, "Tx queue overflow card %d port %d\n",
2328		    card->card_no, port->index);
2329		return NETDEV_TX_OK;
2330	}
2331
2332	/*
2333	 * queue the buffer
2334	 */
2335	spin_lock_irqsave(&card->card_lock, flags);
2336	port->txq[port->txqe] = skb;
2337	port->txqe++;
2338	if (port->txqe == FST_TXQ_DEPTH)
2339		port->txqe = 0;
2340	spin_unlock_irqrestore(&card->card_lock, flags);
2341
2342	/* Scehdule the bottom half which now does transmit processing */
2343	fst_q_work_item(&fst_work_txq, card->card_no);
2344	tasklet_schedule(&fst_tx_task);
2345
2346	return NETDEV_TX_OK;
2347}
2348
2349/*
2350 *      Card setup having checked hardware resources.
2351 *      Should be pretty bizarre if we get an error here (kernel memory
2352 *      exhaustion is one possibility). If we do see a problem we report it
2353 *      via a printk and leave the corresponding interface and all that follow
2354 *      disabled.
2355 */
2356static char *type_strings[] = {
2357	"no hardware",		/* Should never be seen */
2358	"FarSync T2P",
2359	"FarSync T4P",
2360	"FarSync T1U",
2361	"FarSync T2U",
2362	"FarSync T4U",
2363	"FarSync TE1"
2364};
2365
2366static int
2367fst_init_card(struct fst_card_info *card)
2368{
2369	int i;
2370	int err;
2371
2372	/* We're working on a number of ports based on the card ID. If the
2373	 * firmware detects something different later (should never happen)
2374	 * we'll have to revise it in some way then.
2375	 */
2376	for (i = 0; i < card->nports; i++) {
2377		err = register_hdlc_device(card->ports[i].dev);
2378		if (err < 0) {
2379			pr_err("Cannot register HDLC device for port %d (errno %d)\n",
2380				i, -err);
2381			while (i--)
2382				unregister_hdlc_device(card->ports[i].dev);
2383			return err;
2384		}
2385	}
2386
2387	pr_info("%s-%s: %s IRQ%d, %d ports\n",
2388		port_to_dev(&card->ports[0])->name,
2389		port_to_dev(&card->ports[card->nports - 1])->name,
2390		type_strings[card->type], card->irq, card->nports);
2391	return 0;
2392}
2393
2394static const struct net_device_ops fst_ops = {
2395	.ndo_open       = fst_open,
2396	.ndo_stop       = fst_close,
2397	.ndo_change_mtu = hdlc_change_mtu,
2398	.ndo_start_xmit = hdlc_start_xmit,
2399	.ndo_do_ioctl   = fst_ioctl,
2400	.ndo_tx_timeout = fst_tx_timeout,
2401};
2402
2403/*
2404 *      Initialise card when detected.
2405 *      Returns 0 to indicate success, or errno otherwise.
2406 */
2407static int
2408fst_add_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2409{
2410	static int no_of_cards_added = 0;
2411	struct fst_card_info *card;
2412	int err = 0;
2413	int i;
2414
2415	printk_once(KERN_INFO
2416		    pr_fmt("FarSync WAN driver " FST_USER_VERSION
2417			   " (c) 2001-2004 FarSite Communications Ltd.\n"));
2418#if FST_DEBUG
2419	dbg(DBG_ASS, "The value of debug mask is %x\n", fst_debug_mask);
2420#endif
2421	/*
2422	 * We are going to be clever and allow certain cards not to be
2423	 * configured.  An exclude list can be provided in /etc/modules.conf
2424	 */
2425	if (fst_excluded_cards != 0) {
2426		/*
2427		 * There are cards to exclude
2428		 *
2429		 */
2430		for (i = 0; i < fst_excluded_cards; i++) {
2431			if ((pdev->devfn) >> 3 == fst_excluded_list[i]) {
2432				pr_info("FarSync PCI device %d not assigned\n",
2433					(pdev->devfn) >> 3);
2434				return -EBUSY;
2435			}
2436		}
2437	}
2438
2439	/* Allocate driver private data */
2440	card = kzalloc(sizeof(struct fst_card_info), GFP_KERNEL);
2441	if (card == NULL)
2442		return -ENOMEM;
2443
2444	/* Try to enable the device */
2445	if ((err = pci_enable_device(pdev)) != 0) {
2446		pr_err("Failed to enable card. Err %d\n", -err);
2447		goto enable_fail;
2448	}
2449
2450	if ((err = pci_request_regions(pdev, "FarSync")) !=0) {
2451		pr_err("Failed to allocate regions. Err %d\n", -err);
2452		goto regions_fail;
2453	}
2454
2455	/* Get virtual addresses of memory regions */
2456	card->pci_conf = pci_resource_start(pdev, 1);
2457	card->phys_mem = pci_resource_start(pdev, 2);
2458	card->phys_ctlmem = pci_resource_start(pdev, 3);
2459	if ((card->mem = ioremap(card->phys_mem, FST_MEMSIZE)) == NULL) {
2460		pr_err("Physical memory remap failed\n");
2461		err = -ENODEV;
2462		goto ioremap_physmem_fail;
2463	}
2464	if ((card->ctlmem = ioremap(card->phys_ctlmem, 0x10)) == NULL) {
2465		pr_err("Control memory remap failed\n");
2466		err = -ENODEV;
2467		goto ioremap_ctlmem_fail;
2468	}
2469	dbg(DBG_PCI, "kernel mem %p, ctlmem %p\n", card->mem, card->ctlmem);
2470
2471	/* Register the interrupt handler */
2472	if (request_irq(pdev->irq, fst_intr, IRQF_SHARED, FST_DEV_NAME, card)) {
2473		pr_err("Unable to register interrupt %d\n", card->irq);
2474		err = -ENODEV;
2475		goto irq_fail;
2476	}
2477
2478	/* Record info we need */
2479	card->irq = pdev->irq;
2480	card->type = ent->driver_data;
2481	card->family = ((ent->driver_data == FST_TYPE_T2P) ||
2482			(ent->driver_data == FST_TYPE_T4P))
2483	    ? FST_FAMILY_TXP : FST_FAMILY_TXU;
2484	if ((ent->driver_data == FST_TYPE_T1U) ||
2485	    (ent->driver_data == FST_TYPE_TE1))
2486		card->nports = 1;
2487	else
2488		card->nports = ((ent->driver_data == FST_TYPE_T2P) ||
2489				(ent->driver_data == FST_TYPE_T2U)) ? 2 : 4;
2490
2491	card->state = FST_UNINIT;
2492        spin_lock_init ( &card->card_lock );
2493
2494        for ( i = 0 ; i < card->nports ; i++ ) {
2495		struct net_device *dev = alloc_hdlcdev(&card->ports[i]);
2496		hdlc_device *hdlc;
2497		if (!dev) {
2498			while (i--)
2499				free_netdev(card->ports[i].dev);
2500			pr_err("FarSync: out of memory\n");
2501			err = -ENOMEM;
2502			goto hdlcdev_fail;
2503		}
2504		card->ports[i].dev    = dev;
2505                card->ports[i].card   = card;
2506                card->ports[i].index  = i;
2507                card->ports[i].run    = 0;
2508
2509		hdlc = dev_to_hdlc(dev);
2510
2511                /* Fill in the net device info */
2512		/* Since this is a PCI setup this is purely
2513		 * informational. Give them the buffer addresses
2514		 * and basic card I/O.
2515		 */
2516                dev->mem_start   = card->phys_mem
2517                                 + BUF_OFFSET ( txBuffer[i][0][0]);
2518                dev->mem_end     = card->phys_mem
2519                                 + BUF_OFFSET ( txBuffer[i][NUM_TX_BUFFER][0]);
2520                dev->base_addr   = card->pci_conf;
2521                dev->irq         = card->irq;
2522
2523		dev->netdev_ops = &fst_ops;
2524		dev->tx_queue_len = FST_TX_QUEUE_LEN;
2525		dev->watchdog_timeo = FST_TX_TIMEOUT;
2526                hdlc->attach = fst_attach;
2527                hdlc->xmit   = fst_start_xmit;
2528	}
2529
2530	card->device = pdev;
2531
2532	dbg(DBG_PCI, "type %d nports %d irq %d\n", card->type,
2533	    card->nports, card->irq);
2534	dbg(DBG_PCI, "conf %04x mem %08x ctlmem %08x\n",
2535	    card->pci_conf, card->phys_mem, card->phys_ctlmem);
2536
2537	/* Reset the card's processor */
2538	fst_cpureset(card);
2539	card->state = FST_RESET;
2540
2541	/* Initialise DMA (if required) */
2542	fst_init_dma(card);
2543
2544	/* Record driver data for later use */
2545	pci_set_drvdata(pdev, card);
2546
2547	/* Remainder of card setup */
2548	if (no_of_cards_added >= FST_MAX_CARDS) {
2549		pr_err("FarSync: too many cards\n");
2550		err = -ENOMEM;
2551		goto card_array_fail;
2552	}
2553	fst_card_array[no_of_cards_added] = card;
2554	card->card_no = no_of_cards_added++;	/* Record instance and bump it */
2555	err = fst_init_card(card);
2556	if (err)
2557		goto init_card_fail;
2558	if (card->family == FST_FAMILY_TXU) {
2559		/*
2560		 * Allocate a dma buffer for transmit and receives
2561		 */
2562		card->rx_dma_handle_host =
2563		    pci_alloc_consistent(card->device, FST_MAX_MTU,
2564					 &card->rx_dma_handle_card);
2565		if (card->rx_dma_handle_host == NULL) {
2566			pr_err("Could not allocate rx dma buffer\n");
2567			err = -ENOMEM;
2568			goto rx_dma_fail;
2569		}
2570		card->tx_dma_handle_host =
2571		    pci_alloc_consistent(card->device, FST_MAX_MTU,
2572					 &card->tx_dma_handle_card);
2573		if (card->tx_dma_handle_host == NULL) {
2574			pr_err("Could not allocate tx dma buffer\n");
2575			err = -ENOMEM;
2576			goto tx_dma_fail;
2577		}
2578	}
2579	return 0;		/* Success */
2580
2581tx_dma_fail:
2582	pci_free_consistent(card->device, FST_MAX_MTU,
2583			    card->rx_dma_handle_host,
2584			    card->rx_dma_handle_card);
2585rx_dma_fail:
2586	fst_disable_intr(card);
2587	for (i = 0 ; i < card->nports ; i++)
2588		unregister_hdlc_device(card->ports[i].dev);
2589init_card_fail:
2590	fst_card_array[card->card_no] = NULL;
2591card_array_fail:
2592	for (i = 0 ; i < card->nports ; i++)
2593		free_netdev(card->ports[i].dev);
2594hdlcdev_fail:
2595	free_irq(card->irq, card);
2596irq_fail:
2597	iounmap(card->ctlmem);
2598ioremap_ctlmem_fail:
2599	iounmap(card->mem);
2600ioremap_physmem_fail:
2601	pci_release_regions(pdev);
2602regions_fail:
2603	pci_disable_device(pdev);
2604enable_fail:
2605	kfree(card);
2606	return err;
2607}
2608
2609/*
2610 *      Cleanup and close down a card
2611 */
2612static void
2613fst_remove_one(struct pci_dev *pdev)
2614{
2615	struct fst_card_info *card;
2616	int i;
2617
2618	card = pci_get_drvdata(pdev);
2619
2620	for (i = 0; i < card->nports; i++) {
2621		struct net_device *dev = port_to_dev(&card->ports[i]);
2622		unregister_hdlc_device(dev);
2623	}
2624
2625	fst_disable_intr(card);
2626	free_irq(card->irq, card);
2627
2628	iounmap(card->ctlmem);
2629	iounmap(card->mem);
2630	pci_release_regions(pdev);
2631	if (card->family == FST_FAMILY_TXU) {
2632		/*
2633		 * Free dma buffers
2634		 */
2635		pci_free_consistent(card->device, FST_MAX_MTU,
2636				    card->rx_dma_handle_host,
2637				    card->rx_dma_handle_card);
2638		pci_free_consistent(card->device, FST_MAX_MTU,
2639				    card->tx_dma_handle_host,
2640				    card->tx_dma_handle_card);
2641	}
2642	fst_card_array[card->card_no] = NULL;
2643}
2644
2645static struct pci_driver fst_driver = {
2646        .name		= FST_NAME,
2647        .id_table	= fst_pci_dev_id,
2648        .probe		= fst_add_one,
2649        .remove	= fst_remove_one,
2650        .suspend	= NULL,
2651        .resume	= NULL,
2652};
2653
2654static int __init
2655fst_init(void)
2656{
2657	int i;
2658
2659	for (i = 0; i < FST_MAX_CARDS; i++)
2660		fst_card_array[i] = NULL;
2661	spin_lock_init(&fst_work_q_lock);
2662	return pci_register_driver(&fst_driver);
2663}
2664
2665static void __exit
2666fst_cleanup_module(void)
2667{
2668	pr_info("FarSync WAN driver unloading\n");
2669	pci_unregister_driver(&fst_driver);
2670}
2671
2672module_init(fst_init);
2673module_exit(fst_cleanup_module);
2674