1/* 2 * drivers/net/phy/micrel.c 3 * 4 * Driver for Micrel PHYs 5 * 6 * Author: David J. Choi 7 * 8 * Copyright (c) 2010-2013 Micrel, Inc. 9 * Copyright (c) 2014 Johan Hovold <johan@kernel.org> 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the 13 * Free Software Foundation; either version 2 of the License, or (at your 14 * option) any later version. 15 * 16 * Support : Micrel Phys: 17 * Giga phys: ksz9021, ksz9031 18 * 100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041 19 * ksz8021, ksz8031, ksz8051, 20 * ksz8081, ksz8091, 21 * ksz8061, 22 * Switch : ksz8873, ksz886x 23 */ 24 25#include <linux/kernel.h> 26#include <linux/module.h> 27#include <linux/phy.h> 28#include <linux/micrel_phy.h> 29#include <linux/of.h> 30#include <linux/clk.h> 31 32/* Operation Mode Strap Override */ 33#define MII_KSZPHY_OMSO 0x16 34#define KSZPHY_OMSO_B_CAST_OFF BIT(9) 35#define KSZPHY_OMSO_NAND_TREE_ON BIT(5) 36#define KSZPHY_OMSO_RMII_OVERRIDE BIT(1) 37#define KSZPHY_OMSO_MII_OVERRIDE BIT(0) 38 39/* general Interrupt control/status reg in vendor specific block. */ 40#define MII_KSZPHY_INTCS 0x1B 41#define KSZPHY_INTCS_JABBER BIT(15) 42#define KSZPHY_INTCS_RECEIVE_ERR BIT(14) 43#define KSZPHY_INTCS_PAGE_RECEIVE BIT(13) 44#define KSZPHY_INTCS_PARELLEL BIT(12) 45#define KSZPHY_INTCS_LINK_PARTNER_ACK BIT(11) 46#define KSZPHY_INTCS_LINK_DOWN BIT(10) 47#define KSZPHY_INTCS_REMOTE_FAULT BIT(9) 48#define KSZPHY_INTCS_LINK_UP BIT(8) 49#define KSZPHY_INTCS_ALL (KSZPHY_INTCS_LINK_UP |\ 50 KSZPHY_INTCS_LINK_DOWN) 51 52/* PHY Control 1 */ 53#define MII_KSZPHY_CTRL_1 0x1e 54 55/* PHY Control 2 / PHY Control (if no PHY Control 1) */ 56#define MII_KSZPHY_CTRL_2 0x1f 57#define MII_KSZPHY_CTRL MII_KSZPHY_CTRL_2 58/* bitmap of PHY register to set interrupt mode */ 59#define KSZPHY_CTRL_INT_ACTIVE_HIGH BIT(9) 60#define KSZPHY_RMII_REF_CLK_SEL BIT(7) 61 62/* Write/read to/from extended registers */ 63#define MII_KSZPHY_EXTREG 0x0b 64#define KSZPHY_EXTREG_WRITE 0x8000 65 66#define MII_KSZPHY_EXTREG_WRITE 0x0c 67#define MII_KSZPHY_EXTREG_READ 0x0d 68 69/* Extended registers */ 70#define MII_KSZPHY_CLK_CONTROL_PAD_SKEW 0x104 71#define MII_KSZPHY_RX_DATA_PAD_SKEW 0x105 72#define MII_KSZPHY_TX_DATA_PAD_SKEW 0x106 73 74#define PS_TO_REG 200 75 76struct kszphy_type { 77 u32 led_mode_reg; 78 u16 interrupt_level_mask; 79 bool has_broadcast_disable; 80 bool has_nand_tree_disable; 81 bool has_rmii_ref_clk_sel; 82}; 83 84struct kszphy_priv { 85 const struct kszphy_type *type; 86 int led_mode; 87 bool rmii_ref_clk_sel; 88 bool rmii_ref_clk_sel_val; 89}; 90 91static const struct kszphy_type ksz8021_type = { 92 .led_mode_reg = MII_KSZPHY_CTRL_2, 93 .has_broadcast_disable = true, 94 .has_nand_tree_disable = true, 95 .has_rmii_ref_clk_sel = true, 96}; 97 98static const struct kszphy_type ksz8041_type = { 99 .led_mode_reg = MII_KSZPHY_CTRL_1, 100}; 101 102static const struct kszphy_type ksz8051_type = { 103 .led_mode_reg = MII_KSZPHY_CTRL_2, 104 .has_nand_tree_disable = true, 105}; 106 107static const struct kszphy_type ksz8081_type = { 108 .led_mode_reg = MII_KSZPHY_CTRL_2, 109 .has_broadcast_disable = true, 110 .has_nand_tree_disable = true, 111 .has_rmii_ref_clk_sel = true, 112}; 113 114static const struct kszphy_type ks8737_type = { 115 .interrupt_level_mask = BIT(14), 116}; 117 118static const struct kszphy_type ksz9021_type = { 119 .interrupt_level_mask = BIT(14), 120}; 121 122static int kszphy_extended_write(struct phy_device *phydev, 123 u32 regnum, u16 val) 124{ 125 phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum); 126 return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val); 127} 128 129static int kszphy_extended_read(struct phy_device *phydev, 130 u32 regnum) 131{ 132 phy_write(phydev, MII_KSZPHY_EXTREG, regnum); 133 return phy_read(phydev, MII_KSZPHY_EXTREG_READ); 134} 135 136static int kszphy_ack_interrupt(struct phy_device *phydev) 137{ 138 /* bit[7..0] int status, which is a read and clear register. */ 139 int rc; 140 141 rc = phy_read(phydev, MII_KSZPHY_INTCS); 142 143 return (rc < 0) ? rc : 0; 144} 145 146static int kszphy_config_intr(struct phy_device *phydev) 147{ 148 const struct kszphy_type *type = phydev->drv->driver_data; 149 int temp; 150 u16 mask; 151 152 if (type && type->interrupt_level_mask) 153 mask = type->interrupt_level_mask; 154 else 155 mask = KSZPHY_CTRL_INT_ACTIVE_HIGH; 156 157 /* set the interrupt pin active low */ 158 temp = phy_read(phydev, MII_KSZPHY_CTRL); 159 if (temp < 0) 160 return temp; 161 temp &= ~mask; 162 phy_write(phydev, MII_KSZPHY_CTRL, temp); 163 164 /* enable / disable interrupts */ 165 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) 166 temp = KSZPHY_INTCS_ALL; 167 else 168 temp = 0; 169 170 return phy_write(phydev, MII_KSZPHY_INTCS, temp); 171} 172 173static int kszphy_rmii_clk_sel(struct phy_device *phydev, bool val) 174{ 175 int ctrl; 176 177 ctrl = phy_read(phydev, MII_KSZPHY_CTRL); 178 if (ctrl < 0) 179 return ctrl; 180 181 if (val) 182 ctrl |= KSZPHY_RMII_REF_CLK_SEL; 183 else 184 ctrl &= ~KSZPHY_RMII_REF_CLK_SEL; 185 186 return phy_write(phydev, MII_KSZPHY_CTRL, ctrl); 187} 188 189static int kszphy_setup_led(struct phy_device *phydev, u32 reg, int val) 190{ 191 int rc, temp, shift; 192 193 switch (reg) { 194 case MII_KSZPHY_CTRL_1: 195 shift = 14; 196 break; 197 case MII_KSZPHY_CTRL_2: 198 shift = 4; 199 break; 200 default: 201 return -EINVAL; 202 } 203 204 temp = phy_read(phydev, reg); 205 if (temp < 0) { 206 rc = temp; 207 goto out; 208 } 209 210 temp &= ~(3 << shift); 211 temp |= val << shift; 212 rc = phy_write(phydev, reg, temp); 213out: 214 if (rc < 0) 215 dev_err(&phydev->dev, "failed to set led mode\n"); 216 217 return rc; 218} 219 220/* Disable PHY address 0 as the broadcast address, so that it can be used as a 221 * unique (non-broadcast) address on a shared bus. 222 */ 223static int kszphy_broadcast_disable(struct phy_device *phydev) 224{ 225 int ret; 226 227 ret = phy_read(phydev, MII_KSZPHY_OMSO); 228 if (ret < 0) 229 goto out; 230 231 ret = phy_write(phydev, MII_KSZPHY_OMSO, ret | KSZPHY_OMSO_B_CAST_OFF); 232out: 233 if (ret) 234 dev_err(&phydev->dev, "failed to disable broadcast address\n"); 235 236 return ret; 237} 238 239static int kszphy_nand_tree_disable(struct phy_device *phydev) 240{ 241 int ret; 242 243 ret = phy_read(phydev, MII_KSZPHY_OMSO); 244 if (ret < 0) 245 goto out; 246 247 if (!(ret & KSZPHY_OMSO_NAND_TREE_ON)) 248 return 0; 249 250 ret = phy_write(phydev, MII_KSZPHY_OMSO, 251 ret & ~KSZPHY_OMSO_NAND_TREE_ON); 252out: 253 if (ret) 254 dev_err(&phydev->dev, "failed to disable NAND tree mode\n"); 255 256 return ret; 257} 258 259static int kszphy_config_init(struct phy_device *phydev) 260{ 261 struct kszphy_priv *priv = phydev->priv; 262 const struct kszphy_type *type; 263 int ret; 264 265 if (!priv) 266 return 0; 267 268 type = priv->type; 269 270 if (type->has_broadcast_disable) 271 kszphy_broadcast_disable(phydev); 272 273 if (type->has_nand_tree_disable) 274 kszphy_nand_tree_disable(phydev); 275 276 if (priv->rmii_ref_clk_sel) { 277 ret = kszphy_rmii_clk_sel(phydev, priv->rmii_ref_clk_sel_val); 278 if (ret) { 279 dev_err(&phydev->dev, "failed to set rmii reference clock\n"); 280 return ret; 281 } 282 } 283 284 if (priv->led_mode >= 0) 285 kszphy_setup_led(phydev, type->led_mode_reg, priv->led_mode); 286 287 return 0; 288} 289 290static int ksz9021_load_values_from_of(struct phy_device *phydev, 291 struct device_node *of_node, u16 reg, 292 char *field1, char *field2, 293 char *field3, char *field4) 294{ 295 int val1 = -1; 296 int val2 = -2; 297 int val3 = -3; 298 int val4 = -4; 299 int newval; 300 int matches = 0; 301 302 if (!of_property_read_u32(of_node, field1, &val1)) 303 matches++; 304 305 if (!of_property_read_u32(of_node, field2, &val2)) 306 matches++; 307 308 if (!of_property_read_u32(of_node, field3, &val3)) 309 matches++; 310 311 if (!of_property_read_u32(of_node, field4, &val4)) 312 matches++; 313 314 if (!matches) 315 return 0; 316 317 if (matches < 4) 318 newval = kszphy_extended_read(phydev, reg); 319 else 320 newval = 0; 321 322 if (val1 != -1) 323 newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0); 324 325 if (val2 != -2) 326 newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4); 327 328 if (val3 != -3) 329 newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8); 330 331 if (val4 != -4) 332 newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12); 333 334 return kszphy_extended_write(phydev, reg, newval); 335} 336 337static int ksz9021_config_init(struct phy_device *phydev) 338{ 339 struct device *dev = &phydev->dev; 340 struct device_node *of_node = dev->of_node; 341 342 if (!of_node && dev->parent->of_node) 343 of_node = dev->parent->of_node; 344 345 if (of_node) { 346 ksz9021_load_values_from_of(phydev, of_node, 347 MII_KSZPHY_CLK_CONTROL_PAD_SKEW, 348 "txen-skew-ps", "txc-skew-ps", 349 "rxdv-skew-ps", "rxc-skew-ps"); 350 ksz9021_load_values_from_of(phydev, of_node, 351 MII_KSZPHY_RX_DATA_PAD_SKEW, 352 "rxd0-skew-ps", "rxd1-skew-ps", 353 "rxd2-skew-ps", "rxd3-skew-ps"); 354 ksz9021_load_values_from_of(phydev, of_node, 355 MII_KSZPHY_TX_DATA_PAD_SKEW, 356 "txd0-skew-ps", "txd1-skew-ps", 357 "txd2-skew-ps", "txd3-skew-ps"); 358 } 359 return 0; 360} 361 362#define MII_KSZ9031RN_MMD_CTRL_REG 0x0d 363#define MII_KSZ9031RN_MMD_REGDATA_REG 0x0e 364#define OP_DATA 1 365#define KSZ9031_PS_TO_REG 60 366 367/* Extended registers */ 368#define MII_KSZ9031RN_CONTROL_PAD_SKEW 4 369#define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5 370#define MII_KSZ9031RN_TX_DATA_PAD_SKEW 6 371#define MII_KSZ9031RN_CLK_PAD_SKEW 8 372 373static int ksz9031_extended_write(struct phy_device *phydev, 374 u8 mode, u32 dev_addr, u32 regnum, u16 val) 375{ 376 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr); 377 phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum); 378 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr); 379 return phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, val); 380} 381 382static int ksz9031_extended_read(struct phy_device *phydev, 383 u8 mode, u32 dev_addr, u32 regnum) 384{ 385 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr); 386 phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum); 387 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr); 388 return phy_read(phydev, MII_KSZ9031RN_MMD_REGDATA_REG); 389} 390 391static int ksz9031_of_load_skew_values(struct phy_device *phydev, 392 struct device_node *of_node, 393 u16 reg, size_t field_sz, 394 char *field[], u8 numfields) 395{ 396 int val[4] = {-1, -2, -3, -4}; 397 int matches = 0; 398 u16 mask; 399 u16 maxval; 400 u16 newval; 401 int i; 402 403 for (i = 0; i < numfields; i++) 404 if (!of_property_read_u32(of_node, field[i], val + i)) 405 matches++; 406 407 if (!matches) 408 return 0; 409 410 if (matches < numfields) 411 newval = ksz9031_extended_read(phydev, OP_DATA, 2, reg); 412 else 413 newval = 0; 414 415 maxval = (field_sz == 4) ? 0xf : 0x1f; 416 for (i = 0; i < numfields; i++) 417 if (val[i] != -(i + 1)) { 418 mask = 0xffff; 419 mask ^= maxval << (field_sz * i); 420 newval = (newval & mask) | 421 (((val[i] / KSZ9031_PS_TO_REG) & maxval) 422 << (field_sz * i)); 423 } 424 425 return ksz9031_extended_write(phydev, OP_DATA, 2, reg, newval); 426} 427 428static int ksz9031_config_init(struct phy_device *phydev) 429{ 430 struct device *dev = &phydev->dev; 431 struct device_node *of_node = dev->of_node; 432 char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"}; 433 char *rx_data_skews[4] = { 434 "rxd0-skew-ps", "rxd1-skew-ps", 435 "rxd2-skew-ps", "rxd3-skew-ps" 436 }; 437 char *tx_data_skews[4] = { 438 "txd0-skew-ps", "txd1-skew-ps", 439 "txd2-skew-ps", "txd3-skew-ps" 440 }; 441 char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"}; 442 443 if (!of_node && dev->parent->of_node) 444 of_node = dev->parent->of_node; 445 446 if (of_node) { 447 ksz9031_of_load_skew_values(phydev, of_node, 448 MII_KSZ9031RN_CLK_PAD_SKEW, 5, 449 clk_skews, 2); 450 451 ksz9031_of_load_skew_values(phydev, of_node, 452 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4, 453 control_skews, 2); 454 455 ksz9031_of_load_skew_values(phydev, of_node, 456 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4, 457 rx_data_skews, 4); 458 459 ksz9031_of_load_skew_values(phydev, of_node, 460 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4, 461 tx_data_skews, 4); 462 } 463 return 0; 464} 465 466#define KSZ8873MLL_GLOBAL_CONTROL_4 0x06 467#define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX BIT(6) 468#define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED BIT(4) 469static int ksz8873mll_read_status(struct phy_device *phydev) 470{ 471 int regval; 472 473 /* dummy read */ 474 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4); 475 476 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4); 477 478 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX) 479 phydev->duplex = DUPLEX_HALF; 480 else 481 phydev->duplex = DUPLEX_FULL; 482 483 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED) 484 phydev->speed = SPEED_10; 485 else 486 phydev->speed = SPEED_100; 487 488 phydev->link = 1; 489 phydev->pause = phydev->asym_pause = 0; 490 491 return 0; 492} 493 494static int ksz8873mll_config_aneg(struct phy_device *phydev) 495{ 496 return 0; 497} 498 499/* This routine returns -1 as an indication to the caller that the 500 * Micrel ksz9021 10/100/1000 PHY does not support standard IEEE 501 * MMD extended PHY registers. 502 */ 503static int 504ksz9021_rd_mmd_phyreg(struct phy_device *phydev, int ptrad, int devnum, 505 int regnum) 506{ 507 return -1; 508} 509 510/* This routine does nothing since the Micrel ksz9021 does not support 511 * standard IEEE MMD extended PHY registers. 512 */ 513static void 514ksz9021_wr_mmd_phyreg(struct phy_device *phydev, int ptrad, int devnum, 515 int regnum, u32 val) 516{ 517} 518 519static int kszphy_probe(struct phy_device *phydev) 520{ 521 const struct kszphy_type *type = phydev->drv->driver_data; 522 struct device_node *np = phydev->dev.of_node; 523 struct kszphy_priv *priv; 524 struct clk *clk; 525 int ret; 526 527 priv = devm_kzalloc(&phydev->dev, sizeof(*priv), GFP_KERNEL); 528 if (!priv) 529 return -ENOMEM; 530 531 phydev->priv = priv; 532 533 priv->type = type; 534 535 if (type->led_mode_reg) { 536 ret = of_property_read_u32(np, "micrel,led-mode", 537 &priv->led_mode); 538 if (ret) 539 priv->led_mode = -1; 540 541 if (priv->led_mode > 3) { 542 dev_err(&phydev->dev, "invalid led mode: 0x%02x\n", 543 priv->led_mode); 544 priv->led_mode = -1; 545 } 546 } else { 547 priv->led_mode = -1; 548 } 549 550 clk = devm_clk_get(&phydev->dev, "rmii-ref"); 551 /* NOTE: clk may be NULL if building without CONFIG_HAVE_CLK */ 552 if (!IS_ERR_OR_NULL(clk)) { 553 unsigned long rate = clk_get_rate(clk); 554 bool rmii_ref_clk_sel_25_mhz; 555 556 priv->rmii_ref_clk_sel = type->has_rmii_ref_clk_sel; 557 rmii_ref_clk_sel_25_mhz = of_property_read_bool(np, 558 "micrel,rmii-reference-clock-select-25-mhz"); 559 560 if (rate > 24500000 && rate < 25500000) { 561 priv->rmii_ref_clk_sel_val = rmii_ref_clk_sel_25_mhz; 562 } else if (rate > 49500000 && rate < 50500000) { 563 priv->rmii_ref_clk_sel_val = !rmii_ref_clk_sel_25_mhz; 564 } else { 565 dev_err(&phydev->dev, "Clock rate out of range: %ld\n", rate); 566 return -EINVAL; 567 } 568 } 569 570 /* Support legacy board-file configuration */ 571 if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) { 572 priv->rmii_ref_clk_sel = true; 573 priv->rmii_ref_clk_sel_val = true; 574 } 575 576 return 0; 577} 578 579static struct phy_driver ksphy_driver[] = { 580{ 581 .phy_id = PHY_ID_KS8737, 582 .phy_id_mask = 0x00fffff0, 583 .name = "Micrel KS8737", 584 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause), 585 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, 586 .driver_data = &ks8737_type, 587 .config_init = kszphy_config_init, 588 .config_aneg = genphy_config_aneg, 589 .read_status = genphy_read_status, 590 .ack_interrupt = kszphy_ack_interrupt, 591 .config_intr = kszphy_config_intr, 592 .suspend = genphy_suspend, 593 .resume = genphy_resume, 594 .driver = { .owner = THIS_MODULE,}, 595}, { 596 .phy_id = PHY_ID_KSZ8021, 597 .phy_id_mask = 0x00ffffff, 598 .name = "Micrel KSZ8021 or KSZ8031", 599 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause | 600 SUPPORTED_Asym_Pause), 601 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, 602 .driver_data = &ksz8021_type, 603 .probe = kszphy_probe, 604 .config_init = kszphy_config_init, 605 .config_aneg = genphy_config_aneg, 606 .read_status = genphy_read_status, 607 .ack_interrupt = kszphy_ack_interrupt, 608 .config_intr = kszphy_config_intr, 609 .suspend = genphy_suspend, 610 .resume = genphy_resume, 611 .driver = { .owner = THIS_MODULE,}, 612}, { 613 .phy_id = PHY_ID_KSZ8031, 614 .phy_id_mask = 0x00ffffff, 615 .name = "Micrel KSZ8031", 616 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause | 617 SUPPORTED_Asym_Pause), 618 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, 619 .driver_data = &ksz8021_type, 620 .probe = kszphy_probe, 621 .config_init = kszphy_config_init, 622 .config_aneg = genphy_config_aneg, 623 .read_status = genphy_read_status, 624 .ack_interrupt = kszphy_ack_interrupt, 625 .config_intr = kszphy_config_intr, 626 .suspend = genphy_suspend, 627 .resume = genphy_resume, 628 .driver = { .owner = THIS_MODULE,}, 629}, { 630 .phy_id = PHY_ID_KSZ8041, 631 .phy_id_mask = 0x00fffff0, 632 .name = "Micrel KSZ8041", 633 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause 634 | SUPPORTED_Asym_Pause), 635 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, 636 .driver_data = &ksz8041_type, 637 .probe = kszphy_probe, 638 .config_init = kszphy_config_init, 639 .config_aneg = genphy_config_aneg, 640 .read_status = genphy_read_status, 641 .ack_interrupt = kszphy_ack_interrupt, 642 .config_intr = kszphy_config_intr, 643 .suspend = genphy_suspend, 644 .resume = genphy_resume, 645 .driver = { .owner = THIS_MODULE,}, 646}, { 647 .phy_id = PHY_ID_KSZ8041RNLI, 648 .phy_id_mask = 0x00fffff0, 649 .name = "Micrel KSZ8041RNLI", 650 .features = PHY_BASIC_FEATURES | 651 SUPPORTED_Pause | SUPPORTED_Asym_Pause, 652 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, 653 .driver_data = &ksz8041_type, 654 .probe = kszphy_probe, 655 .config_init = kszphy_config_init, 656 .config_aneg = genphy_config_aneg, 657 .read_status = genphy_read_status, 658 .ack_interrupt = kszphy_ack_interrupt, 659 .config_intr = kszphy_config_intr, 660 .suspend = genphy_suspend, 661 .resume = genphy_resume, 662 .driver = { .owner = THIS_MODULE,}, 663}, { 664 .phy_id = PHY_ID_KSZ8051, 665 .phy_id_mask = 0x00fffff0, 666 .name = "Micrel KSZ8051", 667 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause 668 | SUPPORTED_Asym_Pause), 669 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, 670 .driver_data = &ksz8051_type, 671 .probe = kszphy_probe, 672 .config_init = kszphy_config_init, 673 .config_aneg = genphy_config_aneg, 674 .read_status = genphy_read_status, 675 .ack_interrupt = kszphy_ack_interrupt, 676 .config_intr = kszphy_config_intr, 677 .suspend = genphy_suspend, 678 .resume = genphy_resume, 679 .driver = { .owner = THIS_MODULE,}, 680}, { 681 .phy_id = PHY_ID_KSZ8001, 682 .name = "Micrel KSZ8001 or KS8721", 683 .phy_id_mask = 0x00ffffff, 684 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause), 685 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, 686 .driver_data = &ksz8041_type, 687 .probe = kszphy_probe, 688 .config_init = kszphy_config_init, 689 .config_aneg = genphy_config_aneg, 690 .read_status = genphy_read_status, 691 .ack_interrupt = kszphy_ack_interrupt, 692 .config_intr = kszphy_config_intr, 693 .suspend = genphy_suspend, 694 .resume = genphy_resume, 695 .driver = { .owner = THIS_MODULE,}, 696}, { 697 .phy_id = PHY_ID_KSZ8081, 698 .name = "Micrel KSZ8081 or KSZ8091", 699 .phy_id_mask = 0x00fffff0, 700 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause), 701 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, 702 .driver_data = &ksz8081_type, 703 .probe = kszphy_probe, 704 .config_init = kszphy_config_init, 705 .config_aneg = genphy_config_aneg, 706 .read_status = genphy_read_status, 707 .ack_interrupt = kszphy_ack_interrupt, 708 .config_intr = kszphy_config_intr, 709 .suspend = genphy_suspend, 710 .resume = genphy_resume, 711 .driver = { .owner = THIS_MODULE,}, 712}, { 713 .phy_id = PHY_ID_KSZ8061, 714 .name = "Micrel KSZ8061", 715 .phy_id_mask = 0x00fffff0, 716 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause), 717 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, 718 .config_init = kszphy_config_init, 719 .config_aneg = genphy_config_aneg, 720 .read_status = genphy_read_status, 721 .ack_interrupt = kszphy_ack_interrupt, 722 .config_intr = kszphy_config_intr, 723 .suspend = genphy_suspend, 724 .resume = genphy_resume, 725 .driver = { .owner = THIS_MODULE,}, 726}, { 727 .phy_id = PHY_ID_KSZ9021, 728 .phy_id_mask = 0x000ffffe, 729 .name = "Micrel KSZ9021 Gigabit PHY", 730 .features = (PHY_GBIT_FEATURES | SUPPORTED_Pause), 731 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, 732 .driver_data = &ksz9021_type, 733 .config_init = ksz9021_config_init, 734 .config_aneg = genphy_config_aneg, 735 .read_status = genphy_read_status, 736 .ack_interrupt = kszphy_ack_interrupt, 737 .config_intr = kszphy_config_intr, 738 .suspend = genphy_suspend, 739 .resume = genphy_resume, 740 .read_mmd_indirect = ksz9021_rd_mmd_phyreg, 741 .write_mmd_indirect = ksz9021_wr_mmd_phyreg, 742 .driver = { .owner = THIS_MODULE, }, 743}, { 744 .phy_id = PHY_ID_KSZ9031, 745 .phy_id_mask = 0x00fffff0, 746 .name = "Micrel KSZ9031 Gigabit PHY", 747 .features = (PHY_GBIT_FEATURES | SUPPORTED_Pause), 748 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, 749 .driver_data = &ksz9021_type, 750 .config_init = ksz9031_config_init, 751 .config_aneg = genphy_config_aneg, 752 .read_status = genphy_read_status, 753 .ack_interrupt = kszphy_ack_interrupt, 754 .config_intr = kszphy_config_intr, 755 .suspend = genphy_suspend, 756 .resume = genphy_resume, 757 .driver = { .owner = THIS_MODULE, }, 758}, { 759 .phy_id = PHY_ID_KSZ8873MLL, 760 .phy_id_mask = 0x00fffff0, 761 .name = "Micrel KSZ8873MLL Switch", 762 .features = (SUPPORTED_Pause | SUPPORTED_Asym_Pause), 763 .flags = PHY_HAS_MAGICANEG, 764 .config_init = kszphy_config_init, 765 .config_aneg = ksz8873mll_config_aneg, 766 .read_status = ksz8873mll_read_status, 767 .suspend = genphy_suspend, 768 .resume = genphy_resume, 769 .driver = { .owner = THIS_MODULE, }, 770}, { 771 .phy_id = PHY_ID_KSZ886X, 772 .phy_id_mask = 0x00fffff0, 773 .name = "Micrel KSZ886X Switch", 774 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause), 775 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, 776 .config_init = kszphy_config_init, 777 .config_aneg = genphy_config_aneg, 778 .read_status = genphy_read_status, 779 .suspend = genphy_suspend, 780 .resume = genphy_resume, 781 .driver = { .owner = THIS_MODULE, }, 782} }; 783 784module_phy_driver(ksphy_driver); 785 786MODULE_DESCRIPTION("Micrel PHY driver"); 787MODULE_AUTHOR("David J. Choi"); 788MODULE_LICENSE("GPL"); 789 790static struct mdio_device_id __maybe_unused micrel_tbl[] = { 791 { PHY_ID_KSZ9021, 0x000ffffe }, 792 { PHY_ID_KSZ9031, 0x00fffff0 }, 793 { PHY_ID_KSZ8001, 0x00ffffff }, 794 { PHY_ID_KS8737, 0x00fffff0 }, 795 { PHY_ID_KSZ8021, 0x00ffffff }, 796 { PHY_ID_KSZ8031, 0x00ffffff }, 797 { PHY_ID_KSZ8041, 0x00fffff0 }, 798 { PHY_ID_KSZ8051, 0x00fffff0 }, 799 { PHY_ID_KSZ8061, 0x00fffff0 }, 800 { PHY_ID_KSZ8081, 0x00fffff0 }, 801 { PHY_ID_KSZ8873MLL, 0x00fffff0 }, 802 { PHY_ID_KSZ886X, 0x00fffff0 }, 803 { } 804}; 805 806MODULE_DEVICE_TABLE(mdio, micrel_tbl); 807