1/*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses.  You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 *     Redistribution and use in source and binary forms, with or
11 *     without modification, are permitted provided that the following
12 *     conditions are met:
13 *
14 *      - Redistributions of source code must retain the above
15 *        copyright notice, this list of conditions and the following
16 *        disclaimer.
17 *
18 *      - Redistributions in binary form must reproduce the above
19 *        copyright notice, this list of conditions and the following
20 *        disclaimer in the documentation and/or other materials
21 *        provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/kernel.h>
34#include <linux/module.h>
35#include <linux/mlx5/driver.h>
36#include <linux/mlx5/cmd.h>
37#include "mlx5_core.h"
38
39enum {
40	NUM_DRIVER_UARS		= 4,
41	NUM_LOW_LAT_UUARS	= 4,
42};
43
44
45struct mlx5_alloc_uar_mbox_in {
46	struct mlx5_inbox_hdr	hdr;
47	u8			rsvd[8];
48};
49
50struct mlx5_alloc_uar_mbox_out {
51	struct mlx5_outbox_hdr	hdr;
52	__be32			uarn;
53	u8			rsvd[4];
54};
55
56struct mlx5_free_uar_mbox_in {
57	struct mlx5_inbox_hdr	hdr;
58	__be32			uarn;
59	u8			rsvd[4];
60};
61
62struct mlx5_free_uar_mbox_out {
63	struct mlx5_outbox_hdr	hdr;
64	u8			rsvd[8];
65};
66
67int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn)
68{
69	struct mlx5_alloc_uar_mbox_in	in;
70	struct mlx5_alloc_uar_mbox_out	out;
71	int err;
72
73	memset(&in, 0, sizeof(in));
74	memset(&out, 0, sizeof(out));
75	in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_ALLOC_UAR);
76	err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
77	if (err)
78		goto ex;
79
80	if (out.hdr.status) {
81		err = mlx5_cmd_status_to_err(&out.hdr);
82		goto ex;
83	}
84
85	*uarn = be32_to_cpu(out.uarn) & 0xffffff;
86
87ex:
88	return err;
89}
90EXPORT_SYMBOL(mlx5_cmd_alloc_uar);
91
92int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn)
93{
94	struct mlx5_free_uar_mbox_in	in;
95	struct mlx5_free_uar_mbox_out	out;
96	int err;
97
98	memset(&in, 0, sizeof(in));
99	memset(&out, 0, sizeof(out));
100	in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_DEALLOC_UAR);
101	in.uarn = cpu_to_be32(uarn);
102	err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
103	if (err)
104		goto ex;
105
106	if (out.hdr.status)
107		err = mlx5_cmd_status_to_err(&out.hdr);
108
109ex:
110	return err;
111}
112EXPORT_SYMBOL(mlx5_cmd_free_uar);
113
114static int need_uuar_lock(int uuarn)
115{
116	int tot_uuars = NUM_DRIVER_UARS * MLX5_BF_REGS_PER_PAGE;
117
118	if (uuarn == 0 || tot_uuars - NUM_LOW_LAT_UUARS)
119		return 0;
120
121	return 1;
122}
123
124int mlx5_alloc_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari)
125{
126	int tot_uuars = NUM_DRIVER_UARS * MLX5_BF_REGS_PER_PAGE;
127	struct mlx5_bf *bf;
128	phys_addr_t addr;
129	int err;
130	int i;
131
132	uuari->num_uars = NUM_DRIVER_UARS;
133	uuari->num_low_latency_uuars = NUM_LOW_LAT_UUARS;
134
135	mutex_init(&uuari->lock);
136	uuari->uars = kcalloc(uuari->num_uars, sizeof(*uuari->uars), GFP_KERNEL);
137	if (!uuari->uars)
138		return -ENOMEM;
139
140	uuari->bfs = kcalloc(tot_uuars, sizeof(*uuari->bfs), GFP_KERNEL);
141	if (!uuari->bfs) {
142		err = -ENOMEM;
143		goto out_uars;
144	}
145
146	uuari->bitmap = kcalloc(BITS_TO_LONGS(tot_uuars), sizeof(*uuari->bitmap),
147				GFP_KERNEL);
148	if (!uuari->bitmap) {
149		err = -ENOMEM;
150		goto out_bfs;
151	}
152
153	uuari->count = kcalloc(tot_uuars, sizeof(*uuari->count), GFP_KERNEL);
154	if (!uuari->count) {
155		err = -ENOMEM;
156		goto out_bitmap;
157	}
158
159	for (i = 0; i < uuari->num_uars; i++) {
160		err = mlx5_cmd_alloc_uar(dev, &uuari->uars[i].index);
161		if (err)
162			goto out_count;
163
164		addr = dev->iseg_base + ((phys_addr_t)(uuari->uars[i].index) << PAGE_SHIFT);
165		uuari->uars[i].map = ioremap(addr, PAGE_SIZE);
166		if (!uuari->uars[i].map) {
167			mlx5_cmd_free_uar(dev, uuari->uars[i].index);
168			err = -ENOMEM;
169			goto out_count;
170		}
171		mlx5_core_dbg(dev, "allocated uar index 0x%x, mmaped at %p\n",
172			      uuari->uars[i].index, uuari->uars[i].map);
173	}
174
175	for (i = 0; i < tot_uuars; i++) {
176		bf = &uuari->bfs[i];
177
178		bf->buf_size = dev->caps.gen.bf_reg_size / 2;
179		bf->uar = &uuari->uars[i / MLX5_BF_REGS_PER_PAGE];
180		bf->regreg = uuari->uars[i / MLX5_BF_REGS_PER_PAGE].map;
181		bf->reg = NULL; /* Add WC support */
182		bf->offset = (i % MLX5_BF_REGS_PER_PAGE) * dev->caps.gen.bf_reg_size +
183			MLX5_BF_OFFSET;
184		bf->need_lock = need_uuar_lock(i);
185		spin_lock_init(&bf->lock);
186		spin_lock_init(&bf->lock32);
187		bf->uuarn = i;
188	}
189
190	return 0;
191
192out_count:
193	for (i--; i >= 0; i--) {
194		iounmap(uuari->uars[i].map);
195		mlx5_cmd_free_uar(dev, uuari->uars[i].index);
196	}
197	kfree(uuari->count);
198
199out_bitmap:
200	kfree(uuari->bitmap);
201
202out_bfs:
203	kfree(uuari->bfs);
204
205out_uars:
206	kfree(uuari->uars);
207	return err;
208}
209
210int mlx5_free_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari)
211{
212	int i = uuari->num_uars;
213
214	for (i--; i >= 0; i--) {
215		iounmap(uuari->uars[i].map);
216		mlx5_cmd_free_uar(dev, uuari->uars[i].index);
217	}
218
219	kfree(uuari->count);
220	kfree(uuari->bitmap);
221	kfree(uuari->bfs);
222	kfree(uuari->uars);
223
224	return 0;
225}
226