1/* Intel PRO/1000 Linux driver
2 * Copyright(c) 1999 - 2014 Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
11 * more details.
12 *
13 * The full GNU General Public License is included in this distribution in
14 * the file called "COPYING".
15 *
16 * Contact Information:
17 * Linux NICS <linux.nics@intel.com>
18 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
19 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
20 */
21
22#include "e1000.h"
23
24/**
25 *  e1000_raise_eec_clk - Raise EEPROM clock
26 *  @hw: pointer to the HW structure
27 *  @eecd: pointer to the EEPROM
28 *
29 *  Enable/Raise the EEPROM clock bit.
30 **/
31static void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
32{
33	*eecd = *eecd | E1000_EECD_SK;
34	ew32(EECD, *eecd);
35	e1e_flush();
36	udelay(hw->nvm.delay_usec);
37}
38
39/**
40 *  e1000_lower_eec_clk - Lower EEPROM clock
41 *  @hw: pointer to the HW structure
42 *  @eecd: pointer to the EEPROM
43 *
44 *  Clear/Lower the EEPROM clock bit.
45 **/
46static void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
47{
48	*eecd = *eecd & ~E1000_EECD_SK;
49	ew32(EECD, *eecd);
50	e1e_flush();
51	udelay(hw->nvm.delay_usec);
52}
53
54/**
55 *  e1000_shift_out_eec_bits - Shift data bits our to the EEPROM
56 *  @hw: pointer to the HW structure
57 *  @data: data to send to the EEPROM
58 *  @count: number of bits to shift out
59 *
60 *  We need to shift 'count' bits out to the EEPROM.  So, the value in the
61 *  "data" parameter will be shifted out to the EEPROM one bit at a time.
62 *  In order to do this, "data" must be broken down into bits.
63 **/
64static void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
65{
66	struct e1000_nvm_info *nvm = &hw->nvm;
67	u32 eecd = er32(EECD);
68	u32 mask;
69
70	mask = 0x01 << (count - 1);
71	if (nvm->type == e1000_nvm_eeprom_spi)
72		eecd |= E1000_EECD_DO;
73
74	do {
75		eecd &= ~E1000_EECD_DI;
76
77		if (data & mask)
78			eecd |= E1000_EECD_DI;
79
80		ew32(EECD, eecd);
81		e1e_flush();
82
83		udelay(nvm->delay_usec);
84
85		e1000_raise_eec_clk(hw, &eecd);
86		e1000_lower_eec_clk(hw, &eecd);
87
88		mask >>= 1;
89	} while (mask);
90
91	eecd &= ~E1000_EECD_DI;
92	ew32(EECD, eecd);
93}
94
95/**
96 *  e1000_shift_in_eec_bits - Shift data bits in from the EEPROM
97 *  @hw: pointer to the HW structure
98 *  @count: number of bits to shift in
99 *
100 *  In order to read a register from the EEPROM, we need to shift 'count' bits
101 *  in from the EEPROM.  Bits are "shifted in" by raising the clock input to
102 *  the EEPROM (setting the SK bit), and then reading the value of the data out
103 *  "DO" bit.  During this "shifting in" process the data in "DI" bit should
104 *  always be clear.
105 **/
106static u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
107{
108	u32 eecd;
109	u32 i;
110	u16 data;
111
112	eecd = er32(EECD);
113	eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
114	data = 0;
115
116	for (i = 0; i < count; i++) {
117		data <<= 1;
118		e1000_raise_eec_clk(hw, &eecd);
119
120		eecd = er32(EECD);
121
122		eecd &= ~E1000_EECD_DI;
123		if (eecd & E1000_EECD_DO)
124			data |= 1;
125
126		e1000_lower_eec_clk(hw, &eecd);
127	}
128
129	return data;
130}
131
132/**
133 *  e1000e_poll_eerd_eewr_done - Poll for EEPROM read/write completion
134 *  @hw: pointer to the HW structure
135 *  @ee_reg: EEPROM flag for polling
136 *
137 *  Polls the EEPROM status bit for either read or write completion based
138 *  upon the value of 'ee_reg'.
139 **/
140s32 e1000e_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)
141{
142	u32 attempts = 100000;
143	u32 i, reg = 0;
144
145	for (i = 0; i < attempts; i++) {
146		if (ee_reg == E1000_NVM_POLL_READ)
147			reg = er32(EERD);
148		else
149			reg = er32(EEWR);
150
151		if (reg & E1000_NVM_RW_REG_DONE)
152			return 0;
153
154		udelay(5);
155	}
156
157	return -E1000_ERR_NVM;
158}
159
160/**
161 *  e1000e_acquire_nvm - Generic request for access to EEPROM
162 *  @hw: pointer to the HW structure
163 *
164 *  Set the EEPROM access request bit and wait for EEPROM access grant bit.
165 *  Return successful if access grant bit set, else clear the request for
166 *  EEPROM access and return -E1000_ERR_NVM (-1).
167 **/
168s32 e1000e_acquire_nvm(struct e1000_hw *hw)
169{
170	u32 eecd = er32(EECD);
171	s32 timeout = E1000_NVM_GRANT_ATTEMPTS;
172
173	ew32(EECD, eecd | E1000_EECD_REQ);
174	eecd = er32(EECD);
175
176	while (timeout) {
177		if (eecd & E1000_EECD_GNT)
178			break;
179		udelay(5);
180		eecd = er32(EECD);
181		timeout--;
182	}
183
184	if (!timeout) {
185		eecd &= ~E1000_EECD_REQ;
186		ew32(EECD, eecd);
187		e_dbg("Could not acquire NVM grant\n");
188		return -E1000_ERR_NVM;
189	}
190
191	return 0;
192}
193
194/**
195 *  e1000_standby_nvm - Return EEPROM to standby state
196 *  @hw: pointer to the HW structure
197 *
198 *  Return the EEPROM to a standby state.
199 **/
200static void e1000_standby_nvm(struct e1000_hw *hw)
201{
202	struct e1000_nvm_info *nvm = &hw->nvm;
203	u32 eecd = er32(EECD);
204
205	if (nvm->type == e1000_nvm_eeprom_spi) {
206		/* Toggle CS to flush commands */
207		eecd |= E1000_EECD_CS;
208		ew32(EECD, eecd);
209		e1e_flush();
210		udelay(nvm->delay_usec);
211		eecd &= ~E1000_EECD_CS;
212		ew32(EECD, eecd);
213		e1e_flush();
214		udelay(nvm->delay_usec);
215	}
216}
217
218/**
219 *  e1000_stop_nvm - Terminate EEPROM command
220 *  @hw: pointer to the HW structure
221 *
222 *  Terminates the current command by inverting the EEPROM's chip select pin.
223 **/
224static void e1000_stop_nvm(struct e1000_hw *hw)
225{
226	u32 eecd;
227
228	eecd = er32(EECD);
229	if (hw->nvm.type == e1000_nvm_eeprom_spi) {
230		/* Pull CS high */
231		eecd |= E1000_EECD_CS;
232		e1000_lower_eec_clk(hw, &eecd);
233	}
234}
235
236/**
237 *  e1000e_release_nvm - Release exclusive access to EEPROM
238 *  @hw: pointer to the HW structure
239 *
240 *  Stop any current commands to the EEPROM and clear the EEPROM request bit.
241 **/
242void e1000e_release_nvm(struct e1000_hw *hw)
243{
244	u32 eecd;
245
246	e1000_stop_nvm(hw);
247
248	eecd = er32(EECD);
249	eecd &= ~E1000_EECD_REQ;
250	ew32(EECD, eecd);
251}
252
253/**
254 *  e1000_ready_nvm_eeprom - Prepares EEPROM for read/write
255 *  @hw: pointer to the HW structure
256 *
257 *  Setups the EEPROM for reading and writing.
258 **/
259static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw)
260{
261	struct e1000_nvm_info *nvm = &hw->nvm;
262	u32 eecd = er32(EECD);
263	u8 spi_stat_reg;
264
265	if (nvm->type == e1000_nvm_eeprom_spi) {
266		u16 timeout = NVM_MAX_RETRY_SPI;
267
268		/* Clear SK and CS */
269		eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
270		ew32(EECD, eecd);
271		e1e_flush();
272		udelay(1);
273
274		/* Read "Status Register" repeatedly until the LSB is cleared.
275		 * The EEPROM will signal that the command has been completed
276		 * by clearing bit 0 of the internal status register.  If it's
277		 * not cleared within 'timeout', then error out.
278		 */
279		while (timeout) {
280			e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
281						 hw->nvm.opcode_bits);
282			spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8);
283			if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
284				break;
285
286			udelay(5);
287			e1000_standby_nvm(hw);
288			timeout--;
289		}
290
291		if (!timeout) {
292			e_dbg("SPI NVM Status error\n");
293			return -E1000_ERR_NVM;
294		}
295	}
296
297	return 0;
298}
299
300/**
301 *  e1000e_read_nvm_eerd - Reads EEPROM using EERD register
302 *  @hw: pointer to the HW structure
303 *  @offset: offset of word in the EEPROM to read
304 *  @words: number of words to read
305 *  @data: word read from the EEPROM
306 *
307 *  Reads a 16 bit word from the EEPROM using the EERD register.
308 **/
309s32 e1000e_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
310{
311	struct e1000_nvm_info *nvm = &hw->nvm;
312	u32 i, eerd = 0;
313	s32 ret_val = 0;
314
315	/* A check for invalid values:  offset too large, too many words,
316	 * too many words for the offset, and not enough words.
317	 */
318	if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
319	    (words == 0)) {
320		e_dbg("nvm parameter(s) out of bounds\n");
321		return -E1000_ERR_NVM;
322	}
323
324	for (i = 0; i < words; i++) {
325		eerd = ((offset + i) << E1000_NVM_RW_ADDR_SHIFT) +
326		    E1000_NVM_RW_REG_START;
327
328		ew32(EERD, eerd);
329		ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);
330		if (ret_val) {
331			e_dbg("NVM read error: %d\n", ret_val);
332			break;
333		}
334
335		data[i] = (er32(EERD) >> E1000_NVM_RW_REG_DATA);
336	}
337
338	return ret_val;
339}
340
341/**
342 *  e1000e_write_nvm_spi - Write to EEPROM using SPI
343 *  @hw: pointer to the HW structure
344 *  @offset: offset within the EEPROM to be written to
345 *  @words: number of words to write
346 *  @data: 16 bit word(s) to be written to the EEPROM
347 *
348 *  Writes data to EEPROM at offset using SPI interface.
349 *
350 *  If e1000e_update_nvm_checksum is not called after this function , the
351 *  EEPROM will most likely contain an invalid checksum.
352 **/
353s32 e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
354{
355	struct e1000_nvm_info *nvm = &hw->nvm;
356	s32 ret_val = -E1000_ERR_NVM;
357	u16 widx = 0;
358
359	/* A check for invalid values:  offset too large, too many words,
360	 * and not enough words.
361	 */
362	if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
363	    (words == 0)) {
364		e_dbg("nvm parameter(s) out of bounds\n");
365		return -E1000_ERR_NVM;
366	}
367
368	while (widx < words) {
369		u8 write_opcode = NVM_WRITE_OPCODE_SPI;
370
371		ret_val = nvm->ops.acquire(hw);
372		if (ret_val)
373			return ret_val;
374
375		ret_val = e1000_ready_nvm_eeprom(hw);
376		if (ret_val) {
377			nvm->ops.release(hw);
378			return ret_val;
379		}
380
381		e1000_standby_nvm(hw);
382
383		/* Send the WRITE ENABLE command (8 bit opcode) */
384		e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
385					 nvm->opcode_bits);
386
387		e1000_standby_nvm(hw);
388
389		/* Some SPI eeproms use the 8th address bit embedded in the
390		 * opcode
391		 */
392		if ((nvm->address_bits == 8) && (offset >= 128))
393			write_opcode |= NVM_A8_OPCODE_SPI;
394
395		/* Send the Write command (8-bit opcode + addr) */
396		e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
397		e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
398					 nvm->address_bits);
399
400		/* Loop to allow for up to whole page write of eeprom */
401		while (widx < words) {
402			u16 word_out = data[widx];
403
404			word_out = (word_out >> 8) | (word_out << 8);
405			e1000_shift_out_eec_bits(hw, word_out, 16);
406			widx++;
407
408			if ((((offset + widx) * 2) % nvm->page_size) == 0) {
409				e1000_standby_nvm(hw);
410				break;
411			}
412		}
413		usleep_range(10000, 20000);
414		nvm->ops.release(hw);
415	}
416
417	return ret_val;
418}
419
420/**
421 *  e1000_read_pba_string_generic - Read device part number
422 *  @hw: pointer to the HW structure
423 *  @pba_num: pointer to device part number
424 *  @pba_num_size: size of part number buffer
425 *
426 *  Reads the product board assembly (PBA) number from the EEPROM and stores
427 *  the value in pba_num.
428 **/
429s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num,
430				  u32 pba_num_size)
431{
432	s32 ret_val;
433	u16 nvm_data;
434	u16 pba_ptr;
435	u16 offset;
436	u16 length;
437
438	if (pba_num == NULL) {
439		e_dbg("PBA string buffer was null\n");
440		return -E1000_ERR_INVALID_ARGUMENT;
441	}
442
443	ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
444	if (ret_val) {
445		e_dbg("NVM Read Error\n");
446		return ret_val;
447	}
448
449	ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);
450	if (ret_val) {
451		e_dbg("NVM Read Error\n");
452		return ret_val;
453	}
454
455	/* if nvm_data is not ptr guard the PBA must be in legacy format which
456	 * means pba_ptr is actually our second data word for the PBA number
457	 * and we can decode it into an ascii string
458	 */
459	if (nvm_data != NVM_PBA_PTR_GUARD) {
460		e_dbg("NVM PBA number is not stored as string\n");
461
462		/* make sure callers buffer is big enough to store the PBA */
463		if (pba_num_size < E1000_PBANUM_LENGTH) {
464			e_dbg("PBA string buffer too small\n");
465			return E1000_ERR_NO_SPACE;
466		}
467
468		/* extract hex string from data and pba_ptr */
469		pba_num[0] = (nvm_data >> 12) & 0xF;
470		pba_num[1] = (nvm_data >> 8) & 0xF;
471		pba_num[2] = (nvm_data >> 4) & 0xF;
472		pba_num[3] = nvm_data & 0xF;
473		pba_num[4] = (pba_ptr >> 12) & 0xF;
474		pba_num[5] = (pba_ptr >> 8) & 0xF;
475		pba_num[6] = '-';
476		pba_num[7] = 0;
477		pba_num[8] = (pba_ptr >> 4) & 0xF;
478		pba_num[9] = pba_ptr & 0xF;
479
480		/* put a null character on the end of our string */
481		pba_num[10] = '\0';
482
483		/* switch all the data but the '-' to hex char */
484		for (offset = 0; offset < 10; offset++) {
485			if (pba_num[offset] < 0xA)
486				pba_num[offset] += '0';
487			else if (pba_num[offset] < 0x10)
488				pba_num[offset] += 'A' - 0xA;
489		}
490
491		return 0;
492	}
493
494	ret_val = e1000_read_nvm(hw, pba_ptr, 1, &length);
495	if (ret_val) {
496		e_dbg("NVM Read Error\n");
497		return ret_val;
498	}
499
500	if (length == 0xFFFF || length == 0) {
501		e_dbg("NVM PBA number section invalid length\n");
502		return -E1000_ERR_NVM_PBA_SECTION;
503	}
504	/* check if pba_num buffer is big enough */
505	if (pba_num_size < (((u32)length * 2) - 1)) {
506		e_dbg("PBA string buffer too small\n");
507		return -E1000_ERR_NO_SPACE;
508	}
509
510	/* trim pba length from start of string */
511	pba_ptr++;
512	length--;
513
514	for (offset = 0; offset < length; offset++) {
515		ret_val = e1000_read_nvm(hw, pba_ptr + offset, 1, &nvm_data);
516		if (ret_val) {
517			e_dbg("NVM Read Error\n");
518			return ret_val;
519		}
520		pba_num[offset * 2] = (u8)(nvm_data >> 8);
521		pba_num[(offset * 2) + 1] = (u8)(nvm_data & 0xFF);
522	}
523	pba_num[offset * 2] = '\0';
524
525	return 0;
526}
527
528/**
529 *  e1000_read_mac_addr_generic - Read device MAC address
530 *  @hw: pointer to the HW structure
531 *
532 *  Reads the device MAC address from the EEPROM and stores the value.
533 *  Since devices with two ports use the same EEPROM, we increment the
534 *  last bit in the MAC address for the second port.
535 **/
536s32 e1000_read_mac_addr_generic(struct e1000_hw *hw)
537{
538	u32 rar_high;
539	u32 rar_low;
540	u16 i;
541
542	rar_high = er32(RAH(0));
543	rar_low = er32(RAL(0));
544
545	for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++)
546		hw->mac.perm_addr[i] = (u8)(rar_low >> (i * 8));
547
548	for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++)
549		hw->mac.perm_addr[i + 4] = (u8)(rar_high >> (i * 8));
550
551	for (i = 0; i < ETH_ALEN; i++)
552		hw->mac.addr[i] = hw->mac.perm_addr[i];
553
554	return 0;
555}
556
557/**
558 *  e1000e_validate_nvm_checksum_generic - Validate EEPROM checksum
559 *  @hw: pointer to the HW structure
560 *
561 *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
562 *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
563 **/
564s32 e1000e_validate_nvm_checksum_generic(struct e1000_hw *hw)
565{
566	s32 ret_val;
567	u16 checksum = 0;
568	u16 i, nvm_data;
569
570	for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
571		ret_val = e1000_read_nvm(hw, i, 1, &nvm_data);
572		if (ret_val) {
573			e_dbg("NVM Read Error\n");
574			return ret_val;
575		}
576		checksum += nvm_data;
577	}
578
579	if (checksum != (u16)NVM_SUM) {
580		e_dbg("NVM Checksum Invalid\n");
581		return -E1000_ERR_NVM;
582	}
583
584	return 0;
585}
586
587/**
588 *  e1000e_update_nvm_checksum_generic - Update EEPROM checksum
589 *  @hw: pointer to the HW structure
590 *
591 *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
592 *  up to the checksum.  Then calculates the EEPROM checksum and writes the
593 *  value to the EEPROM.
594 **/
595s32 e1000e_update_nvm_checksum_generic(struct e1000_hw *hw)
596{
597	s32 ret_val;
598	u16 checksum = 0;
599	u16 i, nvm_data;
600
601	for (i = 0; i < NVM_CHECKSUM_REG; i++) {
602		ret_val = e1000_read_nvm(hw, i, 1, &nvm_data);
603		if (ret_val) {
604			e_dbg("NVM Read Error while updating checksum.\n");
605			return ret_val;
606		}
607		checksum += nvm_data;
608	}
609	checksum = (u16)NVM_SUM - checksum;
610	ret_val = e1000_write_nvm(hw, NVM_CHECKSUM_REG, 1, &checksum);
611	if (ret_val)
612		e_dbg("NVM Write Error while updating checksum.\n");
613
614	return ret_val;
615}
616
617/**
618 *  e1000e_reload_nvm_generic - Reloads EEPROM
619 *  @hw: pointer to the HW structure
620 *
621 *  Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the
622 *  extended control register.
623 **/
624void e1000e_reload_nvm_generic(struct e1000_hw *hw)
625{
626	u32 ctrl_ext;
627
628	usleep_range(10, 20);
629	ctrl_ext = er32(CTRL_EXT);
630	ctrl_ext |= E1000_CTRL_EXT_EE_RST;
631	ew32(CTRL_EXT, ctrl_ext);
632	e1e_flush();
633}
634