1/* 2 * linux/drivers/net/ethernet/ibm/ehea/ehea_phyp.h 3 * 4 * eHEA ethernet device driver for IBM eServer System p 5 * 6 * (C) Copyright IBM Corp. 2006 7 * 8 * Authors: 9 * Christoph Raisch <raisch@de.ibm.com> 10 * Jan-Bernd Themann <themann@de.ibm.com> 11 * Thomas Klein <tklein@de.ibm.com> 12 * 13 * 14 * This program is free software; you can redistribute it and/or modify 15 * it under the terms of the GNU General Public License as published by 16 * the Free Software Foundation; either version 2, or (at your option) 17 * any later version. 18 * 19 * This program is distributed in the hope that it will be useful, 20 * but WITHOUT ANY WARRANTY; without even the implied warranty of 21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22 * GNU General Public License for more details. 23 * 24 * You should have received a copy of the GNU General Public License 25 * along with this program; if not, write to the Free Software 26 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 27 */ 28 29#ifndef __EHEA_PHYP_H__ 30#define __EHEA_PHYP_H__ 31 32#include <linux/delay.h> 33#include <asm/hvcall.h> 34#include "ehea.h" 35#include "ehea_hw.h" 36 37/* Some abbreviations used here: 38 * 39 * hcp_* - structures, variables and functions releated to Hypervisor Calls 40 */ 41 42/* Number of pages which can be registered at once by H_REGISTER_HEA_RPAGES */ 43#define EHEA_MAX_RPAGE 512 44 45/* Notification Event Queue (NEQ) Entry bit masks */ 46#define NEQE_EVENT_CODE EHEA_BMASK_IBM(2, 7) 47#define NEQE_PORTNUM EHEA_BMASK_IBM(32, 47) 48#define NEQE_PORT_UP EHEA_BMASK_IBM(16, 16) 49#define NEQE_EXTSWITCH_PORT_UP EHEA_BMASK_IBM(17, 17) 50#define NEQE_EXTSWITCH_PRIMARY EHEA_BMASK_IBM(18, 18) 51#define NEQE_PLID EHEA_BMASK_IBM(16, 47) 52 53/* Notification Event Codes */ 54#define EHEA_EC_PORTSTATE_CHG 0x30 55#define EHEA_EC_ADAPTER_MALFUNC 0x32 56#define EHEA_EC_PORT_MALFUNC 0x33 57 58/* Notification Event Log Register (NELR) bit masks */ 59#define NELR_PORT_MALFUNC EHEA_BMASK_IBM(61, 61) 60#define NELR_ADAPTER_MALFUNC EHEA_BMASK_IBM(62, 62) 61#define NELR_PORTSTATE_CHG EHEA_BMASK_IBM(63, 63) 62 63static inline void hcp_epas_ctor(struct h_epas *epas, u64 paddr_kernel, 64 u64 paddr_user) 65{ 66 /* To support 64k pages we must round to 64k page boundary */ 67 epas->kernel.addr = ioremap((paddr_kernel & PAGE_MASK), PAGE_SIZE) + 68 (paddr_kernel & ~PAGE_MASK); 69 epas->user.addr = paddr_user; 70} 71 72static inline void hcp_epas_dtor(struct h_epas *epas) 73{ 74 if (epas->kernel.addr) 75 iounmap((void __iomem *)((u64)epas->kernel.addr & PAGE_MASK)); 76 77 epas->user.addr = 0; 78 epas->kernel.addr = 0; 79} 80 81struct hcp_modify_qp_cb0 { 82 u64 qp_ctl_reg; /* 00 */ 83 u32 max_swqe; /* 02 */ 84 u32 max_rwqe; /* 03 */ 85 u32 port_nb; /* 04 */ 86 u32 reserved0; /* 05 */ 87 u64 qp_aer; /* 06 */ 88 u64 qp_tenure; /* 08 */ 89}; 90 91/* Hcall Query/Modify Queue Pair Control Block 0 Selection Mask Bits */ 92#define H_QPCB0_ALL EHEA_BMASK_IBM(0, 5) 93#define H_QPCB0_QP_CTL_REG EHEA_BMASK_IBM(0, 0) 94#define H_QPCB0_MAX_SWQE EHEA_BMASK_IBM(1, 1) 95#define H_QPCB0_MAX_RWQE EHEA_BMASK_IBM(2, 2) 96#define H_QPCB0_PORT_NB EHEA_BMASK_IBM(3, 3) 97#define H_QPCB0_QP_AER EHEA_BMASK_IBM(4, 4) 98#define H_QPCB0_QP_TENURE EHEA_BMASK_IBM(5, 5) 99 100/* Queue Pair Control Register Status Bits */ 101#define H_QP_CR_ENABLED 0x8000000000000000ULL /* QP enabled */ 102 /* QP States: */ 103#define H_QP_CR_STATE_RESET 0x0000010000000000ULL /* Reset */ 104#define H_QP_CR_STATE_INITIALIZED 0x0000020000000000ULL /* Initialized */ 105#define H_QP_CR_STATE_RDY2RCV 0x0000030000000000ULL /* Ready to recv */ 106#define H_QP_CR_STATE_RDY2SND 0x0000050000000000ULL /* Ready to send */ 107#define H_QP_CR_STATE_ERROR 0x0000800000000000ULL /* Error */ 108#define H_QP_CR_RES_STATE 0x0000007F00000000ULL /* Resultant state */ 109 110struct hcp_modify_qp_cb1 { 111 u32 qpn; /* 00 */ 112 u32 qp_asyn_ev_eq_nb; /* 01 */ 113 u64 sq_cq_handle; /* 02 */ 114 u64 rq_cq_handle; /* 04 */ 115 /* sgel = scatter gather element */ 116 u32 sgel_nb_sq; /* 06 */ 117 u32 sgel_nb_rq1; /* 07 */ 118 u32 sgel_nb_rq2; /* 08 */ 119 u32 sgel_nb_rq3; /* 09 */ 120}; 121 122/* Hcall Query/Modify Queue Pair Control Block 1 Selection Mask Bits */ 123#define H_QPCB1_ALL EHEA_BMASK_IBM(0, 7) 124#define H_QPCB1_QPN EHEA_BMASK_IBM(0, 0) 125#define H_QPCB1_ASYN_EV_EQ_NB EHEA_BMASK_IBM(1, 1) 126#define H_QPCB1_SQ_CQ_HANDLE EHEA_BMASK_IBM(2, 2) 127#define H_QPCB1_RQ_CQ_HANDLE EHEA_BMASK_IBM(3, 3) 128#define H_QPCB1_SGEL_NB_SQ EHEA_BMASK_IBM(4, 4) 129#define H_QPCB1_SGEL_NB_RQ1 EHEA_BMASK_IBM(5, 5) 130#define H_QPCB1_SGEL_NB_RQ2 EHEA_BMASK_IBM(6, 6) 131#define H_QPCB1_SGEL_NB_RQ3 EHEA_BMASK_IBM(7, 7) 132 133struct hcp_query_ehea { 134 u32 cur_num_qps; /* 00 */ 135 u32 cur_num_cqs; /* 01 */ 136 u32 cur_num_eqs; /* 02 */ 137 u32 cur_num_mrs; /* 03 */ 138 u32 auth_level; /* 04 */ 139 u32 max_num_qps; /* 05 */ 140 u32 max_num_cqs; /* 06 */ 141 u32 max_num_eqs; /* 07 */ 142 u32 max_num_mrs; /* 08 */ 143 u32 reserved0; /* 09 */ 144 u32 int_clock_freq; /* 10 */ 145 u32 max_num_pds; /* 11 */ 146 u32 max_num_addr_handles; /* 12 */ 147 u32 max_num_cqes; /* 13 */ 148 u32 max_num_wqes; /* 14 */ 149 u32 max_num_sgel_rq1wqe; /* 15 */ 150 u32 max_num_sgel_rq2wqe; /* 16 */ 151 u32 max_num_sgel_rq3wqe; /* 17 */ 152 u32 mr_page_size; /* 18 */ 153 u32 reserved1; /* 19 */ 154 u64 max_mr_size; /* 20 */ 155 u64 reserved2; /* 22 */ 156 u32 num_ports; /* 24 */ 157 u32 reserved3; /* 25 */ 158 u32 reserved4; /* 26 */ 159 u32 reserved5; /* 27 */ 160 u64 max_mc_mac; /* 28 */ 161 u64 ehea_cap; /* 30 */ 162 u32 max_isn_per_eq; /* 32 */ 163 u32 max_num_neq; /* 33 */ 164 u64 max_num_vlan_ids; /* 34 */ 165 u32 max_num_port_group; /* 36 */ 166 u32 max_num_phys_port; /* 37 */ 167 168}; 169 170/* Hcall Query/Modify Port Control Block defines */ 171#define H_PORT_CB0 0 172#define H_PORT_CB1 1 173#define H_PORT_CB2 2 174#define H_PORT_CB3 3 175#define H_PORT_CB4 4 176#define H_PORT_CB5 5 177#define H_PORT_CB6 6 178#define H_PORT_CB7 7 179 180struct hcp_ehea_port_cb0 { 181 u64 port_mac_addr; 182 u64 port_rc; 183 u64 reserved0; 184 u32 port_op_state; 185 u32 port_speed; 186 u32 ext_swport_op_state; 187 u32 neg_tpf_prpf; 188 u32 num_default_qps; 189 u32 reserved1; 190 u64 default_qpn_arr[16]; 191}; 192 193/* Hcall Query/Modify Port Control Block 0 Selection Mask Bits */ 194#define H_PORT_CB0_ALL EHEA_BMASK_IBM(0, 7) /* Set all bits */ 195#define H_PORT_CB0_MAC EHEA_BMASK_IBM(0, 0) /* MAC address */ 196#define H_PORT_CB0_PRC EHEA_BMASK_IBM(1, 1) /* Port Recv Control */ 197#define H_PORT_CB0_DEFQPNARRAY EHEA_BMASK_IBM(7, 7) /* Default QPN Array */ 198 199/* Hcall Query Port: Returned port speed values */ 200#define H_SPEED_10M_H 1 /* 10 Mbps, Half Duplex */ 201#define H_SPEED_10M_F 2 /* 10 Mbps, Full Duplex */ 202#define H_SPEED_100M_H 3 /* 100 Mbps, Half Duplex */ 203#define H_SPEED_100M_F 4 /* 100 Mbps, Full Duplex */ 204#define H_SPEED_1G_F 6 /* 1 Gbps, Full Duplex */ 205#define H_SPEED_10G_F 8 /* 10 Gbps, Full Duplex */ 206 207/* Port Receive Control Status Bits */ 208#define PXLY_RC_VALID EHEA_BMASK_IBM(49, 49) 209#define PXLY_RC_VLAN_XTRACT EHEA_BMASK_IBM(50, 50) 210#define PXLY_RC_TCP_6_TUPLE EHEA_BMASK_IBM(51, 51) 211#define PXLY_RC_UDP_6_TUPLE EHEA_BMASK_IBM(52, 52) 212#define PXLY_RC_TCP_3_TUPLE EHEA_BMASK_IBM(53, 53) 213#define PXLY_RC_TCP_2_TUPLE EHEA_BMASK_IBM(54, 54) 214#define PXLY_RC_LLC_SNAP EHEA_BMASK_IBM(55, 55) 215#define PXLY_RC_JUMBO_FRAME EHEA_BMASK_IBM(56, 56) 216#define PXLY_RC_FRAG_IP_PKT EHEA_BMASK_IBM(57, 57) 217#define PXLY_RC_TCP_UDP_CHKSUM EHEA_BMASK_IBM(58, 58) 218#define PXLY_RC_IP_CHKSUM EHEA_BMASK_IBM(59, 59) 219#define PXLY_RC_MAC_FILTER EHEA_BMASK_IBM(60, 60) 220#define PXLY_RC_UNTAG_FILTER EHEA_BMASK_IBM(61, 61) 221#define PXLY_RC_VLAN_TAG_FILTER EHEA_BMASK_IBM(62, 63) 222 223#define PXLY_RC_VLAN_FILTER 2 224#define PXLY_RC_VLAN_PERM 0 225 226 227#define H_PORT_CB1_ALL 0x8000000000000000ULL 228 229struct hcp_ehea_port_cb1 { 230 u64 vlan_filter[64]; 231}; 232 233#define H_PORT_CB2_ALL 0xFFE0000000000000ULL 234 235struct hcp_ehea_port_cb2 { 236 u64 rxo; 237 u64 rxucp; 238 u64 rxufd; 239 u64 rxuerr; 240 u64 rxftl; 241 u64 rxmcp; 242 u64 rxbcp; 243 u64 txo; 244 u64 txucp; 245 u64 txmcp; 246 u64 txbcp; 247}; 248 249struct hcp_ehea_port_cb3 { 250 u64 vlan_bc_filter[64]; 251 u64 vlan_mc_filter[64]; 252 u64 vlan_un_filter[64]; 253 u64 port_mac_hash_array[64]; 254}; 255 256#define H_PORT_CB4_ALL 0xF000000000000000ULL 257#define H_PORT_CB4_JUMBO 0x1000000000000000ULL 258#define H_PORT_CB4_SPEED 0x8000000000000000ULL 259 260struct hcp_ehea_port_cb4 { 261 u32 port_speed; 262 u32 pause_frame; 263 u32 ens_port_op_state; 264 u32 jumbo_frame; 265 u32 ens_port_wrap; 266}; 267 268/* Hcall Query/Modify Port Control Block 5 Selection Mask Bits */ 269#define H_PORT_CB5_RCU 0x0001000000000000ULL 270#define PXS_RCU EHEA_BMASK_IBM(61, 63) 271 272struct hcp_ehea_port_cb5 { 273 u64 prc; /* 00 */ 274 u64 uaa; /* 01 */ 275 u64 macvc; /* 02 */ 276 u64 xpcsc; /* 03 */ 277 u64 xpcsp; /* 04 */ 278 u64 pcsid; /* 05 */ 279 u64 xpcsst; /* 06 */ 280 u64 pthlb; /* 07 */ 281 u64 pthrb; /* 08 */ 282 u64 pqu; /* 09 */ 283 u64 pqd; /* 10 */ 284 u64 prt; /* 11 */ 285 u64 wsth; /* 12 */ 286 u64 rcb; /* 13 */ 287 u64 rcm; /* 14 */ 288 u64 rcu; /* 15 */ 289 u64 macc; /* 16 */ 290 u64 pc; /* 17 */ 291 u64 pst; /* 18 */ 292 u64 ducqpn; /* 19 */ 293 u64 mcqpn; /* 20 */ 294 u64 mma; /* 21 */ 295 u64 pmc0h; /* 22 */ 296 u64 pmc0l; /* 23 */ 297 u64 lbc; /* 24 */ 298}; 299 300#define H_PORT_CB6_ALL 0xFFFFFE7FFFFF8000ULL 301 302struct hcp_ehea_port_cb6 { 303 u64 rxo; /* 00 */ 304 u64 rx64; /* 01 */ 305 u64 rx65; /* 02 */ 306 u64 rx128; /* 03 */ 307 u64 rx256; /* 04 */ 308 u64 rx512; /* 05 */ 309 u64 rx1024; /* 06 */ 310 u64 rxbfcs; /* 07 */ 311 u64 rxime; /* 08 */ 312 u64 rxrle; /* 09 */ 313 u64 rxorle; /* 10 */ 314 u64 rxftl; /* 11 */ 315 u64 rxjab; /* 12 */ 316 u64 rxse; /* 13 */ 317 u64 rxce; /* 14 */ 318 u64 rxrf; /* 15 */ 319 u64 rxfrag; /* 16 */ 320 u64 rxuoc; /* 17 */ 321 u64 rxcpf; /* 18 */ 322 u64 rxsb; /* 19 */ 323 u64 rxfd; /* 20 */ 324 u64 rxoerr; /* 21 */ 325 u64 rxaln; /* 22 */ 326 u64 ducqpn; /* 23 */ 327 u64 reserved0; /* 24 */ 328 u64 rxmcp; /* 25 */ 329 u64 rxbcp; /* 26 */ 330 u64 txmcp; /* 27 */ 331 u64 txbcp; /* 28 */ 332 u64 txo; /* 29 */ 333 u64 tx64; /* 30 */ 334 u64 tx65; /* 31 */ 335 u64 tx128; /* 32 */ 336 u64 tx256; /* 33 */ 337 u64 tx512; /* 34 */ 338 u64 tx1024; /* 35 */ 339 u64 txbfcs; /* 36 */ 340 u64 txcpf; /* 37 */ 341 u64 txlf; /* 38 */ 342 u64 txrf; /* 39 */ 343 u64 txime; /* 40 */ 344 u64 txsc; /* 41 */ 345 u64 txmc; /* 42 */ 346 u64 txsqe; /* 43 */ 347 u64 txdef; /* 44 */ 348 u64 txlcol; /* 45 */ 349 u64 txexcol; /* 46 */ 350 u64 txcse; /* 47 */ 351 u64 txbor; /* 48 */ 352}; 353 354#define H_PORT_CB7_DUCQPN 0x8000000000000000ULL 355 356struct hcp_ehea_port_cb7 { 357 u64 def_uc_qpn; 358}; 359 360u64 ehea_h_query_ehea_qp(const u64 adapter_handle, 361 const u8 qp_category, 362 const u64 qp_handle, const u64 sel_mask, 363 void *cb_addr); 364 365u64 ehea_h_modify_ehea_qp(const u64 adapter_handle, 366 const u8 cat, 367 const u64 qp_handle, 368 const u64 sel_mask, 369 void *cb_addr, 370 u64 *inv_attr_id, 371 u64 *proc_mask, u16 *out_swr, u16 *out_rwr); 372 373u64 ehea_h_alloc_resource_eq(const u64 adapter_handle, 374 struct ehea_eq_attr *eq_attr, u64 *eq_handle); 375 376u64 ehea_h_alloc_resource_cq(const u64 adapter_handle, 377 struct ehea_cq_attr *cq_attr, 378 u64 *cq_handle, struct h_epas *epas); 379 380u64 ehea_h_alloc_resource_qp(const u64 adapter_handle, 381 struct ehea_qp_init_attr *init_attr, 382 const u32 pd, 383 u64 *qp_handle, struct h_epas *h_epas); 384 385#define H_REG_RPAGE_PAGE_SIZE EHEA_BMASK_IBM(48, 55) 386#define H_REG_RPAGE_QT EHEA_BMASK_IBM(62, 63) 387 388u64 ehea_h_register_rpage(const u64 adapter_handle, 389 const u8 pagesize, 390 const u8 queue_type, 391 const u64 resource_handle, 392 const u64 log_pageaddr, u64 count); 393 394#define H_DISABLE_GET_EHEA_WQE_P 1 395#define H_DISABLE_GET_SQ_WQE_P 2 396#define H_DISABLE_GET_RQC 3 397 398u64 ehea_h_disable_and_get_hea(const u64 adapter_handle, const u64 qp_handle); 399 400#define FORCE_FREE 1 401#define NORMAL_FREE 0 402 403u64 ehea_h_free_resource(const u64 adapter_handle, const u64 res_handle, 404 u64 force_bit); 405 406u64 ehea_h_alloc_resource_mr(const u64 adapter_handle, const u64 vaddr, 407 const u64 length, const u32 access_ctrl, 408 const u32 pd, u64 *mr_handle, u32 *lkey); 409 410u64 ehea_h_register_rpage_mr(const u64 adapter_handle, const u64 mr_handle, 411 const u8 pagesize, const u8 queue_type, 412 const u64 log_pageaddr, const u64 count); 413 414u64 ehea_h_register_smr(const u64 adapter_handle, const u64 orig_mr_handle, 415 const u64 vaddr_in, const u32 access_ctrl, const u32 pd, 416 struct ehea_mr *mr); 417 418u64 ehea_h_query_ehea(const u64 adapter_handle, void *cb_addr); 419 420/* output param R5 */ 421#define H_MEHEAPORT_CAT EHEA_BMASK_IBM(40, 47) 422#define H_MEHEAPORT_PN EHEA_BMASK_IBM(48, 63) 423 424u64 ehea_h_query_ehea_port(const u64 adapter_handle, const u16 port_num, 425 const u8 cb_cat, const u64 select_mask, 426 void *cb_addr); 427 428u64 ehea_h_modify_ehea_port(const u64 adapter_handle, const u16 port_num, 429 const u8 cb_cat, const u64 select_mask, 430 void *cb_addr); 431 432#define H_REGBCMC_PN EHEA_BMASK_IBM(48, 63) 433#define H_REGBCMC_REGTYPE EHEA_BMASK_IBM(60, 63) 434#define H_REGBCMC_MACADDR EHEA_BMASK_IBM(16, 63) 435#define H_REGBCMC_VLANID EHEA_BMASK_IBM(52, 63) 436 437u64 ehea_h_reg_dereg_bcmc(const u64 adapter_handle, const u16 port_num, 438 const u8 reg_type, const u64 mc_mac_addr, 439 const u16 vlan_id, const u32 hcall_id); 440 441u64 ehea_h_reset_events(const u64 adapter_handle, const u64 neq_handle, 442 const u64 event_mask); 443 444u64 ehea_h_error_data(const u64 adapter_handle, const u64 ressource_handle, 445 void *rblock); 446 447#endif /* __EHEA_PHYP_H__ */ 448