1/* 2 * This file is part of the Chelsio T4 Ethernet driver for Linux. 3 * 4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35#ifndef __T4_REGS_H 36#define __T4_REGS_H 37 38#define MYPF_BASE 0x1b000 39#define MYPF_REG(reg_addr) (MYPF_BASE + (reg_addr)) 40 41#define PF0_BASE 0x1e000 42#define PF0_REG(reg_addr) (PF0_BASE + (reg_addr)) 43 44#define PF_STRIDE 0x400 45#define PF_BASE(idx) (PF0_BASE + (idx) * PF_STRIDE) 46#define PF_REG(idx, reg) (PF_BASE(idx) + (reg)) 47 48#define MYPORT_BASE 0x1c000 49#define MYPORT_REG(reg_addr) (MYPORT_BASE + (reg_addr)) 50 51#define PORT0_BASE 0x20000 52#define PORT0_REG(reg_addr) (PORT0_BASE + (reg_addr)) 53 54#define PORT_STRIDE 0x2000 55#define PORT_BASE(idx) (PORT0_BASE + (idx) * PORT_STRIDE) 56#define PORT_REG(idx, reg) (PORT_BASE(idx) + (reg)) 57 58#define EDC_STRIDE (EDC_1_BASE_ADDR - EDC_0_BASE_ADDR) 59#define EDC_REG(reg, idx) (reg + EDC_STRIDE * idx) 60 61#define PCIE_MEM_ACCESS_REG(reg_addr, idx) ((reg_addr) + (idx) * 8) 62#define PCIE_MAILBOX_REG(reg_addr, idx) ((reg_addr) + (idx) * 8) 63#define MC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) 64#define EDC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) 65 66#define PCIE_FW_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) 67 68#define SGE_PF_KDOORBELL_A 0x0 69 70#define QID_S 15 71#define QID_V(x) ((x) << QID_S) 72 73#define DBPRIO_S 14 74#define DBPRIO_V(x) ((x) << DBPRIO_S) 75#define DBPRIO_F DBPRIO_V(1U) 76 77#define PIDX_S 0 78#define PIDX_V(x) ((x) << PIDX_S) 79 80#define SGE_VF_KDOORBELL_A 0x0 81 82#define DBTYPE_S 13 83#define DBTYPE_V(x) ((x) << DBTYPE_S) 84#define DBTYPE_F DBTYPE_V(1U) 85 86#define PIDX_T5_S 0 87#define PIDX_T5_M 0x1fffU 88#define PIDX_T5_V(x) ((x) << PIDX_T5_S) 89#define PIDX_T5_G(x) (((x) >> PIDX_T5_S) & PIDX_T5_M) 90 91#define SGE_PF_GTS_A 0x4 92 93#define INGRESSQID_S 16 94#define INGRESSQID_V(x) ((x) << INGRESSQID_S) 95 96#define TIMERREG_S 13 97#define TIMERREG_V(x) ((x) << TIMERREG_S) 98 99#define SEINTARM_S 12 100#define SEINTARM_V(x) ((x) << SEINTARM_S) 101 102#define CIDXINC_S 0 103#define CIDXINC_M 0xfffU 104#define CIDXINC_V(x) ((x) << CIDXINC_S) 105 106#define SGE_CONTROL_A 0x1008 107#define SGE_CONTROL2_A 0x1124 108 109#define RXPKTCPLMODE_S 18 110#define RXPKTCPLMODE_V(x) ((x) << RXPKTCPLMODE_S) 111#define RXPKTCPLMODE_F RXPKTCPLMODE_V(1U) 112 113#define EGRSTATUSPAGESIZE_S 17 114#define EGRSTATUSPAGESIZE_V(x) ((x) << EGRSTATUSPAGESIZE_S) 115#define EGRSTATUSPAGESIZE_F EGRSTATUSPAGESIZE_V(1U) 116 117#define PKTSHIFT_S 10 118#define PKTSHIFT_M 0x7U 119#define PKTSHIFT_V(x) ((x) << PKTSHIFT_S) 120#define PKTSHIFT_G(x) (((x) >> PKTSHIFT_S) & PKTSHIFT_M) 121 122#define INGPCIEBOUNDARY_S 7 123#define INGPCIEBOUNDARY_V(x) ((x) << INGPCIEBOUNDARY_S) 124 125#define INGPADBOUNDARY_S 4 126#define INGPADBOUNDARY_M 0x7U 127#define INGPADBOUNDARY_V(x) ((x) << INGPADBOUNDARY_S) 128#define INGPADBOUNDARY_G(x) (((x) >> INGPADBOUNDARY_S) & INGPADBOUNDARY_M) 129 130#define EGRPCIEBOUNDARY_S 1 131#define EGRPCIEBOUNDARY_V(x) ((x) << EGRPCIEBOUNDARY_S) 132 133#define INGPACKBOUNDARY_S 16 134#define INGPACKBOUNDARY_M 0x7U 135#define INGPACKBOUNDARY_V(x) ((x) << INGPACKBOUNDARY_S) 136#define INGPACKBOUNDARY_G(x) (((x) >> INGPACKBOUNDARY_S) \ 137 & INGPACKBOUNDARY_M) 138 139#define GLOBALENABLE_S 0 140#define GLOBALENABLE_V(x) ((x) << GLOBALENABLE_S) 141#define GLOBALENABLE_F GLOBALENABLE_V(1U) 142 143#define SGE_HOST_PAGE_SIZE_A 0x100c 144 145#define HOSTPAGESIZEPF7_S 28 146#define HOSTPAGESIZEPF7_M 0xfU 147#define HOSTPAGESIZEPF7_V(x) ((x) << HOSTPAGESIZEPF7_S) 148#define HOSTPAGESIZEPF7_G(x) (((x) >> HOSTPAGESIZEPF7_S) & HOSTPAGESIZEPF7_M) 149 150#define HOSTPAGESIZEPF6_S 24 151#define HOSTPAGESIZEPF6_M 0xfU 152#define HOSTPAGESIZEPF6_V(x) ((x) << HOSTPAGESIZEPF6_S) 153#define HOSTPAGESIZEPF6_G(x) (((x) >> HOSTPAGESIZEPF6_S) & HOSTPAGESIZEPF6_M) 154 155#define HOSTPAGESIZEPF5_S 20 156#define HOSTPAGESIZEPF5_M 0xfU 157#define HOSTPAGESIZEPF5_V(x) ((x) << HOSTPAGESIZEPF5_S) 158#define HOSTPAGESIZEPF5_G(x) (((x) >> HOSTPAGESIZEPF5_S) & HOSTPAGESIZEPF5_M) 159 160#define HOSTPAGESIZEPF4_S 16 161#define HOSTPAGESIZEPF4_M 0xfU 162#define HOSTPAGESIZEPF4_V(x) ((x) << HOSTPAGESIZEPF4_S) 163#define HOSTPAGESIZEPF4_G(x) (((x) >> HOSTPAGESIZEPF4_S) & HOSTPAGESIZEPF4_M) 164 165#define HOSTPAGESIZEPF3_S 12 166#define HOSTPAGESIZEPF3_M 0xfU 167#define HOSTPAGESIZEPF3_V(x) ((x) << HOSTPAGESIZEPF3_S) 168#define HOSTPAGESIZEPF3_G(x) (((x) >> HOSTPAGESIZEPF3_S) & HOSTPAGESIZEPF3_M) 169 170#define HOSTPAGESIZEPF2_S 8 171#define HOSTPAGESIZEPF2_M 0xfU 172#define HOSTPAGESIZEPF2_V(x) ((x) << HOSTPAGESIZEPF2_S) 173#define HOSTPAGESIZEPF2_G(x) (((x) >> HOSTPAGESIZEPF2_S) & HOSTPAGESIZEPF2_M) 174 175#define HOSTPAGESIZEPF1_S 4 176#define HOSTPAGESIZEPF1_M 0xfU 177#define HOSTPAGESIZEPF1_V(x) ((x) << HOSTPAGESIZEPF1_S) 178#define HOSTPAGESIZEPF1_G(x) (((x) >> HOSTPAGESIZEPF1_S) & HOSTPAGESIZEPF1_M) 179 180#define HOSTPAGESIZEPF0_S 0 181#define HOSTPAGESIZEPF0_M 0xfU 182#define HOSTPAGESIZEPF0_V(x) ((x) << HOSTPAGESIZEPF0_S) 183#define HOSTPAGESIZEPF0_G(x) (((x) >> HOSTPAGESIZEPF0_S) & HOSTPAGESIZEPF0_M) 184 185#define SGE_EGRESS_QUEUES_PER_PAGE_PF_A 0x1010 186#define SGE_EGRESS_QUEUES_PER_PAGE_VF_A 0x1014 187 188#define QUEUESPERPAGEPF1_S 4 189 190#define QUEUESPERPAGEPF0_S 0 191#define QUEUESPERPAGEPF0_M 0xfU 192#define QUEUESPERPAGEPF0_V(x) ((x) << QUEUESPERPAGEPF0_S) 193#define QUEUESPERPAGEPF0_G(x) (((x) >> QUEUESPERPAGEPF0_S) & QUEUESPERPAGEPF0_M) 194 195#define SGE_INT_CAUSE1_A 0x1024 196#define SGE_INT_CAUSE2_A 0x1030 197#define SGE_INT_CAUSE3_A 0x103c 198 199#define ERR_FLM_DBP_S 31 200#define ERR_FLM_DBP_V(x) ((x) << ERR_FLM_DBP_S) 201#define ERR_FLM_DBP_F ERR_FLM_DBP_V(1U) 202 203#define ERR_FLM_IDMA1_S 30 204#define ERR_FLM_IDMA1_V(x) ((x) << ERR_FLM_IDMA1_S) 205#define ERR_FLM_IDMA1_F ERR_FLM_IDMA1_V(1U) 206 207#define ERR_FLM_IDMA0_S 29 208#define ERR_FLM_IDMA0_V(x) ((x) << ERR_FLM_IDMA0_S) 209#define ERR_FLM_IDMA0_F ERR_FLM_IDMA0_V(1U) 210 211#define ERR_FLM_HINT_S 28 212#define ERR_FLM_HINT_V(x) ((x) << ERR_FLM_HINT_S) 213#define ERR_FLM_HINT_F ERR_FLM_HINT_V(1U) 214 215#define ERR_PCIE_ERROR3_S 27 216#define ERR_PCIE_ERROR3_V(x) ((x) << ERR_PCIE_ERROR3_S) 217#define ERR_PCIE_ERROR3_F ERR_PCIE_ERROR3_V(1U) 218 219#define ERR_PCIE_ERROR2_S 26 220#define ERR_PCIE_ERROR2_V(x) ((x) << ERR_PCIE_ERROR2_S) 221#define ERR_PCIE_ERROR2_F ERR_PCIE_ERROR2_V(1U) 222 223#define ERR_PCIE_ERROR1_S 25 224#define ERR_PCIE_ERROR1_V(x) ((x) << ERR_PCIE_ERROR1_S) 225#define ERR_PCIE_ERROR1_F ERR_PCIE_ERROR1_V(1U) 226 227#define ERR_PCIE_ERROR0_S 24 228#define ERR_PCIE_ERROR0_V(x) ((x) << ERR_PCIE_ERROR0_S) 229#define ERR_PCIE_ERROR0_F ERR_PCIE_ERROR0_V(1U) 230 231#define ERR_CPL_EXCEED_IQE_SIZE_S 22 232#define ERR_CPL_EXCEED_IQE_SIZE_V(x) ((x) << ERR_CPL_EXCEED_IQE_SIZE_S) 233#define ERR_CPL_EXCEED_IQE_SIZE_F ERR_CPL_EXCEED_IQE_SIZE_V(1U) 234 235#define ERR_INVALID_CIDX_INC_S 21 236#define ERR_INVALID_CIDX_INC_V(x) ((x) << ERR_INVALID_CIDX_INC_S) 237#define ERR_INVALID_CIDX_INC_F ERR_INVALID_CIDX_INC_V(1U) 238 239#define ERR_CPL_OPCODE_0_S 19 240#define ERR_CPL_OPCODE_0_V(x) ((x) << ERR_CPL_OPCODE_0_S) 241#define ERR_CPL_OPCODE_0_F ERR_CPL_OPCODE_0_V(1U) 242 243#define ERR_DROPPED_DB_S 18 244#define ERR_DROPPED_DB_V(x) ((x) << ERR_DROPPED_DB_S) 245#define ERR_DROPPED_DB_F ERR_DROPPED_DB_V(1U) 246 247#define ERR_DATA_CPL_ON_HIGH_QID1_S 17 248#define ERR_DATA_CPL_ON_HIGH_QID1_V(x) ((x) << ERR_DATA_CPL_ON_HIGH_QID1_S) 249#define ERR_DATA_CPL_ON_HIGH_QID1_F ERR_DATA_CPL_ON_HIGH_QID1_V(1U) 250 251#define ERR_DATA_CPL_ON_HIGH_QID0_S 16 252#define ERR_DATA_CPL_ON_HIGH_QID0_V(x) ((x) << ERR_DATA_CPL_ON_HIGH_QID0_S) 253#define ERR_DATA_CPL_ON_HIGH_QID0_F ERR_DATA_CPL_ON_HIGH_QID0_V(1U) 254 255#define ERR_BAD_DB_PIDX3_S 15 256#define ERR_BAD_DB_PIDX3_V(x) ((x) << ERR_BAD_DB_PIDX3_S) 257#define ERR_BAD_DB_PIDX3_F ERR_BAD_DB_PIDX3_V(1U) 258 259#define ERR_BAD_DB_PIDX2_S 14 260#define ERR_BAD_DB_PIDX2_V(x) ((x) << ERR_BAD_DB_PIDX2_S) 261#define ERR_BAD_DB_PIDX2_F ERR_BAD_DB_PIDX2_V(1U) 262 263#define ERR_BAD_DB_PIDX1_S 13 264#define ERR_BAD_DB_PIDX1_V(x) ((x) << ERR_BAD_DB_PIDX1_S) 265#define ERR_BAD_DB_PIDX1_F ERR_BAD_DB_PIDX1_V(1U) 266 267#define ERR_BAD_DB_PIDX0_S 12 268#define ERR_BAD_DB_PIDX0_V(x) ((x) << ERR_BAD_DB_PIDX0_S) 269#define ERR_BAD_DB_PIDX0_F ERR_BAD_DB_PIDX0_V(1U) 270 271#define ERR_ING_CTXT_PRIO_S 10 272#define ERR_ING_CTXT_PRIO_V(x) ((x) << ERR_ING_CTXT_PRIO_S) 273#define ERR_ING_CTXT_PRIO_F ERR_ING_CTXT_PRIO_V(1U) 274 275#define ERR_EGR_CTXT_PRIO_S 9 276#define ERR_EGR_CTXT_PRIO_V(x) ((x) << ERR_EGR_CTXT_PRIO_S) 277#define ERR_EGR_CTXT_PRIO_F ERR_EGR_CTXT_PRIO_V(1U) 278 279#define DBFIFO_HP_INT_S 8 280#define DBFIFO_HP_INT_V(x) ((x) << DBFIFO_HP_INT_S) 281#define DBFIFO_HP_INT_F DBFIFO_HP_INT_V(1U) 282 283#define DBFIFO_LP_INT_S 7 284#define DBFIFO_LP_INT_V(x) ((x) << DBFIFO_LP_INT_S) 285#define DBFIFO_LP_INT_F DBFIFO_LP_INT_V(1U) 286 287#define INGRESS_SIZE_ERR_S 5 288#define INGRESS_SIZE_ERR_V(x) ((x) << INGRESS_SIZE_ERR_S) 289#define INGRESS_SIZE_ERR_F INGRESS_SIZE_ERR_V(1U) 290 291#define EGRESS_SIZE_ERR_S 4 292#define EGRESS_SIZE_ERR_V(x) ((x) << EGRESS_SIZE_ERR_S) 293#define EGRESS_SIZE_ERR_F EGRESS_SIZE_ERR_V(1U) 294 295#define SGE_INT_ENABLE3_A 0x1040 296#define SGE_FL_BUFFER_SIZE0_A 0x1044 297#define SGE_FL_BUFFER_SIZE1_A 0x1048 298#define SGE_FL_BUFFER_SIZE2_A 0x104c 299#define SGE_FL_BUFFER_SIZE3_A 0x1050 300#define SGE_FL_BUFFER_SIZE4_A 0x1054 301#define SGE_FL_BUFFER_SIZE5_A 0x1058 302#define SGE_FL_BUFFER_SIZE6_A 0x105c 303#define SGE_FL_BUFFER_SIZE7_A 0x1060 304#define SGE_FL_BUFFER_SIZE8_A 0x1064 305 306#define SGE_INGRESS_RX_THRESHOLD_A 0x10a0 307 308#define THRESHOLD_0_S 24 309#define THRESHOLD_0_M 0x3fU 310#define THRESHOLD_0_V(x) ((x) << THRESHOLD_0_S) 311#define THRESHOLD_0_G(x) (((x) >> THRESHOLD_0_S) & THRESHOLD_0_M) 312 313#define THRESHOLD_1_S 16 314#define THRESHOLD_1_M 0x3fU 315#define THRESHOLD_1_V(x) ((x) << THRESHOLD_1_S) 316#define THRESHOLD_1_G(x) (((x) >> THRESHOLD_1_S) & THRESHOLD_1_M) 317 318#define THRESHOLD_2_S 8 319#define THRESHOLD_2_M 0x3fU 320#define THRESHOLD_2_V(x) ((x) << THRESHOLD_2_S) 321#define THRESHOLD_2_G(x) (((x) >> THRESHOLD_2_S) & THRESHOLD_2_M) 322 323#define THRESHOLD_3_S 0 324#define THRESHOLD_3_M 0x3fU 325#define THRESHOLD_3_V(x) ((x) << THRESHOLD_3_S) 326#define THRESHOLD_3_G(x) (((x) >> THRESHOLD_3_S) & THRESHOLD_3_M) 327 328#define SGE_CONM_CTRL_A 0x1094 329 330#define EGRTHRESHOLD_S 8 331#define EGRTHRESHOLD_M 0x3fU 332#define EGRTHRESHOLD_V(x) ((x) << EGRTHRESHOLD_S) 333#define EGRTHRESHOLD_G(x) (((x) >> EGRTHRESHOLD_S) & EGRTHRESHOLD_M) 334 335#define EGRTHRESHOLDPACKING_S 14 336#define EGRTHRESHOLDPACKING_M 0x3fU 337#define EGRTHRESHOLDPACKING_V(x) ((x) << EGRTHRESHOLDPACKING_S) 338#define EGRTHRESHOLDPACKING_G(x) \ 339 (((x) >> EGRTHRESHOLDPACKING_S) & EGRTHRESHOLDPACKING_M) 340 341#define SGE_TIMESTAMP_LO_A 0x1098 342#define SGE_TIMESTAMP_HI_A 0x109c 343 344#define TSOP_S 28 345#define TSOP_M 0x3U 346#define TSOP_V(x) ((x) << TSOP_S) 347#define TSOP_G(x) (((x) >> TSOP_S) & TSOP_M) 348 349#define TSVAL_S 0 350#define TSVAL_M 0xfffffffU 351#define TSVAL_V(x) ((x) << TSVAL_S) 352#define TSVAL_G(x) (((x) >> TSVAL_S) & TSVAL_M) 353 354#define SGE_DBFIFO_STATUS_A 0x10a4 355 356#define HP_INT_THRESH_S 28 357#define HP_INT_THRESH_M 0xfU 358#define HP_INT_THRESH_V(x) ((x) << HP_INT_THRESH_S) 359 360#define LP_INT_THRESH_S 12 361#define LP_INT_THRESH_M 0xfU 362#define LP_INT_THRESH_V(x) ((x) << LP_INT_THRESH_S) 363 364#define SGE_DOORBELL_CONTROL_A 0x10a8 365 366#define NOCOALESCE_S 26 367#define NOCOALESCE_V(x) ((x) << NOCOALESCE_S) 368#define NOCOALESCE_F NOCOALESCE_V(1U) 369 370#define ENABLE_DROP_S 13 371#define ENABLE_DROP_V(x) ((x) << ENABLE_DROP_S) 372#define ENABLE_DROP_F ENABLE_DROP_V(1U) 373 374#define SGE_TIMER_VALUE_0_AND_1_A 0x10b8 375 376#define TIMERVALUE0_S 16 377#define TIMERVALUE0_M 0xffffU 378#define TIMERVALUE0_V(x) ((x) << TIMERVALUE0_S) 379#define TIMERVALUE0_G(x) (((x) >> TIMERVALUE0_S) & TIMERVALUE0_M) 380 381#define TIMERVALUE1_S 0 382#define TIMERVALUE1_M 0xffffU 383#define TIMERVALUE1_V(x) ((x) << TIMERVALUE1_S) 384#define TIMERVALUE1_G(x) (((x) >> TIMERVALUE1_S) & TIMERVALUE1_M) 385 386#define SGE_TIMER_VALUE_2_AND_3_A 0x10bc 387 388#define TIMERVALUE2_S 16 389#define TIMERVALUE2_M 0xffffU 390#define TIMERVALUE2_V(x) ((x) << TIMERVALUE2_S) 391#define TIMERVALUE2_G(x) (((x) >> TIMERVALUE2_S) & TIMERVALUE2_M) 392 393#define TIMERVALUE3_S 0 394#define TIMERVALUE3_M 0xffffU 395#define TIMERVALUE3_V(x) ((x) << TIMERVALUE3_S) 396#define TIMERVALUE3_G(x) (((x) >> TIMERVALUE3_S) & TIMERVALUE3_M) 397 398#define SGE_TIMER_VALUE_4_AND_5_A 0x10c0 399 400#define TIMERVALUE4_S 16 401#define TIMERVALUE4_M 0xffffU 402#define TIMERVALUE4_V(x) ((x) << TIMERVALUE4_S) 403#define TIMERVALUE4_G(x) (((x) >> TIMERVALUE4_S) & TIMERVALUE4_M) 404 405#define TIMERVALUE5_S 0 406#define TIMERVALUE5_M 0xffffU 407#define TIMERVALUE5_V(x) ((x) << TIMERVALUE5_S) 408#define TIMERVALUE5_G(x) (((x) >> TIMERVALUE5_S) & TIMERVALUE5_M) 409 410#define SGE_DEBUG_INDEX_A 0x10cc 411#define SGE_DEBUG_DATA_HIGH_A 0x10d0 412#define SGE_DEBUG_DATA_LOW_A 0x10d4 413 414#define SGE_DEBUG_DATA_LOW_INDEX_2_A 0x12c8 415#define SGE_DEBUG_DATA_LOW_INDEX_3_A 0x12cc 416#define SGE_DEBUG_DATA_HIGH_INDEX_10_A 0x12a8 417 418#define SGE_INGRESS_QUEUES_PER_PAGE_PF_A 0x10f4 419#define SGE_INGRESS_QUEUES_PER_PAGE_VF_A 0x10f8 420 421#define HP_INT_THRESH_S 28 422#define HP_INT_THRESH_M 0xfU 423#define HP_INT_THRESH_V(x) ((x) << HP_INT_THRESH_S) 424 425#define HP_COUNT_S 16 426#define HP_COUNT_M 0x7ffU 427#define HP_COUNT_G(x) (((x) >> HP_COUNT_S) & HP_COUNT_M) 428 429#define LP_INT_THRESH_S 12 430#define LP_INT_THRESH_M 0xfU 431#define LP_INT_THRESH_V(x) ((x) << LP_INT_THRESH_S) 432 433#define LP_COUNT_S 0 434#define LP_COUNT_M 0x7ffU 435#define LP_COUNT_G(x) (((x) >> LP_COUNT_S) & LP_COUNT_M) 436 437#define LP_INT_THRESH_T5_S 18 438#define LP_INT_THRESH_T5_M 0xfffU 439#define LP_INT_THRESH_T5_V(x) ((x) << LP_INT_THRESH_T5_S) 440 441#define LP_COUNT_T5_S 0 442#define LP_COUNT_T5_M 0x3ffffU 443#define LP_COUNT_T5_G(x) (((x) >> LP_COUNT_T5_S) & LP_COUNT_T5_M) 444 445#define SGE_DOORBELL_CONTROL_A 0x10a8 446 447#define SGE_STAT_TOTAL_A 0x10e4 448#define SGE_STAT_MATCH_A 0x10e8 449#define SGE_STAT_CFG_A 0x10ec 450 451#define STATSOURCE_T5_S 9 452#define STATSOURCE_T5_V(x) ((x) << STATSOURCE_T5_S) 453 454#define SGE_DBFIFO_STATUS2_A 0x1118 455 456#define HP_INT_THRESH_T5_S 10 457#define HP_INT_THRESH_T5_M 0xfU 458#define HP_INT_THRESH_T5_V(x) ((x) << HP_INT_THRESH_T5_S) 459 460#define HP_COUNT_T5_S 0 461#define HP_COUNT_T5_M 0x3ffU 462#define HP_COUNT_T5_G(x) (((x) >> HP_COUNT_T5_S) & HP_COUNT_T5_M) 463 464#define ENABLE_DROP_S 13 465#define ENABLE_DROP_V(x) ((x) << ENABLE_DROP_S) 466#define ENABLE_DROP_F ENABLE_DROP_V(1U) 467 468#define DROPPED_DB_S 0 469#define DROPPED_DB_V(x) ((x) << DROPPED_DB_S) 470#define DROPPED_DB_F DROPPED_DB_V(1U) 471 472#define SGE_CTXT_CMD_A 0x11fc 473#define SGE_DBQ_CTXT_BADDR_A 0x1084 474 475/* registers for module PCIE */ 476#define PCIE_PF_CFG_A 0x40 477 478#define AIVEC_S 4 479#define AIVEC_M 0x3ffU 480#define AIVEC_V(x) ((x) << AIVEC_S) 481 482#define PCIE_PF_CLI_A 0x44 483#define PCIE_INT_CAUSE_A 0x3004 484 485#define UNXSPLCPLERR_S 29 486#define UNXSPLCPLERR_V(x) ((x) << UNXSPLCPLERR_S) 487#define UNXSPLCPLERR_F UNXSPLCPLERR_V(1U) 488 489#define PCIEPINT_S 28 490#define PCIEPINT_V(x) ((x) << PCIEPINT_S) 491#define PCIEPINT_F PCIEPINT_V(1U) 492 493#define PCIESINT_S 27 494#define PCIESINT_V(x) ((x) << PCIESINT_S) 495#define PCIESINT_F PCIESINT_V(1U) 496 497#define RPLPERR_S 26 498#define RPLPERR_V(x) ((x) << RPLPERR_S) 499#define RPLPERR_F RPLPERR_V(1U) 500 501#define RXWRPERR_S 25 502#define RXWRPERR_V(x) ((x) << RXWRPERR_S) 503#define RXWRPERR_F RXWRPERR_V(1U) 504 505#define RXCPLPERR_S 24 506#define RXCPLPERR_V(x) ((x) << RXCPLPERR_S) 507#define RXCPLPERR_F RXCPLPERR_V(1U) 508 509#define PIOTAGPERR_S 23 510#define PIOTAGPERR_V(x) ((x) << PIOTAGPERR_S) 511#define PIOTAGPERR_F PIOTAGPERR_V(1U) 512 513#define MATAGPERR_S 22 514#define MATAGPERR_V(x) ((x) << MATAGPERR_S) 515#define MATAGPERR_F MATAGPERR_V(1U) 516 517#define INTXCLRPERR_S 21 518#define INTXCLRPERR_V(x) ((x) << INTXCLRPERR_S) 519#define INTXCLRPERR_F INTXCLRPERR_V(1U) 520 521#define FIDPERR_S 20 522#define FIDPERR_V(x) ((x) << FIDPERR_S) 523#define FIDPERR_F FIDPERR_V(1U) 524 525#define CFGSNPPERR_S 19 526#define CFGSNPPERR_V(x) ((x) << CFGSNPPERR_S) 527#define CFGSNPPERR_F CFGSNPPERR_V(1U) 528 529#define HRSPPERR_S 18 530#define HRSPPERR_V(x) ((x) << HRSPPERR_S) 531#define HRSPPERR_F HRSPPERR_V(1U) 532 533#define HREQPERR_S 17 534#define HREQPERR_V(x) ((x) << HREQPERR_S) 535#define HREQPERR_F HREQPERR_V(1U) 536 537#define HCNTPERR_S 16 538#define HCNTPERR_V(x) ((x) << HCNTPERR_S) 539#define HCNTPERR_F HCNTPERR_V(1U) 540 541#define DRSPPERR_S 15 542#define DRSPPERR_V(x) ((x) << DRSPPERR_S) 543#define DRSPPERR_F DRSPPERR_V(1U) 544 545#define DREQPERR_S 14 546#define DREQPERR_V(x) ((x) << DREQPERR_S) 547#define DREQPERR_F DREQPERR_V(1U) 548 549#define DCNTPERR_S 13 550#define DCNTPERR_V(x) ((x) << DCNTPERR_S) 551#define DCNTPERR_F DCNTPERR_V(1U) 552 553#define CRSPPERR_S 12 554#define CRSPPERR_V(x) ((x) << CRSPPERR_S) 555#define CRSPPERR_F CRSPPERR_V(1U) 556 557#define CREQPERR_S 11 558#define CREQPERR_V(x) ((x) << CREQPERR_S) 559#define CREQPERR_F CREQPERR_V(1U) 560 561#define CCNTPERR_S 10 562#define CCNTPERR_V(x) ((x) << CCNTPERR_S) 563#define CCNTPERR_F CCNTPERR_V(1U) 564 565#define TARTAGPERR_S 9 566#define TARTAGPERR_V(x) ((x) << TARTAGPERR_S) 567#define TARTAGPERR_F TARTAGPERR_V(1U) 568 569#define PIOREQPERR_S 8 570#define PIOREQPERR_V(x) ((x) << PIOREQPERR_S) 571#define PIOREQPERR_F PIOREQPERR_V(1U) 572 573#define PIOCPLPERR_S 7 574#define PIOCPLPERR_V(x) ((x) << PIOCPLPERR_S) 575#define PIOCPLPERR_F PIOCPLPERR_V(1U) 576 577#define MSIXDIPERR_S 6 578#define MSIXDIPERR_V(x) ((x) << MSIXDIPERR_S) 579#define MSIXDIPERR_F MSIXDIPERR_V(1U) 580 581#define MSIXDATAPERR_S 5 582#define MSIXDATAPERR_V(x) ((x) << MSIXDATAPERR_S) 583#define MSIXDATAPERR_F MSIXDATAPERR_V(1U) 584 585#define MSIXADDRHPERR_S 4 586#define MSIXADDRHPERR_V(x) ((x) << MSIXADDRHPERR_S) 587#define MSIXADDRHPERR_F MSIXADDRHPERR_V(1U) 588 589#define MSIXADDRLPERR_S 3 590#define MSIXADDRLPERR_V(x) ((x) << MSIXADDRLPERR_S) 591#define MSIXADDRLPERR_F MSIXADDRLPERR_V(1U) 592 593#define MSIDATAPERR_S 2 594#define MSIDATAPERR_V(x) ((x) << MSIDATAPERR_S) 595#define MSIDATAPERR_F MSIDATAPERR_V(1U) 596 597#define MSIADDRHPERR_S 1 598#define MSIADDRHPERR_V(x) ((x) << MSIADDRHPERR_S) 599#define MSIADDRHPERR_F MSIADDRHPERR_V(1U) 600 601#define MSIADDRLPERR_S 0 602#define MSIADDRLPERR_V(x) ((x) << MSIADDRLPERR_S) 603#define MSIADDRLPERR_F MSIADDRLPERR_V(1U) 604 605#define READRSPERR_S 29 606#define READRSPERR_V(x) ((x) << READRSPERR_S) 607#define READRSPERR_F READRSPERR_V(1U) 608 609#define TRGT1GRPPERR_S 28 610#define TRGT1GRPPERR_V(x) ((x) << TRGT1GRPPERR_S) 611#define TRGT1GRPPERR_F TRGT1GRPPERR_V(1U) 612 613#define IPSOTPERR_S 27 614#define IPSOTPERR_V(x) ((x) << IPSOTPERR_S) 615#define IPSOTPERR_F IPSOTPERR_V(1U) 616 617#define IPRETRYPERR_S 26 618#define IPRETRYPERR_V(x) ((x) << IPRETRYPERR_S) 619#define IPRETRYPERR_F IPRETRYPERR_V(1U) 620 621#define IPRXDATAGRPPERR_S 25 622#define IPRXDATAGRPPERR_V(x) ((x) << IPRXDATAGRPPERR_S) 623#define IPRXDATAGRPPERR_F IPRXDATAGRPPERR_V(1U) 624 625#define IPRXHDRGRPPERR_S 24 626#define IPRXHDRGRPPERR_V(x) ((x) << IPRXHDRGRPPERR_S) 627#define IPRXHDRGRPPERR_F IPRXHDRGRPPERR_V(1U) 628 629#define MAGRPPERR_S 22 630#define MAGRPPERR_V(x) ((x) << MAGRPPERR_S) 631#define MAGRPPERR_F MAGRPPERR_V(1U) 632 633#define VFIDPERR_S 21 634#define VFIDPERR_V(x) ((x) << VFIDPERR_S) 635#define VFIDPERR_F VFIDPERR_V(1U) 636 637#define HREQWRPERR_S 16 638#define HREQWRPERR_V(x) ((x) << HREQWRPERR_S) 639#define HREQWRPERR_F HREQWRPERR_V(1U) 640 641#define DREQWRPERR_S 13 642#define DREQWRPERR_V(x) ((x) << DREQWRPERR_S) 643#define DREQWRPERR_F DREQWRPERR_V(1U) 644 645#define CREQRDPERR_S 11 646#define CREQRDPERR_V(x) ((x) << CREQRDPERR_S) 647#define CREQRDPERR_F CREQRDPERR_V(1U) 648 649#define MSTTAGQPERR_S 10 650#define MSTTAGQPERR_V(x) ((x) << MSTTAGQPERR_S) 651#define MSTTAGQPERR_F MSTTAGQPERR_V(1U) 652 653#define PIOREQGRPPERR_S 8 654#define PIOREQGRPPERR_V(x) ((x) << PIOREQGRPPERR_S) 655#define PIOREQGRPPERR_F PIOREQGRPPERR_V(1U) 656 657#define PIOCPLGRPPERR_S 7 658#define PIOCPLGRPPERR_V(x) ((x) << PIOCPLGRPPERR_S) 659#define PIOCPLGRPPERR_F PIOCPLGRPPERR_V(1U) 660 661#define MSIXSTIPERR_S 2 662#define MSIXSTIPERR_V(x) ((x) << MSIXSTIPERR_S) 663#define MSIXSTIPERR_F MSIXSTIPERR_V(1U) 664 665#define MSTTIMEOUTPERR_S 1 666#define MSTTIMEOUTPERR_V(x) ((x) << MSTTIMEOUTPERR_S) 667#define MSTTIMEOUTPERR_F MSTTIMEOUTPERR_V(1U) 668 669#define MSTGRPPERR_S 0 670#define MSTGRPPERR_V(x) ((x) << MSTGRPPERR_S) 671#define MSTGRPPERR_F MSTGRPPERR_V(1U) 672 673#define PCIE_NONFAT_ERR_A 0x3010 674#define PCIE_CFG_SPACE_REQ_A 0x3060 675#define PCIE_CFG_SPACE_DATA_A 0x3064 676#define PCIE_MEM_ACCESS_BASE_WIN_A 0x3068 677 678#define PCIEOFST_S 10 679#define PCIEOFST_M 0x3fffffU 680#define PCIEOFST_G(x) (((x) >> PCIEOFST_S) & PCIEOFST_M) 681 682#define BIR_S 8 683#define BIR_M 0x3U 684#define BIR_V(x) ((x) << BIR_S) 685#define BIR_G(x) (((x) >> BIR_S) & BIR_M) 686 687#define WINDOW_S 0 688#define WINDOW_M 0xffU 689#define WINDOW_V(x) ((x) << WINDOW_S) 690#define WINDOW_G(x) (((x) >> WINDOW_S) & WINDOW_M) 691 692#define PCIE_MEM_ACCESS_OFFSET_A 0x306c 693 694#define ENABLE_S 30 695#define ENABLE_V(x) ((x) << ENABLE_S) 696#define ENABLE_F ENABLE_V(1U) 697 698#define LOCALCFG_S 28 699#define LOCALCFG_V(x) ((x) << LOCALCFG_S) 700#define LOCALCFG_F LOCALCFG_V(1U) 701 702#define FUNCTION_S 12 703#define FUNCTION_V(x) ((x) << FUNCTION_S) 704 705#define REGISTER_S 0 706#define REGISTER_V(x) ((x) << REGISTER_S) 707 708#define PFNUM_S 0 709#define PFNUM_V(x) ((x) << PFNUM_S) 710 711#define PCIE_FW_A 0x30b8 712#define PCIE_FW_PF_A 0x30bc 713 714#define PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS_A 0x5908 715 716#define RNPP_S 31 717#define RNPP_V(x) ((x) << RNPP_S) 718#define RNPP_F RNPP_V(1U) 719 720#define RPCP_S 29 721#define RPCP_V(x) ((x) << RPCP_S) 722#define RPCP_F RPCP_V(1U) 723 724#define RCIP_S 27 725#define RCIP_V(x) ((x) << RCIP_S) 726#define RCIP_F RCIP_V(1U) 727 728#define RCCP_S 26 729#define RCCP_V(x) ((x) << RCCP_S) 730#define RCCP_F RCCP_V(1U) 731 732#define RFTP_S 23 733#define RFTP_V(x) ((x) << RFTP_S) 734#define RFTP_F RFTP_V(1U) 735 736#define PTRP_S 20 737#define PTRP_V(x) ((x) << PTRP_S) 738#define PTRP_F PTRP_V(1U) 739 740#define PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A 0x59a4 741 742#define TPCP_S 30 743#define TPCP_V(x) ((x) << TPCP_S) 744#define TPCP_F TPCP_V(1U) 745 746#define TNPP_S 29 747#define TNPP_V(x) ((x) << TNPP_S) 748#define TNPP_F TNPP_V(1U) 749 750#define TFTP_S 28 751#define TFTP_V(x) ((x) << TFTP_S) 752#define TFTP_F TFTP_V(1U) 753 754#define TCAP_S 27 755#define TCAP_V(x) ((x) << TCAP_S) 756#define TCAP_F TCAP_V(1U) 757 758#define TCIP_S 26 759#define TCIP_V(x) ((x) << TCIP_S) 760#define TCIP_F TCIP_V(1U) 761 762#define RCAP_S 25 763#define RCAP_V(x) ((x) << RCAP_S) 764#define RCAP_F RCAP_V(1U) 765 766#define PLUP_S 23 767#define PLUP_V(x) ((x) << PLUP_S) 768#define PLUP_F PLUP_V(1U) 769 770#define PLDN_S 22 771#define PLDN_V(x) ((x) << PLDN_S) 772#define PLDN_F PLDN_V(1U) 773 774#define OTDD_S 21 775#define OTDD_V(x) ((x) << OTDD_S) 776#define OTDD_F OTDD_V(1U) 777 778#define GTRP_S 20 779#define GTRP_V(x) ((x) << GTRP_S) 780#define GTRP_F GTRP_V(1U) 781 782#define RDPE_S 18 783#define RDPE_V(x) ((x) << RDPE_S) 784#define RDPE_F RDPE_V(1U) 785 786#define TDCE_S 17 787#define TDCE_V(x) ((x) << TDCE_S) 788#define TDCE_F TDCE_V(1U) 789 790#define TDUE_S 16 791#define TDUE_V(x) ((x) << TDUE_S) 792#define TDUE_F TDUE_V(1U) 793 794/* registers for module MC */ 795#define MC_INT_CAUSE_A 0x7518 796#define MC_P_INT_CAUSE_A 0x41318 797 798#define ECC_UE_INT_CAUSE_S 2 799#define ECC_UE_INT_CAUSE_V(x) ((x) << ECC_UE_INT_CAUSE_S) 800#define ECC_UE_INT_CAUSE_F ECC_UE_INT_CAUSE_V(1U) 801 802#define ECC_CE_INT_CAUSE_S 1 803#define ECC_CE_INT_CAUSE_V(x) ((x) << ECC_CE_INT_CAUSE_S) 804#define ECC_CE_INT_CAUSE_F ECC_CE_INT_CAUSE_V(1U) 805 806#define PERR_INT_CAUSE_S 0 807#define PERR_INT_CAUSE_V(x) ((x) << PERR_INT_CAUSE_S) 808#define PERR_INT_CAUSE_F PERR_INT_CAUSE_V(1U) 809 810#define MC_ECC_STATUS_A 0x751c 811#define MC_P_ECC_STATUS_A 0x4131c 812 813#define ECC_CECNT_S 16 814#define ECC_CECNT_M 0xffffU 815#define ECC_CECNT_V(x) ((x) << ECC_CECNT_S) 816#define ECC_CECNT_G(x) (((x) >> ECC_CECNT_S) & ECC_CECNT_M) 817 818#define ECC_UECNT_S 0 819#define ECC_UECNT_M 0xffffU 820#define ECC_UECNT_V(x) ((x) << ECC_UECNT_S) 821#define ECC_UECNT_G(x) (((x) >> ECC_UECNT_S) & ECC_UECNT_M) 822 823#define MC_BIST_CMD_A 0x7600 824 825#define START_BIST_S 31 826#define START_BIST_V(x) ((x) << START_BIST_S) 827#define START_BIST_F START_BIST_V(1U) 828 829#define BIST_CMD_GAP_S 8 830#define BIST_CMD_GAP_V(x) ((x) << BIST_CMD_GAP_S) 831 832#define BIST_OPCODE_S 0 833#define BIST_OPCODE_V(x) ((x) << BIST_OPCODE_S) 834 835#define MC_BIST_CMD_ADDR_A 0x7604 836#define MC_BIST_CMD_LEN_A 0x7608 837#define MC_BIST_DATA_PATTERN_A 0x760c 838 839#define MC_BIST_STATUS_RDATA_A 0x7688 840 841/* registers for module MA */ 842#define MA_EDRAM0_BAR_A 0x77c0 843 844#define EDRAM0_SIZE_S 0 845#define EDRAM0_SIZE_M 0xfffU 846#define EDRAM0_SIZE_V(x) ((x) << EDRAM0_SIZE_S) 847#define EDRAM0_SIZE_G(x) (((x) >> EDRAM0_SIZE_S) & EDRAM0_SIZE_M) 848 849#define MA_EDRAM1_BAR_A 0x77c4 850 851#define EDRAM1_SIZE_S 0 852#define EDRAM1_SIZE_M 0xfffU 853#define EDRAM1_SIZE_V(x) ((x) << EDRAM1_SIZE_S) 854#define EDRAM1_SIZE_G(x) (((x) >> EDRAM1_SIZE_S) & EDRAM1_SIZE_M) 855 856#define MA_EXT_MEMORY_BAR_A 0x77c8 857 858#define EXT_MEM_SIZE_S 0 859#define EXT_MEM_SIZE_M 0xfffU 860#define EXT_MEM_SIZE_V(x) ((x) << EXT_MEM_SIZE_S) 861#define EXT_MEM_SIZE_G(x) (((x) >> EXT_MEM_SIZE_S) & EXT_MEM_SIZE_M) 862 863#define MA_EXT_MEMORY1_BAR_A 0x7808 864 865#define EXT_MEM1_SIZE_S 0 866#define EXT_MEM1_SIZE_M 0xfffU 867#define EXT_MEM1_SIZE_V(x) ((x) << EXT_MEM1_SIZE_S) 868#define EXT_MEM1_SIZE_G(x) (((x) >> EXT_MEM1_SIZE_S) & EXT_MEM1_SIZE_M) 869 870#define MA_EXT_MEMORY0_BAR_A 0x77c8 871 872#define EXT_MEM0_SIZE_S 0 873#define EXT_MEM0_SIZE_M 0xfffU 874#define EXT_MEM0_SIZE_V(x) ((x) << EXT_MEM0_SIZE_S) 875#define EXT_MEM0_SIZE_G(x) (((x) >> EXT_MEM0_SIZE_S) & EXT_MEM0_SIZE_M) 876 877#define MA_TARGET_MEM_ENABLE_A 0x77d8 878 879#define EXT_MEM_ENABLE_S 2 880#define EXT_MEM_ENABLE_V(x) ((x) << EXT_MEM_ENABLE_S) 881#define EXT_MEM_ENABLE_F EXT_MEM_ENABLE_V(1U) 882 883#define EDRAM1_ENABLE_S 1 884#define EDRAM1_ENABLE_V(x) ((x) << EDRAM1_ENABLE_S) 885#define EDRAM1_ENABLE_F EDRAM1_ENABLE_V(1U) 886 887#define EDRAM0_ENABLE_S 0 888#define EDRAM0_ENABLE_V(x) ((x) << EDRAM0_ENABLE_S) 889#define EDRAM0_ENABLE_F EDRAM0_ENABLE_V(1U) 890 891#define EXT_MEM1_ENABLE_S 4 892#define EXT_MEM1_ENABLE_V(x) ((x) << EXT_MEM1_ENABLE_S) 893#define EXT_MEM1_ENABLE_F EXT_MEM1_ENABLE_V(1U) 894 895#define EXT_MEM0_ENABLE_S 2 896#define EXT_MEM0_ENABLE_V(x) ((x) << EXT_MEM0_ENABLE_S) 897#define EXT_MEM0_ENABLE_F EXT_MEM0_ENABLE_V(1U) 898 899#define MA_INT_CAUSE_A 0x77e0 900 901#define MEM_PERR_INT_CAUSE_S 1 902#define MEM_PERR_INT_CAUSE_V(x) ((x) << MEM_PERR_INT_CAUSE_S) 903#define MEM_PERR_INT_CAUSE_F MEM_PERR_INT_CAUSE_V(1U) 904 905#define MEM_WRAP_INT_CAUSE_S 0 906#define MEM_WRAP_INT_CAUSE_V(x) ((x) << MEM_WRAP_INT_CAUSE_S) 907#define MEM_WRAP_INT_CAUSE_F MEM_WRAP_INT_CAUSE_V(1U) 908 909#define MA_INT_WRAP_STATUS_A 0x77e4 910 911#define MEM_WRAP_ADDRESS_S 4 912#define MEM_WRAP_ADDRESS_M 0xfffffffU 913#define MEM_WRAP_ADDRESS_G(x) (((x) >> MEM_WRAP_ADDRESS_S) & MEM_WRAP_ADDRESS_M) 914 915#define MEM_WRAP_CLIENT_NUM_S 0 916#define MEM_WRAP_CLIENT_NUM_M 0xfU 917#define MEM_WRAP_CLIENT_NUM_G(x) \ 918 (((x) >> MEM_WRAP_CLIENT_NUM_S) & MEM_WRAP_CLIENT_NUM_M) 919 920#define MA_PARITY_ERROR_STATUS_A 0x77f4 921#define MA_PARITY_ERROR_STATUS1_A 0x77f4 922#define MA_PARITY_ERROR_STATUS2_A 0x7804 923 924/* registers for module EDC_0 */ 925#define EDC_0_BASE_ADDR 0x7900 926 927#define EDC_BIST_CMD_A 0x7904 928#define EDC_BIST_CMD_ADDR_A 0x7908 929#define EDC_BIST_CMD_LEN_A 0x790c 930#define EDC_BIST_DATA_PATTERN_A 0x7910 931#define EDC_BIST_STATUS_RDATA_A 0x7928 932#define EDC_INT_CAUSE_A 0x7978 933 934#define ECC_UE_PAR_S 5 935#define ECC_UE_PAR_V(x) ((x) << ECC_UE_PAR_S) 936#define ECC_UE_PAR_F ECC_UE_PAR_V(1U) 937 938#define ECC_CE_PAR_S 4 939#define ECC_CE_PAR_V(x) ((x) << ECC_CE_PAR_S) 940#define ECC_CE_PAR_F ECC_CE_PAR_V(1U) 941 942#define PERR_PAR_CAUSE_S 3 943#define PERR_PAR_CAUSE_V(x) ((x) << PERR_PAR_CAUSE_S) 944#define PERR_PAR_CAUSE_F PERR_PAR_CAUSE_V(1U) 945 946#define EDC_ECC_STATUS_A 0x797c 947 948/* registers for module EDC_1 */ 949#define EDC_1_BASE_ADDR 0x7980 950 951/* registers for module CIM */ 952#define CIM_BOOT_CFG_A 0x7b00 953#define CIM_PF_MAILBOX_CTRL_SHADOW_COPY_A 0x290 954 955#define BOOTADDR_M 0xffffff00U 956 957#define UPCRST_S 0 958#define UPCRST_V(x) ((x) << UPCRST_S) 959#define UPCRST_F UPCRST_V(1U) 960 961#define CIM_PF_MAILBOX_DATA_A 0x240 962#define CIM_PF_MAILBOX_CTRL_A 0x280 963 964#define MBMSGVALID_S 3 965#define MBMSGVALID_V(x) ((x) << MBMSGVALID_S) 966#define MBMSGVALID_F MBMSGVALID_V(1U) 967 968#define MBINTREQ_S 2 969#define MBINTREQ_V(x) ((x) << MBINTREQ_S) 970#define MBINTREQ_F MBINTREQ_V(1U) 971 972#define MBOWNER_S 0 973#define MBOWNER_M 0x3U 974#define MBOWNER_V(x) ((x) << MBOWNER_S) 975#define MBOWNER_G(x) (((x) >> MBOWNER_S) & MBOWNER_M) 976 977#define CIM_PF_HOST_INT_ENABLE_A 0x288 978 979#define MBMSGRDYINTEN_S 19 980#define MBMSGRDYINTEN_V(x) ((x) << MBMSGRDYINTEN_S) 981#define MBMSGRDYINTEN_F MBMSGRDYINTEN_V(1U) 982 983#define CIM_PF_HOST_INT_CAUSE_A 0x28c 984 985#define MBMSGRDYINT_S 19 986#define MBMSGRDYINT_V(x) ((x) << MBMSGRDYINT_S) 987#define MBMSGRDYINT_F MBMSGRDYINT_V(1U) 988 989#define CIM_HOST_INT_CAUSE_A 0x7b2c 990 991#define TIEQOUTPARERRINT_S 20 992#define TIEQOUTPARERRINT_V(x) ((x) << TIEQOUTPARERRINT_S) 993#define TIEQOUTPARERRINT_F TIEQOUTPARERRINT_V(1U) 994 995#define TIEQINPARERRINT_S 19 996#define TIEQINPARERRINT_V(x) ((x) << TIEQINPARERRINT_S) 997#define TIEQINPARERRINT_F TIEQINPARERRINT_V(1U) 998 999#define PREFDROPINT_S 1 1000#define PREFDROPINT_V(x) ((x) << PREFDROPINT_S) 1001#define PREFDROPINT_F PREFDROPINT_V(1U) 1002 1003#define UPACCNONZERO_S 0 1004#define UPACCNONZERO_V(x) ((x) << UPACCNONZERO_S) 1005#define UPACCNONZERO_F UPACCNONZERO_V(1U) 1006 1007#define MBHOSTPARERR_S 18 1008#define MBHOSTPARERR_V(x) ((x) << MBHOSTPARERR_S) 1009#define MBHOSTPARERR_F MBHOSTPARERR_V(1U) 1010 1011#define MBUPPARERR_S 17 1012#define MBUPPARERR_V(x) ((x) << MBUPPARERR_S) 1013#define MBUPPARERR_F MBUPPARERR_V(1U) 1014 1015#define IBQTP0PARERR_S 16 1016#define IBQTP0PARERR_V(x) ((x) << IBQTP0PARERR_S) 1017#define IBQTP0PARERR_F IBQTP0PARERR_V(1U) 1018 1019#define IBQTP1PARERR_S 15 1020#define IBQTP1PARERR_V(x) ((x) << IBQTP1PARERR_S) 1021#define IBQTP1PARERR_F IBQTP1PARERR_V(1U) 1022 1023#define IBQULPPARERR_S 14 1024#define IBQULPPARERR_V(x) ((x) << IBQULPPARERR_S) 1025#define IBQULPPARERR_F IBQULPPARERR_V(1U) 1026 1027#define IBQSGELOPARERR_S 13 1028#define IBQSGELOPARERR_V(x) ((x) << IBQSGELOPARERR_S) 1029#define IBQSGELOPARERR_F IBQSGELOPARERR_V(1U) 1030 1031#define IBQSGEHIPARERR_S 12 1032#define IBQSGEHIPARERR_V(x) ((x) << IBQSGEHIPARERR_S) 1033#define IBQSGEHIPARERR_F IBQSGEHIPARERR_V(1U) 1034 1035#define IBQNCSIPARERR_S 11 1036#define IBQNCSIPARERR_V(x) ((x) << IBQNCSIPARERR_S) 1037#define IBQNCSIPARERR_F IBQNCSIPARERR_V(1U) 1038 1039#define OBQULP0PARERR_S 10 1040#define OBQULP0PARERR_V(x) ((x) << OBQULP0PARERR_S) 1041#define OBQULP0PARERR_F OBQULP0PARERR_V(1U) 1042 1043#define OBQULP1PARERR_S 9 1044#define OBQULP1PARERR_V(x) ((x) << OBQULP1PARERR_S) 1045#define OBQULP1PARERR_F OBQULP1PARERR_V(1U) 1046 1047#define OBQULP2PARERR_S 8 1048#define OBQULP2PARERR_V(x) ((x) << OBQULP2PARERR_S) 1049#define OBQULP2PARERR_F OBQULP2PARERR_V(1U) 1050 1051#define OBQULP3PARERR_S 7 1052#define OBQULP3PARERR_V(x) ((x) << OBQULP3PARERR_S) 1053#define OBQULP3PARERR_F OBQULP3PARERR_V(1U) 1054 1055#define OBQSGEPARERR_S 6 1056#define OBQSGEPARERR_V(x) ((x) << OBQSGEPARERR_S) 1057#define OBQSGEPARERR_F OBQSGEPARERR_V(1U) 1058 1059#define OBQNCSIPARERR_S 5 1060#define OBQNCSIPARERR_V(x) ((x) << OBQNCSIPARERR_S) 1061#define OBQNCSIPARERR_F OBQNCSIPARERR_V(1U) 1062 1063#define CIM_HOST_UPACC_INT_CAUSE_A 0x7b34 1064 1065#define EEPROMWRINT_S 30 1066#define EEPROMWRINT_V(x) ((x) << EEPROMWRINT_S) 1067#define EEPROMWRINT_F EEPROMWRINT_V(1U) 1068 1069#define TIMEOUTMAINT_S 29 1070#define TIMEOUTMAINT_V(x) ((x) << TIMEOUTMAINT_S) 1071#define TIMEOUTMAINT_F TIMEOUTMAINT_V(1U) 1072 1073#define TIMEOUTINT_S 28 1074#define TIMEOUTINT_V(x) ((x) << TIMEOUTINT_S) 1075#define TIMEOUTINT_F TIMEOUTINT_V(1U) 1076 1077#define RSPOVRLOOKUPINT_S 27 1078#define RSPOVRLOOKUPINT_V(x) ((x) << RSPOVRLOOKUPINT_S) 1079#define RSPOVRLOOKUPINT_F RSPOVRLOOKUPINT_V(1U) 1080 1081#define REQOVRLOOKUPINT_S 26 1082#define REQOVRLOOKUPINT_V(x) ((x) << REQOVRLOOKUPINT_S) 1083#define REQOVRLOOKUPINT_F REQOVRLOOKUPINT_V(1U) 1084 1085#define BLKWRPLINT_S 25 1086#define BLKWRPLINT_V(x) ((x) << BLKWRPLINT_S) 1087#define BLKWRPLINT_F BLKWRPLINT_V(1U) 1088 1089#define BLKRDPLINT_S 24 1090#define BLKRDPLINT_V(x) ((x) << BLKRDPLINT_S) 1091#define BLKRDPLINT_F BLKRDPLINT_V(1U) 1092 1093#define SGLWRPLINT_S 23 1094#define SGLWRPLINT_V(x) ((x) << SGLWRPLINT_S) 1095#define SGLWRPLINT_F SGLWRPLINT_V(1U) 1096 1097#define SGLRDPLINT_S 22 1098#define SGLRDPLINT_V(x) ((x) << SGLRDPLINT_S) 1099#define SGLRDPLINT_F SGLRDPLINT_V(1U) 1100 1101#define BLKWRCTLINT_S 21 1102#define BLKWRCTLINT_V(x) ((x) << BLKWRCTLINT_S) 1103#define BLKWRCTLINT_F BLKWRCTLINT_V(1U) 1104 1105#define BLKRDCTLINT_S 20 1106#define BLKRDCTLINT_V(x) ((x) << BLKRDCTLINT_S) 1107#define BLKRDCTLINT_F BLKRDCTLINT_V(1U) 1108 1109#define SGLWRCTLINT_S 19 1110#define SGLWRCTLINT_V(x) ((x) << SGLWRCTLINT_S) 1111#define SGLWRCTLINT_F SGLWRCTLINT_V(1U) 1112 1113#define SGLRDCTLINT_S 18 1114#define SGLRDCTLINT_V(x) ((x) << SGLRDCTLINT_S) 1115#define SGLRDCTLINT_F SGLRDCTLINT_V(1U) 1116 1117#define BLKWREEPROMINT_S 17 1118#define BLKWREEPROMINT_V(x) ((x) << BLKWREEPROMINT_S) 1119#define BLKWREEPROMINT_F BLKWREEPROMINT_V(1U) 1120 1121#define BLKRDEEPROMINT_S 16 1122#define BLKRDEEPROMINT_V(x) ((x) << BLKRDEEPROMINT_S) 1123#define BLKRDEEPROMINT_F BLKRDEEPROMINT_V(1U) 1124 1125#define SGLWREEPROMINT_S 15 1126#define SGLWREEPROMINT_V(x) ((x) << SGLWREEPROMINT_S) 1127#define SGLWREEPROMINT_F SGLWREEPROMINT_V(1U) 1128 1129#define SGLRDEEPROMINT_S 14 1130#define SGLRDEEPROMINT_V(x) ((x) << SGLRDEEPROMINT_S) 1131#define SGLRDEEPROMINT_F SGLRDEEPROMINT_V(1U) 1132 1133#define BLKWRFLASHINT_S 13 1134#define BLKWRFLASHINT_V(x) ((x) << BLKWRFLASHINT_S) 1135#define BLKWRFLASHINT_F BLKWRFLASHINT_V(1U) 1136 1137#define BLKRDFLASHINT_S 12 1138#define BLKRDFLASHINT_V(x) ((x) << BLKRDFLASHINT_S) 1139#define BLKRDFLASHINT_F BLKRDFLASHINT_V(1U) 1140 1141#define SGLWRFLASHINT_S 11 1142#define SGLWRFLASHINT_V(x) ((x) << SGLWRFLASHINT_S) 1143#define SGLWRFLASHINT_F SGLWRFLASHINT_V(1U) 1144 1145#define SGLRDFLASHINT_S 10 1146#define SGLRDFLASHINT_V(x) ((x) << SGLRDFLASHINT_S) 1147#define SGLRDFLASHINT_F SGLRDFLASHINT_V(1U) 1148 1149#define BLKWRBOOTINT_S 9 1150#define BLKWRBOOTINT_V(x) ((x) << BLKWRBOOTINT_S) 1151#define BLKWRBOOTINT_F BLKWRBOOTINT_V(1U) 1152 1153#define BLKRDBOOTINT_S 8 1154#define BLKRDBOOTINT_V(x) ((x) << BLKRDBOOTINT_S) 1155#define BLKRDBOOTINT_F BLKRDBOOTINT_V(1U) 1156 1157#define SGLWRBOOTINT_S 7 1158#define SGLWRBOOTINT_V(x) ((x) << SGLWRBOOTINT_S) 1159#define SGLWRBOOTINT_F SGLWRBOOTINT_V(1U) 1160 1161#define SGLRDBOOTINT_S 6 1162#define SGLRDBOOTINT_V(x) ((x) << SGLRDBOOTINT_S) 1163#define SGLRDBOOTINT_F SGLRDBOOTINT_V(1U) 1164 1165#define ILLWRBEINT_S 5 1166#define ILLWRBEINT_V(x) ((x) << ILLWRBEINT_S) 1167#define ILLWRBEINT_F ILLWRBEINT_V(1U) 1168 1169#define ILLRDBEINT_S 4 1170#define ILLRDBEINT_V(x) ((x) << ILLRDBEINT_S) 1171#define ILLRDBEINT_F ILLRDBEINT_V(1U) 1172 1173#define ILLRDINT_S 3 1174#define ILLRDINT_V(x) ((x) << ILLRDINT_S) 1175#define ILLRDINT_F ILLRDINT_V(1U) 1176 1177#define ILLWRINT_S 2 1178#define ILLWRINT_V(x) ((x) << ILLWRINT_S) 1179#define ILLWRINT_F ILLWRINT_V(1U) 1180 1181#define ILLTRANSINT_S 1 1182#define ILLTRANSINT_V(x) ((x) << ILLTRANSINT_S) 1183#define ILLTRANSINT_F ILLTRANSINT_V(1U) 1184 1185#define RSVDSPACEINT_S 0 1186#define RSVDSPACEINT_V(x) ((x) << RSVDSPACEINT_S) 1187#define RSVDSPACEINT_F RSVDSPACEINT_V(1U) 1188 1189/* registers for module TP */ 1190#define DBGLAWHLF_S 23 1191#define DBGLAWHLF_V(x) ((x) << DBGLAWHLF_S) 1192#define DBGLAWHLF_F DBGLAWHLF_V(1U) 1193 1194#define DBGLAWPTR_S 16 1195#define DBGLAWPTR_M 0x7fU 1196#define DBGLAWPTR_G(x) (((x) >> DBGLAWPTR_S) & DBGLAWPTR_M) 1197 1198#define DBGLAENABLE_S 12 1199#define DBGLAENABLE_V(x) ((x) << DBGLAENABLE_S) 1200#define DBGLAENABLE_F DBGLAENABLE_V(1U) 1201 1202#define DBGLARPTR_S 0 1203#define DBGLARPTR_M 0x7fU 1204#define DBGLARPTR_V(x) ((x) << DBGLARPTR_S) 1205 1206#define TP_DBG_LA_DATAL_A 0x7ed8 1207#define TP_DBG_LA_CONFIG_A 0x7ed4 1208#define TP_OUT_CONFIG_A 0x7d04 1209#define TP_GLOBAL_CONFIG_A 0x7d08 1210 1211#define DBGLAMODE_S 14 1212#define DBGLAMODE_M 0x3U 1213#define DBGLAMODE_G(x) (((x) >> DBGLAMODE_S) & DBGLAMODE_M) 1214 1215#define FIVETUPLELOOKUP_S 17 1216#define FIVETUPLELOOKUP_M 0x3U 1217#define FIVETUPLELOOKUP_V(x) ((x) << FIVETUPLELOOKUP_S) 1218#define FIVETUPLELOOKUP_G(x) (((x) >> FIVETUPLELOOKUP_S) & FIVETUPLELOOKUP_M) 1219 1220#define TP_PARA_REG2_A 0x7d68 1221 1222#define MAXRXDATA_S 16 1223#define MAXRXDATA_M 0xffffU 1224#define MAXRXDATA_G(x) (((x) >> MAXRXDATA_S) & MAXRXDATA_M) 1225 1226#define TP_TIMER_RESOLUTION_A 0x7d90 1227 1228#define TIMERRESOLUTION_S 16 1229#define TIMERRESOLUTION_M 0xffU 1230#define TIMERRESOLUTION_G(x) (((x) >> TIMERRESOLUTION_S) & TIMERRESOLUTION_M) 1231 1232#define TIMESTAMPRESOLUTION_S 8 1233#define TIMESTAMPRESOLUTION_M 0xffU 1234#define TIMESTAMPRESOLUTION_G(x) \ 1235 (((x) >> TIMESTAMPRESOLUTION_S) & TIMESTAMPRESOLUTION_M) 1236 1237#define DELAYEDACKRESOLUTION_S 0 1238#define DELAYEDACKRESOLUTION_M 0xffU 1239#define DELAYEDACKRESOLUTION_G(x) \ 1240 (((x) >> DELAYEDACKRESOLUTION_S) & DELAYEDACKRESOLUTION_M) 1241 1242#define TP_SHIFT_CNT_A 0x7dc0 1243#define TP_RXT_MIN_A 0x7d98 1244#define TP_RXT_MAX_A 0x7d9c 1245#define TP_PERS_MIN_A 0x7da0 1246#define TP_PERS_MAX_A 0x7da4 1247#define TP_KEEP_IDLE_A 0x7da8 1248#define TP_KEEP_INTVL_A 0x7dac 1249#define TP_INIT_SRTT_A 0x7db0 1250#define TP_DACK_TIMER_A 0x7db4 1251#define TP_FINWAIT2_TIMER_A 0x7db8 1252 1253#define INITSRTT_S 0 1254#define INITSRTT_M 0xffffU 1255#define INITSRTT_G(x) (((x) >> INITSRTT_S) & INITSRTT_M) 1256 1257#define PERSMAX_S 0 1258#define PERSMAX_M 0x3fffffffU 1259#define PERSMAX_V(x) ((x) << PERSMAX_S) 1260#define PERSMAX_G(x) (((x) >> PERSMAX_S) & PERSMAX_M) 1261 1262#define SYNSHIFTMAX_S 24 1263#define SYNSHIFTMAX_M 0xffU 1264#define SYNSHIFTMAX_V(x) ((x) << SYNSHIFTMAX_S) 1265#define SYNSHIFTMAX_G(x) (((x) >> SYNSHIFTMAX_S) & SYNSHIFTMAX_M) 1266 1267#define RXTSHIFTMAXR1_S 20 1268#define RXTSHIFTMAXR1_M 0xfU 1269#define RXTSHIFTMAXR1_V(x) ((x) << RXTSHIFTMAXR1_S) 1270#define RXTSHIFTMAXR1_G(x) (((x) >> RXTSHIFTMAXR1_S) & RXTSHIFTMAXR1_M) 1271 1272#define RXTSHIFTMAXR2_S 16 1273#define RXTSHIFTMAXR2_M 0xfU 1274#define RXTSHIFTMAXR2_V(x) ((x) << RXTSHIFTMAXR2_S) 1275#define RXTSHIFTMAXR2_G(x) (((x) >> RXTSHIFTMAXR2_S) & RXTSHIFTMAXR2_M) 1276 1277#define PERSHIFTBACKOFFMAX_S 12 1278#define PERSHIFTBACKOFFMAX_M 0xfU 1279#define PERSHIFTBACKOFFMAX_V(x) ((x) << PERSHIFTBACKOFFMAX_S) 1280#define PERSHIFTBACKOFFMAX_G(x) \ 1281 (((x) >> PERSHIFTBACKOFFMAX_S) & PERSHIFTBACKOFFMAX_M) 1282 1283#define PERSHIFTMAX_S 8 1284#define PERSHIFTMAX_M 0xfU 1285#define PERSHIFTMAX_V(x) ((x) << PERSHIFTMAX_S) 1286#define PERSHIFTMAX_G(x) (((x) >> PERSHIFTMAX_S) & PERSHIFTMAX_M) 1287 1288#define KEEPALIVEMAXR1_S 4 1289#define KEEPALIVEMAXR1_M 0xfU 1290#define KEEPALIVEMAXR1_V(x) ((x) << KEEPALIVEMAXR1_S) 1291#define KEEPALIVEMAXR1_G(x) (((x) >> KEEPALIVEMAXR1_S) & KEEPALIVEMAXR1_M) 1292 1293#define KEEPALIVEMAXR2_S 0 1294#define KEEPALIVEMAXR2_M 0xfU 1295#define KEEPALIVEMAXR2_V(x) ((x) << KEEPALIVEMAXR2_S) 1296#define KEEPALIVEMAXR2_G(x) (((x) >> KEEPALIVEMAXR2_S) & KEEPALIVEMAXR2_M) 1297 1298#define ROWINDEX_S 16 1299#define ROWINDEX_V(x) ((x) << ROWINDEX_S) 1300 1301#define TP_CCTRL_TABLE_A 0x7ddc 1302#define TP_MTU_TABLE_A 0x7de4 1303 1304#define MTUINDEX_S 24 1305#define MTUINDEX_V(x) ((x) << MTUINDEX_S) 1306 1307#define MTUWIDTH_S 16 1308#define MTUWIDTH_M 0xfU 1309#define MTUWIDTH_V(x) ((x) << MTUWIDTH_S) 1310#define MTUWIDTH_G(x) (((x) >> MTUWIDTH_S) & MTUWIDTH_M) 1311 1312#define MTUVALUE_S 0 1313#define MTUVALUE_M 0x3fffU 1314#define MTUVALUE_V(x) ((x) << MTUVALUE_S) 1315#define MTUVALUE_G(x) (((x) >> MTUVALUE_S) & MTUVALUE_M) 1316 1317#define TP_RSS_LKP_TABLE_A 0x7dec 1318 1319#define LKPTBLROWVLD_S 31 1320#define LKPTBLROWVLD_V(x) ((x) << LKPTBLROWVLD_S) 1321#define LKPTBLROWVLD_F LKPTBLROWVLD_V(1U) 1322 1323#define LKPTBLQUEUE1_S 10 1324#define LKPTBLQUEUE1_M 0x3ffU 1325#define LKPTBLQUEUE1_G(x) (((x) >> LKPTBLQUEUE1_S) & LKPTBLQUEUE1_M) 1326 1327#define LKPTBLQUEUE0_S 0 1328#define LKPTBLQUEUE0_M 0x3ffU 1329#define LKPTBLQUEUE0_G(x) (((x) >> LKPTBLQUEUE0_S) & LKPTBLQUEUE0_M) 1330 1331#define TP_PIO_ADDR_A 0x7e40 1332#define TP_PIO_DATA_A 0x7e44 1333#define TP_MIB_INDEX_A 0x7e50 1334#define TP_MIB_DATA_A 0x7e54 1335#define TP_INT_CAUSE_A 0x7e74 1336 1337#define FLMTXFLSTEMPTY_S 30 1338#define FLMTXFLSTEMPTY_V(x) ((x) << FLMTXFLSTEMPTY_S) 1339#define FLMTXFLSTEMPTY_F FLMTXFLSTEMPTY_V(1U) 1340 1341#define TP_VLAN_PRI_MAP_A 0x140 1342 1343#define FRAGMENTATION_S 9 1344#define FRAGMENTATION_V(x) ((x) << FRAGMENTATION_S) 1345#define FRAGMENTATION_F FRAGMENTATION_V(1U) 1346 1347#define MPSHITTYPE_S 8 1348#define MPSHITTYPE_V(x) ((x) << MPSHITTYPE_S) 1349#define MPSHITTYPE_F MPSHITTYPE_V(1U) 1350 1351#define MACMATCH_S 7 1352#define MACMATCH_V(x) ((x) << MACMATCH_S) 1353#define MACMATCH_F MACMATCH_V(1U) 1354 1355#define ETHERTYPE_S 6 1356#define ETHERTYPE_V(x) ((x) << ETHERTYPE_S) 1357#define ETHERTYPE_F ETHERTYPE_V(1U) 1358 1359#define PROTOCOL_S 5 1360#define PROTOCOL_V(x) ((x) << PROTOCOL_S) 1361#define PROTOCOL_F PROTOCOL_V(1U) 1362 1363#define TOS_S 4 1364#define TOS_V(x) ((x) << TOS_S) 1365#define TOS_F TOS_V(1U) 1366 1367#define VLAN_S 3 1368#define VLAN_V(x) ((x) << VLAN_S) 1369#define VLAN_F VLAN_V(1U) 1370 1371#define VNIC_ID_S 2 1372#define VNIC_ID_V(x) ((x) << VNIC_ID_S) 1373#define VNIC_ID_F VNIC_ID_V(1U) 1374 1375#define PORT_S 1 1376#define PORT_V(x) ((x) << PORT_S) 1377#define PORT_F PORT_V(1U) 1378 1379#define FCOE_S 0 1380#define FCOE_V(x) ((x) << FCOE_S) 1381#define FCOE_F FCOE_V(1U) 1382 1383#define FILTERMODE_S 15 1384#define FILTERMODE_V(x) ((x) << FILTERMODE_S) 1385#define FILTERMODE_F FILTERMODE_V(1U) 1386 1387#define FCOEMASK_S 14 1388#define FCOEMASK_V(x) ((x) << FCOEMASK_S) 1389#define FCOEMASK_F FCOEMASK_V(1U) 1390 1391#define TP_INGRESS_CONFIG_A 0x141 1392 1393#define VNIC_S 11 1394#define VNIC_V(x) ((x) << VNIC_S) 1395#define VNIC_F VNIC_V(1U) 1396 1397#define CSUM_HAS_PSEUDO_HDR_S 10 1398#define CSUM_HAS_PSEUDO_HDR_V(x) ((x) << CSUM_HAS_PSEUDO_HDR_S) 1399#define CSUM_HAS_PSEUDO_HDR_F CSUM_HAS_PSEUDO_HDR_V(1U) 1400 1401#define TP_MIB_MAC_IN_ERR_0_A 0x0 1402#define TP_MIB_TCP_OUT_RST_A 0xc 1403#define TP_MIB_TCP_IN_SEG_HI_A 0x10 1404#define TP_MIB_TCP_IN_SEG_LO_A 0x11 1405#define TP_MIB_TCP_OUT_SEG_HI_A 0x12 1406#define TP_MIB_TCP_OUT_SEG_LO_A 0x13 1407#define TP_MIB_TCP_RXT_SEG_HI_A 0x14 1408#define TP_MIB_TCP_RXT_SEG_LO_A 0x15 1409#define TP_MIB_TNL_CNG_DROP_0_A 0x18 1410#define TP_MIB_TCP_V6IN_ERR_0_A 0x28 1411#define TP_MIB_TCP_V6OUT_RST_A 0x2c 1412#define TP_MIB_OFD_ARP_DROP_A 0x36 1413#define TP_MIB_TNL_DROP_0_A 0x44 1414#define TP_MIB_OFD_VLN_DROP_0_A 0x58 1415 1416#define ULP_TX_INT_CAUSE_A 0x8dcc 1417 1418#define PBL_BOUND_ERR_CH3_S 31 1419#define PBL_BOUND_ERR_CH3_V(x) ((x) << PBL_BOUND_ERR_CH3_S) 1420#define PBL_BOUND_ERR_CH3_F PBL_BOUND_ERR_CH3_V(1U) 1421 1422#define PBL_BOUND_ERR_CH2_S 30 1423#define PBL_BOUND_ERR_CH2_V(x) ((x) << PBL_BOUND_ERR_CH2_S) 1424#define PBL_BOUND_ERR_CH2_F PBL_BOUND_ERR_CH2_V(1U) 1425 1426#define PBL_BOUND_ERR_CH1_S 29 1427#define PBL_BOUND_ERR_CH1_V(x) ((x) << PBL_BOUND_ERR_CH1_S) 1428#define PBL_BOUND_ERR_CH1_F PBL_BOUND_ERR_CH1_V(1U) 1429 1430#define PBL_BOUND_ERR_CH0_S 28 1431#define PBL_BOUND_ERR_CH0_V(x) ((x) << PBL_BOUND_ERR_CH0_S) 1432#define PBL_BOUND_ERR_CH0_F PBL_BOUND_ERR_CH0_V(1U) 1433 1434#define PM_RX_INT_CAUSE_A 0x8fdc 1435#define PM_RX_STAT_CONFIG_A 0x8fc8 1436#define PM_RX_STAT_COUNT_A 0x8fcc 1437#define PM_RX_STAT_LSB_A 0x8fd0 1438#define PM_RX_DBG_CTRL_A 0x8fd0 1439#define PM_RX_DBG_DATA_A 0x8fd4 1440#define PM_RX_DBG_STAT_MSB_A 0x10013 1441 1442#define PMRX_FRAMING_ERROR_F 0x003ffff0U 1443 1444#define ZERO_E_CMD_ERROR_S 22 1445#define ZERO_E_CMD_ERROR_V(x) ((x) << ZERO_E_CMD_ERROR_S) 1446#define ZERO_E_CMD_ERROR_F ZERO_E_CMD_ERROR_V(1U) 1447 1448#define OCSPI_PAR_ERROR_S 3 1449#define OCSPI_PAR_ERROR_V(x) ((x) << OCSPI_PAR_ERROR_S) 1450#define OCSPI_PAR_ERROR_F OCSPI_PAR_ERROR_V(1U) 1451 1452#define DB_OPTIONS_PAR_ERROR_S 2 1453#define DB_OPTIONS_PAR_ERROR_V(x) ((x) << DB_OPTIONS_PAR_ERROR_S) 1454#define DB_OPTIONS_PAR_ERROR_F DB_OPTIONS_PAR_ERROR_V(1U) 1455 1456#define IESPI_PAR_ERROR_S 1 1457#define IESPI_PAR_ERROR_V(x) ((x) << IESPI_PAR_ERROR_S) 1458#define IESPI_PAR_ERROR_F IESPI_PAR_ERROR_V(1U) 1459 1460#define PMRX_E_PCMD_PAR_ERROR_S 0 1461#define PMRX_E_PCMD_PAR_ERROR_V(x) ((x) << PMRX_E_PCMD_PAR_ERROR_S) 1462#define PMRX_E_PCMD_PAR_ERROR_F PMRX_E_PCMD_PAR_ERROR_V(1U) 1463 1464#define PM_TX_INT_CAUSE_A 0x8ffc 1465#define PM_TX_STAT_CONFIG_A 0x8fe8 1466#define PM_TX_STAT_COUNT_A 0x8fec 1467#define PM_TX_STAT_LSB_A 0x8ff0 1468#define PM_TX_DBG_CTRL_A 0x8ff0 1469#define PM_TX_DBG_DATA_A 0x8ff4 1470#define PM_TX_DBG_STAT_MSB_A 0x1001a 1471 1472#define PCMD_LEN_OVFL0_S 31 1473#define PCMD_LEN_OVFL0_V(x) ((x) << PCMD_LEN_OVFL0_S) 1474#define PCMD_LEN_OVFL0_F PCMD_LEN_OVFL0_V(1U) 1475 1476#define PCMD_LEN_OVFL1_S 30 1477#define PCMD_LEN_OVFL1_V(x) ((x) << PCMD_LEN_OVFL1_S) 1478#define PCMD_LEN_OVFL1_F PCMD_LEN_OVFL1_V(1U) 1479 1480#define PCMD_LEN_OVFL2_S 29 1481#define PCMD_LEN_OVFL2_V(x) ((x) << PCMD_LEN_OVFL2_S) 1482#define PCMD_LEN_OVFL2_F PCMD_LEN_OVFL2_V(1U) 1483 1484#define ZERO_C_CMD_ERROR_S 28 1485#define ZERO_C_CMD_ERROR_V(x) ((x) << ZERO_C_CMD_ERROR_S) 1486#define ZERO_C_CMD_ERROR_F ZERO_C_CMD_ERROR_V(1U) 1487 1488#define PMTX_FRAMING_ERROR_F 0x0ffffff0U 1489 1490#define OESPI_PAR_ERROR_S 3 1491#define OESPI_PAR_ERROR_V(x) ((x) << OESPI_PAR_ERROR_S) 1492#define OESPI_PAR_ERROR_F OESPI_PAR_ERROR_V(1U) 1493 1494#define ICSPI_PAR_ERROR_S 1 1495#define ICSPI_PAR_ERROR_V(x) ((x) << ICSPI_PAR_ERROR_S) 1496#define ICSPI_PAR_ERROR_F ICSPI_PAR_ERROR_V(1U) 1497 1498#define PMTX_C_PCMD_PAR_ERROR_S 0 1499#define PMTX_C_PCMD_PAR_ERROR_V(x) ((x) << PMTX_C_PCMD_PAR_ERROR_S) 1500#define PMTX_C_PCMD_PAR_ERROR_F PMTX_C_PCMD_PAR_ERROR_V(1U) 1501 1502#define MPS_PORT_STAT_TX_PORT_BYTES_L 0x400 1503#define MPS_PORT_STAT_TX_PORT_BYTES_H 0x404 1504#define MPS_PORT_STAT_TX_PORT_FRAMES_L 0x408 1505#define MPS_PORT_STAT_TX_PORT_FRAMES_H 0x40c 1506#define MPS_PORT_STAT_TX_PORT_BCAST_L 0x410 1507#define MPS_PORT_STAT_TX_PORT_BCAST_H 0x414 1508#define MPS_PORT_STAT_TX_PORT_MCAST_L 0x418 1509#define MPS_PORT_STAT_TX_PORT_MCAST_H 0x41c 1510#define MPS_PORT_STAT_TX_PORT_UCAST_L 0x420 1511#define MPS_PORT_STAT_TX_PORT_UCAST_H 0x424 1512#define MPS_PORT_STAT_TX_PORT_ERROR_L 0x428 1513#define MPS_PORT_STAT_TX_PORT_ERROR_H 0x42c 1514#define MPS_PORT_STAT_TX_PORT_64B_L 0x430 1515#define MPS_PORT_STAT_TX_PORT_64B_H 0x434 1516#define MPS_PORT_STAT_TX_PORT_65B_127B_L 0x438 1517#define MPS_PORT_STAT_TX_PORT_65B_127B_H 0x43c 1518#define MPS_PORT_STAT_TX_PORT_128B_255B_L 0x440 1519#define MPS_PORT_STAT_TX_PORT_128B_255B_H 0x444 1520#define MPS_PORT_STAT_TX_PORT_256B_511B_L 0x448 1521#define MPS_PORT_STAT_TX_PORT_256B_511B_H 0x44c 1522#define MPS_PORT_STAT_TX_PORT_512B_1023B_L 0x450 1523#define MPS_PORT_STAT_TX_PORT_512B_1023B_H 0x454 1524#define MPS_PORT_STAT_TX_PORT_1024B_1518B_L 0x458 1525#define MPS_PORT_STAT_TX_PORT_1024B_1518B_H 0x45c 1526#define MPS_PORT_STAT_TX_PORT_1519B_MAX_L 0x460 1527#define MPS_PORT_STAT_TX_PORT_1519B_MAX_H 0x464 1528#define MPS_PORT_STAT_TX_PORT_DROP_L 0x468 1529#define MPS_PORT_STAT_TX_PORT_DROP_H 0x46c 1530#define MPS_PORT_STAT_TX_PORT_PAUSE_L 0x470 1531#define MPS_PORT_STAT_TX_PORT_PAUSE_H 0x474 1532#define MPS_PORT_STAT_TX_PORT_PPP0_L 0x478 1533#define MPS_PORT_STAT_TX_PORT_PPP0_H 0x47c 1534#define MPS_PORT_STAT_TX_PORT_PPP1_L 0x480 1535#define MPS_PORT_STAT_TX_PORT_PPP1_H 0x484 1536#define MPS_PORT_STAT_TX_PORT_PPP2_L 0x488 1537#define MPS_PORT_STAT_TX_PORT_PPP2_H 0x48c 1538#define MPS_PORT_STAT_TX_PORT_PPP3_L 0x490 1539#define MPS_PORT_STAT_TX_PORT_PPP3_H 0x494 1540#define MPS_PORT_STAT_TX_PORT_PPP4_L 0x498 1541#define MPS_PORT_STAT_TX_PORT_PPP4_H 0x49c 1542#define MPS_PORT_STAT_TX_PORT_PPP5_L 0x4a0 1543#define MPS_PORT_STAT_TX_PORT_PPP5_H 0x4a4 1544#define MPS_PORT_STAT_TX_PORT_PPP6_L 0x4a8 1545#define MPS_PORT_STAT_TX_PORT_PPP6_H 0x4ac 1546#define MPS_PORT_STAT_TX_PORT_PPP7_L 0x4b0 1547#define MPS_PORT_STAT_TX_PORT_PPP7_H 0x4b4 1548#define MPS_PORT_STAT_LB_PORT_BYTES_L 0x4c0 1549#define MPS_PORT_STAT_LB_PORT_BYTES_H 0x4c4 1550#define MPS_PORT_STAT_LB_PORT_FRAMES_L 0x4c8 1551#define MPS_PORT_STAT_LB_PORT_FRAMES_H 0x4cc 1552#define MPS_PORT_STAT_LB_PORT_BCAST_L 0x4d0 1553#define MPS_PORT_STAT_LB_PORT_BCAST_H 0x4d4 1554#define MPS_PORT_STAT_LB_PORT_MCAST_L 0x4d8 1555#define MPS_PORT_STAT_LB_PORT_MCAST_H 0x4dc 1556#define MPS_PORT_STAT_LB_PORT_UCAST_L 0x4e0 1557#define MPS_PORT_STAT_LB_PORT_UCAST_H 0x4e4 1558#define MPS_PORT_STAT_LB_PORT_ERROR_L 0x4e8 1559#define MPS_PORT_STAT_LB_PORT_ERROR_H 0x4ec 1560#define MPS_PORT_STAT_LB_PORT_64B_L 0x4f0 1561#define MPS_PORT_STAT_LB_PORT_64B_H 0x4f4 1562#define MPS_PORT_STAT_LB_PORT_65B_127B_L 0x4f8 1563#define MPS_PORT_STAT_LB_PORT_65B_127B_H 0x4fc 1564#define MPS_PORT_STAT_LB_PORT_128B_255B_L 0x500 1565#define MPS_PORT_STAT_LB_PORT_128B_255B_H 0x504 1566#define MPS_PORT_STAT_LB_PORT_256B_511B_L 0x508 1567#define MPS_PORT_STAT_LB_PORT_256B_511B_H 0x50c 1568#define MPS_PORT_STAT_LB_PORT_512B_1023B_L 0x510 1569#define MPS_PORT_STAT_LB_PORT_512B_1023B_H 0x514 1570#define MPS_PORT_STAT_LB_PORT_1024B_1518B_L 0x518 1571#define MPS_PORT_STAT_LB_PORT_1024B_1518B_H 0x51c 1572#define MPS_PORT_STAT_LB_PORT_1519B_MAX_L 0x520 1573#define MPS_PORT_STAT_LB_PORT_1519B_MAX_H 0x524 1574#define MPS_PORT_STAT_LB_PORT_DROP_FRAMES 0x528 1575#define MPS_PORT_STAT_RX_PORT_BYTES_L 0x540 1576#define MPS_PORT_STAT_RX_PORT_BYTES_H 0x544 1577#define MPS_PORT_STAT_RX_PORT_FRAMES_L 0x548 1578#define MPS_PORT_STAT_RX_PORT_FRAMES_H 0x54c 1579#define MPS_PORT_STAT_RX_PORT_BCAST_L 0x550 1580#define MPS_PORT_STAT_RX_PORT_BCAST_H 0x554 1581#define MPS_PORT_STAT_RX_PORT_MCAST_L 0x558 1582#define MPS_PORT_STAT_RX_PORT_MCAST_H 0x55c 1583#define MPS_PORT_STAT_RX_PORT_UCAST_L 0x560 1584#define MPS_PORT_STAT_RX_PORT_UCAST_H 0x564 1585#define MPS_PORT_STAT_RX_PORT_MTU_ERROR_L 0x568 1586#define MPS_PORT_STAT_RX_PORT_MTU_ERROR_H 0x56c 1587#define MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L 0x570 1588#define MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_H 0x574 1589#define MPS_PORT_STAT_RX_PORT_CRC_ERROR_L 0x578 1590#define MPS_PORT_STAT_RX_PORT_CRC_ERROR_H 0x57c 1591#define MPS_PORT_STAT_RX_PORT_LEN_ERROR_L 0x580 1592#define MPS_PORT_STAT_RX_PORT_LEN_ERROR_H 0x584 1593#define MPS_PORT_STAT_RX_PORT_SYM_ERROR_L 0x588 1594#define MPS_PORT_STAT_RX_PORT_SYM_ERROR_H 0x58c 1595#define MPS_PORT_STAT_RX_PORT_64B_L 0x590 1596#define MPS_PORT_STAT_RX_PORT_64B_H 0x594 1597#define MPS_PORT_STAT_RX_PORT_65B_127B_L 0x598 1598#define MPS_PORT_STAT_RX_PORT_65B_127B_H 0x59c 1599#define MPS_PORT_STAT_RX_PORT_128B_255B_L 0x5a0 1600#define MPS_PORT_STAT_RX_PORT_128B_255B_H 0x5a4 1601#define MPS_PORT_STAT_RX_PORT_256B_511B_L 0x5a8 1602#define MPS_PORT_STAT_RX_PORT_256B_511B_H 0x5ac 1603#define MPS_PORT_STAT_RX_PORT_512B_1023B_L 0x5b0 1604#define MPS_PORT_STAT_RX_PORT_512B_1023B_H 0x5b4 1605#define MPS_PORT_STAT_RX_PORT_1024B_1518B_L 0x5b8 1606#define MPS_PORT_STAT_RX_PORT_1024B_1518B_H 0x5bc 1607#define MPS_PORT_STAT_RX_PORT_1519B_MAX_L 0x5c0 1608#define MPS_PORT_STAT_RX_PORT_1519B_MAX_H 0x5c4 1609#define MPS_PORT_STAT_RX_PORT_PAUSE_L 0x5c8 1610#define MPS_PORT_STAT_RX_PORT_PAUSE_H 0x5cc 1611#define MPS_PORT_STAT_RX_PORT_PPP0_L 0x5d0 1612#define MPS_PORT_STAT_RX_PORT_PPP0_H 0x5d4 1613#define MPS_PORT_STAT_RX_PORT_PPP1_L 0x5d8 1614#define MPS_PORT_STAT_RX_PORT_PPP1_H 0x5dc 1615#define MPS_PORT_STAT_RX_PORT_PPP2_L 0x5e0 1616#define MPS_PORT_STAT_RX_PORT_PPP2_H 0x5e4 1617#define MPS_PORT_STAT_RX_PORT_PPP3_L 0x5e8 1618#define MPS_PORT_STAT_RX_PORT_PPP3_H 0x5ec 1619#define MPS_PORT_STAT_RX_PORT_PPP4_L 0x5f0 1620#define MPS_PORT_STAT_RX_PORT_PPP4_H 0x5f4 1621#define MPS_PORT_STAT_RX_PORT_PPP5_L 0x5f8 1622#define MPS_PORT_STAT_RX_PORT_PPP5_H 0x5fc 1623#define MPS_PORT_STAT_RX_PORT_PPP6_L 0x600 1624#define MPS_PORT_STAT_RX_PORT_PPP6_H 0x604 1625#define MPS_PORT_STAT_RX_PORT_PPP7_L 0x608 1626#define MPS_PORT_STAT_RX_PORT_PPP7_H 0x60c 1627#define MPS_PORT_STAT_RX_PORT_LESS_64B_L 0x610 1628#define MPS_PORT_STAT_RX_PORT_LESS_64B_H 0x614 1629#define MAC_PORT_MAGIC_MACID_LO 0x824 1630#define MAC_PORT_MAGIC_MACID_HI 0x828 1631 1632#define MAC_PORT_EPIO_DATA0_A 0x8c0 1633#define MAC_PORT_EPIO_DATA1_A 0x8c4 1634#define MAC_PORT_EPIO_DATA2_A 0x8c8 1635#define MAC_PORT_EPIO_DATA3_A 0x8cc 1636#define MAC_PORT_EPIO_OP_A 0x8d0 1637 1638#define MAC_PORT_CFG2_A 0x818 1639 1640#define MPS_CMN_CTL_A 0x9000 1641 1642#define NUMPORTS_S 0 1643#define NUMPORTS_M 0x3U 1644#define NUMPORTS_G(x) (((x) >> NUMPORTS_S) & NUMPORTS_M) 1645 1646#define MPS_INT_CAUSE_A 0x9008 1647#define MPS_TX_INT_CAUSE_A 0x9408 1648 1649#define FRMERR_S 15 1650#define FRMERR_V(x) ((x) << FRMERR_S) 1651#define FRMERR_F FRMERR_V(1U) 1652 1653#define SECNTERR_S 14 1654#define SECNTERR_V(x) ((x) << SECNTERR_S) 1655#define SECNTERR_F SECNTERR_V(1U) 1656 1657#define BUBBLE_S 13 1658#define BUBBLE_V(x) ((x) << BUBBLE_S) 1659#define BUBBLE_F BUBBLE_V(1U) 1660 1661#define TXDESCFIFO_S 9 1662#define TXDESCFIFO_M 0xfU 1663#define TXDESCFIFO_V(x) ((x) << TXDESCFIFO_S) 1664 1665#define TXDATAFIFO_S 5 1666#define TXDATAFIFO_M 0xfU 1667#define TXDATAFIFO_V(x) ((x) << TXDATAFIFO_S) 1668 1669#define NCSIFIFO_S 4 1670#define NCSIFIFO_V(x) ((x) << NCSIFIFO_S) 1671#define NCSIFIFO_F NCSIFIFO_V(1U) 1672 1673#define TPFIFO_S 0 1674#define TPFIFO_M 0xfU 1675#define TPFIFO_V(x) ((x) << TPFIFO_S) 1676 1677#define MPS_STAT_PERR_INT_CAUSE_SRAM_A 0x9614 1678#define MPS_STAT_PERR_INT_CAUSE_TX_FIFO_A 0x9620 1679#define MPS_STAT_PERR_INT_CAUSE_RX_FIFO_A 0x962c 1680 1681#define MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L 0x9640 1682#define MPS_STAT_RX_BG_0_MAC_DROP_FRAME_H 0x9644 1683#define MPS_STAT_RX_BG_1_MAC_DROP_FRAME_L 0x9648 1684#define MPS_STAT_RX_BG_1_MAC_DROP_FRAME_H 0x964c 1685#define MPS_STAT_RX_BG_2_MAC_DROP_FRAME_L 0x9650 1686#define MPS_STAT_RX_BG_2_MAC_DROP_FRAME_H 0x9654 1687#define MPS_STAT_RX_BG_3_MAC_DROP_FRAME_L 0x9658 1688#define MPS_STAT_RX_BG_3_MAC_DROP_FRAME_H 0x965c 1689#define MPS_STAT_RX_BG_0_LB_DROP_FRAME_L 0x9660 1690#define MPS_STAT_RX_BG_0_LB_DROP_FRAME_H 0x9664 1691#define MPS_STAT_RX_BG_1_LB_DROP_FRAME_L 0x9668 1692#define MPS_STAT_RX_BG_1_LB_DROP_FRAME_H 0x966c 1693#define MPS_STAT_RX_BG_2_LB_DROP_FRAME_L 0x9670 1694#define MPS_STAT_RX_BG_2_LB_DROP_FRAME_H 0x9674 1695#define MPS_STAT_RX_BG_3_LB_DROP_FRAME_L 0x9678 1696#define MPS_STAT_RX_BG_3_LB_DROP_FRAME_H 0x967c 1697#define MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L 0x9680 1698#define MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_H 0x9684 1699#define MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_L 0x9688 1700#define MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_H 0x968c 1701#define MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_L 0x9690 1702#define MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_H 0x9694 1703#define MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_L 0x9698 1704#define MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_H 0x969c 1705#define MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_L 0x96a0 1706#define MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_H 0x96a4 1707#define MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_L 0x96a8 1708#define MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_H 0x96ac 1709#define MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_L 0x96b0 1710#define MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_H 0x96b4 1711#define MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_L 0x96b8 1712#define MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_H 0x96bc 1713 1714#define MPS_TRC_CFG_A 0x9800 1715 1716#define TRCFIFOEMPTY_S 4 1717#define TRCFIFOEMPTY_V(x) ((x) << TRCFIFOEMPTY_S) 1718#define TRCFIFOEMPTY_F TRCFIFOEMPTY_V(1U) 1719 1720#define TRCIGNOREDROPINPUT_S 3 1721#define TRCIGNOREDROPINPUT_V(x) ((x) << TRCIGNOREDROPINPUT_S) 1722#define TRCIGNOREDROPINPUT_F TRCIGNOREDROPINPUT_V(1U) 1723 1724#define TRCKEEPDUPLICATES_S 2 1725#define TRCKEEPDUPLICATES_V(x) ((x) << TRCKEEPDUPLICATES_S) 1726#define TRCKEEPDUPLICATES_F TRCKEEPDUPLICATES_V(1U) 1727 1728#define TRCEN_S 1 1729#define TRCEN_V(x) ((x) << TRCEN_S) 1730#define TRCEN_F TRCEN_V(1U) 1731 1732#define TRCMULTIFILTER_S 0 1733#define TRCMULTIFILTER_V(x) ((x) << TRCMULTIFILTER_S) 1734#define TRCMULTIFILTER_F TRCMULTIFILTER_V(1U) 1735 1736#define MPS_TRC_RSS_CONTROL_A 0x9808 1737#define MPS_T5_TRC_RSS_CONTROL_A 0xa00c 1738 1739#define RSSCONTROL_S 16 1740#define RSSCONTROL_V(x) ((x) << RSSCONTROL_S) 1741 1742#define QUEUENUMBER_S 0 1743#define QUEUENUMBER_V(x) ((x) << QUEUENUMBER_S) 1744 1745#define TP_RSS_CONFIG_A 0x7df0 1746 1747#define TNL4TUPENIPV6_S 31 1748#define TNL4TUPENIPV6_V(x) ((x) << TNL4TUPENIPV6_S) 1749#define TNL4TUPENIPV6_F TNL4TUPENIPV6_V(1U) 1750 1751#define TNL2TUPENIPV6_S 30 1752#define TNL2TUPENIPV6_V(x) ((x) << TNL2TUPENIPV6_S) 1753#define TNL2TUPENIPV6_F TNL2TUPENIPV6_V(1U) 1754 1755#define TNL4TUPENIPV4_S 29 1756#define TNL4TUPENIPV4_V(x) ((x) << TNL4TUPENIPV4_S) 1757#define TNL4TUPENIPV4_F TNL4TUPENIPV4_V(1U) 1758 1759#define TNL2TUPENIPV4_S 28 1760#define TNL2TUPENIPV4_V(x) ((x) << TNL2TUPENIPV4_S) 1761#define TNL2TUPENIPV4_F TNL2TUPENIPV4_V(1U) 1762 1763#define TNLTCPSEL_S 27 1764#define TNLTCPSEL_V(x) ((x) << TNLTCPSEL_S) 1765#define TNLTCPSEL_F TNLTCPSEL_V(1U) 1766 1767#define TNLIP6SEL_S 26 1768#define TNLIP6SEL_V(x) ((x) << TNLIP6SEL_S) 1769#define TNLIP6SEL_F TNLIP6SEL_V(1U) 1770 1771#define TNLVRTSEL_S 25 1772#define TNLVRTSEL_V(x) ((x) << TNLVRTSEL_S) 1773#define TNLVRTSEL_F TNLVRTSEL_V(1U) 1774 1775#define TNLMAPEN_S 24 1776#define TNLMAPEN_V(x) ((x) << TNLMAPEN_S) 1777#define TNLMAPEN_F TNLMAPEN_V(1U) 1778 1779#define OFDHASHSAVE_S 19 1780#define OFDHASHSAVE_V(x) ((x) << OFDHASHSAVE_S) 1781#define OFDHASHSAVE_F OFDHASHSAVE_V(1U) 1782 1783#define OFDVRTSEL_S 18 1784#define OFDVRTSEL_V(x) ((x) << OFDVRTSEL_S) 1785#define OFDVRTSEL_F OFDVRTSEL_V(1U) 1786 1787#define OFDMAPEN_S 17 1788#define OFDMAPEN_V(x) ((x) << OFDMAPEN_S) 1789#define OFDMAPEN_F OFDMAPEN_V(1U) 1790 1791#define OFDLKPEN_S 16 1792#define OFDLKPEN_V(x) ((x) << OFDLKPEN_S) 1793#define OFDLKPEN_F OFDLKPEN_V(1U) 1794 1795#define SYN4TUPENIPV6_S 15 1796#define SYN4TUPENIPV6_V(x) ((x) << SYN4TUPENIPV6_S) 1797#define SYN4TUPENIPV6_F SYN4TUPENIPV6_V(1U) 1798 1799#define SYN2TUPENIPV6_S 14 1800#define SYN2TUPENIPV6_V(x) ((x) << SYN2TUPENIPV6_S) 1801#define SYN2TUPENIPV6_F SYN2TUPENIPV6_V(1U) 1802 1803#define SYN4TUPENIPV4_S 13 1804#define SYN4TUPENIPV4_V(x) ((x) << SYN4TUPENIPV4_S) 1805#define SYN4TUPENIPV4_F SYN4TUPENIPV4_V(1U) 1806 1807#define SYN2TUPENIPV4_S 12 1808#define SYN2TUPENIPV4_V(x) ((x) << SYN2TUPENIPV4_S) 1809#define SYN2TUPENIPV4_F SYN2TUPENIPV4_V(1U) 1810 1811#define SYNIP6SEL_S 11 1812#define SYNIP6SEL_V(x) ((x) << SYNIP6SEL_S) 1813#define SYNIP6SEL_F SYNIP6SEL_V(1U) 1814 1815#define SYNVRTSEL_S 10 1816#define SYNVRTSEL_V(x) ((x) << SYNVRTSEL_S) 1817#define SYNVRTSEL_F SYNVRTSEL_V(1U) 1818 1819#define SYNMAPEN_S 9 1820#define SYNMAPEN_V(x) ((x) << SYNMAPEN_S) 1821#define SYNMAPEN_F SYNMAPEN_V(1U) 1822 1823#define SYNLKPEN_S 8 1824#define SYNLKPEN_V(x) ((x) << SYNLKPEN_S) 1825#define SYNLKPEN_F SYNLKPEN_V(1U) 1826 1827#define CHANNELENABLE_S 7 1828#define CHANNELENABLE_V(x) ((x) << CHANNELENABLE_S) 1829#define CHANNELENABLE_F CHANNELENABLE_V(1U) 1830 1831#define PORTENABLE_S 6 1832#define PORTENABLE_V(x) ((x) << PORTENABLE_S) 1833#define PORTENABLE_F PORTENABLE_V(1U) 1834 1835#define TNLALLLOOKUP_S 5 1836#define TNLALLLOOKUP_V(x) ((x) << TNLALLLOOKUP_S) 1837#define TNLALLLOOKUP_F TNLALLLOOKUP_V(1U) 1838 1839#define VIRTENABLE_S 4 1840#define VIRTENABLE_V(x) ((x) << VIRTENABLE_S) 1841#define VIRTENABLE_F VIRTENABLE_V(1U) 1842 1843#define CONGESTIONENABLE_S 3 1844#define CONGESTIONENABLE_V(x) ((x) << CONGESTIONENABLE_S) 1845#define CONGESTIONENABLE_F CONGESTIONENABLE_V(1U) 1846 1847#define HASHTOEPLITZ_S 2 1848#define HASHTOEPLITZ_V(x) ((x) << HASHTOEPLITZ_S) 1849#define HASHTOEPLITZ_F HASHTOEPLITZ_V(1U) 1850 1851#define UDPENABLE_S 1 1852#define UDPENABLE_V(x) ((x) << UDPENABLE_S) 1853#define UDPENABLE_F UDPENABLE_V(1U) 1854 1855#define DISABLE_S 0 1856#define DISABLE_V(x) ((x) << DISABLE_S) 1857#define DISABLE_F DISABLE_V(1U) 1858 1859#define TP_RSS_CONFIG_TNL_A 0x7df4 1860 1861#define MASKSIZE_S 28 1862#define MASKSIZE_M 0xfU 1863#define MASKSIZE_V(x) ((x) << MASKSIZE_S) 1864#define MASKSIZE_G(x) (((x) >> MASKSIZE_S) & MASKSIZE_M) 1865 1866#define MASKFILTER_S 16 1867#define MASKFILTER_M 0x7ffU 1868#define MASKFILTER_V(x) ((x) << MASKFILTER_S) 1869#define MASKFILTER_G(x) (((x) >> MASKFILTER_S) & MASKFILTER_M) 1870 1871#define USEWIRECH_S 0 1872#define USEWIRECH_V(x) ((x) << USEWIRECH_S) 1873#define USEWIRECH_F USEWIRECH_V(1U) 1874 1875#define HASHALL_S 2 1876#define HASHALL_V(x) ((x) << HASHALL_S) 1877#define HASHALL_F HASHALL_V(1U) 1878 1879#define HASHETH_S 1 1880#define HASHETH_V(x) ((x) << HASHETH_S) 1881#define HASHETH_F HASHETH_V(1U) 1882 1883#define TP_RSS_CONFIG_OFD_A 0x7df8 1884 1885#define RRCPLMAPEN_S 20 1886#define RRCPLMAPEN_V(x) ((x) << RRCPLMAPEN_S) 1887#define RRCPLMAPEN_F RRCPLMAPEN_V(1U) 1888 1889#define RRCPLQUEWIDTH_S 16 1890#define RRCPLQUEWIDTH_M 0xfU 1891#define RRCPLQUEWIDTH_V(x) ((x) << RRCPLQUEWIDTH_S) 1892#define RRCPLQUEWIDTH_G(x) (((x) >> RRCPLQUEWIDTH_S) & RRCPLQUEWIDTH_M) 1893 1894#define TP_RSS_CONFIG_SYN_A 0x7dfc 1895#define TP_RSS_CONFIG_VRT_A 0x7e00 1896 1897#define VFRDRG_S 25 1898#define VFRDRG_V(x) ((x) << VFRDRG_S) 1899#define VFRDRG_F VFRDRG_V(1U) 1900 1901#define VFRDEN_S 24 1902#define VFRDEN_V(x) ((x) << VFRDEN_S) 1903#define VFRDEN_F VFRDEN_V(1U) 1904 1905#define VFPERREN_S 23 1906#define VFPERREN_V(x) ((x) << VFPERREN_S) 1907#define VFPERREN_F VFPERREN_V(1U) 1908 1909#define KEYPERREN_S 22 1910#define KEYPERREN_V(x) ((x) << KEYPERREN_S) 1911#define KEYPERREN_F KEYPERREN_V(1U) 1912 1913#define DISABLEVLAN_S 21 1914#define DISABLEVLAN_V(x) ((x) << DISABLEVLAN_S) 1915#define DISABLEVLAN_F DISABLEVLAN_V(1U) 1916 1917#define ENABLEUP0_S 20 1918#define ENABLEUP0_V(x) ((x) << ENABLEUP0_S) 1919#define ENABLEUP0_F ENABLEUP0_V(1U) 1920 1921#define HASHDELAY_S 16 1922#define HASHDELAY_M 0xfU 1923#define HASHDELAY_V(x) ((x) << HASHDELAY_S) 1924#define HASHDELAY_G(x) (((x) >> HASHDELAY_S) & HASHDELAY_M) 1925 1926#define VFWRADDR_S 8 1927#define VFWRADDR_M 0x7fU 1928#define VFWRADDR_V(x) ((x) << VFWRADDR_S) 1929#define VFWRADDR_G(x) (((x) >> VFWRADDR_S) & VFWRADDR_M) 1930 1931#define KEYMODE_S 6 1932#define KEYMODE_M 0x3U 1933#define KEYMODE_V(x) ((x) << KEYMODE_S) 1934#define KEYMODE_G(x) (((x) >> KEYMODE_S) & KEYMODE_M) 1935 1936#define VFWREN_S 5 1937#define VFWREN_V(x) ((x) << VFWREN_S) 1938#define VFWREN_F VFWREN_V(1U) 1939 1940#define KEYWREN_S 4 1941#define KEYWREN_V(x) ((x) << KEYWREN_S) 1942#define KEYWREN_F KEYWREN_V(1U) 1943 1944#define KEYWRADDR_S 0 1945#define KEYWRADDR_M 0xfU 1946#define KEYWRADDR_V(x) ((x) << KEYWRADDR_S) 1947#define KEYWRADDR_G(x) (((x) >> KEYWRADDR_S) & KEYWRADDR_M) 1948 1949#define KEYWRADDRX_S 30 1950#define KEYWRADDRX_M 0x3U 1951#define KEYWRADDRX_V(x) ((x) << KEYWRADDRX_S) 1952#define KEYWRADDRX_G(x) (((x) >> KEYWRADDRX_S) & KEYWRADDRX_M) 1953 1954#define KEYEXTEND_S 26 1955#define KEYEXTEND_V(x) ((x) << KEYEXTEND_S) 1956#define KEYEXTEND_F KEYEXTEND_V(1U) 1957 1958#define LKPIDXSIZE_S 24 1959#define LKPIDXSIZE_M 0x3U 1960#define LKPIDXSIZE_V(x) ((x) << LKPIDXSIZE_S) 1961#define LKPIDXSIZE_G(x) (((x) >> LKPIDXSIZE_S) & LKPIDXSIZE_M) 1962 1963#define TP_RSS_VFL_CONFIG_A 0x3a 1964#define TP_RSS_VFH_CONFIG_A 0x3b 1965 1966#define ENABLEUDPHASH_S 31 1967#define ENABLEUDPHASH_V(x) ((x) << ENABLEUDPHASH_S) 1968#define ENABLEUDPHASH_F ENABLEUDPHASH_V(1U) 1969 1970#define VFUPEN_S 30 1971#define VFUPEN_V(x) ((x) << VFUPEN_S) 1972#define VFUPEN_F VFUPEN_V(1U) 1973 1974#define VFVLNEX_S 28 1975#define VFVLNEX_V(x) ((x) << VFVLNEX_S) 1976#define VFVLNEX_F VFVLNEX_V(1U) 1977 1978#define VFPRTEN_S 27 1979#define VFPRTEN_V(x) ((x) << VFPRTEN_S) 1980#define VFPRTEN_F VFPRTEN_V(1U) 1981 1982#define VFCHNEN_S 26 1983#define VFCHNEN_V(x) ((x) << VFCHNEN_S) 1984#define VFCHNEN_F VFCHNEN_V(1U) 1985 1986#define DEFAULTQUEUE_S 16 1987#define DEFAULTQUEUE_M 0x3ffU 1988#define DEFAULTQUEUE_G(x) (((x) >> DEFAULTQUEUE_S) & DEFAULTQUEUE_M) 1989 1990#define VFIP6TWOTUPEN_S 6 1991#define VFIP6TWOTUPEN_V(x) ((x) << VFIP6TWOTUPEN_S) 1992#define VFIP6TWOTUPEN_F VFIP6TWOTUPEN_V(1U) 1993 1994#define VFIP4FOURTUPEN_S 5 1995#define VFIP4FOURTUPEN_V(x) ((x) << VFIP4FOURTUPEN_S) 1996#define VFIP4FOURTUPEN_F VFIP4FOURTUPEN_V(1U) 1997 1998#define VFIP4TWOTUPEN_S 4 1999#define VFIP4TWOTUPEN_V(x) ((x) << VFIP4TWOTUPEN_S) 2000#define VFIP4TWOTUPEN_F VFIP4TWOTUPEN_V(1U) 2001 2002#define KEYINDEX_S 0 2003#define KEYINDEX_M 0xfU 2004#define KEYINDEX_G(x) (((x) >> KEYINDEX_S) & KEYINDEX_M) 2005 2006#define MAPENABLE_S 31 2007#define MAPENABLE_V(x) ((x) << MAPENABLE_S) 2008#define MAPENABLE_F MAPENABLE_V(1U) 2009 2010#define CHNENABLE_S 30 2011#define CHNENABLE_V(x) ((x) << CHNENABLE_S) 2012#define CHNENABLE_F CHNENABLE_V(1U) 2013 2014#define PRTENABLE_S 29 2015#define PRTENABLE_V(x) ((x) << PRTENABLE_S) 2016#define PRTENABLE_F PRTENABLE_V(1U) 2017 2018#define UDPFOURTUPEN_S 28 2019#define UDPFOURTUPEN_V(x) ((x) << UDPFOURTUPEN_S) 2020#define UDPFOURTUPEN_F UDPFOURTUPEN_V(1U) 2021 2022#define IP6FOURTUPEN_S 27 2023#define IP6FOURTUPEN_V(x) ((x) << IP6FOURTUPEN_S) 2024#define IP6FOURTUPEN_F IP6FOURTUPEN_V(1U) 2025 2026#define IP6TWOTUPEN_S 26 2027#define IP6TWOTUPEN_V(x) ((x) << IP6TWOTUPEN_S) 2028#define IP6TWOTUPEN_F IP6TWOTUPEN_V(1U) 2029 2030#define IP4FOURTUPEN_S 25 2031#define IP4FOURTUPEN_V(x) ((x) << IP4FOURTUPEN_S) 2032#define IP4FOURTUPEN_F IP4FOURTUPEN_V(1U) 2033 2034#define IP4TWOTUPEN_S 24 2035#define IP4TWOTUPEN_V(x) ((x) << IP4TWOTUPEN_S) 2036#define IP4TWOTUPEN_F IP4TWOTUPEN_V(1U) 2037 2038#define IVFWIDTH_S 20 2039#define IVFWIDTH_M 0xfU 2040#define IVFWIDTH_V(x) ((x) << IVFWIDTH_S) 2041#define IVFWIDTH_G(x) (((x) >> IVFWIDTH_S) & IVFWIDTH_M) 2042 2043#define CH1DEFAULTQUEUE_S 10 2044#define CH1DEFAULTQUEUE_M 0x3ffU 2045#define CH1DEFAULTQUEUE_V(x) ((x) << CH1DEFAULTQUEUE_S) 2046#define CH1DEFAULTQUEUE_G(x) (((x) >> CH1DEFAULTQUEUE_S) & CH1DEFAULTQUEUE_M) 2047 2048#define CH0DEFAULTQUEUE_S 0 2049#define CH0DEFAULTQUEUE_M 0x3ffU 2050#define CH0DEFAULTQUEUE_V(x) ((x) << CH0DEFAULTQUEUE_S) 2051#define CH0DEFAULTQUEUE_G(x) (((x) >> CH0DEFAULTQUEUE_S) & CH0DEFAULTQUEUE_M) 2052 2053#define VFLKPIDX_S 8 2054#define VFLKPIDX_M 0xffU 2055#define VFLKPIDX_G(x) (((x) >> VFLKPIDX_S) & VFLKPIDX_M) 2056 2057#define TP_RSS_CONFIG_CNG_A 0x7e04 2058#define TP_RSS_SECRET_KEY0_A 0x40 2059#define TP_RSS_PF0_CONFIG_A 0x30 2060#define TP_RSS_PF_MAP_A 0x38 2061#define TP_RSS_PF_MSK_A 0x39 2062 2063#define PF1LKPIDX_S 3 2064 2065#define PF0LKPIDX_M 0x7U 2066 2067#define PF1MSKSIZE_S 4 2068#define PF1MSKSIZE_M 0xfU 2069 2070#define CHNCOUNT3_S 31 2071#define CHNCOUNT3_V(x) ((x) << CHNCOUNT3_S) 2072#define CHNCOUNT3_F CHNCOUNT3_V(1U) 2073 2074#define CHNCOUNT2_S 30 2075#define CHNCOUNT2_V(x) ((x) << CHNCOUNT2_S) 2076#define CHNCOUNT2_F CHNCOUNT2_V(1U) 2077 2078#define CHNCOUNT1_S 29 2079#define CHNCOUNT1_V(x) ((x) << CHNCOUNT1_S) 2080#define CHNCOUNT1_F CHNCOUNT1_V(1U) 2081 2082#define CHNCOUNT0_S 28 2083#define CHNCOUNT0_V(x) ((x) << CHNCOUNT0_S) 2084#define CHNCOUNT0_F CHNCOUNT0_V(1U) 2085 2086#define CHNUNDFLOW3_S 27 2087#define CHNUNDFLOW3_V(x) ((x) << CHNUNDFLOW3_S) 2088#define CHNUNDFLOW3_F CHNUNDFLOW3_V(1U) 2089 2090#define CHNUNDFLOW2_S 26 2091#define CHNUNDFLOW2_V(x) ((x) << CHNUNDFLOW2_S) 2092#define CHNUNDFLOW2_F CHNUNDFLOW2_V(1U) 2093 2094#define CHNUNDFLOW1_S 25 2095#define CHNUNDFLOW1_V(x) ((x) << CHNUNDFLOW1_S) 2096#define CHNUNDFLOW1_F CHNUNDFLOW1_V(1U) 2097 2098#define CHNUNDFLOW0_S 24 2099#define CHNUNDFLOW0_V(x) ((x) << CHNUNDFLOW0_S) 2100#define CHNUNDFLOW0_F CHNUNDFLOW0_V(1U) 2101 2102#define RSTCHN3_S 19 2103#define RSTCHN3_V(x) ((x) << RSTCHN3_S) 2104#define RSTCHN3_F RSTCHN3_V(1U) 2105 2106#define RSTCHN2_S 18 2107#define RSTCHN2_V(x) ((x) << RSTCHN2_S) 2108#define RSTCHN2_F RSTCHN2_V(1U) 2109 2110#define RSTCHN1_S 17 2111#define RSTCHN1_V(x) ((x) << RSTCHN1_S) 2112#define RSTCHN1_F RSTCHN1_V(1U) 2113 2114#define RSTCHN0_S 16 2115#define RSTCHN0_V(x) ((x) << RSTCHN0_S) 2116#define RSTCHN0_F RSTCHN0_V(1U) 2117 2118#define UPDVLD_S 15 2119#define UPDVLD_V(x) ((x) << UPDVLD_S) 2120#define UPDVLD_F UPDVLD_V(1U) 2121 2122#define XOFF_S 14 2123#define XOFF_V(x) ((x) << XOFF_S) 2124#define XOFF_F XOFF_V(1U) 2125 2126#define UPDCHN3_S 13 2127#define UPDCHN3_V(x) ((x) << UPDCHN3_S) 2128#define UPDCHN3_F UPDCHN3_V(1U) 2129 2130#define UPDCHN2_S 12 2131#define UPDCHN2_V(x) ((x) << UPDCHN2_S) 2132#define UPDCHN2_F UPDCHN2_V(1U) 2133 2134#define UPDCHN1_S 11 2135#define UPDCHN1_V(x) ((x) << UPDCHN1_S) 2136#define UPDCHN1_F UPDCHN1_V(1U) 2137 2138#define UPDCHN0_S 10 2139#define UPDCHN0_V(x) ((x) << UPDCHN0_S) 2140#define UPDCHN0_F UPDCHN0_V(1U) 2141 2142#define QUEUE_S 0 2143#define QUEUE_M 0x3ffU 2144#define QUEUE_V(x) ((x) << QUEUE_S) 2145#define QUEUE_G(x) (((x) >> QUEUE_S) & QUEUE_M) 2146 2147#define MPS_TRC_INT_CAUSE_A 0x985c 2148 2149#define MISCPERR_S 8 2150#define MISCPERR_V(x) ((x) << MISCPERR_S) 2151#define MISCPERR_F MISCPERR_V(1U) 2152 2153#define PKTFIFO_S 4 2154#define PKTFIFO_M 0xfU 2155#define PKTFIFO_V(x) ((x) << PKTFIFO_S) 2156 2157#define FILTMEM_S 0 2158#define FILTMEM_M 0xfU 2159#define FILTMEM_V(x) ((x) << FILTMEM_S) 2160 2161#define MPS_CLS_INT_CAUSE_A 0xd028 2162 2163#define HASHSRAM_S 2 2164#define HASHSRAM_V(x) ((x) << HASHSRAM_S) 2165#define HASHSRAM_F HASHSRAM_V(1U) 2166 2167#define MATCHTCAM_S 1 2168#define MATCHTCAM_V(x) ((x) << MATCHTCAM_S) 2169#define MATCHTCAM_F MATCHTCAM_V(1U) 2170 2171#define MATCHSRAM_S 0 2172#define MATCHSRAM_V(x) ((x) << MATCHSRAM_S) 2173#define MATCHSRAM_F MATCHSRAM_V(1U) 2174 2175#define MPS_RX_PERR_INT_CAUSE_A 0x11074 2176 2177#define MPS_CLS_TCAM_Y_L_A 0xf000 2178#define MPS_CLS_TCAM_X_L_A 0xf008 2179 2180#define MPS_CLS_TCAM_Y_L(idx) (MPS_CLS_TCAM_Y_L_A + (idx) * 16) 2181#define NUM_MPS_CLS_TCAM_Y_L_INSTANCES 512 2182 2183#define MPS_CLS_TCAM_X_L(idx) (MPS_CLS_TCAM_X_L_A + (idx) * 16) 2184#define NUM_MPS_CLS_TCAM_X_L_INSTANCES 512 2185 2186#define MPS_CLS_SRAM_L_A 0xe000 2187#define MPS_CLS_SRAM_H_A 0xe004 2188 2189#define MPS_CLS_SRAM_L(idx) (MPS_CLS_SRAM_L_A + (idx) * 8) 2190#define NUM_MPS_CLS_SRAM_L_INSTANCES 336 2191 2192#define MPS_CLS_SRAM_H(idx) (MPS_CLS_SRAM_H_A + (idx) * 8) 2193#define NUM_MPS_CLS_SRAM_H_INSTANCES 336 2194 2195#define MULTILISTEN0_S 25 2196 2197#define REPLICATE_S 11 2198#define REPLICATE_V(x) ((x) << REPLICATE_S) 2199#define REPLICATE_F REPLICATE_V(1U) 2200 2201#define PF_S 8 2202#define PF_M 0x7U 2203#define PF_G(x) (((x) >> PF_S) & PF_M) 2204 2205#define VF_VALID_S 7 2206#define VF_VALID_V(x) ((x) << VF_VALID_S) 2207#define VF_VALID_F VF_VALID_V(1U) 2208 2209#define VF_S 0 2210#define VF_M 0x7fU 2211#define VF_G(x) (((x) >> VF_S) & VF_M) 2212 2213#define SRAM_PRIO3_S 22 2214#define SRAM_PRIO3_M 0x7U 2215#define SRAM_PRIO3_G(x) (((x) >> SRAM_PRIO3_S) & SRAM_PRIO3_M) 2216 2217#define SRAM_PRIO2_S 19 2218#define SRAM_PRIO2_M 0x7U 2219#define SRAM_PRIO2_G(x) (((x) >> SRAM_PRIO2_S) & SRAM_PRIO2_M) 2220 2221#define SRAM_PRIO1_S 16 2222#define SRAM_PRIO1_M 0x7U 2223#define SRAM_PRIO1_G(x) (((x) >> SRAM_PRIO1_S) & SRAM_PRIO1_M) 2224 2225#define SRAM_PRIO0_S 13 2226#define SRAM_PRIO0_M 0x7U 2227#define SRAM_PRIO0_G(x) (((x) >> SRAM_PRIO0_S) & SRAM_PRIO0_M) 2228 2229#define SRAM_VLD_S 12 2230#define SRAM_VLD_V(x) ((x) << SRAM_VLD_S) 2231#define SRAM_VLD_F SRAM_VLD_V(1U) 2232 2233#define PORTMAP_S 0 2234#define PORTMAP_M 0xfU 2235#define PORTMAP_G(x) (((x) >> PORTMAP_S) & PORTMAP_M) 2236 2237#define CPL_INTR_CAUSE_A 0x19054 2238 2239#define CIM_OP_MAP_PERR_S 5 2240#define CIM_OP_MAP_PERR_V(x) ((x) << CIM_OP_MAP_PERR_S) 2241#define CIM_OP_MAP_PERR_F CIM_OP_MAP_PERR_V(1U) 2242 2243#define CIM_OVFL_ERROR_S 4 2244#define CIM_OVFL_ERROR_V(x) ((x) << CIM_OVFL_ERROR_S) 2245#define CIM_OVFL_ERROR_F CIM_OVFL_ERROR_V(1U) 2246 2247#define TP_FRAMING_ERROR_S 3 2248#define TP_FRAMING_ERROR_V(x) ((x) << TP_FRAMING_ERROR_S) 2249#define TP_FRAMING_ERROR_F TP_FRAMING_ERROR_V(1U) 2250 2251#define SGE_FRAMING_ERROR_S 2 2252#define SGE_FRAMING_ERROR_V(x) ((x) << SGE_FRAMING_ERROR_S) 2253#define SGE_FRAMING_ERROR_F SGE_FRAMING_ERROR_V(1U) 2254 2255#define CIM_FRAMING_ERROR_S 1 2256#define CIM_FRAMING_ERROR_V(x) ((x) << CIM_FRAMING_ERROR_S) 2257#define CIM_FRAMING_ERROR_F CIM_FRAMING_ERROR_V(1U) 2258 2259#define ZERO_SWITCH_ERROR_S 0 2260#define ZERO_SWITCH_ERROR_V(x) ((x) << ZERO_SWITCH_ERROR_S) 2261#define ZERO_SWITCH_ERROR_F ZERO_SWITCH_ERROR_V(1U) 2262 2263#define SMB_INT_CAUSE_A 0x19090 2264 2265#define MSTTXFIFOPARINT_S 21 2266#define MSTTXFIFOPARINT_V(x) ((x) << MSTTXFIFOPARINT_S) 2267#define MSTTXFIFOPARINT_F MSTTXFIFOPARINT_V(1U) 2268 2269#define MSTRXFIFOPARINT_S 20 2270#define MSTRXFIFOPARINT_V(x) ((x) << MSTRXFIFOPARINT_S) 2271#define MSTRXFIFOPARINT_F MSTRXFIFOPARINT_V(1U) 2272 2273#define SLVFIFOPARINT_S 19 2274#define SLVFIFOPARINT_V(x) ((x) << SLVFIFOPARINT_S) 2275#define SLVFIFOPARINT_F SLVFIFOPARINT_V(1U) 2276 2277#define ULP_RX_INT_CAUSE_A 0x19158 2278#define ULP_RX_ISCSI_TAGMASK_A 0x19164 2279#define ULP_RX_ISCSI_PSZ_A 0x19168 2280#define ULP_RX_LA_CTL_A 0x1923c 2281#define ULP_RX_LA_RDPTR_A 0x19240 2282#define ULP_RX_LA_RDDATA_A 0x19244 2283#define ULP_RX_LA_WRPTR_A 0x19248 2284 2285#define HPZ3_S 24 2286#define HPZ3_V(x) ((x) << HPZ3_S) 2287 2288#define HPZ2_S 16 2289#define HPZ2_V(x) ((x) << HPZ2_S) 2290 2291#define HPZ1_S 8 2292#define HPZ1_V(x) ((x) << HPZ1_S) 2293 2294#define HPZ0_S 0 2295#define HPZ0_V(x) ((x) << HPZ0_S) 2296 2297#define ULP_RX_TDDP_PSZ_A 0x19178 2298 2299/* registers for module SF */ 2300#define SF_DATA_A 0x193f8 2301#define SF_OP_A 0x193fc 2302 2303#define SF_BUSY_S 31 2304#define SF_BUSY_V(x) ((x) << SF_BUSY_S) 2305#define SF_BUSY_F SF_BUSY_V(1U) 2306 2307#define SF_LOCK_S 4 2308#define SF_LOCK_V(x) ((x) << SF_LOCK_S) 2309#define SF_LOCK_F SF_LOCK_V(1U) 2310 2311#define SF_CONT_S 3 2312#define SF_CONT_V(x) ((x) << SF_CONT_S) 2313#define SF_CONT_F SF_CONT_V(1U) 2314 2315#define BYTECNT_S 1 2316#define BYTECNT_V(x) ((x) << BYTECNT_S) 2317 2318#define OP_S 0 2319#define OP_V(x) ((x) << OP_S) 2320#define OP_F OP_V(1U) 2321 2322#define PL_PF_INT_CAUSE_A 0x3c0 2323 2324#define PFSW_S 3 2325#define PFSW_V(x) ((x) << PFSW_S) 2326#define PFSW_F PFSW_V(1U) 2327 2328#define PFCIM_S 1 2329#define PFCIM_V(x) ((x) << PFCIM_S) 2330#define PFCIM_F PFCIM_V(1U) 2331 2332#define PL_PF_INT_ENABLE_A 0x3c4 2333#define PL_PF_CTL_A 0x3c8 2334 2335#define PL_WHOAMI_A 0x19400 2336 2337#define SOURCEPF_S 8 2338#define SOURCEPF_M 0x7U 2339#define SOURCEPF_G(x) (((x) >> SOURCEPF_S) & SOURCEPF_M) 2340 2341#define PL_INT_CAUSE_A 0x1940c 2342 2343#define ULP_TX_S 27 2344#define ULP_TX_V(x) ((x) << ULP_TX_S) 2345#define ULP_TX_F ULP_TX_V(1U) 2346 2347#define SGE_S 26 2348#define SGE_V(x) ((x) << SGE_S) 2349#define SGE_F SGE_V(1U) 2350 2351#define CPL_SWITCH_S 24 2352#define CPL_SWITCH_V(x) ((x) << CPL_SWITCH_S) 2353#define CPL_SWITCH_F CPL_SWITCH_V(1U) 2354 2355#define ULP_RX_S 23 2356#define ULP_RX_V(x) ((x) << ULP_RX_S) 2357#define ULP_RX_F ULP_RX_V(1U) 2358 2359#define PM_RX_S 22 2360#define PM_RX_V(x) ((x) << PM_RX_S) 2361#define PM_RX_F PM_RX_V(1U) 2362 2363#define PM_TX_S 21 2364#define PM_TX_V(x) ((x) << PM_TX_S) 2365#define PM_TX_F PM_TX_V(1U) 2366 2367#define MA_S 20 2368#define MA_V(x) ((x) << MA_S) 2369#define MA_F MA_V(1U) 2370 2371#define TP_S 19 2372#define TP_V(x) ((x) << TP_S) 2373#define TP_F TP_V(1U) 2374 2375#define LE_S 18 2376#define LE_V(x) ((x) << LE_S) 2377#define LE_F LE_V(1U) 2378 2379#define EDC1_S 17 2380#define EDC1_V(x) ((x) << EDC1_S) 2381#define EDC1_F EDC1_V(1U) 2382 2383#define EDC0_S 16 2384#define EDC0_V(x) ((x) << EDC0_S) 2385#define EDC0_F EDC0_V(1U) 2386 2387#define MC_S 15 2388#define MC_V(x) ((x) << MC_S) 2389#define MC_F MC_V(1U) 2390 2391#define PCIE_S 14 2392#define PCIE_V(x) ((x) << PCIE_S) 2393#define PCIE_F PCIE_V(1U) 2394 2395#define XGMAC_KR1_S 12 2396#define XGMAC_KR1_V(x) ((x) << XGMAC_KR1_S) 2397#define XGMAC_KR1_F XGMAC_KR1_V(1U) 2398 2399#define XGMAC_KR0_S 11 2400#define XGMAC_KR0_V(x) ((x) << XGMAC_KR0_S) 2401#define XGMAC_KR0_F XGMAC_KR0_V(1U) 2402 2403#define XGMAC1_S 10 2404#define XGMAC1_V(x) ((x) << XGMAC1_S) 2405#define XGMAC1_F XGMAC1_V(1U) 2406 2407#define XGMAC0_S 9 2408#define XGMAC0_V(x) ((x) << XGMAC0_S) 2409#define XGMAC0_F XGMAC0_V(1U) 2410 2411#define SMB_S 8 2412#define SMB_V(x) ((x) << SMB_S) 2413#define SMB_F SMB_V(1U) 2414 2415#define SF_S 7 2416#define SF_V(x) ((x) << SF_S) 2417#define SF_F SF_V(1U) 2418 2419#define PL_S 6 2420#define PL_V(x) ((x) << PL_S) 2421#define PL_F PL_V(1U) 2422 2423#define NCSI_S 5 2424#define NCSI_V(x) ((x) << NCSI_S) 2425#define NCSI_F NCSI_V(1U) 2426 2427#define MPS_S 4 2428#define MPS_V(x) ((x) << MPS_S) 2429#define MPS_F MPS_V(1U) 2430 2431#define CIM_S 0 2432#define CIM_V(x) ((x) << CIM_S) 2433#define CIM_F CIM_V(1U) 2434 2435#define MC1_S 31 2436 2437#define PL_INT_ENABLE_A 0x19410 2438#define PL_INT_MAP0_A 0x19414 2439#define PL_RST_A 0x19428 2440 2441#define PIORST_S 1 2442#define PIORST_V(x) ((x) << PIORST_S) 2443#define PIORST_F PIORST_V(1U) 2444 2445#define PIORSTMODE_S 0 2446#define PIORSTMODE_V(x) ((x) << PIORSTMODE_S) 2447#define PIORSTMODE_F PIORSTMODE_V(1U) 2448 2449#define PL_PL_INT_CAUSE_A 0x19430 2450 2451#define FATALPERR_S 4 2452#define FATALPERR_V(x) ((x) << FATALPERR_S) 2453#define FATALPERR_F FATALPERR_V(1U) 2454 2455#define PERRVFID_S 0 2456#define PERRVFID_V(x) ((x) << PERRVFID_S) 2457#define PERRVFID_F PERRVFID_V(1U) 2458 2459#define PL_REV_A 0x1943c 2460 2461#define REV_S 0 2462#define REV_M 0xfU 2463#define REV_V(x) ((x) << REV_S) 2464#define REV_G(x) (((x) >> REV_S) & REV_M) 2465 2466#define LE_DB_INT_CAUSE_A 0x19c3c 2467 2468#define REQQPARERR_S 16 2469#define REQQPARERR_V(x) ((x) << REQQPARERR_S) 2470#define REQQPARERR_F REQQPARERR_V(1U) 2471 2472#define UNKNOWNCMD_S 15 2473#define UNKNOWNCMD_V(x) ((x) << UNKNOWNCMD_S) 2474#define UNKNOWNCMD_F UNKNOWNCMD_V(1U) 2475 2476#define PARITYERR_S 6 2477#define PARITYERR_V(x) ((x) << PARITYERR_S) 2478#define PARITYERR_F PARITYERR_V(1U) 2479 2480#define LIPMISS_S 5 2481#define LIPMISS_V(x) ((x) << LIPMISS_S) 2482#define LIPMISS_F LIPMISS_V(1U) 2483 2484#define LIP0_S 4 2485#define LIP0_V(x) ((x) << LIP0_S) 2486#define LIP0_F LIP0_V(1U) 2487 2488#define NCSI_INT_CAUSE_A 0x1a0d8 2489 2490#define CIM_DM_PRTY_ERR_S 8 2491#define CIM_DM_PRTY_ERR_V(x) ((x) << CIM_DM_PRTY_ERR_S) 2492#define CIM_DM_PRTY_ERR_F CIM_DM_PRTY_ERR_V(1U) 2493 2494#define MPS_DM_PRTY_ERR_S 7 2495#define MPS_DM_PRTY_ERR_V(x) ((x) << MPS_DM_PRTY_ERR_S) 2496#define MPS_DM_PRTY_ERR_F MPS_DM_PRTY_ERR_V(1U) 2497 2498#define TXFIFO_PRTY_ERR_S 1 2499#define TXFIFO_PRTY_ERR_V(x) ((x) << TXFIFO_PRTY_ERR_S) 2500#define TXFIFO_PRTY_ERR_F TXFIFO_PRTY_ERR_V(1U) 2501 2502#define RXFIFO_PRTY_ERR_S 0 2503#define RXFIFO_PRTY_ERR_V(x) ((x) << RXFIFO_PRTY_ERR_S) 2504#define RXFIFO_PRTY_ERR_F RXFIFO_PRTY_ERR_V(1U) 2505 2506#define XGMAC_PORT_CFG2_A 0x1018 2507 2508#define PATEN_S 18 2509#define PATEN_V(x) ((x) << PATEN_S) 2510#define PATEN_F PATEN_V(1U) 2511 2512#define MAGICEN_S 17 2513#define MAGICEN_V(x) ((x) << MAGICEN_S) 2514#define MAGICEN_F MAGICEN_V(1U) 2515 2516#define XGMAC_PORT_MAGIC_MACID_LO 0x1024 2517#define XGMAC_PORT_MAGIC_MACID_HI 0x1028 2518 2519#define XGMAC_PORT_EPIO_DATA0_A 0x10c0 2520#define XGMAC_PORT_EPIO_DATA1_A 0x10c4 2521#define XGMAC_PORT_EPIO_DATA2_A 0x10c8 2522#define XGMAC_PORT_EPIO_DATA3_A 0x10cc 2523#define XGMAC_PORT_EPIO_OP_A 0x10d0 2524 2525#define EPIOWR_S 8 2526#define EPIOWR_V(x) ((x) << EPIOWR_S) 2527#define EPIOWR_F EPIOWR_V(1U) 2528 2529#define ADDRESS_S 0 2530#define ADDRESS_V(x) ((x) << ADDRESS_S) 2531 2532#define MAC_PORT_INT_CAUSE_A 0x8dc 2533#define XGMAC_PORT_INT_CAUSE_A 0x10dc 2534 2535#define TP_TX_MOD_QUEUE_REQ_MAP_A 0x7e28 2536 2537#define TP_TX_MOD_QUEUE_WEIGHT0_A 0x7e30 2538#define TP_TX_MOD_CHANNEL_WEIGHT_A 0x7e34 2539 2540#define TX_MOD_QUEUE_REQ_MAP_S 0 2541#define TX_MOD_QUEUE_REQ_MAP_V(x) ((x) << TX_MOD_QUEUE_REQ_MAP_S) 2542 2543#define TX_MODQ_WEIGHT3_S 24 2544#define TX_MODQ_WEIGHT3_V(x) ((x) << TX_MODQ_WEIGHT3_S) 2545 2546#define TX_MODQ_WEIGHT2_S 16 2547#define TX_MODQ_WEIGHT2_V(x) ((x) << TX_MODQ_WEIGHT2_S) 2548 2549#define TX_MODQ_WEIGHT1_S 8 2550#define TX_MODQ_WEIGHT1_V(x) ((x) << TX_MODQ_WEIGHT1_S) 2551 2552#define TX_MODQ_WEIGHT0_S 0 2553#define TX_MODQ_WEIGHT0_V(x) ((x) << TX_MODQ_WEIGHT0_S) 2554 2555#define TP_TX_SCHED_HDR_A 0x23 2556#define TP_TX_SCHED_FIFO_A 0x24 2557#define TP_TX_SCHED_PCMD_A 0x25 2558 2559#define NUM_MPS_CLS_SRAM_L_INSTANCES 336 2560#define NUM_MPS_T5_CLS_SRAM_L_INSTANCES 512 2561 2562#define T5_PORT0_BASE 0x30000 2563#define T5_PORT_STRIDE 0x4000 2564#define T5_PORT_BASE(idx) (T5_PORT0_BASE + (idx) * T5_PORT_STRIDE) 2565#define T5_PORT_REG(idx, reg) (T5_PORT_BASE(idx) + (reg)) 2566 2567#define MC_0_BASE_ADDR 0x40000 2568#define MC_1_BASE_ADDR 0x48000 2569#define MC_STRIDE (MC_1_BASE_ADDR - MC_0_BASE_ADDR) 2570#define MC_REG(reg, idx) (reg + MC_STRIDE * idx) 2571 2572#define MC_P_BIST_CMD_A 0x41400 2573#define MC_P_BIST_CMD_ADDR_A 0x41404 2574#define MC_P_BIST_CMD_LEN_A 0x41408 2575#define MC_P_BIST_DATA_PATTERN_A 0x4140c 2576#define MC_P_BIST_STATUS_RDATA_A 0x41488 2577 2578#define EDC_T50_BASE_ADDR 0x50000 2579 2580#define EDC_H_BIST_CMD_A 0x50004 2581#define EDC_H_BIST_CMD_ADDR_A 0x50008 2582#define EDC_H_BIST_CMD_LEN_A 0x5000c 2583#define EDC_H_BIST_DATA_PATTERN_A 0x50010 2584#define EDC_H_BIST_STATUS_RDATA_A 0x50028 2585 2586#define EDC_T51_BASE_ADDR 0x50800 2587 2588#define EDC_STRIDE_T5 (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR) 2589#define EDC_REG_T5(reg, idx) (reg + EDC_STRIDE_T5 * idx) 2590 2591#define PL_VF_REV_A 0x4 2592#define PL_VF_WHOAMI_A 0x0 2593#define PL_VF_REVISION_A 0x8 2594 2595/* registers for module CIM */ 2596#define CIM_HOST_ACC_CTRL_A 0x7b50 2597#define CIM_HOST_ACC_DATA_A 0x7b54 2598#define UP_UP_DBG_LA_CFG_A 0x140 2599#define UP_UP_DBG_LA_DATA_A 0x144 2600 2601#define HOSTBUSY_S 17 2602#define HOSTBUSY_V(x) ((x) << HOSTBUSY_S) 2603#define HOSTBUSY_F HOSTBUSY_V(1U) 2604 2605#define HOSTWRITE_S 16 2606#define HOSTWRITE_V(x) ((x) << HOSTWRITE_S) 2607#define HOSTWRITE_F HOSTWRITE_V(1U) 2608 2609#define CIM_IBQ_DBG_CFG_A 0x7b60 2610 2611#define IBQDBGADDR_S 16 2612#define IBQDBGADDR_M 0xfffU 2613#define IBQDBGADDR_V(x) ((x) << IBQDBGADDR_S) 2614#define IBQDBGADDR_G(x) (((x) >> IBQDBGADDR_S) & IBQDBGADDR_M) 2615 2616#define IBQDBGBUSY_S 1 2617#define IBQDBGBUSY_V(x) ((x) << IBQDBGBUSY_S) 2618#define IBQDBGBUSY_F IBQDBGBUSY_V(1U) 2619 2620#define IBQDBGEN_S 0 2621#define IBQDBGEN_V(x) ((x) << IBQDBGEN_S) 2622#define IBQDBGEN_F IBQDBGEN_V(1U) 2623 2624#define CIM_OBQ_DBG_CFG_A 0x7b64 2625 2626#define OBQDBGADDR_S 16 2627#define OBQDBGADDR_M 0xfffU 2628#define OBQDBGADDR_V(x) ((x) << OBQDBGADDR_S) 2629#define OBQDBGADDR_G(x) (((x) >> OBQDBGADDR_S) & OBQDBGADDR_M) 2630 2631#define OBQDBGBUSY_S 1 2632#define OBQDBGBUSY_V(x) ((x) << OBQDBGBUSY_S) 2633#define OBQDBGBUSY_F OBQDBGBUSY_V(1U) 2634 2635#define OBQDBGEN_S 0 2636#define OBQDBGEN_V(x) ((x) << OBQDBGEN_S) 2637#define OBQDBGEN_F OBQDBGEN_V(1U) 2638 2639#define CIM_IBQ_DBG_DATA_A 0x7b68 2640#define CIM_OBQ_DBG_DATA_A 0x7b6c 2641 2642#define UPDBGLARDEN_S 1 2643#define UPDBGLARDEN_V(x) ((x) << UPDBGLARDEN_S) 2644#define UPDBGLARDEN_F UPDBGLARDEN_V(1U) 2645 2646#define UPDBGLAEN_S 0 2647#define UPDBGLAEN_V(x) ((x) << UPDBGLAEN_S) 2648#define UPDBGLAEN_F UPDBGLAEN_V(1U) 2649 2650#define UPDBGLARDPTR_S 2 2651#define UPDBGLARDPTR_M 0xfffU 2652#define UPDBGLARDPTR_V(x) ((x) << UPDBGLARDPTR_S) 2653 2654#define UPDBGLAWRPTR_S 16 2655#define UPDBGLAWRPTR_M 0xfffU 2656#define UPDBGLAWRPTR_G(x) (((x) >> UPDBGLAWRPTR_S) & UPDBGLAWRPTR_M) 2657 2658#define UPDBGLACAPTPCONLY_S 30 2659#define UPDBGLACAPTPCONLY_V(x) ((x) << UPDBGLACAPTPCONLY_S) 2660#define UPDBGLACAPTPCONLY_F UPDBGLACAPTPCONLY_V(1U) 2661 2662#define CIM_QUEUE_CONFIG_REF_A 0x7b48 2663#define CIM_QUEUE_CONFIG_CTRL_A 0x7b4c 2664 2665#define CIMQSIZE_S 24 2666#define CIMQSIZE_M 0x3fU 2667#define CIMQSIZE_G(x) (((x) >> CIMQSIZE_S) & CIMQSIZE_M) 2668 2669#define CIMQBASE_S 16 2670#define CIMQBASE_M 0x3fU 2671#define CIMQBASE_G(x) (((x) >> CIMQBASE_S) & CIMQBASE_M) 2672 2673#define QUEFULLTHRSH_S 0 2674#define QUEFULLTHRSH_M 0x1ffU 2675#define QUEFULLTHRSH_G(x) (((x) >> QUEFULLTHRSH_S) & QUEFULLTHRSH_M) 2676 2677#define UP_IBQ_0_RDADDR_A 0x10 2678#define UP_IBQ_0_SHADOW_RDADDR_A 0x280 2679#define UP_OBQ_0_REALADDR_A 0x104 2680#define UP_OBQ_0_SHADOW_REALADDR_A 0x394 2681 2682#define IBQRDADDR_S 0 2683#define IBQRDADDR_M 0x1fffU 2684#define IBQRDADDR_G(x) (((x) >> IBQRDADDR_S) & IBQRDADDR_M) 2685 2686#define IBQWRADDR_S 0 2687#define IBQWRADDR_M 0x1fffU 2688#define IBQWRADDR_G(x) (((x) >> IBQWRADDR_S) & IBQWRADDR_M) 2689 2690#define QUERDADDR_S 0 2691#define QUERDADDR_M 0x7fffU 2692#define QUERDADDR_G(x) (((x) >> QUERDADDR_S) & QUERDADDR_M) 2693 2694#define QUEREMFLITS_S 0 2695#define QUEREMFLITS_M 0x7ffU 2696#define QUEREMFLITS_G(x) (((x) >> QUEREMFLITS_S) & QUEREMFLITS_M) 2697 2698#define QUEEOPCNT_S 16 2699#define QUEEOPCNT_M 0xfffU 2700#define QUEEOPCNT_G(x) (((x) >> QUEEOPCNT_S) & QUEEOPCNT_M) 2701 2702#define QUESOPCNT_S 0 2703#define QUESOPCNT_M 0xfffU 2704#define QUESOPCNT_G(x) (((x) >> QUESOPCNT_S) & QUESOPCNT_M) 2705 2706#define OBQSELECT_S 4 2707#define OBQSELECT_V(x) ((x) << OBQSELECT_S) 2708#define OBQSELECT_F OBQSELECT_V(1U) 2709 2710#define IBQSELECT_S 3 2711#define IBQSELECT_V(x) ((x) << IBQSELECT_S) 2712#define IBQSELECT_F IBQSELECT_V(1U) 2713 2714#define QUENUMSELECT_S 0 2715#define QUENUMSELECT_V(x) ((x) << QUENUMSELECT_S) 2716 2717#endif /* __T4_REGS_H */ 2718