1/* 2 * linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver 3 * 4 * Header file for Host Controller registers and I/O accessors. 5 * 6 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or (at 11 * your option) any later version. 12 */ 13#ifndef __SDHCI_HW_H 14#define __SDHCI_HW_H 15 16#include <linux/scatterlist.h> 17#include <linux/compiler.h> 18#include <linux/types.h> 19#include <linux/io.h> 20 21#include <linux/mmc/host.h> 22 23/* 24 * Controller registers 25 */ 26 27#define SDHCI_DMA_ADDRESS 0x00 28#define SDHCI_ARGUMENT2 SDHCI_DMA_ADDRESS 29 30#define SDHCI_BLOCK_SIZE 0x04 31#define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) 32 33#define SDHCI_BLOCK_COUNT 0x06 34 35#define SDHCI_ARGUMENT 0x08 36 37#define SDHCI_TRANSFER_MODE 0x0C 38#define SDHCI_TRNS_DMA 0x01 39#define SDHCI_TRNS_BLK_CNT_EN 0x02 40#define SDHCI_TRNS_AUTO_CMD12 0x04 41#define SDHCI_TRNS_AUTO_CMD23 0x08 42#define SDHCI_TRNS_READ 0x10 43#define SDHCI_TRNS_MULTI 0x20 44 45#define SDHCI_COMMAND 0x0E 46#define SDHCI_CMD_RESP_MASK 0x03 47#define SDHCI_CMD_CRC 0x08 48#define SDHCI_CMD_INDEX 0x10 49#define SDHCI_CMD_DATA 0x20 50#define SDHCI_CMD_ABORTCMD 0xC0 51 52#define SDHCI_CMD_RESP_NONE 0x00 53#define SDHCI_CMD_RESP_LONG 0x01 54#define SDHCI_CMD_RESP_SHORT 0x02 55#define SDHCI_CMD_RESP_SHORT_BUSY 0x03 56 57#define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff)) 58#define SDHCI_GET_CMD(c) ((c>>8) & 0x3f) 59 60#define SDHCI_RESPONSE 0x10 61 62#define SDHCI_BUFFER 0x20 63 64#define SDHCI_PRESENT_STATE 0x24 65#define SDHCI_CMD_INHIBIT 0x00000001 66#define SDHCI_DATA_INHIBIT 0x00000002 67#define SDHCI_DOING_WRITE 0x00000100 68#define SDHCI_DOING_READ 0x00000200 69#define SDHCI_SPACE_AVAILABLE 0x00000400 70#define SDHCI_DATA_AVAILABLE 0x00000800 71#define SDHCI_CARD_PRESENT 0x00010000 72#define SDHCI_WRITE_PROTECT 0x00080000 73#define SDHCI_DATA_LVL_MASK 0x00F00000 74#define SDHCI_DATA_LVL_SHIFT 20 75#define SDHCI_DATA_0_LVL_MASK 0x00100000 76 77#define SDHCI_HOST_CONTROL 0x28 78#define SDHCI_CTRL_LED 0x01 79#define SDHCI_CTRL_4BITBUS 0x02 80#define SDHCI_CTRL_HISPD 0x04 81#define SDHCI_CTRL_DMA_MASK 0x18 82#define SDHCI_CTRL_SDMA 0x00 83#define SDHCI_CTRL_ADMA1 0x08 84#define SDHCI_CTRL_ADMA32 0x10 85#define SDHCI_CTRL_ADMA64 0x18 86#define SDHCI_CTRL_8BITBUS 0x20 87 88#define SDHCI_POWER_CONTROL 0x29 89#define SDHCI_POWER_ON 0x01 90#define SDHCI_POWER_180 0x0A 91#define SDHCI_POWER_300 0x0C 92#define SDHCI_POWER_330 0x0E 93 94#define SDHCI_BLOCK_GAP_CONTROL 0x2A 95 96#define SDHCI_WAKE_UP_CONTROL 0x2B 97#define SDHCI_WAKE_ON_INT 0x01 98#define SDHCI_WAKE_ON_INSERT 0x02 99#define SDHCI_WAKE_ON_REMOVE 0x04 100 101#define SDHCI_CLOCK_CONTROL 0x2C 102#define SDHCI_DIVIDER_SHIFT 8 103#define SDHCI_DIVIDER_HI_SHIFT 6 104#define SDHCI_DIV_MASK 0xFF 105#define SDHCI_DIV_MASK_LEN 8 106#define SDHCI_DIV_HI_MASK 0x300 107#define SDHCI_PROG_CLOCK_MODE 0x0020 108#define SDHCI_CLOCK_CARD_EN 0x0004 109#define SDHCI_CLOCK_INT_STABLE 0x0002 110#define SDHCI_CLOCK_INT_EN 0x0001 111 112#define SDHCI_TIMEOUT_CONTROL 0x2E 113 114#define SDHCI_SOFTWARE_RESET 0x2F 115#define SDHCI_RESET_ALL 0x01 116#define SDHCI_RESET_CMD 0x02 117#define SDHCI_RESET_DATA 0x04 118 119#define SDHCI_INT_STATUS 0x30 120#define SDHCI_INT_ENABLE 0x34 121#define SDHCI_SIGNAL_ENABLE 0x38 122#define SDHCI_INT_RESPONSE 0x00000001 123#define SDHCI_INT_DATA_END 0x00000002 124#define SDHCI_INT_BLK_GAP 0x00000004 125#define SDHCI_INT_DMA_END 0x00000008 126#define SDHCI_INT_SPACE_AVAIL 0x00000010 127#define SDHCI_INT_DATA_AVAIL 0x00000020 128#define SDHCI_INT_CARD_INSERT 0x00000040 129#define SDHCI_INT_CARD_REMOVE 0x00000080 130#define SDHCI_INT_CARD_INT 0x00000100 131#define SDHCI_INT_ERROR 0x00008000 132#define SDHCI_INT_TIMEOUT 0x00010000 133#define SDHCI_INT_CRC 0x00020000 134#define SDHCI_INT_END_BIT 0x00040000 135#define SDHCI_INT_INDEX 0x00080000 136#define SDHCI_INT_DATA_TIMEOUT 0x00100000 137#define SDHCI_INT_DATA_CRC 0x00200000 138#define SDHCI_INT_DATA_END_BIT 0x00400000 139#define SDHCI_INT_BUS_POWER 0x00800000 140#define SDHCI_INT_ACMD12ERR 0x01000000 141#define SDHCI_INT_ADMA_ERROR 0x02000000 142 143#define SDHCI_INT_NORMAL_MASK 0x00007FFF 144#define SDHCI_INT_ERROR_MASK 0xFFFF8000 145 146#define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \ 147 SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX) 148#define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \ 149 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \ 150 SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \ 151 SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR | \ 152 SDHCI_INT_BLK_GAP) 153#define SDHCI_INT_ALL_MASK ((unsigned int)-1) 154 155#define SDHCI_ACMD12_ERR 0x3C 156 157#define SDHCI_HOST_CONTROL2 0x3E 158#define SDHCI_CTRL_UHS_MASK 0x0007 159#define SDHCI_CTRL_UHS_SDR12 0x0000 160#define SDHCI_CTRL_UHS_SDR25 0x0001 161#define SDHCI_CTRL_UHS_SDR50 0x0002 162#define SDHCI_CTRL_UHS_SDR104 0x0003 163#define SDHCI_CTRL_UHS_DDR50 0x0004 164#define SDHCI_CTRL_HS400 0x0005 /* Non-standard */ 165#define SDHCI_CTRL_VDD_180 0x0008 166#define SDHCI_CTRL_DRV_TYPE_MASK 0x0030 167#define SDHCI_CTRL_DRV_TYPE_B 0x0000 168#define SDHCI_CTRL_DRV_TYPE_A 0x0010 169#define SDHCI_CTRL_DRV_TYPE_C 0x0020 170#define SDHCI_CTRL_DRV_TYPE_D 0x0030 171#define SDHCI_CTRL_EXEC_TUNING 0x0040 172#define SDHCI_CTRL_TUNED_CLK 0x0080 173#define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000 174 175#define SDHCI_CAPABILITIES 0x40 176#define SDHCI_TIMEOUT_CLK_MASK 0x0000003F 177#define SDHCI_TIMEOUT_CLK_SHIFT 0 178#define SDHCI_TIMEOUT_CLK_UNIT 0x00000080 179#define SDHCI_CLOCK_BASE_MASK 0x00003F00 180#define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00 181#define SDHCI_CLOCK_BASE_SHIFT 8 182#define SDHCI_MAX_BLOCK_MASK 0x00030000 183#define SDHCI_MAX_BLOCK_SHIFT 16 184#define SDHCI_CAN_DO_8BIT 0x00040000 185#define SDHCI_CAN_DO_ADMA2 0x00080000 186#define SDHCI_CAN_DO_ADMA1 0x00100000 187#define SDHCI_CAN_DO_HISPD 0x00200000 188#define SDHCI_CAN_DO_SDMA 0x00400000 189#define SDHCI_CAN_VDD_330 0x01000000 190#define SDHCI_CAN_VDD_300 0x02000000 191#define SDHCI_CAN_VDD_180 0x04000000 192#define SDHCI_CAN_64BIT 0x10000000 193 194#define SDHCI_SUPPORT_SDR50 0x00000001 195#define SDHCI_SUPPORT_SDR104 0x00000002 196#define SDHCI_SUPPORT_DDR50 0x00000004 197#define SDHCI_DRIVER_TYPE_A 0x00000010 198#define SDHCI_DRIVER_TYPE_C 0x00000020 199#define SDHCI_DRIVER_TYPE_D 0x00000040 200#define SDHCI_RETUNING_TIMER_COUNT_MASK 0x00000F00 201#define SDHCI_RETUNING_TIMER_COUNT_SHIFT 8 202#define SDHCI_USE_SDR50_TUNING 0x00002000 203#define SDHCI_RETUNING_MODE_MASK 0x0000C000 204#define SDHCI_RETUNING_MODE_SHIFT 14 205#define SDHCI_CLOCK_MUL_MASK 0x00FF0000 206#define SDHCI_CLOCK_MUL_SHIFT 16 207#define SDHCI_SUPPORT_HS400 0x80000000 /* Non-standard */ 208 209#define SDHCI_CAPABILITIES_1 0x44 210 211#define SDHCI_MAX_CURRENT 0x48 212#define SDHCI_MAX_CURRENT_LIMIT 0xFF 213#define SDHCI_MAX_CURRENT_330_MASK 0x0000FF 214#define SDHCI_MAX_CURRENT_330_SHIFT 0 215#define SDHCI_MAX_CURRENT_300_MASK 0x00FF00 216#define SDHCI_MAX_CURRENT_300_SHIFT 8 217#define SDHCI_MAX_CURRENT_180_MASK 0xFF0000 218#define SDHCI_MAX_CURRENT_180_SHIFT 16 219#define SDHCI_MAX_CURRENT_MULTIPLIER 4 220 221/* 4C-4F reserved for more max current */ 222 223#define SDHCI_SET_ACMD12_ERROR 0x50 224#define SDHCI_SET_INT_ERROR 0x52 225 226#define SDHCI_ADMA_ERROR 0x54 227 228/* 55-57 reserved */ 229 230#define SDHCI_ADMA_ADDRESS 0x58 231#define SDHCI_ADMA_ADDRESS_HI 0x5C 232 233/* 60-FB reserved */ 234 235#define SDHCI_PRESET_FOR_SDR12 0x66 236#define SDHCI_PRESET_FOR_SDR25 0x68 237#define SDHCI_PRESET_FOR_SDR50 0x6A 238#define SDHCI_PRESET_FOR_SDR104 0x6C 239#define SDHCI_PRESET_FOR_DDR50 0x6E 240#define SDHCI_PRESET_FOR_HS400 0x74 /* Non-standard */ 241#define SDHCI_PRESET_DRV_MASK 0xC000 242#define SDHCI_PRESET_DRV_SHIFT 14 243#define SDHCI_PRESET_CLKGEN_SEL_MASK 0x400 244#define SDHCI_PRESET_CLKGEN_SEL_SHIFT 10 245#define SDHCI_PRESET_SDCLK_FREQ_MASK 0x3FF 246#define SDHCI_PRESET_SDCLK_FREQ_SHIFT 0 247 248#define SDHCI_SLOT_INT_STATUS 0xFC 249 250#define SDHCI_HOST_VERSION 0xFE 251#define SDHCI_VENDOR_VER_MASK 0xFF00 252#define SDHCI_VENDOR_VER_SHIFT 8 253#define SDHCI_SPEC_VER_MASK 0x00FF 254#define SDHCI_SPEC_VER_SHIFT 0 255#define SDHCI_SPEC_100 0 256#define SDHCI_SPEC_200 1 257#define SDHCI_SPEC_300 2 258 259/* 260 * End of controller registers. 261 */ 262 263#define SDHCI_MAX_DIV_SPEC_200 256 264#define SDHCI_MAX_DIV_SPEC_300 2046 265 266/* 267 * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2. 268 */ 269#define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024) 270#define SDHCI_DEFAULT_BOUNDARY_ARG (ilog2(SDHCI_DEFAULT_BOUNDARY_SIZE) - 12) 271 272/* ADMA2 32-bit DMA descriptor size */ 273#define SDHCI_ADMA2_32_DESC_SZ 8 274 275/* ADMA2 32-bit DMA alignment */ 276#define SDHCI_ADMA2_32_ALIGN 4 277 278/* ADMA2 32-bit descriptor */ 279struct sdhci_adma2_32_desc { 280 __le16 cmd; 281 __le16 len; 282 __le32 addr; 283} __packed __aligned(SDHCI_ADMA2_32_ALIGN); 284 285/* ADMA2 64-bit DMA descriptor size */ 286#define SDHCI_ADMA2_64_DESC_SZ 12 287 288/* ADMA2 64-bit DMA alignment */ 289#define SDHCI_ADMA2_64_ALIGN 8 290 291/* 292 * ADMA2 64-bit descriptor. Note 12-byte descriptor can't always be 8-byte 293 * aligned. 294 */ 295struct sdhci_adma2_64_desc { 296 __le16 cmd; 297 __le16 len; 298 __le32 addr_lo; 299 __le32 addr_hi; 300} __packed __aligned(4); 301 302#define ADMA2_TRAN_VALID 0x21 303#define ADMA2_NOP_END_VALID 0x3 304#define ADMA2_END 0x2 305 306/* 307 * Maximum segments assuming a 512KiB maximum requisition size and a minimum 308 * 4KiB page size. 309 */ 310#define SDHCI_MAX_SEGS 128 311 312enum sdhci_cookie { 313 COOKIE_UNMAPPED, 314 COOKIE_MAPPED, 315 COOKIE_GIVEN, 316}; 317 318struct sdhci_host { 319 /* Data set by hardware interface driver */ 320 const char *hw_name; /* Hardware bus name */ 321 322 unsigned int quirks; /* Deviations from spec. */ 323 324/* Controller doesn't honor resets unless we touch the clock register */ 325#define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0) 326/* Controller has bad caps bits, but really supports DMA */ 327#define SDHCI_QUIRK_FORCE_DMA (1<<1) 328/* Controller doesn't like to be reset when there is no card inserted. */ 329#define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2) 330/* Controller doesn't like clearing the power reg before a change */ 331#define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3) 332/* Controller has flaky internal state so reset it on each ios change */ 333#define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS (1<<4) 334/* Controller has an unusable DMA engine */ 335#define SDHCI_QUIRK_BROKEN_DMA (1<<5) 336/* Controller has an unusable ADMA engine */ 337#define SDHCI_QUIRK_BROKEN_ADMA (1<<6) 338/* Controller can only DMA from 32-bit aligned addresses */ 339#define SDHCI_QUIRK_32BIT_DMA_ADDR (1<<7) 340/* Controller can only DMA chunk sizes that are a multiple of 32 bits */ 341#define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<8) 342/* Controller can only ADMA chunks that are a multiple of 32 bits */ 343#define SDHCI_QUIRK_32BIT_ADMA_SIZE (1<<9) 344/* Controller needs to be reset after each request to stay stable */ 345#define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<10) 346/* Controller needs voltage and power writes to happen separately */ 347#define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1<<11) 348/* Controller provides an incorrect timeout value for transfers */ 349#define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1<<12) 350/* Controller has an issue with buffer bits for small transfers */ 351#define SDHCI_QUIRK_BROKEN_SMALL_PIO (1<<13) 352/* Controller does not provide transfer-complete interrupt when not busy */ 353#define SDHCI_QUIRK_NO_BUSY_IRQ (1<<14) 354/* Controller has unreliable card detection */ 355#define SDHCI_QUIRK_BROKEN_CARD_DETECTION (1<<15) 356/* Controller reports inverted write-protect state */ 357#define SDHCI_QUIRK_INVERTED_WRITE_PROTECT (1<<16) 358/* Controller does not like fast PIO transfers */ 359#define SDHCI_QUIRK_PIO_NEEDS_DELAY (1<<18) 360/* Controller has to be forced to use block size of 2048 bytes */ 361#define SDHCI_QUIRK_FORCE_BLK_SZ_2048 (1<<20) 362/* Controller cannot do multi-block transfers */ 363#define SDHCI_QUIRK_NO_MULTIBLOCK (1<<21) 364/* Controller can only handle 1-bit data transfers */ 365#define SDHCI_QUIRK_FORCE_1_BIT_DATA (1<<22) 366/* Controller needs 10ms delay between applying power and clock */ 367#define SDHCI_QUIRK_DELAY_AFTER_POWER (1<<23) 368/* Controller uses SDCLK instead of TMCLK for data timeouts */ 369#define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK (1<<24) 370/* Controller reports wrong base clock capability */ 371#define SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN (1<<25) 372/* Controller cannot support End Attribute in NOP ADMA descriptor */ 373#define SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC (1<<26) 374/* Controller is missing device caps. Use caps provided by host */ 375#define SDHCI_QUIRK_MISSING_CAPS (1<<27) 376/* Controller uses Auto CMD12 command to stop the transfer */ 377#define SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 (1<<28) 378/* Controller doesn't have HISPD bit field in HI-SPEED SD card */ 379#define SDHCI_QUIRK_NO_HISPD_BIT (1<<29) 380/* Controller treats ADMA descriptors with length 0000h incorrectly */ 381#define SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC (1<<30) 382/* The read-only detection via SDHCI_PRESENT_STATE register is unstable */ 383#define SDHCI_QUIRK_UNSTABLE_RO_DETECT (1<<31) 384 385 unsigned int quirks2; /* More deviations from spec. */ 386 387#define SDHCI_QUIRK2_HOST_OFF_CARD_ON (1<<0) 388#define SDHCI_QUIRK2_HOST_NO_CMD23 (1<<1) 389/* The system physically doesn't support 1.8v, even if the host does */ 390#define SDHCI_QUIRK2_NO_1_8_V (1<<2) 391#define SDHCI_QUIRK2_PRESET_VALUE_BROKEN (1<<3) 392#define SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON (1<<4) 393/* Controller has a non-standard host control register */ 394#define SDHCI_QUIRK2_BROKEN_HOST_CONTROL (1<<5) 395/* Controller does not support HS200 */ 396#define SDHCI_QUIRK2_BROKEN_HS200 (1<<6) 397/* Controller does not support DDR50 */ 398#define SDHCI_QUIRK2_BROKEN_DDR50 (1<<7) 399/* Stop command (CMD12) can set Transfer Complete when not using MMC_RSP_BUSY */ 400#define SDHCI_QUIRK2_STOP_WITH_TC (1<<8) 401/* Controller does not support 64-bit DMA */ 402#define SDHCI_QUIRK2_BROKEN_64_BIT_DMA (1<<9) 403/* need clear transfer mode register before send cmd */ 404#define SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD (1<<10) 405/* Capability register bit-63 indicates HS400 support */ 406#define SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 (1<<11) 407/* forced tuned clock */ 408#define SDHCI_QUIRK2_TUNING_WORK_AROUND (1<<12) 409/* disable the block count for single block transactions */ 410#define SDHCI_QUIRK2_SUPPORT_SINGLE (1<<13) 411/* Controller broken with using ACMD23 */ 412#define SDHCI_QUIRK2_ACMD23_BROKEN (1<<14) 413 414 int irq; /* Device IRQ */ 415 void __iomem *ioaddr; /* Mapped address */ 416 417 const struct sdhci_ops *ops; /* Low level hw interface */ 418 419 /* Internal data */ 420 struct mmc_host *mmc; /* MMC structure */ 421 u64 dma_mask; /* custom DMA mask */ 422 423#if defined(CONFIG_LEDS_CLASS) || defined(CONFIG_LEDS_CLASS_MODULE) 424 struct led_classdev led; /* LED control */ 425 char led_name[32]; 426#endif 427 428 spinlock_t lock; /* Mutex */ 429 430 int flags; /* Host attributes */ 431#define SDHCI_USE_SDMA (1<<0) /* Host is SDMA capable */ 432#define SDHCI_USE_ADMA (1<<1) /* Host is ADMA capable */ 433#define SDHCI_REQ_USE_DMA (1<<2) /* Use DMA for this req. */ 434#define SDHCI_DEVICE_DEAD (1<<3) /* Device unresponsive */ 435#define SDHCI_SDR50_NEEDS_TUNING (1<<4) /* SDR50 needs tuning */ 436#define SDHCI_NEEDS_RETUNING (1<<5) /* Host needs retuning */ 437#define SDHCI_AUTO_CMD12 (1<<6) /* Auto CMD12 support */ 438#define SDHCI_AUTO_CMD23 (1<<7) /* Auto CMD23 support */ 439#define SDHCI_PV_ENABLED (1<<8) /* Preset value enabled */ 440#define SDHCI_SDIO_IRQ_ENABLED (1<<9) /* SDIO irq enabled */ 441#define SDHCI_SDR104_NEEDS_TUNING (1<<10) /* SDR104/HS200 needs tuning */ 442#define SDHCI_USING_RETUNING_TIMER (1<<11) /* Host is using a retuning timer for the card */ 443#define SDHCI_USE_64_BIT_DMA (1<<12) /* Use 64-bit DMA */ 444#define SDHCI_HS400_TUNING (1<<13) /* Tuning for HS400 */ 445 446 unsigned int version; /* SDHCI spec. version */ 447 448 unsigned int max_clk; /* Max possible freq (MHz) */ 449 unsigned int timeout_clk; /* Timeout freq (KHz) */ 450 unsigned int clk_mul; /* Clock Muliplier value */ 451 452 unsigned int clock; /* Current clock (MHz) */ 453 u8 pwr; /* Current voltage */ 454 455 bool runtime_suspended; /* Host is runtime suspended */ 456 bool bus_on; /* Bus power prevents runtime suspend */ 457 bool preset_enabled; /* Preset is enabled */ 458 459 struct mmc_request *mrq; /* Current request */ 460 struct mmc_command *cmd; /* Current command */ 461 struct mmc_data *data; /* Current data request */ 462 unsigned int data_early:1; /* Data finished before cmd */ 463 unsigned int busy_handle:1; /* Handling the order of Busy-end */ 464 465 struct sg_mapping_iter sg_miter; /* SG state for PIO */ 466 unsigned int blocks; /* remaining PIO blocks */ 467 468 int sg_count; /* Mapped sg entries */ 469 470 void *adma_table; /* ADMA descriptor table */ 471 void *align_buffer; /* Bounce buffer */ 472 473 size_t adma_table_sz; /* ADMA descriptor table size */ 474 size_t align_buffer_sz; /* Bounce buffer size */ 475 476 dma_addr_t adma_addr; /* Mapped ADMA descr. table */ 477 dma_addr_t align_addr; /* Mapped bounce buffer */ 478 479 unsigned int desc_sz; /* ADMA descriptor size */ 480 unsigned int align_sz; /* ADMA alignment */ 481 unsigned int align_mask; /* ADMA alignment mask */ 482 483 struct tasklet_struct finish_tasklet; /* Tasklet structures */ 484 485 struct timer_list timer; /* Timer for timeouts */ 486 487 u32 caps; /* Alternative CAPABILITY_0 */ 488 u32 caps1; /* Alternative CAPABILITY_1 */ 489 490 unsigned int ocr_avail_sdio; /* OCR bit masks */ 491 unsigned int ocr_avail_sd; 492 unsigned int ocr_avail_mmc; 493 u32 ocr_mask; /* available voltages */ 494 495 unsigned timing; /* Current timing */ 496 497 u32 thread_isr; 498 499 /* cached registers */ 500 u32 ier; 501 502 wait_queue_head_t buf_ready_int; /* Waitqueue for Buffer Read Ready interrupt */ 503 unsigned int tuning_done; /* Condition flag set when CMD19 succeeds */ 504 505 unsigned int tuning_count; /* Timer count for re-tuning */ 506 unsigned int tuning_mode; /* Re-tuning mode supported by host */ 507#define SDHCI_TUNING_MODE_1 0 508 struct timer_list tuning_timer; /* Timer for tuning */ 509 510 unsigned long private[0] ____cacheline_aligned; 511}; 512 513struct sdhci_ops { 514#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS 515 u32 (*read_l)(struct sdhci_host *host, int reg); 516 u16 (*read_w)(struct sdhci_host *host, int reg); 517 u8 (*read_b)(struct sdhci_host *host, int reg); 518 void (*write_l)(struct sdhci_host *host, u32 val, int reg); 519 void (*write_w)(struct sdhci_host *host, u16 val, int reg); 520 void (*write_b)(struct sdhci_host *host, u8 val, int reg); 521#endif 522 523 void (*set_clock)(struct sdhci_host *host, unsigned int clock); 524 525 int (*enable_dma)(struct sdhci_host *host); 526 unsigned int (*get_max_clock)(struct sdhci_host *host); 527 unsigned int (*get_min_clock)(struct sdhci_host *host); 528 unsigned int (*get_timeout_clock)(struct sdhci_host *host); 529 unsigned int (*get_max_timeout_count)(struct sdhci_host *host); 530 void (*set_timeout)(struct sdhci_host *host, 531 struct mmc_command *cmd); 532 void (*set_bus_width)(struct sdhci_host *host, int width); 533 void (*platform_send_init_74_clocks)(struct sdhci_host *host, 534 u8 power_mode); 535 unsigned int (*get_ro)(struct sdhci_host *host); 536 void (*reset)(struct sdhci_host *host, u8 mask); 537 int (*platform_execute_tuning)(struct sdhci_host *host, u32 opcode); 538 void (*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs); 539 void (*hw_reset)(struct sdhci_host *host); 540 void (*adma_workaround)(struct sdhci_host *host, u32 intmask); 541 void (*platform_init)(struct sdhci_host *host); 542 void (*card_event)(struct sdhci_host *host); 543 void (*voltage_switch)(struct sdhci_host *host); 544}; 545 546#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS 547 548static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) 549{ 550 if (unlikely(host->ops->write_l)) 551 host->ops->write_l(host, val, reg); 552 else 553 writel(val, host->ioaddr + reg); 554} 555 556static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) 557{ 558 if (unlikely(host->ops->write_w)) 559 host->ops->write_w(host, val, reg); 560 else 561 writew(val, host->ioaddr + reg); 562} 563 564static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) 565{ 566 if (unlikely(host->ops->write_b)) 567 host->ops->write_b(host, val, reg); 568 else 569 writeb(val, host->ioaddr + reg); 570} 571 572static inline u32 sdhci_readl(struct sdhci_host *host, int reg) 573{ 574 if (unlikely(host->ops->read_l)) 575 return host->ops->read_l(host, reg); 576 else 577 return readl(host->ioaddr + reg); 578} 579 580static inline u16 sdhci_readw(struct sdhci_host *host, int reg) 581{ 582 if (unlikely(host->ops->read_w)) 583 return host->ops->read_w(host, reg); 584 else 585 return readw(host->ioaddr + reg); 586} 587 588static inline u8 sdhci_readb(struct sdhci_host *host, int reg) 589{ 590 if (unlikely(host->ops->read_b)) 591 return host->ops->read_b(host, reg); 592 else 593 return readb(host->ioaddr + reg); 594} 595 596#else 597 598static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) 599{ 600 writel(val, host->ioaddr + reg); 601} 602 603static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) 604{ 605 writew(val, host->ioaddr + reg); 606} 607 608static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) 609{ 610 writeb(val, host->ioaddr + reg); 611} 612 613static inline u32 sdhci_readl(struct sdhci_host *host, int reg) 614{ 615 return readl(host->ioaddr + reg); 616} 617 618static inline u16 sdhci_readw(struct sdhci_host *host, int reg) 619{ 620 return readw(host->ioaddr + reg); 621} 622 623static inline u8 sdhci_readb(struct sdhci_host *host, int reg) 624{ 625 return readb(host->ioaddr + reg); 626} 627 628#endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */ 629 630extern struct sdhci_host *sdhci_alloc_host(struct device *dev, 631 size_t priv_size); 632extern void sdhci_free_host(struct sdhci_host *host); 633 634static inline void *sdhci_priv(struct sdhci_host *host) 635{ 636 return (void *)host->private; 637} 638 639extern void sdhci_card_detect(struct sdhci_host *host); 640extern int sdhci_add_host(struct sdhci_host *host); 641extern void sdhci_remove_host(struct sdhci_host *host, int dead); 642extern void sdhci_send_command(struct sdhci_host *host, 643 struct mmc_command *cmd); 644 645static inline bool sdhci_sdio_irq_enabled(struct sdhci_host *host) 646{ 647 return !!(host->flags & SDHCI_SDIO_IRQ_ENABLED); 648} 649 650void sdhci_set_clock(struct sdhci_host *host, unsigned int clock); 651void sdhci_set_bus_width(struct sdhci_host *host, int width); 652void sdhci_reset(struct sdhci_host *host, u8 mask); 653void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing); 654 655#ifdef CONFIG_PM 656extern int sdhci_suspend_host(struct sdhci_host *host); 657extern int sdhci_resume_host(struct sdhci_host *host); 658extern void sdhci_enable_irq_wakeups(struct sdhci_host *host); 659extern int sdhci_runtime_suspend_host(struct sdhci_host *host); 660extern int sdhci_runtime_resume_host(struct sdhci_host *host); 661#endif 662 663#endif /* __SDHCI_HW_H */ 664