1/* 2 * Defines for the EMIF driver 3 * 4 * Copyright (C) 2012 Texas Instruments, Inc. 5 * 6 * Benoit Cousson (b-cousson@ti.com) 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12#ifndef __EMIF_H 13#define __EMIF_H 14 15/* 16 * Maximum number of different frequencies supported by EMIF driver 17 * Determines the number of entries in the pointer array for register 18 * cache 19 */ 20#define EMIF_MAX_NUM_FREQUENCIES 6 21 22/* State of the core voltage */ 23#define DDR_VOLTAGE_STABLE 0 24#define DDR_VOLTAGE_RAMPING 1 25 26/* Defines for timing De-rating */ 27#define EMIF_NORMAL_TIMINGS 0 28#define EMIF_DERATED_TIMINGS 1 29 30/* Length of the forced read idle period in terms of cycles */ 31#define EMIF_READ_IDLE_LEN_VAL 5 32 33/* 34 * forced read idle interval to be used when voltage 35 * is changed as part of DVFS/DPS - 1ms 36 */ 37#define READ_IDLE_INTERVAL_DVFS (1*1000000) 38 39/* 40 * Forced read idle interval to be used when voltage is stable 41 * 50us - or maximum value will do 42 */ 43#define READ_IDLE_INTERVAL_NORMAL (50*1000000) 44 45/* DLL calibration interval when voltage is NOT stable - 1us */ 46#define DLL_CALIB_INTERVAL_DVFS (1*1000000) 47 48#define DLL_CALIB_ACK_WAIT_VAL 5 49 50/* Interval between ZQCS commands - hw team recommended value */ 51#define EMIF_ZQCS_INTERVAL_US (50*1000) 52/* Enable ZQ Calibration on exiting Self-refresh */ 53#define ZQ_SFEXITEN_ENABLE 1 54/* 55 * ZQ Calibration simultaneously on both chip-selects: 56 * Needs one calibration resistor per CS 57 */ 58#define ZQ_DUALCALEN_DISABLE 0 59#define ZQ_DUALCALEN_ENABLE 1 60 61#define T_ZQCS_DEFAULT_NS 90 62#define T_ZQCL_DEFAULT_NS 360 63#define T_ZQINIT_DEFAULT_NS 1000 64 65/* DPD_EN */ 66#define DPD_DISABLE 0 67#define DPD_ENABLE 1 68 69/* 70 * Default values for the low-power entry to be used if not provided by user. 71 * OMAP4/5 has a hw bug(i735) due to which this value can not be less than 512 72 * Timeout values are in DDR clock 'cycles' and frequency threshold in Hz 73 */ 74#define EMIF_LP_MODE_TIMEOUT_PERFORMANCE 2048 75#define EMIF_LP_MODE_TIMEOUT_POWER 512 76#define EMIF_LP_MODE_FREQ_THRESHOLD 400000000 77 78/* DDR_PHY_CTRL_1 values for EMIF4D - ATTILA PHY combination */ 79#define EMIF_DDR_PHY_CTRL_1_BASE_VAL_ATTILAPHY 0x049FF000 80#define EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ_ATTILAPHY 0x41 81#define EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ_ATTILAPHY 0x80 82#define EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS_ATTILAPHY 0xFF 83 84/* DDR_PHY_CTRL_1 values for EMIF4D5 INTELLIPHY combination */ 85#define EMIF_DDR_PHY_CTRL_1_BASE_VAL_INTELLIPHY 0x0E084200 86#define EMIF_PHY_TOTAL_READ_LATENCY_INTELLIPHY_PS 10000 87 88/* TEMP_ALERT_CONFIG - corresponding to temp gradient 5 C/s */ 89#define TEMP_ALERT_POLL_INTERVAL_DEFAULT_MS 360 90 91#define EMIF_T_CSTA 3 92#define EMIF_T_PDLL_UL 128 93 94/* External PHY control registers magic values */ 95#define EMIF_EXT_PHY_CTRL_1_VAL 0x04020080 96#define EMIF_EXT_PHY_CTRL_5_VAL 0x04010040 97#define EMIF_EXT_PHY_CTRL_6_VAL 0x01004010 98#define EMIF_EXT_PHY_CTRL_7_VAL 0x00001004 99#define EMIF_EXT_PHY_CTRL_8_VAL 0x04010040 100#define EMIF_EXT_PHY_CTRL_9_VAL 0x01004010 101#define EMIF_EXT_PHY_CTRL_10_VAL 0x00001004 102#define EMIF_EXT_PHY_CTRL_11_VAL 0x00000000 103#define EMIF_EXT_PHY_CTRL_12_VAL 0x00000000 104#define EMIF_EXT_PHY_CTRL_13_VAL 0x00000000 105#define EMIF_EXT_PHY_CTRL_14_VAL 0x80080080 106#define EMIF_EXT_PHY_CTRL_15_VAL 0x00800800 107#define EMIF_EXT_PHY_CTRL_16_VAL 0x08102040 108#define EMIF_EXT_PHY_CTRL_17_VAL 0x00000001 109#define EMIF_EXT_PHY_CTRL_18_VAL 0x540A8150 110#define EMIF_EXT_PHY_CTRL_19_VAL 0xA81502A0 111#define EMIF_EXT_PHY_CTRL_20_VAL 0x002A0540 112#define EMIF_EXT_PHY_CTRL_21_VAL 0x00000000 113#define EMIF_EXT_PHY_CTRL_22_VAL 0x00000000 114#define EMIF_EXT_PHY_CTRL_23_VAL 0x00000000 115#define EMIF_EXT_PHY_CTRL_24_VAL 0x00000077 116 117#define EMIF_INTELLI_PHY_DQS_GATE_OPENING_DELAY_PS 1200 118 119/* Registers offset */ 120#define EMIF_MODULE_ID_AND_REVISION 0x0000 121#define EMIF_STATUS 0x0004 122#define EMIF_SDRAM_CONFIG 0x0008 123#define EMIF_SDRAM_CONFIG_2 0x000c 124#define EMIF_SDRAM_REFRESH_CONTROL 0x0010 125#define EMIF_SDRAM_REFRESH_CTRL_SHDW 0x0014 126#define EMIF_SDRAM_TIMING_1 0x0018 127#define EMIF_SDRAM_TIMING_1_SHDW 0x001c 128#define EMIF_SDRAM_TIMING_2 0x0020 129#define EMIF_SDRAM_TIMING_2_SHDW 0x0024 130#define EMIF_SDRAM_TIMING_3 0x0028 131#define EMIF_SDRAM_TIMING_3_SHDW 0x002c 132#define EMIF_LPDDR2_NVM_TIMING 0x0030 133#define EMIF_LPDDR2_NVM_TIMING_SHDW 0x0034 134#define EMIF_POWER_MANAGEMENT_CONTROL 0x0038 135#define EMIF_POWER_MANAGEMENT_CTRL_SHDW 0x003c 136#define EMIF_LPDDR2_MODE_REG_DATA 0x0040 137#define EMIF_LPDDR2_MODE_REG_CONFIG 0x0050 138#define EMIF_OCP_CONFIG 0x0054 139#define EMIF_OCP_CONFIG_VALUE_1 0x0058 140#define EMIF_OCP_CONFIG_VALUE_2 0x005c 141#define EMIF_IODFT_TEST_LOGIC_GLOBAL_CONTROL 0x0060 142#define EMIF_IODFT_TEST_LOGIC_CTRL_MISR_RESULT 0x0064 143#define EMIF_IODFT_TEST_LOGIC_ADDRESS_MISR_RESULT 0x0068 144#define EMIF_IODFT_TEST_LOGIC_DATA_MISR_RESULT_1 0x006c 145#define EMIF_IODFT_TEST_LOGIC_DATA_MISR_RESULT_2 0x0070 146#define EMIF_IODFT_TEST_LOGIC_DATA_MISR_RESULT_3 0x0074 147#define EMIF_PERFORMANCE_COUNTER_1 0x0080 148#define EMIF_PERFORMANCE_COUNTER_2 0x0084 149#define EMIF_PERFORMANCE_COUNTER_CONFIG 0x0088 150#define EMIF_PERFORMANCE_COUNTER_MASTER_REGION_SELECT 0x008c 151#define EMIF_PERFORMANCE_COUNTER_TIME 0x0090 152#define EMIF_MISC_REG 0x0094 153#define EMIF_DLL_CALIB_CTRL 0x0098 154#define EMIF_DLL_CALIB_CTRL_SHDW 0x009c 155#define EMIF_END_OF_INTERRUPT 0x00a0 156#define EMIF_SYSTEM_OCP_INTERRUPT_RAW_STATUS 0x00a4 157#define EMIF_LL_OCP_INTERRUPT_RAW_STATUS 0x00a8 158#define EMIF_SYSTEM_OCP_INTERRUPT_STATUS 0x00ac 159#define EMIF_LL_OCP_INTERRUPT_STATUS 0x00b0 160#define EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_SET 0x00b4 161#define EMIF_LL_OCP_INTERRUPT_ENABLE_SET 0x00b8 162#define EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_CLEAR 0x00bc 163#define EMIF_LL_OCP_INTERRUPT_ENABLE_CLEAR 0x00c0 164#define EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG 0x00c8 165#define EMIF_TEMPERATURE_ALERT_CONFIG 0x00cc 166#define EMIF_OCP_ERROR_LOG 0x00d0 167#define EMIF_READ_WRITE_LEVELING_RAMP_WINDOW 0x00d4 168#define EMIF_READ_WRITE_LEVELING_RAMP_CONTROL 0x00d8 169#define EMIF_READ_WRITE_LEVELING_CONTROL 0x00dc 170#define EMIF_DDR_PHY_CTRL_1 0x00e4 171#define EMIF_DDR_PHY_CTRL_1_SHDW 0x00e8 172#define EMIF_DDR_PHY_CTRL_2 0x00ec 173#define EMIF_PRIORITY_TO_CLASS_OF_SERVICE_MAPPING 0x0100 174#define EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_1_MAPPING 0x0104 175#define EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_2_MAPPING 0x0108 176#define EMIF_READ_WRITE_EXECUTION_THRESHOLD 0x0120 177#define EMIF_COS_CONFIG 0x0124 178#define EMIF_PHY_STATUS_1 0x0140 179#define EMIF_PHY_STATUS_2 0x0144 180#define EMIF_PHY_STATUS_3 0x0148 181#define EMIF_PHY_STATUS_4 0x014c 182#define EMIF_PHY_STATUS_5 0x0150 183#define EMIF_PHY_STATUS_6 0x0154 184#define EMIF_PHY_STATUS_7 0x0158 185#define EMIF_PHY_STATUS_8 0x015c 186#define EMIF_PHY_STATUS_9 0x0160 187#define EMIF_PHY_STATUS_10 0x0164 188#define EMIF_PHY_STATUS_11 0x0168 189#define EMIF_PHY_STATUS_12 0x016c 190#define EMIF_PHY_STATUS_13 0x0170 191#define EMIF_PHY_STATUS_14 0x0174 192#define EMIF_PHY_STATUS_15 0x0178 193#define EMIF_PHY_STATUS_16 0x017c 194#define EMIF_PHY_STATUS_17 0x0180 195#define EMIF_PHY_STATUS_18 0x0184 196#define EMIF_PHY_STATUS_19 0x0188 197#define EMIF_PHY_STATUS_20 0x018c 198#define EMIF_PHY_STATUS_21 0x0190 199#define EMIF_EXT_PHY_CTRL_1 0x0200 200#define EMIF_EXT_PHY_CTRL_1_SHDW 0x0204 201#define EMIF_EXT_PHY_CTRL_2 0x0208 202#define EMIF_EXT_PHY_CTRL_2_SHDW 0x020c 203#define EMIF_EXT_PHY_CTRL_3 0x0210 204#define EMIF_EXT_PHY_CTRL_3_SHDW 0x0214 205#define EMIF_EXT_PHY_CTRL_4 0x0218 206#define EMIF_EXT_PHY_CTRL_4_SHDW 0x021c 207#define EMIF_EXT_PHY_CTRL_5 0x0220 208#define EMIF_EXT_PHY_CTRL_5_SHDW 0x0224 209#define EMIF_EXT_PHY_CTRL_6 0x0228 210#define EMIF_EXT_PHY_CTRL_6_SHDW 0x022c 211#define EMIF_EXT_PHY_CTRL_7 0x0230 212#define EMIF_EXT_PHY_CTRL_7_SHDW 0x0234 213#define EMIF_EXT_PHY_CTRL_8 0x0238 214#define EMIF_EXT_PHY_CTRL_8_SHDW 0x023c 215#define EMIF_EXT_PHY_CTRL_9 0x0240 216#define EMIF_EXT_PHY_CTRL_9_SHDW 0x0244 217#define EMIF_EXT_PHY_CTRL_10 0x0248 218#define EMIF_EXT_PHY_CTRL_10_SHDW 0x024c 219#define EMIF_EXT_PHY_CTRL_11 0x0250 220#define EMIF_EXT_PHY_CTRL_11_SHDW 0x0254 221#define EMIF_EXT_PHY_CTRL_12 0x0258 222#define EMIF_EXT_PHY_CTRL_12_SHDW 0x025c 223#define EMIF_EXT_PHY_CTRL_13 0x0260 224#define EMIF_EXT_PHY_CTRL_13_SHDW 0x0264 225#define EMIF_EXT_PHY_CTRL_14 0x0268 226#define EMIF_EXT_PHY_CTRL_14_SHDW 0x026c 227#define EMIF_EXT_PHY_CTRL_15 0x0270 228#define EMIF_EXT_PHY_CTRL_15_SHDW 0x0274 229#define EMIF_EXT_PHY_CTRL_16 0x0278 230#define EMIF_EXT_PHY_CTRL_16_SHDW 0x027c 231#define EMIF_EXT_PHY_CTRL_17 0x0280 232#define EMIF_EXT_PHY_CTRL_17_SHDW 0x0284 233#define EMIF_EXT_PHY_CTRL_18 0x0288 234#define EMIF_EXT_PHY_CTRL_18_SHDW 0x028c 235#define EMIF_EXT_PHY_CTRL_19 0x0290 236#define EMIF_EXT_PHY_CTRL_19_SHDW 0x0294 237#define EMIF_EXT_PHY_CTRL_20 0x0298 238#define EMIF_EXT_PHY_CTRL_20_SHDW 0x029c 239#define EMIF_EXT_PHY_CTRL_21 0x02a0 240#define EMIF_EXT_PHY_CTRL_21_SHDW 0x02a4 241#define EMIF_EXT_PHY_CTRL_22 0x02a8 242#define EMIF_EXT_PHY_CTRL_22_SHDW 0x02ac 243#define EMIF_EXT_PHY_CTRL_23 0x02b0 244#define EMIF_EXT_PHY_CTRL_23_SHDW 0x02b4 245#define EMIF_EXT_PHY_CTRL_24 0x02b8 246#define EMIF_EXT_PHY_CTRL_24_SHDW 0x02bc 247#define EMIF_EXT_PHY_CTRL_25 0x02c0 248#define EMIF_EXT_PHY_CTRL_25_SHDW 0x02c4 249#define EMIF_EXT_PHY_CTRL_26 0x02c8 250#define EMIF_EXT_PHY_CTRL_26_SHDW 0x02cc 251#define EMIF_EXT_PHY_CTRL_27 0x02d0 252#define EMIF_EXT_PHY_CTRL_27_SHDW 0x02d4 253#define EMIF_EXT_PHY_CTRL_28 0x02d8 254#define EMIF_EXT_PHY_CTRL_28_SHDW 0x02dc 255#define EMIF_EXT_PHY_CTRL_29 0x02e0 256#define EMIF_EXT_PHY_CTRL_29_SHDW 0x02e4 257#define EMIF_EXT_PHY_CTRL_30 0x02e8 258#define EMIF_EXT_PHY_CTRL_30_SHDW 0x02ec 259 260/* Registers shifts and masks */ 261 262/* EMIF_MODULE_ID_AND_REVISION */ 263#define SCHEME_SHIFT 30 264#define SCHEME_MASK (0x3 << 30) 265#define MODULE_ID_SHIFT 16 266#define MODULE_ID_MASK (0xfff << 16) 267#define RTL_VERSION_SHIFT 11 268#define RTL_VERSION_MASK (0x1f << 11) 269#define MAJOR_REVISION_SHIFT 8 270#define MAJOR_REVISION_MASK (0x7 << 8) 271#define MINOR_REVISION_SHIFT 0 272#define MINOR_REVISION_MASK (0x3f << 0) 273 274/* STATUS */ 275#define BE_SHIFT 31 276#define BE_MASK (1 << 31) 277#define DUAL_CLK_MODE_SHIFT 30 278#define DUAL_CLK_MODE_MASK (1 << 30) 279#define FAST_INIT_SHIFT 29 280#define FAST_INIT_MASK (1 << 29) 281#define RDLVLGATETO_SHIFT 6 282#define RDLVLGATETO_MASK (1 << 6) 283#define RDLVLTO_SHIFT 5 284#define RDLVLTO_MASK (1 << 5) 285#define WRLVLTO_SHIFT 4 286#define WRLVLTO_MASK (1 << 4) 287#define PHY_DLL_READY_SHIFT 2 288#define PHY_DLL_READY_MASK (1 << 2) 289 290/* SDRAM_CONFIG */ 291#define SDRAM_TYPE_SHIFT 29 292#define SDRAM_TYPE_MASK (0x7 << 29) 293#define IBANK_POS_SHIFT 27 294#define IBANK_POS_MASK (0x3 << 27) 295#define DDR_TERM_SHIFT 24 296#define DDR_TERM_MASK (0x7 << 24) 297#define DDR2_DDQS_SHIFT 23 298#define DDR2_DDQS_MASK (1 << 23) 299#define DYN_ODT_SHIFT 21 300#define DYN_ODT_MASK (0x3 << 21) 301#define DDR_DISABLE_DLL_SHIFT 20 302#define DDR_DISABLE_DLL_MASK (1 << 20) 303#define SDRAM_DRIVE_SHIFT 18 304#define SDRAM_DRIVE_MASK (0x3 << 18) 305#define CWL_SHIFT 16 306#define CWL_MASK (0x3 << 16) 307#define NARROW_MODE_SHIFT 14 308#define NARROW_MODE_MASK (0x3 << 14) 309#define CL_SHIFT 10 310#define CL_MASK (0xf << 10) 311#define ROWSIZE_SHIFT 7 312#define ROWSIZE_MASK (0x7 << 7) 313#define IBANK_SHIFT 4 314#define IBANK_MASK (0x7 << 4) 315#define EBANK_SHIFT 3 316#define EBANK_MASK (1 << 3) 317#define PAGESIZE_SHIFT 0 318#define PAGESIZE_MASK (0x7 << 0) 319 320/* SDRAM_CONFIG_2 */ 321#define CS1NVMEN_SHIFT 30 322#define CS1NVMEN_MASK (1 << 30) 323#define EBANK_POS_SHIFT 27 324#define EBANK_POS_MASK (1 << 27) 325#define RDBNUM_SHIFT 4 326#define RDBNUM_MASK (0x3 << 4) 327#define RDBSIZE_SHIFT 0 328#define RDBSIZE_MASK (0x7 << 0) 329 330/* SDRAM_REFRESH_CONTROL */ 331#define INITREF_DIS_SHIFT 31 332#define INITREF_DIS_MASK (1 << 31) 333#define SRT_SHIFT 29 334#define SRT_MASK (1 << 29) 335#define ASR_SHIFT 28 336#define ASR_MASK (1 << 28) 337#define PASR_SHIFT 24 338#define PASR_MASK (0x7 << 24) 339#define REFRESH_RATE_SHIFT 0 340#define REFRESH_RATE_MASK (0xffff << 0) 341 342/* SDRAM_TIMING_1 */ 343#define T_RTW_SHIFT 29 344#define T_RTW_MASK (0x7 << 29) 345#define T_RP_SHIFT 25 346#define T_RP_MASK (0xf << 25) 347#define T_RCD_SHIFT 21 348#define T_RCD_MASK (0xf << 21) 349#define T_WR_SHIFT 17 350#define T_WR_MASK (0xf << 17) 351#define T_RAS_SHIFT 12 352#define T_RAS_MASK (0x1f << 12) 353#define T_RC_SHIFT 6 354#define T_RC_MASK (0x3f << 6) 355#define T_RRD_SHIFT 3 356#define T_RRD_MASK (0x7 << 3) 357#define T_WTR_SHIFT 0 358#define T_WTR_MASK (0x7 << 0) 359 360/* SDRAM_TIMING_2 */ 361#define T_XP_SHIFT 28 362#define T_XP_MASK (0x7 << 28) 363#define T_ODT_SHIFT 25 364#define T_ODT_MASK (0x7 << 25) 365#define T_XSNR_SHIFT 16 366#define T_XSNR_MASK (0x1ff << 16) 367#define T_XSRD_SHIFT 6 368#define T_XSRD_MASK (0x3ff << 6) 369#define T_RTP_SHIFT 3 370#define T_RTP_MASK (0x7 << 3) 371#define T_CKE_SHIFT 0 372#define T_CKE_MASK (0x7 << 0) 373 374/* SDRAM_TIMING_3 */ 375#define T_PDLL_UL_SHIFT 28 376#define T_PDLL_UL_MASK (0xf << 28) 377#define T_CSTA_SHIFT 24 378#define T_CSTA_MASK (0xf << 24) 379#define T_CKESR_SHIFT 21 380#define T_CKESR_MASK (0x7 << 21) 381#define ZQ_ZQCS_SHIFT 15 382#define ZQ_ZQCS_MASK (0x3f << 15) 383#define T_TDQSCKMAX_SHIFT 13 384#define T_TDQSCKMAX_MASK (0x3 << 13) 385#define T_RFC_SHIFT 4 386#define T_RFC_MASK (0x1ff << 4) 387#define T_RAS_MAX_SHIFT 0 388#define T_RAS_MAX_MASK (0xf << 0) 389 390/* POWER_MANAGEMENT_CONTROL */ 391#define PD_TIM_SHIFT 12 392#define PD_TIM_MASK (0xf << 12) 393#define DPD_EN_SHIFT 11 394#define DPD_EN_MASK (1 << 11) 395#define LP_MODE_SHIFT 8 396#define LP_MODE_MASK (0x7 << 8) 397#define SR_TIM_SHIFT 4 398#define SR_TIM_MASK (0xf << 4) 399#define CS_TIM_SHIFT 0 400#define CS_TIM_MASK (0xf << 0) 401 402/* LPDDR2_MODE_REG_DATA */ 403#define VALUE_0_SHIFT 0 404#define VALUE_0_MASK (0x7f << 0) 405 406/* LPDDR2_MODE_REG_CONFIG */ 407#define CS_SHIFT 31 408#define CS_MASK (1 << 31) 409#define REFRESH_EN_SHIFT 30 410#define REFRESH_EN_MASK (1 << 30) 411#define ADDRESS_SHIFT 0 412#define ADDRESS_MASK (0xff << 0) 413 414/* OCP_CONFIG */ 415#define SYS_THRESH_MAX_SHIFT 24 416#define SYS_THRESH_MAX_MASK (0xf << 24) 417#define MPU_THRESH_MAX_SHIFT 20 418#define MPU_THRESH_MAX_MASK (0xf << 20) 419#define LL_THRESH_MAX_SHIFT 16 420#define LL_THRESH_MAX_MASK (0xf << 16) 421 422/* PERFORMANCE_COUNTER_1 */ 423#define COUNTER1_SHIFT 0 424#define COUNTER1_MASK (0xffffffff << 0) 425 426/* PERFORMANCE_COUNTER_2 */ 427#define COUNTER2_SHIFT 0 428#define COUNTER2_MASK (0xffffffff << 0) 429 430/* PERFORMANCE_COUNTER_CONFIG */ 431#define CNTR2_MCONNID_EN_SHIFT 31 432#define CNTR2_MCONNID_EN_MASK (1 << 31) 433#define CNTR2_REGION_EN_SHIFT 30 434#define CNTR2_REGION_EN_MASK (1 << 30) 435#define CNTR2_CFG_SHIFT 16 436#define CNTR2_CFG_MASK (0xf << 16) 437#define CNTR1_MCONNID_EN_SHIFT 15 438#define CNTR1_MCONNID_EN_MASK (1 << 15) 439#define CNTR1_REGION_EN_SHIFT 14 440#define CNTR1_REGION_EN_MASK (1 << 14) 441#define CNTR1_CFG_SHIFT 0 442#define CNTR1_CFG_MASK (0xf << 0) 443 444/* PERFORMANCE_COUNTER_MASTER_REGION_SELECT */ 445#define MCONNID2_SHIFT 24 446#define MCONNID2_MASK (0xff << 24) 447#define REGION_SEL2_SHIFT 16 448#define REGION_SEL2_MASK (0x3 << 16) 449#define MCONNID1_SHIFT 8 450#define MCONNID1_MASK (0xff << 8) 451#define REGION_SEL1_SHIFT 0 452#define REGION_SEL1_MASK (0x3 << 0) 453 454/* PERFORMANCE_COUNTER_TIME */ 455#define TOTAL_TIME_SHIFT 0 456#define TOTAL_TIME_MASK (0xffffffff << 0) 457 458/* DLL_CALIB_CTRL */ 459#define ACK_WAIT_SHIFT 16 460#define ACK_WAIT_MASK (0xf << 16) 461#define DLL_CALIB_INTERVAL_SHIFT 0 462#define DLL_CALIB_INTERVAL_MASK (0x1ff << 0) 463 464/* END_OF_INTERRUPT */ 465#define EOI_SHIFT 0 466#define EOI_MASK (1 << 0) 467 468/* SYSTEM_OCP_INTERRUPT_RAW_STATUS */ 469#define DNV_SYS_SHIFT 2 470#define DNV_SYS_MASK (1 << 2) 471#define TA_SYS_SHIFT 1 472#define TA_SYS_MASK (1 << 1) 473#define ERR_SYS_SHIFT 0 474#define ERR_SYS_MASK (1 << 0) 475 476/* LOW_LATENCY_OCP_INTERRUPT_RAW_STATUS */ 477#define DNV_LL_SHIFT 2 478#define DNV_LL_MASK (1 << 2) 479#define TA_LL_SHIFT 1 480#define TA_LL_MASK (1 << 1) 481#define ERR_LL_SHIFT 0 482#define ERR_LL_MASK (1 << 0) 483 484/* SYSTEM_OCP_INTERRUPT_ENABLE_SET */ 485#define EN_DNV_SYS_SHIFT 2 486#define EN_DNV_SYS_MASK (1 << 2) 487#define EN_TA_SYS_SHIFT 1 488#define EN_TA_SYS_MASK (1 << 1) 489#define EN_ERR_SYS_SHIFT 0 490#define EN_ERR_SYS_MASK (1 << 0) 491 492/* LOW_LATENCY_OCP_INTERRUPT_ENABLE_SET */ 493#define EN_DNV_LL_SHIFT 2 494#define EN_DNV_LL_MASK (1 << 2) 495#define EN_TA_LL_SHIFT 1 496#define EN_TA_LL_MASK (1 << 1) 497#define EN_ERR_LL_SHIFT 0 498#define EN_ERR_LL_MASK (1 << 0) 499 500/* SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG */ 501#define ZQ_CS1EN_SHIFT 31 502#define ZQ_CS1EN_MASK (1 << 31) 503#define ZQ_CS0EN_SHIFT 30 504#define ZQ_CS0EN_MASK (1 << 30) 505#define ZQ_DUALCALEN_SHIFT 29 506#define ZQ_DUALCALEN_MASK (1 << 29) 507#define ZQ_SFEXITEN_SHIFT 28 508#define ZQ_SFEXITEN_MASK (1 << 28) 509#define ZQ_ZQINIT_MULT_SHIFT 18 510#define ZQ_ZQINIT_MULT_MASK (0x3 << 18) 511#define ZQ_ZQCL_MULT_SHIFT 16 512#define ZQ_ZQCL_MULT_MASK (0x3 << 16) 513#define ZQ_REFINTERVAL_SHIFT 0 514#define ZQ_REFINTERVAL_MASK (0xffff << 0) 515 516/* TEMPERATURE_ALERT_CONFIG */ 517#define TA_CS1EN_SHIFT 31 518#define TA_CS1EN_MASK (1 << 31) 519#define TA_CS0EN_SHIFT 30 520#define TA_CS0EN_MASK (1 << 30) 521#define TA_SFEXITEN_SHIFT 28 522#define TA_SFEXITEN_MASK (1 << 28) 523#define TA_DEVWDT_SHIFT 26 524#define TA_DEVWDT_MASK (0x3 << 26) 525#define TA_DEVCNT_SHIFT 24 526#define TA_DEVCNT_MASK (0x3 << 24) 527#define TA_REFINTERVAL_SHIFT 0 528#define TA_REFINTERVAL_MASK (0x3fffff << 0) 529 530/* OCP_ERROR_LOG */ 531#define MADDRSPACE_SHIFT 14 532#define MADDRSPACE_MASK (0x3 << 14) 533#define MBURSTSEQ_SHIFT 11 534#define MBURSTSEQ_MASK (0x7 << 11) 535#define MCMD_SHIFT 8 536#define MCMD_MASK (0x7 << 8) 537#define MCONNID_SHIFT 0 538#define MCONNID_MASK (0xff << 0) 539 540/* DDR_PHY_CTRL_1 - EMIF4D */ 541#define DLL_SLAVE_DLY_CTRL_SHIFT_4D 4 542#define DLL_SLAVE_DLY_CTRL_MASK_4D (0xFF << 4) 543#define READ_LATENCY_SHIFT_4D 0 544#define READ_LATENCY_MASK_4D (0xf << 0) 545 546/* DDR_PHY_CTRL_1 - EMIF4D5 */ 547#define DLL_HALF_DELAY_SHIFT_4D5 21 548#define DLL_HALF_DELAY_MASK_4D5 (1 << 21) 549#define READ_LATENCY_SHIFT_4D5 0 550#define READ_LATENCY_MASK_4D5 (0x1f << 0) 551 552/* DDR_PHY_CTRL_1_SHDW */ 553#define DDR_PHY_CTRL_1_SHDW_SHIFT 5 554#define DDR_PHY_CTRL_1_SHDW_MASK (0x7ffffff << 5) 555#define READ_LATENCY_SHDW_SHIFT 0 556#define READ_LATENCY_SHDW_MASK (0x1f << 0) 557 558#ifndef __ASSEMBLY__ 559/* 560 * Structure containing shadow of important registers in EMIF 561 * The calculation function fills in this structure to be later used for 562 * initialisation and DVFS 563 */ 564struct emif_regs { 565 u32 freq; 566 u32 ref_ctrl_shdw; 567 u32 ref_ctrl_shdw_derated; 568 u32 sdram_tim1_shdw; 569 u32 sdram_tim1_shdw_derated; 570 u32 sdram_tim2_shdw; 571 u32 sdram_tim3_shdw; 572 u32 sdram_tim3_shdw_derated; 573 u32 pwr_mgmt_ctrl_shdw; 574 union { 575 u32 read_idle_ctrl_shdw_normal; 576 u32 dll_calib_ctrl_shdw_normal; 577 }; 578 union { 579 u32 read_idle_ctrl_shdw_volt_ramp; 580 u32 dll_calib_ctrl_shdw_volt_ramp; 581 }; 582 583 u32 phy_ctrl_1_shdw; 584 u32 ext_phy_ctrl_2_shdw; 585 u32 ext_phy_ctrl_3_shdw; 586 u32 ext_phy_ctrl_4_shdw; 587}; 588#endif /* __ASSEMBLY__ */ 589#endif /* __EMIF_H */ 590