1/* 2 * Realtek RTL28xxU DVB USB driver 3 * 4 * Copyright (C) 2009 Antti Palosaari <crope@iki.fi> 5 * Copyright (C) 2011 Antti Palosaari <crope@iki.fi> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, write to the Free Software Foundation, Inc., 19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 20 */ 21 22#ifndef RTL28XXU_H 23#define RTL28XXU_H 24 25#include <linux/platform_device.h> 26 27#include "dvb_usb.h" 28 29#include "rtl2830.h" 30#include "rtl2832.h" 31#include "rtl2832_sdr.h" 32#include "mn88472.h" 33#include "mn88473.h" 34 35#include "qt1010.h" 36#include "mt2060.h" 37#include "mxl5005s.h" 38#include "fc0012.h" 39#include "fc0013.h" 40#include "e4000.h" 41#include "fc2580.h" 42#include "tua9001.h" 43#include "r820t.h" 44 45/* 46 * USB commands 47 * (usb_control_msg() index parameter) 48 */ 49 50#define DEMOD 0x0000 51#define USB 0x0100 52#define SYS 0x0200 53#define I2C 0x0300 54#define I2C_DA 0x0600 55 56#define CMD_WR_FLAG 0x0010 57#define CMD_DEMOD_RD 0x0000 58#define CMD_DEMOD_WR 0x0010 59#define CMD_USB_RD 0x0100 60#define CMD_USB_WR 0x0110 61#define CMD_SYS_RD 0x0200 62#define CMD_IR_RD 0x0201 63#define CMD_IR_WR 0x0211 64#define CMD_SYS_WR 0x0210 65#define CMD_I2C_RD 0x0300 66#define CMD_I2C_WR 0x0310 67#define CMD_I2C_DA_RD 0x0600 68#define CMD_I2C_DA_WR 0x0610 69 70 71struct rtl28xxu_dev { 72 u8 buf[128]; 73 u8 chip_id; 74 u8 tuner; 75 char *tuner_name; 76 u8 page; /* integrated demod active register page */ 77 struct i2c_adapter *demod_i2c_adapter; 78 bool rc_active; 79 struct i2c_client *i2c_client_demod; 80 struct i2c_client *i2c_client_tuner; 81 struct i2c_client *i2c_client_slave_demod; 82 struct platform_device *platform_device_sdr; 83 #define SLAVE_DEMOD_NONE 0 84 #define SLAVE_DEMOD_MN88472 1 85 #define SLAVE_DEMOD_MN88473 2 86 unsigned int slave_demod:2; 87 union { 88 struct rtl2830_platform_data rtl2830_platform_data; 89 struct rtl2832_platform_data rtl2832_platform_data; 90 }; 91}; 92 93enum rtl28xxu_chip_id { 94 CHIP_ID_NONE, 95 CHIP_ID_RTL2831U, 96 CHIP_ID_RTL2832U, 97}; 98 99/* XXX: Hack. This must be keep sync with rtl2832 demod driver. */ 100enum rtl28xxu_tuner { 101 TUNER_NONE, 102 103 TUNER_RTL2830_QT1010 = 0x10, 104 TUNER_RTL2830_MT2060, 105 TUNER_RTL2830_MXL5005S, 106 107 TUNER_RTL2832_MT2266 = 0x20, 108 TUNER_RTL2832_FC2580, 109 TUNER_RTL2832_MT2063, 110 TUNER_RTL2832_MAX3543, 111 TUNER_RTL2832_TUA9001, 112 TUNER_RTL2832_MXL5007T, 113 TUNER_RTL2832_FC0012, 114 TUNER_RTL2832_E4000, 115 TUNER_RTL2832_TDA18272, 116 TUNER_RTL2832_FC0013, 117 TUNER_RTL2832_R820T, 118 TUNER_RTL2832_R828D, 119}; 120 121struct rtl28xxu_req { 122 u16 value; 123 u16 index; 124 u16 size; 125 u8 *data; 126}; 127 128struct rtl28xxu_reg_val { 129 u16 reg; 130 u8 val; 131}; 132 133struct rtl28xxu_reg_val_mask { 134 u16 reg; 135 u8 val; 136 u8 mask; 137}; 138 139/* 140 * memory map 141 * 142 * 0x0000 DEMOD : demodulator 143 * 0x2000 USB : SIE, USB endpoint, debug, DMA 144 * 0x3000 SYS : system 145 * 0xfc00 RC : remote controller (not RTL2831U) 146 */ 147 148/* 149 * USB registers 150 */ 151/* SIE Control Registers */ 152#define USB_SYSCTL 0x2000 /* USB system control */ 153#define USB_SYSCTL_0 0x2000 /* USB system control */ 154#define USB_SYSCTL_1 0x2001 /* USB system control */ 155#define USB_SYSCTL_2 0x2002 /* USB system control */ 156#define USB_SYSCTL_3 0x2003 /* USB system control */ 157#define USB_IRQSTAT 0x2008 /* SIE interrupt status */ 158#define USB_IRQEN 0x200C /* SIE interrupt enable */ 159#define USB_CTRL 0x2010 /* USB control */ 160#define USB_STAT 0x2014 /* USB status */ 161#define USB_DEVADDR 0x2018 /* USB device address */ 162#define USB_TEST 0x201C /* USB test mode */ 163#define USB_FRAME_NUMBER 0x2020 /* frame number */ 164#define USB_FIFO_ADDR 0x2028 /* address of SIE FIFO RAM */ 165#define USB_FIFO_CMD 0x202A /* SIE FIFO RAM access command */ 166#define USB_FIFO_DATA 0x2030 /* SIE FIFO RAM data */ 167/* Endpoint Registers */ 168#define EP0_SETUPA 0x20F8 /* EP 0 setup packet lower byte */ 169#define EP0_SETUPB 0x20FC /* EP 0 setup packet higher byte */ 170#define USB_EP0_CFG 0x2104 /* EP 0 configure */ 171#define USB_EP0_CTL 0x2108 /* EP 0 control */ 172#define USB_EP0_STAT 0x210C /* EP 0 status */ 173#define USB_EP0_IRQSTAT 0x2110 /* EP 0 interrupt status */ 174#define USB_EP0_IRQEN 0x2114 /* EP 0 interrupt enable */ 175#define USB_EP0_MAXPKT 0x2118 /* EP 0 max packet size */ 176#define USB_EP0_BC 0x2120 /* EP 0 FIFO byte counter */ 177#define USB_EPA_CFG 0x2144 /* EP A configure */ 178#define USB_EPA_CFG_0 0x2144 /* EP A configure */ 179#define USB_EPA_CFG_1 0x2145 /* EP A configure */ 180#define USB_EPA_CFG_2 0x2146 /* EP A configure */ 181#define USB_EPA_CFG_3 0x2147 /* EP A configure */ 182#define USB_EPA_CTL 0x2148 /* EP A control */ 183#define USB_EPA_CTL_0 0x2148 /* EP A control */ 184#define USB_EPA_CTL_1 0x2149 /* EP A control */ 185#define USB_EPA_CTL_2 0x214A /* EP A control */ 186#define USB_EPA_CTL_3 0x214B /* EP A control */ 187#define USB_EPA_STAT 0x214C /* EP A status */ 188#define USB_EPA_IRQSTAT 0x2150 /* EP A interrupt status */ 189#define USB_EPA_IRQEN 0x2154 /* EP A interrupt enable */ 190#define USB_EPA_MAXPKT 0x2158 /* EP A max packet size */ 191#define USB_EPA_MAXPKT_0 0x2158 /* EP A max packet size */ 192#define USB_EPA_MAXPKT_1 0x2159 /* EP A max packet size */ 193#define USB_EPA_MAXPKT_2 0x215A /* EP A max packet size */ 194#define USB_EPA_MAXPKT_3 0x215B /* EP A max packet size */ 195#define USB_EPA_FIFO_CFG 0x2160 /* EP A FIFO configure */ 196#define USB_EPA_FIFO_CFG_0 0x2160 /* EP A FIFO configure */ 197#define USB_EPA_FIFO_CFG_1 0x2161 /* EP A FIFO configure */ 198#define USB_EPA_FIFO_CFG_2 0x2162 /* EP A FIFO configure */ 199#define USB_EPA_FIFO_CFG_3 0x2163 /* EP A FIFO configure */ 200/* Debug Registers */ 201#define USB_PHYTSTDIS 0x2F04 /* PHY test disable */ 202#define USB_TOUT_VAL 0x2F08 /* USB time-out time */ 203#define USB_VDRCTRL 0x2F10 /* UTMI vendor signal control */ 204#define USB_VSTAIN 0x2F14 /* UTMI vendor signal status in */ 205#define USB_VLOADM 0x2F18 /* UTMI load vendor signal status in */ 206#define USB_VSTAOUT 0x2F1C /* UTMI vendor signal status out */ 207#define USB_UTMI_TST 0x2F80 /* UTMI test */ 208#define USB_UTMI_STATUS 0x2F84 /* UTMI status */ 209#define USB_TSTCTL 0x2F88 /* test control */ 210#define USB_TSTCTL2 0x2F8C /* test control 2 */ 211#define USB_PID_FORCE 0x2F90 /* force PID */ 212#define USB_PKTERR_CNT 0x2F94 /* packet error counter */ 213#define USB_RXERR_CNT 0x2F98 /* RX error counter */ 214#define USB_MEM_BIST 0x2F9C /* MEM BIST test */ 215#define USB_SLBBIST 0x2FA0 /* self-loop-back BIST */ 216#define USB_CNTTEST 0x2FA4 /* counter test */ 217#define USB_PHYTST 0x2FC0 /* USB PHY test */ 218#define USB_DBGIDX 0x2FF0 /* select individual block debug signal */ 219#define USB_DBGMUX 0x2FF4 /* debug signal module mux */ 220 221/* 222 * SYS registers 223 */ 224/* demod control registers */ 225#define SYS_SYS0 0x3000 /* include DEMOD_CTL, GPO, GPI, GPOE */ 226#define SYS_DEMOD_CTL 0x3000 /* control register for DVB-T demodulator */ 227/* GPIO registers */ 228#define SYS_GPIO_OUT_VAL 0x3001 /* output value of GPIO */ 229#define SYS_GPIO_IN_VAL 0x3002 /* input value of GPIO */ 230#define SYS_GPIO_OUT_EN 0x3003 /* output enable of GPIO */ 231#define SYS_SYS1 0x3004 /* include GPD, SYSINTE, SYSINTS, GP_CFG0 */ 232#define SYS_GPIO_DIR 0x3004 /* direction control for GPIO */ 233#define SYS_SYSINTE 0x3005 /* system interrupt enable */ 234#define SYS_SYSINTS 0x3006 /* system interrupt status */ 235#define SYS_GPIO_CFG0 0x3007 /* PAD configuration for GPIO0-GPIO3 */ 236#define SYS_SYS2 0x3008 /* include GP_CFG1 and 3 reserved bytes */ 237#define SYS_GPIO_CFG1 0x3008 /* PAD configuration for GPIO4 */ 238#define SYS_DEMOD_CTL1 0x300B 239 240/* IrDA registers */ 241#define SYS_IRRC_PSR 0x3020 /* IR protocol selection */ 242#define SYS_IRRC_PER 0x3024 /* IR protocol extension */ 243#define SYS_IRRC_SF 0x3028 /* IR sampling frequency */ 244#define SYS_IRRC_DPIR 0x302C /* IR data package interval */ 245#define SYS_IRRC_CR 0x3030 /* IR control */ 246#define SYS_IRRC_RP 0x3034 /* IR read port */ 247#define SYS_IRRC_SR 0x3038 /* IR status */ 248/* I2C master registers */ 249#define SYS_I2CCR 0x3040 /* I2C clock */ 250#define SYS_I2CMCR 0x3044 /* I2C master control */ 251#define SYS_I2CMSTR 0x3048 /* I2C master SCL timing */ 252#define SYS_I2CMSR 0x304C /* I2C master status */ 253#define SYS_I2CMFR 0x3050 /* I2C master FIFO */ 254 255/* 256 * IR registers 257 */ 258#define IR_RX_BUF 0xFC00 259#define IR_RX_IE 0xFD00 260#define IR_RX_IF 0xFD01 261#define IR_RX_CTRL 0xFD02 262#define IR_RX_CFG 0xFD03 263#define IR_MAX_DURATION0 0xFD04 264#define IR_MAX_DURATION1 0xFD05 265#define IR_IDLE_LEN0 0xFD06 266#define IR_IDLE_LEN1 0xFD07 267#define IR_GLITCH_LEN 0xFD08 268#define IR_RX_BUF_CTRL 0xFD09 269#define IR_RX_BUF_DATA 0xFD0A 270#define IR_RX_BC 0xFD0B 271#define IR_RX_CLK 0xFD0C 272#define IR_RX_C_COUNT_L 0xFD0D 273#define IR_RX_C_COUNT_H 0xFD0E 274#define IR_SUSPEND_CTRL 0xFD10 275#define IR_ERR_TOL_CTRL 0xFD11 276#define IR_UNIT_LEN 0xFD12 277#define IR_ERR_TOL_LEN 0xFD13 278#define IR_MAX_H_TOL_LEN 0xFD14 279#define IR_MAX_L_TOL_LEN 0xFD15 280#define IR_MASK_CTRL 0xFD16 281#define IR_MASK_DATA 0xFD17 282#define IR_RES_MASK_ADDR 0xFD18 283#define IR_RES_MASK_T_LEN 0xFD19 284 285#endif 286