1/* 2 * Driver for the Conexant CX23885 PCIe bridge 3 * 4 * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * 15 * GNU General Public License for more details. 16 */ 17 18#include <linux/init.h> 19#include <linux/module.h> 20#include <linux/pci.h> 21#include <linux/delay.h> 22#include <media/cx25840.h> 23#include <linux/firmware.h> 24#include <misc/altera.h> 25 26#include "cx23885.h" 27#include "tuner-xc2028.h" 28#include "netup-eeprom.h" 29#include "netup-init.h" 30#include "altera-ci.h" 31#include "xc4000.h" 32#include "xc5000.h" 33#include "cx23888-ir.h" 34 35static unsigned int netup_card_rev = 4; 36module_param(netup_card_rev, int, 0644); 37MODULE_PARM_DESC(netup_card_rev, 38 "NetUP Dual DVB-T/C CI card revision"); 39static unsigned int enable_885_ir; 40module_param(enable_885_ir, int, 0644); 41MODULE_PARM_DESC(enable_885_ir, 42 "Enable integrated IR controller for supported\n" 43 "\t\t CX2388[57] boards that are wired for it:\n" 44 "\t\t\tHVR-1250 (reported safe)\n" 45 "\t\t\tTerraTec Cinergy T PCIe Dual (not well tested, appears to be safe)\n" 46 "\t\t\tTeVii S470 (reported unsafe)\n" 47 "\t\t This can cause an interrupt storm with some cards.\n" 48 "\t\t Default: 0 [Disabled]"); 49 50/* ------------------------------------------------------------------ */ 51/* board config info */ 52 53struct cx23885_board cx23885_boards[] = { 54 [CX23885_BOARD_UNKNOWN] = { 55 .name = "UNKNOWN/GENERIC", 56 /* Ensure safe default for unknown boards */ 57 .clk_freq = 0, 58 .input = {{ 59 .type = CX23885_VMUX_COMPOSITE1, 60 .vmux = 0, 61 }, { 62 .type = CX23885_VMUX_COMPOSITE2, 63 .vmux = 1, 64 }, { 65 .type = CX23885_VMUX_COMPOSITE3, 66 .vmux = 2, 67 }, { 68 .type = CX23885_VMUX_COMPOSITE4, 69 .vmux = 3, 70 } }, 71 }, 72 [CX23885_BOARD_HAUPPAUGE_HVR1800lp] = { 73 .name = "Hauppauge WinTV-HVR1800lp", 74 .portc = CX23885_MPEG_DVB, 75 .input = {{ 76 .type = CX23885_VMUX_TELEVISION, 77 .vmux = 0, 78 .gpio0 = 0xff00, 79 }, { 80 .type = CX23885_VMUX_DEBUG, 81 .vmux = 0, 82 .gpio0 = 0xff01, 83 }, { 84 .type = CX23885_VMUX_COMPOSITE1, 85 .vmux = 1, 86 .gpio0 = 0xff02, 87 }, { 88 .type = CX23885_VMUX_SVIDEO, 89 .vmux = 2, 90 .gpio0 = 0xff02, 91 } }, 92 }, 93 [CX23885_BOARD_HAUPPAUGE_HVR1800] = { 94 .name = "Hauppauge WinTV-HVR1800", 95 .porta = CX23885_ANALOG_VIDEO, 96 .portb = CX23885_MPEG_ENCODER, 97 .portc = CX23885_MPEG_DVB, 98 .tuner_type = TUNER_PHILIPS_TDA8290, 99 .tuner_addr = 0x42, /* 0x84 >> 1 */ 100 .tuner_bus = 1, 101 .input = {{ 102 .type = CX23885_VMUX_TELEVISION, 103 .vmux = CX25840_VIN7_CH3 | 104 CX25840_VIN5_CH2 | 105 CX25840_VIN2_CH1, 106 .amux = CX25840_AUDIO8, 107 .gpio0 = 0, 108 }, { 109 .type = CX23885_VMUX_COMPOSITE1, 110 .vmux = CX25840_VIN7_CH3 | 111 CX25840_VIN4_CH2 | 112 CX25840_VIN6_CH1, 113 .amux = CX25840_AUDIO7, 114 .gpio0 = 0, 115 }, { 116 .type = CX23885_VMUX_SVIDEO, 117 .vmux = CX25840_VIN7_CH3 | 118 CX25840_VIN4_CH2 | 119 CX25840_VIN8_CH1 | 120 CX25840_SVIDEO_ON, 121 .amux = CX25840_AUDIO7, 122 .gpio0 = 0, 123 } }, 124 }, 125 [CX23885_BOARD_HAUPPAUGE_HVR1250] = { 126 .name = "Hauppauge WinTV-HVR1250", 127 .porta = CX23885_ANALOG_VIDEO, 128 .portc = CX23885_MPEG_DVB, 129#ifdef MT2131_NO_ANALOG_SUPPORT_YET 130 .tuner_type = TUNER_PHILIPS_TDA8290, 131 .tuner_addr = 0x42, /* 0x84 >> 1 */ 132 .tuner_bus = 1, 133#endif 134 .force_bff = 1, 135 .input = {{ 136#ifdef MT2131_NO_ANALOG_SUPPORT_YET 137 .type = CX23885_VMUX_TELEVISION, 138 .vmux = CX25840_VIN7_CH3 | 139 CX25840_VIN5_CH2 | 140 CX25840_VIN2_CH1, 141 .amux = CX25840_AUDIO8, 142 .gpio0 = 0xff00, 143 }, { 144#endif 145 .type = CX23885_VMUX_COMPOSITE1, 146 .vmux = CX25840_VIN7_CH3 | 147 CX25840_VIN4_CH2 | 148 CX25840_VIN6_CH1, 149 .amux = CX25840_AUDIO7, 150 .gpio0 = 0xff02, 151 }, { 152 .type = CX23885_VMUX_SVIDEO, 153 .vmux = CX25840_VIN7_CH3 | 154 CX25840_VIN4_CH2 | 155 CX25840_VIN8_CH1 | 156 CX25840_SVIDEO_ON, 157 .amux = CX25840_AUDIO7, 158 .gpio0 = 0xff02, 159 } }, 160 }, 161 [CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP] = { 162 .name = "DViCO FusionHDTV5 Express", 163 .portb = CX23885_MPEG_DVB, 164 }, 165 [CX23885_BOARD_HAUPPAUGE_HVR1500Q] = { 166 .name = "Hauppauge WinTV-HVR1500Q", 167 .portc = CX23885_MPEG_DVB, 168 }, 169 [CX23885_BOARD_HAUPPAUGE_HVR1500] = { 170 .name = "Hauppauge WinTV-HVR1500", 171 .porta = CX23885_ANALOG_VIDEO, 172 .portc = CX23885_MPEG_DVB, 173 .tuner_type = TUNER_XC2028, 174 .tuner_addr = 0x61, /* 0xc2 >> 1 */ 175 .input = {{ 176 .type = CX23885_VMUX_TELEVISION, 177 .vmux = CX25840_VIN7_CH3 | 178 CX25840_VIN5_CH2 | 179 CX25840_VIN2_CH1, 180 .gpio0 = 0, 181 }, { 182 .type = CX23885_VMUX_COMPOSITE1, 183 .vmux = CX25840_VIN7_CH3 | 184 CX25840_VIN4_CH2 | 185 CX25840_VIN6_CH1, 186 .gpio0 = 0, 187 }, { 188 .type = CX23885_VMUX_SVIDEO, 189 .vmux = CX25840_VIN7_CH3 | 190 CX25840_VIN4_CH2 | 191 CX25840_VIN8_CH1 | 192 CX25840_SVIDEO_ON, 193 .gpio0 = 0, 194 } }, 195 }, 196 [CX23885_BOARD_HAUPPAUGE_HVR1200] = { 197 .name = "Hauppauge WinTV-HVR1200", 198 .portc = CX23885_MPEG_DVB, 199 }, 200 [CX23885_BOARD_HAUPPAUGE_HVR1700] = { 201 .name = "Hauppauge WinTV-HVR1700", 202 .portc = CX23885_MPEG_DVB, 203 }, 204 [CX23885_BOARD_HAUPPAUGE_HVR1400] = { 205 .name = "Hauppauge WinTV-HVR1400", 206 .portc = CX23885_MPEG_DVB, 207 }, 208 [CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP] = { 209 .name = "DViCO FusionHDTV7 Dual Express", 210 .portb = CX23885_MPEG_DVB, 211 .portc = CX23885_MPEG_DVB, 212 }, 213 [CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP] = { 214 .name = "DViCO FusionHDTV DVB-T Dual Express", 215 .portb = CX23885_MPEG_DVB, 216 .portc = CX23885_MPEG_DVB, 217 }, 218 [CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H] = { 219 .name = "Leadtek Winfast PxDVR3200 H", 220 .portc = CX23885_MPEG_DVB, 221 }, 222 [CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200] = { 223 .name = "Leadtek Winfast PxPVR2200", 224 .porta = CX23885_ANALOG_VIDEO, 225 .tuner_type = TUNER_XC2028, 226 .tuner_addr = 0x61, 227 .tuner_bus = 1, 228 .input = {{ 229 .type = CX23885_VMUX_TELEVISION, 230 .vmux = CX25840_VIN2_CH1 | 231 CX25840_VIN5_CH2, 232 .amux = CX25840_AUDIO8, 233 .gpio0 = 0x704040, 234 }, { 235 .type = CX23885_VMUX_COMPOSITE1, 236 .vmux = CX25840_COMPOSITE1, 237 .amux = CX25840_AUDIO7, 238 .gpio0 = 0x704040, 239 }, { 240 .type = CX23885_VMUX_SVIDEO, 241 .vmux = CX25840_SVIDEO_LUMA3 | 242 CX25840_SVIDEO_CHROMA4, 243 .amux = CX25840_AUDIO7, 244 .gpio0 = 0x704040, 245 }, { 246 .type = CX23885_VMUX_COMPONENT, 247 .vmux = CX25840_VIN7_CH1 | 248 CX25840_VIN6_CH2 | 249 CX25840_VIN8_CH3 | 250 CX25840_COMPONENT_ON, 251 .amux = CX25840_AUDIO7, 252 .gpio0 = 0x704040, 253 } }, 254 }, 255 [CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000] = { 256 .name = "Leadtek Winfast PxDVR3200 H XC4000", 257 .porta = CX23885_ANALOG_VIDEO, 258 .portc = CX23885_MPEG_DVB, 259 .tuner_type = TUNER_XC4000, 260 .tuner_addr = 0x61, 261 .radio_type = UNSET, 262 .radio_addr = ADDR_UNSET, 263 .input = {{ 264 .type = CX23885_VMUX_TELEVISION, 265 .vmux = CX25840_VIN2_CH1 | 266 CX25840_VIN5_CH2 | 267 CX25840_NONE0_CH3, 268 }, { 269 .type = CX23885_VMUX_COMPOSITE1, 270 .vmux = CX25840_COMPOSITE1, 271 }, { 272 .type = CX23885_VMUX_SVIDEO, 273 .vmux = CX25840_SVIDEO_LUMA3 | 274 CX25840_SVIDEO_CHROMA4, 275 }, { 276 .type = CX23885_VMUX_COMPONENT, 277 .vmux = CX25840_VIN7_CH1 | 278 CX25840_VIN6_CH2 | 279 CX25840_VIN8_CH3 | 280 CX25840_COMPONENT_ON, 281 } }, 282 }, 283 [CX23885_BOARD_COMPRO_VIDEOMATE_E650F] = { 284 .name = "Compro VideoMate E650F", 285 .portc = CX23885_MPEG_DVB, 286 }, 287 [CX23885_BOARD_TBS_6920] = { 288 .name = "TurboSight TBS 6920", 289 .portb = CX23885_MPEG_DVB, 290 }, 291 [CX23885_BOARD_TBS_6980] = { 292 .name = "TurboSight TBS 6980", 293 .portb = CX23885_MPEG_DVB, 294 .portc = CX23885_MPEG_DVB, 295 }, 296 [CX23885_BOARD_TBS_6981] = { 297 .name = "TurboSight TBS 6981", 298 .portb = CX23885_MPEG_DVB, 299 .portc = CX23885_MPEG_DVB, 300 }, 301 [CX23885_BOARD_TEVII_S470] = { 302 .name = "TeVii S470", 303 .portb = CX23885_MPEG_DVB, 304 }, 305 [CX23885_BOARD_DVBWORLD_2005] = { 306 .name = "DVBWorld DVB-S2 2005", 307 .portb = CX23885_MPEG_DVB, 308 }, 309 [CX23885_BOARD_NETUP_DUAL_DVBS2_CI] = { 310 .ci_type = 1, 311 .name = "NetUP Dual DVB-S2 CI", 312 .portb = CX23885_MPEG_DVB, 313 .portc = CX23885_MPEG_DVB, 314 }, 315 [CX23885_BOARD_HAUPPAUGE_HVR1270] = { 316 .name = "Hauppauge WinTV-HVR1270", 317 .portc = CX23885_MPEG_DVB, 318 }, 319 [CX23885_BOARD_HAUPPAUGE_HVR1275] = { 320 .name = "Hauppauge WinTV-HVR1275", 321 .portc = CX23885_MPEG_DVB, 322 }, 323 [CX23885_BOARD_HAUPPAUGE_HVR1255] = { 324 .name = "Hauppauge WinTV-HVR1255", 325 .porta = CX23885_ANALOG_VIDEO, 326 .portc = CX23885_MPEG_DVB, 327 .tuner_type = TUNER_ABSENT, 328 .tuner_addr = 0x42, /* 0x84 >> 1 */ 329 .force_bff = 1, 330 .input = {{ 331 .type = CX23885_VMUX_TELEVISION, 332 .vmux = CX25840_VIN7_CH3 | 333 CX25840_VIN5_CH2 | 334 CX25840_VIN2_CH1 | 335 CX25840_DIF_ON, 336 .amux = CX25840_AUDIO8, 337 }, { 338 .type = CX23885_VMUX_COMPOSITE1, 339 .vmux = CX25840_VIN7_CH3 | 340 CX25840_VIN4_CH2 | 341 CX25840_VIN6_CH1, 342 .amux = CX25840_AUDIO7, 343 }, { 344 .type = CX23885_VMUX_SVIDEO, 345 .vmux = CX25840_VIN7_CH3 | 346 CX25840_VIN4_CH2 | 347 CX25840_VIN8_CH1 | 348 CX25840_SVIDEO_ON, 349 .amux = CX25840_AUDIO7, 350 } }, 351 }, 352 [CX23885_BOARD_HAUPPAUGE_HVR1255_22111] = { 353 .name = "Hauppauge WinTV-HVR1255", 354 .porta = CX23885_ANALOG_VIDEO, 355 .portc = CX23885_MPEG_DVB, 356 .tuner_type = TUNER_ABSENT, 357 .tuner_addr = 0x42, /* 0x84 >> 1 */ 358 .force_bff = 1, 359 .input = {{ 360 .type = CX23885_VMUX_TELEVISION, 361 .vmux = CX25840_VIN7_CH3 | 362 CX25840_VIN5_CH2 | 363 CX25840_VIN2_CH1 | 364 CX25840_DIF_ON, 365 .amux = CX25840_AUDIO8, 366 }, { 367 .type = CX23885_VMUX_SVIDEO, 368 .vmux = CX25840_VIN7_CH3 | 369 CX25840_VIN4_CH2 | 370 CX25840_VIN8_CH1 | 371 CX25840_SVIDEO_ON, 372 .amux = CX25840_AUDIO7, 373 } }, 374 }, 375 [CX23885_BOARD_HAUPPAUGE_HVR1210] = { 376 .name = "Hauppauge WinTV-HVR1210", 377 .portc = CX23885_MPEG_DVB, 378 }, 379 [CX23885_BOARD_MYGICA_X8506] = { 380 .name = "Mygica X8506 DMB-TH", 381 .tuner_type = TUNER_XC5000, 382 .tuner_addr = 0x61, 383 .tuner_bus = 1, 384 .porta = CX23885_ANALOG_VIDEO, 385 .portb = CX23885_MPEG_DVB, 386 .input = { 387 { 388 .type = CX23885_VMUX_TELEVISION, 389 .vmux = CX25840_COMPOSITE2, 390 }, 391 { 392 .type = CX23885_VMUX_COMPOSITE1, 393 .vmux = CX25840_COMPOSITE8, 394 }, 395 { 396 .type = CX23885_VMUX_SVIDEO, 397 .vmux = CX25840_SVIDEO_LUMA3 | 398 CX25840_SVIDEO_CHROMA4, 399 }, 400 { 401 .type = CX23885_VMUX_COMPONENT, 402 .vmux = CX25840_COMPONENT_ON | 403 CX25840_VIN1_CH1 | 404 CX25840_VIN6_CH2 | 405 CX25840_VIN7_CH3, 406 }, 407 }, 408 }, 409 [CX23885_BOARD_MAGICPRO_PROHDTVE2] = { 410 .name = "Magic-Pro ProHDTV Extreme 2", 411 .tuner_type = TUNER_XC5000, 412 .tuner_addr = 0x61, 413 .tuner_bus = 1, 414 .porta = CX23885_ANALOG_VIDEO, 415 .portb = CX23885_MPEG_DVB, 416 .input = { 417 { 418 .type = CX23885_VMUX_TELEVISION, 419 .vmux = CX25840_COMPOSITE2, 420 }, 421 { 422 .type = CX23885_VMUX_COMPOSITE1, 423 .vmux = CX25840_COMPOSITE8, 424 }, 425 { 426 .type = CX23885_VMUX_SVIDEO, 427 .vmux = CX25840_SVIDEO_LUMA3 | 428 CX25840_SVIDEO_CHROMA4, 429 }, 430 { 431 .type = CX23885_VMUX_COMPONENT, 432 .vmux = CX25840_COMPONENT_ON | 433 CX25840_VIN1_CH1 | 434 CX25840_VIN6_CH2 | 435 CX25840_VIN7_CH3, 436 }, 437 }, 438 }, 439 [CX23885_BOARD_HAUPPAUGE_HVR1850] = { 440 .name = "Hauppauge WinTV-HVR1850", 441 .porta = CX23885_ANALOG_VIDEO, 442 .portb = CX23885_MPEG_ENCODER, 443 .portc = CX23885_MPEG_DVB, 444 .tuner_type = TUNER_ABSENT, 445 .tuner_addr = 0x42, /* 0x84 >> 1 */ 446 .force_bff = 1, 447 .input = {{ 448 .type = CX23885_VMUX_TELEVISION, 449 .vmux = CX25840_VIN7_CH3 | 450 CX25840_VIN5_CH2 | 451 CX25840_VIN2_CH1 | 452 CX25840_DIF_ON, 453 .amux = CX25840_AUDIO8, 454 }, { 455 .type = CX23885_VMUX_COMPOSITE1, 456 .vmux = CX25840_VIN7_CH3 | 457 CX25840_VIN4_CH2 | 458 CX25840_VIN6_CH1, 459 .amux = CX25840_AUDIO7, 460 }, { 461 .type = CX23885_VMUX_SVIDEO, 462 .vmux = CX25840_VIN7_CH3 | 463 CX25840_VIN4_CH2 | 464 CX25840_VIN8_CH1 | 465 CX25840_SVIDEO_ON, 466 .amux = CX25840_AUDIO7, 467 } }, 468 }, 469 [CX23885_BOARD_COMPRO_VIDEOMATE_E800] = { 470 .name = "Compro VideoMate E800", 471 .portc = CX23885_MPEG_DVB, 472 }, 473 [CX23885_BOARD_HAUPPAUGE_HVR1290] = { 474 .name = "Hauppauge WinTV-HVR1290", 475 .portc = CX23885_MPEG_DVB, 476 }, 477 [CX23885_BOARD_MYGICA_X8558PRO] = { 478 .name = "Mygica X8558 PRO DMB-TH", 479 .portb = CX23885_MPEG_DVB, 480 .portc = CX23885_MPEG_DVB, 481 }, 482 [CX23885_BOARD_LEADTEK_WINFAST_PXTV1200] = { 483 .name = "LEADTEK WinFast PxTV1200", 484 .porta = CX23885_ANALOG_VIDEO, 485 .tuner_type = TUNER_XC2028, 486 .tuner_addr = 0x61, 487 .tuner_bus = 1, 488 .input = {{ 489 .type = CX23885_VMUX_TELEVISION, 490 .vmux = CX25840_VIN2_CH1 | 491 CX25840_VIN5_CH2 | 492 CX25840_NONE0_CH3, 493 }, { 494 .type = CX23885_VMUX_COMPOSITE1, 495 .vmux = CX25840_COMPOSITE1, 496 }, { 497 .type = CX23885_VMUX_SVIDEO, 498 .vmux = CX25840_SVIDEO_LUMA3 | 499 CX25840_SVIDEO_CHROMA4, 500 }, { 501 .type = CX23885_VMUX_COMPONENT, 502 .vmux = CX25840_VIN7_CH1 | 503 CX25840_VIN6_CH2 | 504 CX25840_VIN8_CH3 | 505 CX25840_COMPONENT_ON, 506 } }, 507 }, 508 [CX23885_BOARD_GOTVIEW_X5_3D_HYBRID] = { 509 .name = "GoTView X5 3D Hybrid", 510 .tuner_type = TUNER_XC5000, 511 .tuner_addr = 0x64, 512 .tuner_bus = 1, 513 .porta = CX23885_ANALOG_VIDEO, 514 .portb = CX23885_MPEG_DVB, 515 .input = {{ 516 .type = CX23885_VMUX_TELEVISION, 517 .vmux = CX25840_VIN2_CH1 | 518 CX25840_VIN5_CH2, 519 .gpio0 = 0x02, 520 }, { 521 .type = CX23885_VMUX_COMPOSITE1, 522 .vmux = CX23885_VMUX_COMPOSITE1, 523 }, { 524 .type = CX23885_VMUX_SVIDEO, 525 .vmux = CX25840_SVIDEO_LUMA3 | 526 CX25840_SVIDEO_CHROMA4, 527 } }, 528 }, 529 [CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF] = { 530 .ci_type = 2, 531 .name = "NetUP Dual DVB-T/C-CI RF", 532 .porta = CX23885_ANALOG_VIDEO, 533 .portb = CX23885_MPEG_DVB, 534 .portc = CX23885_MPEG_DVB, 535 .num_fds_portb = 2, 536 .num_fds_portc = 2, 537 .tuner_type = TUNER_XC5000, 538 .tuner_addr = 0x64, 539 .input = { { 540 .type = CX23885_VMUX_TELEVISION, 541 .vmux = CX25840_COMPOSITE1, 542 } }, 543 }, 544 [CX23885_BOARD_MPX885] = { 545 .name = "MPX-885", 546 .porta = CX23885_ANALOG_VIDEO, 547 .input = {{ 548 .type = CX23885_VMUX_COMPOSITE1, 549 .vmux = CX25840_COMPOSITE1, 550 .amux = CX25840_AUDIO6, 551 .gpio0 = 0, 552 }, { 553 .type = CX23885_VMUX_COMPOSITE2, 554 .vmux = CX25840_COMPOSITE2, 555 .amux = CX25840_AUDIO6, 556 .gpio0 = 0, 557 }, { 558 .type = CX23885_VMUX_COMPOSITE3, 559 .vmux = CX25840_COMPOSITE3, 560 .amux = CX25840_AUDIO7, 561 .gpio0 = 0, 562 }, { 563 .type = CX23885_VMUX_COMPOSITE4, 564 .vmux = CX25840_COMPOSITE4, 565 .amux = CX25840_AUDIO7, 566 .gpio0 = 0, 567 } }, 568 }, 569 [CX23885_BOARD_MYGICA_X8507] = { 570 .name = "Mygica X8502/X8507 ISDB-T", 571 .tuner_type = TUNER_XC5000, 572 .tuner_addr = 0x61, 573 .tuner_bus = 1, 574 .porta = CX23885_ANALOG_VIDEO, 575 .portb = CX23885_MPEG_DVB, 576 .input = { 577 { 578 .type = CX23885_VMUX_TELEVISION, 579 .vmux = CX25840_COMPOSITE2, 580 .amux = CX25840_AUDIO8, 581 }, 582 { 583 .type = CX23885_VMUX_COMPOSITE1, 584 .vmux = CX25840_COMPOSITE8, 585 .amux = CX25840_AUDIO7, 586 }, 587 { 588 .type = CX23885_VMUX_SVIDEO, 589 .vmux = CX25840_SVIDEO_LUMA3 | 590 CX25840_SVIDEO_CHROMA4, 591 .amux = CX25840_AUDIO7, 592 }, 593 { 594 .type = CX23885_VMUX_COMPONENT, 595 .vmux = CX25840_COMPONENT_ON | 596 CX25840_VIN1_CH1 | 597 CX25840_VIN6_CH2 | 598 CX25840_VIN7_CH3, 599 .amux = CX25840_AUDIO7, 600 }, 601 }, 602 }, 603 [CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL] = { 604 .name = "TerraTec Cinergy T PCIe Dual", 605 .portb = CX23885_MPEG_DVB, 606 .portc = CX23885_MPEG_DVB, 607 }, 608 [CX23885_BOARD_TEVII_S471] = { 609 .name = "TeVii S471", 610 .portb = CX23885_MPEG_DVB, 611 }, 612 [CX23885_BOARD_PROF_8000] = { 613 .name = "Prof Revolution DVB-S2 8000", 614 .portb = CX23885_MPEG_DVB, 615 }, 616 [CX23885_BOARD_HAUPPAUGE_HVR4400] = { 617 .name = "Hauppauge WinTV-HVR4400/HVR5500", 618 .porta = CX23885_ANALOG_VIDEO, 619 .portb = CX23885_MPEG_DVB, 620 .portc = CX23885_MPEG_DVB, 621 .tuner_type = TUNER_NXP_TDA18271, 622 .tuner_addr = 0x60, /* 0xc0 >> 1 */ 623 .tuner_bus = 1, 624 }, 625 [CX23885_BOARD_HAUPPAUGE_STARBURST] = { 626 .name = "Hauppauge WinTV Starburst", 627 .portb = CX23885_MPEG_DVB, 628 }, 629 [CX23885_BOARD_AVERMEDIA_HC81R] = { 630 .name = "AVerTV Hybrid Express Slim HC81R", 631 .tuner_type = TUNER_XC2028, 632 .tuner_addr = 0x61, /* 0xc2 >> 1 */ 633 .tuner_bus = 1, 634 .porta = CX23885_ANALOG_VIDEO, 635 .input = {{ 636 .type = CX23885_VMUX_TELEVISION, 637 .vmux = CX25840_VIN2_CH1 | 638 CX25840_VIN5_CH2 | 639 CX25840_NONE0_CH3 | 640 CX25840_NONE1_CH3, 641 .amux = CX25840_AUDIO8, 642 }, { 643 .type = CX23885_VMUX_SVIDEO, 644 .vmux = CX25840_VIN8_CH1 | 645 CX25840_NONE_CH2 | 646 CX25840_VIN7_CH3 | 647 CX25840_SVIDEO_ON, 648 .amux = CX25840_AUDIO6, 649 }, { 650 .type = CX23885_VMUX_COMPONENT, 651 .vmux = CX25840_VIN1_CH1 | 652 CX25840_NONE_CH2 | 653 CX25840_NONE0_CH3 | 654 CX25840_NONE1_CH3, 655 .amux = CX25840_AUDIO6, 656 } }, 657 }, 658 [CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2] = { 659 .name = "DViCO FusionHDTV DVB-T Dual Express2", 660 .portb = CX23885_MPEG_DVB, 661 .portc = CX23885_MPEG_DVB, 662 }, 663 [CX23885_BOARD_HAUPPAUGE_IMPACTVCBE] = { 664 .name = "Hauppauge ImpactVCB-e", 665 .tuner_type = TUNER_ABSENT, 666 .porta = CX23885_ANALOG_VIDEO, 667 .input = {{ 668 .type = CX23885_VMUX_COMPOSITE1, 669 .vmux = CX25840_VIN7_CH3 | 670 CX25840_VIN4_CH2 | 671 CX25840_VIN6_CH1, 672 .amux = CX25840_AUDIO7, 673 }, { 674 .type = CX23885_VMUX_SVIDEO, 675 .vmux = CX25840_VIN7_CH3 | 676 CX25840_VIN4_CH2 | 677 CX25840_VIN8_CH1 | 678 CX25840_SVIDEO_ON, 679 .amux = CX25840_AUDIO7, 680 } }, 681 }, 682 [CX23885_BOARD_DVBSKY_T9580] = { 683 .name = "DVBSky T9580", 684 .portb = CX23885_MPEG_DVB, 685 .portc = CX23885_MPEG_DVB, 686 }, 687 [CX23885_BOARD_DVBSKY_T980C] = { 688 .name = "DVBSky T980C", 689 .portb = CX23885_MPEG_DVB, 690 }, 691 [CX23885_BOARD_DVBSKY_S950C] = { 692 .name = "DVBSky S950C", 693 .portb = CX23885_MPEG_DVB, 694 }, 695 [CX23885_BOARD_TT_CT2_4500_CI] = { 696 .name = "Technotrend TT-budget CT2-4500 CI", 697 .portb = CX23885_MPEG_DVB, 698 }, 699 [CX23885_BOARD_DVBSKY_S950] = { 700 .name = "DVBSky S950", 701 .portb = CX23885_MPEG_DVB, 702 }, 703 [CX23885_BOARD_DVBSKY_S952] = { 704 .name = "DVBSky S952", 705 .portb = CX23885_MPEG_DVB, 706 .portc = CX23885_MPEG_DVB, 707 }, 708 [CX23885_BOARD_DVBSKY_T982] = { 709 .name = "DVBSky T982", 710 .portb = CX23885_MPEG_DVB, 711 .portc = CX23885_MPEG_DVB, 712 }, 713 [CX23885_BOARD_HAUPPAUGE_HVR5525] = { 714 .name = "Hauppauge WinTV-HVR5525", 715 .portb = CX23885_MPEG_DVB, 716 .portc = CX23885_MPEG_DVB, 717 }, 718}; 719const unsigned int cx23885_bcount = ARRAY_SIZE(cx23885_boards); 720 721/* ------------------------------------------------------------------ */ 722/* PCI subsystem IDs */ 723 724struct cx23885_subid cx23885_subids[] = { 725 { 726 .subvendor = 0x0070, 727 .subdevice = 0x3400, 728 .card = CX23885_BOARD_UNKNOWN, 729 }, { 730 .subvendor = 0x0070, 731 .subdevice = 0x7600, 732 .card = CX23885_BOARD_HAUPPAUGE_HVR1800lp, 733 }, { 734 .subvendor = 0x0070, 735 .subdevice = 0x7800, 736 .card = CX23885_BOARD_HAUPPAUGE_HVR1800, 737 }, { 738 .subvendor = 0x0070, 739 .subdevice = 0x7801, 740 .card = CX23885_BOARD_HAUPPAUGE_HVR1800, 741 }, { 742 .subvendor = 0x0070, 743 .subdevice = 0x7809, 744 .card = CX23885_BOARD_HAUPPAUGE_HVR1800, 745 }, { 746 .subvendor = 0x0070, 747 .subdevice = 0x7911, 748 .card = CX23885_BOARD_HAUPPAUGE_HVR1250, 749 }, { 750 .subvendor = 0x18ac, 751 .subdevice = 0xd500, 752 .card = CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP, 753 }, { 754 .subvendor = 0x0070, 755 .subdevice = 0x7790, 756 .card = CX23885_BOARD_HAUPPAUGE_HVR1500Q, 757 }, { 758 .subvendor = 0x0070, 759 .subdevice = 0x7797, 760 .card = CX23885_BOARD_HAUPPAUGE_HVR1500Q, 761 }, { 762 .subvendor = 0x0070, 763 .subdevice = 0x7710, 764 .card = CX23885_BOARD_HAUPPAUGE_HVR1500, 765 }, { 766 .subvendor = 0x0070, 767 .subdevice = 0x7717, 768 .card = CX23885_BOARD_HAUPPAUGE_HVR1500, 769 }, { 770 .subvendor = 0x0070, 771 .subdevice = 0x71d1, 772 .card = CX23885_BOARD_HAUPPAUGE_HVR1200, 773 }, { 774 .subvendor = 0x0070, 775 .subdevice = 0x71d3, 776 .card = CX23885_BOARD_HAUPPAUGE_HVR1200, 777 }, { 778 .subvendor = 0x0070, 779 .subdevice = 0x8101, 780 .card = CX23885_BOARD_HAUPPAUGE_HVR1700, 781 }, { 782 .subvendor = 0x0070, 783 .subdevice = 0x8010, 784 .card = CX23885_BOARD_HAUPPAUGE_HVR1400, 785 }, { 786 .subvendor = 0x18ac, 787 .subdevice = 0xd618, 788 .card = CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP, 789 }, { 790 .subvendor = 0x18ac, 791 .subdevice = 0xdb78, 792 .card = CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP, 793 }, { 794 .subvendor = 0x107d, 795 .subdevice = 0x6681, 796 .card = CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H, 797 }, { 798 .subvendor = 0x107d, 799 .subdevice = 0x6f21, 800 .card = CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200, 801 }, { 802 .subvendor = 0x107d, 803 .subdevice = 0x6f39, 804 .card = CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000, 805 }, { 806 .subvendor = 0x185b, 807 .subdevice = 0xe800, 808 .card = CX23885_BOARD_COMPRO_VIDEOMATE_E650F, 809 }, { 810 .subvendor = 0x6920, 811 .subdevice = 0x8888, 812 .card = CX23885_BOARD_TBS_6920, 813 }, { 814 .subvendor = 0x6980, 815 .subdevice = 0x8888, 816 .card = CX23885_BOARD_TBS_6980, 817 }, { 818 .subvendor = 0x6981, 819 .subdevice = 0x8888, 820 .card = CX23885_BOARD_TBS_6981, 821 }, { 822 .subvendor = 0xd470, 823 .subdevice = 0x9022, 824 .card = CX23885_BOARD_TEVII_S470, 825 }, { 826 .subvendor = 0x0001, 827 .subdevice = 0x2005, 828 .card = CX23885_BOARD_DVBWORLD_2005, 829 }, { 830 .subvendor = 0x1b55, 831 .subdevice = 0x2a2c, 832 .card = CX23885_BOARD_NETUP_DUAL_DVBS2_CI, 833 }, { 834 .subvendor = 0x0070, 835 .subdevice = 0x2211, 836 .card = CX23885_BOARD_HAUPPAUGE_HVR1270, 837 }, { 838 .subvendor = 0x0070, 839 .subdevice = 0x2215, 840 .card = CX23885_BOARD_HAUPPAUGE_HVR1275, 841 }, { 842 .subvendor = 0x0070, 843 .subdevice = 0x221d, 844 .card = CX23885_BOARD_HAUPPAUGE_HVR1275, 845 }, { 846 .subvendor = 0x0070, 847 .subdevice = 0x2251, 848 .card = CX23885_BOARD_HAUPPAUGE_HVR1255, 849 }, { 850 .subvendor = 0x0070, 851 .subdevice = 0x2259, 852 .card = CX23885_BOARD_HAUPPAUGE_HVR1255_22111, 853 }, { 854 .subvendor = 0x0070, 855 .subdevice = 0x2291, 856 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, 857 }, { 858 .subvendor = 0x0070, 859 .subdevice = 0x2295, 860 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, 861 }, { 862 .subvendor = 0x0070, 863 .subdevice = 0x2299, 864 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, 865 }, { 866 .subvendor = 0x0070, 867 .subdevice = 0x229d, 868 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */ 869 }, { 870 .subvendor = 0x0070, 871 .subdevice = 0x22f0, 872 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, 873 }, { 874 .subvendor = 0x0070, 875 .subdevice = 0x22f1, 876 .card = CX23885_BOARD_HAUPPAUGE_HVR1255, 877 }, { 878 .subvendor = 0x0070, 879 .subdevice = 0x22f2, 880 .card = CX23885_BOARD_HAUPPAUGE_HVR1275, 881 }, { 882 .subvendor = 0x0070, 883 .subdevice = 0x22f3, 884 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */ 885 }, { 886 .subvendor = 0x0070, 887 .subdevice = 0x22f4, 888 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, 889 }, { 890 .subvendor = 0x0070, 891 .subdevice = 0x22f5, 892 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */ 893 }, { 894 .subvendor = 0x14f1, 895 .subdevice = 0x8651, 896 .card = CX23885_BOARD_MYGICA_X8506, 897 }, { 898 .subvendor = 0x14f1, 899 .subdevice = 0x8657, 900 .card = CX23885_BOARD_MAGICPRO_PROHDTVE2, 901 }, { 902 .subvendor = 0x0070, 903 .subdevice = 0x8541, 904 .card = CX23885_BOARD_HAUPPAUGE_HVR1850, 905 }, { 906 .subvendor = 0x1858, 907 .subdevice = 0xe800, 908 .card = CX23885_BOARD_COMPRO_VIDEOMATE_E800, 909 }, { 910 .subvendor = 0x0070, 911 .subdevice = 0x8551, 912 .card = CX23885_BOARD_HAUPPAUGE_HVR1290, 913 }, { 914 .subvendor = 0x14f1, 915 .subdevice = 0x8578, 916 .card = CX23885_BOARD_MYGICA_X8558PRO, 917 }, { 918 .subvendor = 0x107d, 919 .subdevice = 0x6f22, 920 .card = CX23885_BOARD_LEADTEK_WINFAST_PXTV1200, 921 }, { 922 .subvendor = 0x5654, 923 .subdevice = 0x2390, 924 .card = CX23885_BOARD_GOTVIEW_X5_3D_HYBRID, 925 }, { 926 .subvendor = 0x1b55, 927 .subdevice = 0xe2e4, 928 .card = CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF, 929 }, { 930 .subvendor = 0x14f1, 931 .subdevice = 0x8502, 932 .card = CX23885_BOARD_MYGICA_X8507, 933 }, { 934 .subvendor = 0x153b, 935 .subdevice = 0x117e, 936 .card = CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL, 937 }, { 938 .subvendor = 0xd471, 939 .subdevice = 0x9022, 940 .card = CX23885_BOARD_TEVII_S471, 941 }, { 942 .subvendor = 0x8000, 943 .subdevice = 0x3034, 944 .card = CX23885_BOARD_PROF_8000, 945 }, { 946 .subvendor = 0x0070, 947 .subdevice = 0xc108, 948 .card = CX23885_BOARD_HAUPPAUGE_HVR4400, /* Hauppauge WinTV HVR-4400 (Model 121xxx, Hybrid DVB-T/S2, IR) */ 949 }, { 950 .subvendor = 0x0070, 951 .subdevice = 0xc138, 952 .card = CX23885_BOARD_HAUPPAUGE_HVR4400, /* Hauppauge WinTV HVR-5500 (Model 121xxx, Hybrid DVB-T/C/S2, IR) */ 953 }, { 954 .subvendor = 0x0070, 955 .subdevice = 0xc12a, 956 .card = CX23885_BOARD_HAUPPAUGE_STARBURST, /* Hauppauge WinTV Starburst (Model 121x00, DVB-S2, IR) */ 957 }, { 958 .subvendor = 0x0070, 959 .subdevice = 0xc1f8, 960 .card = CX23885_BOARD_HAUPPAUGE_HVR4400, /* Hauppauge WinTV HVR-5500 (Model 121xxx, Hybrid DVB-T/C/S2, IR) */ 961 }, { 962 .subvendor = 0x1461, 963 .subdevice = 0xd939, 964 .card = CX23885_BOARD_AVERMEDIA_HC81R, 965 }, { 966 .subvendor = 0x0070, 967 .subdevice = 0x7133, 968 .card = CX23885_BOARD_HAUPPAUGE_IMPACTVCBE, 969 }, { 970 .subvendor = 0x18ac, 971 .subdevice = 0xdb98, 972 .card = CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2, 973 }, { 974 .subvendor = 0x4254, 975 .subdevice = 0x9580, 976 .card = CX23885_BOARD_DVBSKY_T9580, 977 }, { 978 .subvendor = 0x4254, 979 .subdevice = 0x980c, 980 .card = CX23885_BOARD_DVBSKY_T980C, 981 }, { 982 .subvendor = 0x4254, 983 .subdevice = 0x950c, 984 .card = CX23885_BOARD_DVBSKY_S950C, 985 }, { 986 .subvendor = 0x13c2, 987 .subdevice = 0x3013, 988 .card = CX23885_BOARD_TT_CT2_4500_CI, 989 }, { 990 .subvendor = 0x4254, 991 .subdevice = 0x0950, 992 .card = CX23885_BOARD_DVBSKY_S950, 993 }, { 994 .subvendor = 0x4254, 995 .subdevice = 0x0952, 996 .card = CX23885_BOARD_DVBSKY_S952, 997 }, { 998 .subvendor = 0x4254, 999 .subdevice = 0x0982, 1000 .card = CX23885_BOARD_DVBSKY_T982, 1001 }, { 1002 .subvendor = 0x0070, 1003 .subdevice = 0xf038, 1004 .card = CX23885_BOARD_HAUPPAUGE_HVR5525, 1005 }, 1006}; 1007const unsigned int cx23885_idcount = ARRAY_SIZE(cx23885_subids); 1008 1009void cx23885_card_list(struct cx23885_dev *dev) 1010{ 1011 int i; 1012 1013 if (0 == dev->pci->subsystem_vendor && 1014 0 == dev->pci->subsystem_device) { 1015 printk(KERN_INFO 1016 "%s: Board has no valid PCIe Subsystem ID and can't\n" 1017 "%s: be autodetected. Pass card=<n> insmod option\n" 1018 "%s: to workaround that. Redirect complaints to the\n" 1019 "%s: vendor of the TV card. Best regards,\n" 1020 "%s: -- tux\n", 1021 dev->name, dev->name, dev->name, dev->name, dev->name); 1022 } else { 1023 printk(KERN_INFO 1024 "%s: Your board isn't known (yet) to the driver.\n" 1025 "%s: Try to pick one of the existing card configs via\n" 1026 "%s: card=<n> insmod option. Updating to the latest\n" 1027 "%s: version might help as well.\n", 1028 dev->name, dev->name, dev->name, dev->name); 1029 } 1030 printk(KERN_INFO "%s: Here is a list of valid choices for the card=<n> insmod option:\n", 1031 dev->name); 1032 for (i = 0; i < cx23885_bcount; i++) 1033 printk(KERN_INFO "%s: card=%d -> %s\n", 1034 dev->name, i, cx23885_boards[i].name); 1035} 1036 1037static void hauppauge_eeprom(struct cx23885_dev *dev, u8 *eeprom_data) 1038{ 1039 struct tveeprom tv; 1040 1041 tveeprom_hauppauge_analog(&dev->i2c_bus[0].i2c_client, &tv, 1042 eeprom_data); 1043 1044 /* Make sure we support the board model */ 1045 switch (tv.model) { 1046 case 22001: 1047 /* WinTV-HVR1270 (PCIe, Retail, half height) 1048 * ATSC/QAM and basic analog, IR Blast */ 1049 case 22009: 1050 /* WinTV-HVR1210 (PCIe, Retail, half height) 1051 * DVB-T and basic analog, IR Blast */ 1052 case 22011: 1053 /* WinTV-HVR1270 (PCIe, Retail, half height) 1054 * ATSC/QAM and basic analog, IR Recv */ 1055 case 22019: 1056 /* WinTV-HVR1210 (PCIe, Retail, half height) 1057 * DVB-T and basic analog, IR Recv */ 1058 case 22021: 1059 /* WinTV-HVR1275 (PCIe, Retail, half height) 1060 * ATSC/QAM and basic analog, IR Recv */ 1061 case 22029: 1062 /* WinTV-HVR1210 (PCIe, Retail, half height) 1063 * DVB-T and basic analog, IR Recv */ 1064 case 22101: 1065 /* WinTV-HVR1270 (PCIe, Retail, full height) 1066 * ATSC/QAM and basic analog, IR Blast */ 1067 case 22109: 1068 /* WinTV-HVR1210 (PCIe, Retail, full height) 1069 * DVB-T and basic analog, IR Blast */ 1070 case 22111: 1071 /* WinTV-HVR1270 (PCIe, Retail, full height) 1072 * ATSC/QAM and basic analog, IR Recv */ 1073 case 22119: 1074 /* WinTV-HVR1210 (PCIe, Retail, full height) 1075 * DVB-T and basic analog, IR Recv */ 1076 case 22121: 1077 /* WinTV-HVR1275 (PCIe, Retail, full height) 1078 * ATSC/QAM and basic analog, IR Recv */ 1079 case 22129: 1080 /* WinTV-HVR1210 (PCIe, Retail, full height) 1081 * DVB-T and basic analog, IR Recv */ 1082 case 71009: 1083 /* WinTV-HVR1200 (PCIe, Retail, full height) 1084 * DVB-T and basic analog */ 1085 case 71100: 1086 /* WinTV-ImpactVCB-e (PCIe, Retail, half height) 1087 * Basic analog */ 1088 case 71359: 1089 /* WinTV-HVR1200 (PCIe, OEM, half height) 1090 * DVB-T and basic analog */ 1091 case 71439: 1092 /* WinTV-HVR1200 (PCIe, OEM, half height) 1093 * DVB-T and basic analog */ 1094 case 71449: 1095 /* WinTV-HVR1200 (PCIe, OEM, full height) 1096 * DVB-T and basic analog */ 1097 case 71939: 1098 /* WinTV-HVR1200 (PCIe, OEM, half height) 1099 * DVB-T and basic analog */ 1100 case 71949: 1101 /* WinTV-HVR1200 (PCIe, OEM, full height) 1102 * DVB-T and basic analog */ 1103 case 71959: 1104 /* WinTV-HVR1200 (PCIe, OEM, full height) 1105 * DVB-T and basic analog */ 1106 case 71979: 1107 /* WinTV-HVR1200 (PCIe, OEM, half height) 1108 * DVB-T and basic analog */ 1109 case 71999: 1110 /* WinTV-HVR1200 (PCIe, OEM, full height) 1111 * DVB-T and basic analog */ 1112 case 76601: 1113 /* WinTV-HVR1800lp (PCIe, Retail, No IR, Dual 1114 channel ATSC and MPEG2 HW Encoder */ 1115 case 77001: 1116 /* WinTV-HVR1500 (Express Card, OEM, No IR, ATSC 1117 and Basic analog */ 1118 case 77011: 1119 /* WinTV-HVR1500 (Express Card, Retail, No IR, ATSC 1120 and Basic analog */ 1121 case 77041: 1122 /* WinTV-HVR1500Q (Express Card, OEM, No IR, ATSC/QAM 1123 and Basic analog */ 1124 case 77051: 1125 /* WinTV-HVR1500Q (Express Card, Retail, No IR, ATSC/QAM 1126 and Basic analog */ 1127 case 78011: 1128 /* WinTV-HVR1800 (PCIe, Retail, 3.5mm in, IR, No FM, 1129 Dual channel ATSC and MPEG2 HW Encoder */ 1130 case 78501: 1131 /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, FM, 1132 Dual channel ATSC and MPEG2 HW Encoder */ 1133 case 78521: 1134 /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, FM, 1135 Dual channel ATSC and MPEG2 HW Encoder */ 1136 case 78531: 1137 /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, No FM, 1138 Dual channel ATSC and MPEG2 HW Encoder */ 1139 case 78631: 1140 /* WinTV-HVR1800 (PCIe, OEM, No IR, No FM, 1141 Dual channel ATSC and MPEG2 HW Encoder */ 1142 case 79001: 1143 /* WinTV-HVR1250 (PCIe, Retail, IR, full height, 1144 ATSC and Basic analog */ 1145 case 79101: 1146 /* WinTV-HVR1250 (PCIe, Retail, IR, half height, 1147 ATSC and Basic analog */ 1148 case 79501: 1149 /* WinTV-HVR1250 (PCIe, No IR, half height, 1150 ATSC [at least] and Basic analog) */ 1151 case 79561: 1152 /* WinTV-HVR1250 (PCIe, OEM, No IR, half height, 1153 ATSC and Basic analog */ 1154 case 79571: 1155 /* WinTV-HVR1250 (PCIe, OEM, No IR, full height, 1156 ATSC and Basic analog */ 1157 case 79671: 1158 /* WinTV-HVR1250 (PCIe, OEM, No IR, half height, 1159 ATSC and Basic analog */ 1160 case 80019: 1161 /* WinTV-HVR1400 (Express Card, Retail, IR, 1162 * DVB-T and Basic analog */ 1163 case 81509: 1164 /* WinTV-HVR1700 (PCIe, OEM, No IR, half height) 1165 * DVB-T and MPEG2 HW Encoder */ 1166 case 81519: 1167 /* WinTV-HVR1700 (PCIe, OEM, No IR, full height) 1168 * DVB-T and MPEG2 HW Encoder */ 1169 break; 1170 case 85021: 1171 /* WinTV-HVR1850 (PCIe, Retail, 3.5mm in, IR, FM, 1172 Dual channel ATSC and MPEG2 HW Encoder */ 1173 break; 1174 case 85721: 1175 /* WinTV-HVR1290 (PCIe, OEM, RCA in, IR, 1176 Dual channel ATSC and Basic analog */ 1177 case 150329: 1178 /* WinTV-HVR5525 (PCIe, DVB-S/S2, DVB-T/T2/C) */ 1179 break; 1180 default: 1181 printk(KERN_WARNING "%s: warning: " 1182 "unknown hauppauge model #%d\n", 1183 dev->name, tv.model); 1184 break; 1185 } 1186 1187 printk(KERN_INFO "%s: hauppauge eeprom: model=%d\n", 1188 dev->name, tv.model); 1189} 1190 1191/* Some TBS cards require initing a chip using a bitbanged SPI attached 1192 to the cx23885 gpio's. If this chip doesn't get init'ed the demod 1193 doesn't respond to any command. */ 1194static void tbs_card_init(struct cx23885_dev *dev) 1195{ 1196 int i; 1197 const u8 buf[] = { 1198 0xe0, 0x06, 0x66, 0x33, 0x65, 1199 0x01, 0x17, 0x06, 0xde}; 1200 1201 switch (dev->board) { 1202 case CX23885_BOARD_TBS_6980: 1203 case CX23885_BOARD_TBS_6981: 1204 cx_set(GP0_IO, 0x00070007); 1205 usleep_range(1000, 10000); 1206 cx_clear(GP0_IO, 2); 1207 usleep_range(1000, 10000); 1208 for (i = 0; i < 9 * 8; i++) { 1209 cx_clear(GP0_IO, 7); 1210 usleep_range(1000, 10000); 1211 cx_set(GP0_IO, 1212 ((buf[i >> 3] >> (7 - (i & 7))) & 1) | 4); 1213 usleep_range(1000, 10000); 1214 } 1215 cx_set(GP0_IO, 7); 1216 break; 1217 } 1218} 1219 1220int cx23885_tuner_callback(void *priv, int component, int command, int arg) 1221{ 1222 struct cx23885_tsport *port = priv; 1223 struct cx23885_dev *dev = port->dev; 1224 u32 bitmask = 0; 1225 1226 if ((command == XC2028_RESET_CLK) || (command == XC2028_I2C_FLUSH)) 1227 return 0; 1228 1229 if (command != 0) { 1230 printk(KERN_ERR "%s(): Unknown command 0x%x.\n", 1231 __func__, command); 1232 return -EINVAL; 1233 } 1234 1235 switch (dev->board) { 1236 case CX23885_BOARD_HAUPPAUGE_HVR1400: 1237 case CX23885_BOARD_HAUPPAUGE_HVR1500: 1238 case CX23885_BOARD_HAUPPAUGE_HVR1500Q: 1239 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H: 1240 case CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200: 1241 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000: 1242 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F: 1243 case CX23885_BOARD_COMPRO_VIDEOMATE_E800: 1244 case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200: 1245 /* Tuner Reset Command */ 1246 bitmask = 0x04; 1247 break; 1248 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP: 1249 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: 1250 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2: 1251 /* Two identical tuners on two different i2c buses, 1252 * we need to reset the correct gpio. */ 1253 if (port->nr == 1) 1254 bitmask = 0x01; 1255 else if (port->nr == 2) 1256 bitmask = 0x04; 1257 break; 1258 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID: 1259 /* Tuner Reset Command */ 1260 bitmask = 0x02; 1261 break; 1262 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: 1263 altera_ci_tuner_reset(dev, port->nr); 1264 break; 1265 case CX23885_BOARD_AVERMEDIA_HC81R: 1266 /* XC3028L Reset Command */ 1267 bitmask = 1 << 2; 1268 break; 1269 } 1270 1271 if (bitmask) { 1272 /* Drive the tuner into reset and back out */ 1273 cx_clear(GP0_IO, bitmask); 1274 mdelay(200); 1275 cx_set(GP0_IO, bitmask); 1276 } 1277 1278 return 0; 1279} 1280 1281void cx23885_gpio_setup(struct cx23885_dev *dev) 1282{ 1283 switch (dev->board) { 1284 case CX23885_BOARD_HAUPPAUGE_HVR1250: 1285 /* GPIO-0 cx24227 demodulator reset */ 1286 cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */ 1287 break; 1288 case CX23885_BOARD_HAUPPAUGE_HVR1500: 1289 /* GPIO-0 cx24227 demodulator */ 1290 /* GPIO-2 xc3028 tuner */ 1291 1292 /* Put the parts into reset */ 1293 cx_set(GP0_IO, 0x00050000); 1294 cx_clear(GP0_IO, 0x00000005); 1295 msleep(5); 1296 1297 /* Bring the parts out of reset */ 1298 cx_set(GP0_IO, 0x00050005); 1299 break; 1300 case CX23885_BOARD_HAUPPAUGE_HVR1500Q: 1301 /* GPIO-0 cx24227 demodulator reset */ 1302 /* GPIO-2 xc5000 tuner reset */ 1303 cx_set(GP0_IO, 0x00050005); /* Bring the part out of reset */ 1304 break; 1305 case CX23885_BOARD_HAUPPAUGE_HVR1800: 1306 /* GPIO-0 656_CLK */ 1307 /* GPIO-1 656_D0 */ 1308 /* GPIO-2 8295A Reset */ 1309 /* GPIO-3-10 cx23417 data0-7 */ 1310 /* GPIO-11-14 cx23417 addr0-3 */ 1311 /* GPIO-15-18 cx23417 READY, CS, RD, WR */ 1312 /* GPIO-19 IR_RX */ 1313 1314 /* CX23417 GPIO's */ 1315 /* EIO15 Zilog Reset */ 1316 /* EIO14 S5H1409/CX24227 Reset */ 1317 mc417_gpio_enable(dev, GPIO_15 | GPIO_14, 1); 1318 1319 /* Put the demod into reset and protect the eeprom */ 1320 mc417_gpio_clear(dev, GPIO_15 | GPIO_14); 1321 mdelay(100); 1322 1323 /* Bring the demod and blaster out of reset */ 1324 mc417_gpio_set(dev, GPIO_15 | GPIO_14); 1325 mdelay(100); 1326 1327 /* Force the TDA8295A into reset and back */ 1328 cx23885_gpio_enable(dev, GPIO_2, 1); 1329 cx23885_gpio_set(dev, GPIO_2); 1330 mdelay(20); 1331 cx23885_gpio_clear(dev, GPIO_2); 1332 mdelay(20); 1333 cx23885_gpio_set(dev, GPIO_2); 1334 mdelay(20); 1335 break; 1336 case CX23885_BOARD_HAUPPAUGE_HVR1200: 1337 /* GPIO-0 tda10048 demodulator reset */ 1338 /* GPIO-2 tda18271 tuner reset */ 1339 1340 /* Put the parts into reset and back */ 1341 cx_set(GP0_IO, 0x00050000); 1342 mdelay(20); 1343 cx_clear(GP0_IO, 0x00000005); 1344 mdelay(20); 1345 cx_set(GP0_IO, 0x00050005); 1346 break; 1347 case CX23885_BOARD_HAUPPAUGE_HVR1700: 1348 /* GPIO-0 TDA10048 demodulator reset */ 1349 /* GPIO-2 TDA8295A Reset */ 1350 /* GPIO-3-10 cx23417 data0-7 */ 1351 /* GPIO-11-14 cx23417 addr0-3 */ 1352 /* GPIO-15-18 cx23417 READY, CS, RD, WR */ 1353 1354 /* The following GPIO's are on the interna AVCore (cx25840) */ 1355 /* GPIO-19 IR_RX */ 1356 /* GPIO-20 IR_TX 416/DVBT Select */ 1357 /* GPIO-21 IIS DAT */ 1358 /* GPIO-22 IIS WCLK */ 1359 /* GPIO-23 IIS BCLK */ 1360 1361 /* Put the parts into reset and back */ 1362 cx_set(GP0_IO, 0x00050000); 1363 mdelay(20); 1364 cx_clear(GP0_IO, 0x00000005); 1365 mdelay(20); 1366 cx_set(GP0_IO, 0x00050005); 1367 break; 1368 case CX23885_BOARD_HAUPPAUGE_HVR1400: 1369 /* GPIO-0 Dibcom7000p demodulator reset */ 1370 /* GPIO-2 xc3028L tuner reset */ 1371 /* GPIO-13 LED */ 1372 1373 /* Put the parts into reset and back */ 1374 cx_set(GP0_IO, 0x00050000); 1375 mdelay(20); 1376 cx_clear(GP0_IO, 0x00000005); 1377 mdelay(20); 1378 cx_set(GP0_IO, 0x00050005); 1379 break; 1380 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP: 1381 /* GPIO-0 xc5000 tuner reset i2c bus 0 */ 1382 /* GPIO-1 s5h1409 demod reset i2c bus 0 */ 1383 /* GPIO-2 xc5000 tuner reset i2c bus 1 */ 1384 /* GPIO-3 s5h1409 demod reset i2c bus 0 */ 1385 1386 /* Put the parts into reset and back */ 1387 cx_set(GP0_IO, 0x000f0000); 1388 mdelay(20); 1389 cx_clear(GP0_IO, 0x0000000f); 1390 mdelay(20); 1391 cx_set(GP0_IO, 0x000f000f); 1392 break; 1393 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: 1394 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2: 1395 /* GPIO-0 portb xc3028 reset */ 1396 /* GPIO-1 portb zl10353 reset */ 1397 /* GPIO-2 portc xc3028 reset */ 1398 /* GPIO-3 portc zl10353 reset */ 1399 1400 /* Put the parts into reset and back */ 1401 cx_set(GP0_IO, 0x000f0000); 1402 mdelay(20); 1403 cx_clear(GP0_IO, 0x0000000f); 1404 mdelay(20); 1405 cx_set(GP0_IO, 0x000f000f); 1406 break; 1407 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H: 1408 case CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200: 1409 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000: 1410 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F: 1411 case CX23885_BOARD_COMPRO_VIDEOMATE_E800: 1412 case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200: 1413 /* GPIO-2 xc3028 tuner reset */ 1414 1415 /* The following GPIO's are on the internal AVCore (cx25840) */ 1416 /* GPIO-? zl10353 demod reset */ 1417 1418 /* Put the parts into reset and back */ 1419 cx_set(GP0_IO, 0x00040000); 1420 mdelay(20); 1421 cx_clear(GP0_IO, 0x00000004); 1422 mdelay(20); 1423 cx_set(GP0_IO, 0x00040004); 1424 break; 1425 case CX23885_BOARD_TBS_6920: 1426 case CX23885_BOARD_TBS_6980: 1427 case CX23885_BOARD_TBS_6981: 1428 case CX23885_BOARD_PROF_8000: 1429 cx_write(MC417_CTL, 0x00000036); 1430 cx_write(MC417_OEN, 0x00001000); 1431 cx_set(MC417_RWD, 0x00000002); 1432 mdelay(200); 1433 cx_clear(MC417_RWD, 0x00000800); 1434 mdelay(200); 1435 cx_set(MC417_RWD, 0x00000800); 1436 mdelay(200); 1437 break; 1438 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: 1439 /* GPIO-0 INTA from CiMax1 1440 GPIO-1 INTB from CiMax2 1441 GPIO-2 reset chips 1442 GPIO-3 to GPIO-10 data/addr for CA 1443 GPIO-11 ~CS0 to CiMax1 1444 GPIO-12 ~CS1 to CiMax2 1445 GPIO-13 ADL0 load LSB addr 1446 GPIO-14 ADL1 load MSB addr 1447 GPIO-15 ~RDY from CiMax 1448 GPIO-17 ~RD to CiMax 1449 GPIO-18 ~WR to CiMax 1450 */ 1451 cx_set(GP0_IO, 0x00040000); /* GPIO as out */ 1452 /* GPIO1 and GPIO2 as INTA and INTB from CiMaxes, reset low */ 1453 cx_clear(GP0_IO, 0x00030004); 1454 mdelay(100);/* reset delay */ 1455 cx_set(GP0_IO, 0x00040004); /* GPIO as out, reset high */ 1456 cx_write(MC417_CTL, 0x00000037);/* enable GPIO3-18 pins */ 1457 /* GPIO-15 IN as ~ACK, rest as OUT */ 1458 cx_write(MC417_OEN, 0x00001000); 1459 /* ~RD, ~WR high; ADL0, ADL1 low; ~CS0, ~CS1 high */ 1460 cx_write(MC417_RWD, 0x0000c300); 1461 /* enable irq */ 1462 cx_write(GPIO_ISM, 0x00000000);/* INTERRUPTS active low*/ 1463 break; 1464 case CX23885_BOARD_HAUPPAUGE_HVR1270: 1465 case CX23885_BOARD_HAUPPAUGE_HVR1275: 1466 case CX23885_BOARD_HAUPPAUGE_HVR1255: 1467 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111: 1468 case CX23885_BOARD_HAUPPAUGE_HVR1210: 1469 /* GPIO-5 RF Control: 0 = RF1 Terrestrial, 1 = RF2 Cable */ 1470 /* GPIO-6 I2C Gate which can isolate the demod from the bus */ 1471 /* GPIO-9 Demod reset */ 1472 1473 /* Put the parts into reset and back */ 1474 cx23885_gpio_enable(dev, GPIO_9 | GPIO_6 | GPIO_5, 1); 1475 cx23885_gpio_set(dev, GPIO_9 | GPIO_6 | GPIO_5); 1476 cx23885_gpio_clear(dev, GPIO_9); 1477 mdelay(20); 1478 cx23885_gpio_set(dev, GPIO_9); 1479 break; 1480 case CX23885_BOARD_MYGICA_X8506: 1481 case CX23885_BOARD_MAGICPRO_PROHDTVE2: 1482 case CX23885_BOARD_MYGICA_X8507: 1483 /* GPIO-0 (0)Analog / (1)Digital TV */ 1484 /* GPIO-1 reset XC5000 */ 1485 /* GPIO-2 demod reset */ 1486 cx23885_gpio_enable(dev, GPIO_0 | GPIO_1 | GPIO_2, 1); 1487 cx23885_gpio_clear(dev, GPIO_1 | GPIO_2); 1488 mdelay(100); 1489 cx23885_gpio_set(dev, GPIO_0 | GPIO_1 | GPIO_2); 1490 mdelay(100); 1491 break; 1492 case CX23885_BOARD_MYGICA_X8558PRO: 1493 /* GPIO-0 reset first ATBM8830 */ 1494 /* GPIO-1 reset second ATBM8830 */ 1495 cx23885_gpio_enable(dev, GPIO_0 | GPIO_1, 1); 1496 cx23885_gpio_clear(dev, GPIO_0 | GPIO_1); 1497 mdelay(100); 1498 cx23885_gpio_set(dev, GPIO_0 | GPIO_1); 1499 mdelay(100); 1500 break; 1501 case CX23885_BOARD_HAUPPAUGE_HVR1850: 1502 case CX23885_BOARD_HAUPPAUGE_HVR1290: 1503 /* GPIO-0 656_CLK */ 1504 /* GPIO-1 656_D0 */ 1505 /* GPIO-2 Wake# */ 1506 /* GPIO-3-10 cx23417 data0-7 */ 1507 /* GPIO-11-14 cx23417 addr0-3 */ 1508 /* GPIO-15-18 cx23417 READY, CS, RD, WR */ 1509 /* GPIO-19 IR_RX */ 1510 /* GPIO-20 C_IR_TX */ 1511 /* GPIO-21 I2S DAT */ 1512 /* GPIO-22 I2S WCLK */ 1513 /* GPIO-23 I2S BCLK */ 1514 /* ALT GPIO: EXP GPIO LATCH */ 1515 1516 /* CX23417 GPIO's */ 1517 /* GPIO-14 S5H1411/CX24228 Reset */ 1518 /* GPIO-13 EEPROM write protect */ 1519 mc417_gpio_enable(dev, GPIO_14 | GPIO_13, 1); 1520 1521 /* Put the demod into reset and protect the eeprom */ 1522 mc417_gpio_clear(dev, GPIO_14 | GPIO_13); 1523 mdelay(100); 1524 1525 /* Bring the demod out of reset */ 1526 mc417_gpio_set(dev, GPIO_14); 1527 mdelay(100); 1528 1529 /* CX24228 GPIO */ 1530 /* Connected to IF / Mux */ 1531 break; 1532 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID: 1533 cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */ 1534 break; 1535 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: 1536 /* GPIO-0 ~INT in 1537 GPIO-1 TMS out 1538 GPIO-2 ~reset chips out 1539 GPIO-3 to GPIO-10 data/addr for CA in/out 1540 GPIO-11 ~CS out 1541 GPIO-12 ADDR out 1542 GPIO-13 ~WR out 1543 GPIO-14 ~RD out 1544 GPIO-15 ~RDY in 1545 GPIO-16 TCK out 1546 GPIO-17 TDO in 1547 GPIO-18 TDI out 1548 */ 1549 cx_set(GP0_IO, 0x00060000); /* GPIO-1,2 as out */ 1550 /* GPIO-0 as INT, reset & TMS low */ 1551 cx_clear(GP0_IO, 0x00010006); 1552 mdelay(100);/* reset delay */ 1553 cx_set(GP0_IO, 0x00000004); /* reset high */ 1554 cx_write(MC417_CTL, 0x00000037);/* enable GPIO-3..18 pins */ 1555 /* GPIO-17 is TDO in, GPIO-15 is ~RDY in, rest is out */ 1556 cx_write(MC417_OEN, 0x00005000); 1557 /* ~RD, ~WR high; ADDR low; ~CS high */ 1558 cx_write(MC417_RWD, 0x00000d00); 1559 /* enable irq */ 1560 cx_write(GPIO_ISM, 0x00000000);/* INTERRUPTS active low*/ 1561 break; 1562 case CX23885_BOARD_HAUPPAUGE_HVR4400: 1563 case CX23885_BOARD_HAUPPAUGE_STARBURST: 1564 /* GPIO-8 tda10071 demod reset */ 1565 /* GPIO-9 si2165 demod reset (only HVR4400/HVR5500)*/ 1566 1567 /* Put the parts into reset and back */ 1568 cx23885_gpio_enable(dev, GPIO_8 | GPIO_9, 1); 1569 1570 cx23885_gpio_clear(dev, GPIO_8 | GPIO_9); 1571 mdelay(100); 1572 cx23885_gpio_set(dev, GPIO_8 | GPIO_9); 1573 mdelay(100); 1574 1575 break; 1576 case CX23885_BOARD_AVERMEDIA_HC81R: 1577 cx_clear(MC417_CTL, 1); 1578 /* GPIO-0,1,2 setup direction as output */ 1579 cx_set(GP0_IO, 0x00070000); 1580 mdelay(10); 1581 /* AF9013 demod reset */ 1582 cx_set(GP0_IO, 0x00010001); 1583 mdelay(10); 1584 cx_clear(GP0_IO, 0x00010001); 1585 mdelay(10); 1586 cx_set(GP0_IO, 0x00010001); 1587 mdelay(10); 1588 /* demod tune? */ 1589 cx_clear(GP0_IO, 0x00030003); 1590 mdelay(10); 1591 cx_set(GP0_IO, 0x00020002); 1592 mdelay(10); 1593 cx_set(GP0_IO, 0x00010001); 1594 mdelay(10); 1595 cx_clear(GP0_IO, 0x00020002); 1596 /* XC3028L tuner reset */ 1597 cx_set(GP0_IO, 0x00040004); 1598 cx_clear(GP0_IO, 0x00040004); 1599 cx_set(GP0_IO, 0x00040004); 1600 mdelay(60); 1601 break; 1602 case CX23885_BOARD_DVBSKY_T9580: 1603 case CX23885_BOARD_DVBSKY_S952: 1604 case CX23885_BOARD_DVBSKY_T982: 1605 /* enable GPIO3-18 pins */ 1606 cx_write(MC417_CTL, 0x00000037); 1607 cx23885_gpio_enable(dev, GPIO_2 | GPIO_11, 1); 1608 cx23885_gpio_clear(dev, GPIO_2 | GPIO_11); 1609 mdelay(100); 1610 cx23885_gpio_set(dev, GPIO_2 | GPIO_11); 1611 break; 1612 case CX23885_BOARD_DVBSKY_T980C: 1613 case CX23885_BOARD_DVBSKY_S950C: 1614 case CX23885_BOARD_TT_CT2_4500_CI: 1615 /* 1616 * GPIO-0 INTA from CiMax, input 1617 * GPIO-1 reset CiMax, output, high active 1618 * GPIO-2 reset demod, output, low active 1619 * GPIO-3 to GPIO-10 data/addr for CAM 1620 * GPIO-11 ~CS0 to CiMax1 1621 * GPIO-12 ~CS1 to CiMax2 1622 * GPIO-13 ADL0 load LSB addr 1623 * GPIO-14 ADL1 load MSB addr 1624 * GPIO-15 ~RDY from CiMax 1625 * GPIO-17 ~RD to CiMax 1626 * GPIO-18 ~WR to CiMax 1627 */ 1628 1629 cx_set(GP0_IO, 0x00060002); /* GPIO 1/2 as output */ 1630 cx_clear(GP0_IO, 0x00010004); /* GPIO 0 as input */ 1631 mdelay(100); /* reset delay */ 1632 cx_set(GP0_IO, 0x00060004); /* GPIO as out, reset high */ 1633 cx_clear(GP0_IO, 0x00010002); 1634 cx_write(MC417_CTL, 0x00000037); /* enable GPIO3-18 pins */ 1635 1636 /* GPIO-15 IN as ~ACK, rest as OUT */ 1637 cx_write(MC417_OEN, 0x00001000); 1638 1639 /* ~RD, ~WR high; ADL0, ADL1 low; ~CS0, ~CS1 high */ 1640 cx_write(MC417_RWD, 0x0000c300); 1641 1642 /* enable irq */ 1643 cx_write(GPIO_ISM, 0x00000000); /* INTERRUPTS active low */ 1644 break; 1645 case CX23885_BOARD_DVBSKY_S950: 1646 cx23885_gpio_enable(dev, GPIO_2, 1); 1647 cx23885_gpio_clear(dev, GPIO_2); 1648 msleep(100); 1649 cx23885_gpio_set(dev, GPIO_2); 1650 break; 1651 case CX23885_BOARD_HAUPPAUGE_HVR5525: 1652 /* 1653 * GPIO-00 IR_WIDE 1654 * GPIO-02 wake# 1655 * GPIO-03 VAUX Pres. 1656 * GPIO-07 PROG# 1657 * GPIO-08 SAT_RESN 1658 * GPIO-09 TER_RESN 1659 * GPIO-10 B2_SENSE 1660 * GPIO-11 B1_SENSE 1661 * GPIO-15 IR_LED_STATUS 1662 * GPIO-19 IR_NARROW 1663 * GPIO-20 Blauster1 1664 * ALTGPIO VAUX_SWITCH 1665 * AUX_PLL_CLK : Blaster2 1666 */ 1667 /* Put the parts into reset and back */ 1668 cx23885_gpio_enable(dev, GPIO_8 | GPIO_9, 1); 1669 cx23885_gpio_clear(dev, GPIO_8 | GPIO_9); 1670 msleep(100); 1671 cx23885_gpio_set(dev, GPIO_8 | GPIO_9); 1672 msleep(100); 1673 break; 1674 } 1675} 1676 1677int cx23885_ir_init(struct cx23885_dev *dev) 1678{ 1679 static struct v4l2_subdev_io_pin_config ir_rxtx_pin_cfg[] = { 1680 { 1681 .flags = V4L2_SUBDEV_IO_PIN_INPUT, 1682 .pin = CX23885_PIN_IR_RX_GPIO19, 1683 .function = CX23885_PAD_IR_RX, 1684 .value = 0, 1685 .strength = CX25840_PIN_DRIVE_MEDIUM, 1686 }, { 1687 .flags = V4L2_SUBDEV_IO_PIN_OUTPUT, 1688 .pin = CX23885_PIN_IR_TX_GPIO20, 1689 .function = CX23885_PAD_IR_TX, 1690 .value = 0, 1691 .strength = CX25840_PIN_DRIVE_MEDIUM, 1692 } 1693 }; 1694 const size_t ir_rxtx_pin_cfg_count = ARRAY_SIZE(ir_rxtx_pin_cfg); 1695 1696 static struct v4l2_subdev_io_pin_config ir_rx_pin_cfg[] = { 1697 { 1698 .flags = V4L2_SUBDEV_IO_PIN_INPUT, 1699 .pin = CX23885_PIN_IR_RX_GPIO19, 1700 .function = CX23885_PAD_IR_RX, 1701 .value = 0, 1702 .strength = CX25840_PIN_DRIVE_MEDIUM, 1703 } 1704 }; 1705 const size_t ir_rx_pin_cfg_count = ARRAY_SIZE(ir_rx_pin_cfg); 1706 1707 struct v4l2_subdev_ir_parameters params; 1708 int ret = 0; 1709 switch (dev->board) { 1710 case CX23885_BOARD_HAUPPAUGE_HVR1500: 1711 case CX23885_BOARD_HAUPPAUGE_HVR1500Q: 1712 case CX23885_BOARD_HAUPPAUGE_HVR1800: 1713 case CX23885_BOARD_HAUPPAUGE_HVR1200: 1714 case CX23885_BOARD_HAUPPAUGE_HVR1400: 1715 case CX23885_BOARD_HAUPPAUGE_HVR1275: 1716 case CX23885_BOARD_HAUPPAUGE_HVR1255: 1717 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111: 1718 case CX23885_BOARD_HAUPPAUGE_HVR1210: 1719 /* FIXME: Implement me */ 1720 break; 1721 case CX23885_BOARD_HAUPPAUGE_HVR1270: 1722 ret = cx23888_ir_probe(dev); 1723 if (ret) 1724 break; 1725 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_888_IR); 1726 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config, 1727 ir_rx_pin_cfg_count, ir_rx_pin_cfg); 1728 break; 1729 case CX23885_BOARD_HAUPPAUGE_HVR1850: 1730 case CX23885_BOARD_HAUPPAUGE_HVR1290: 1731 ret = cx23888_ir_probe(dev); 1732 if (ret) 1733 break; 1734 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_888_IR); 1735 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config, 1736 ir_rxtx_pin_cfg_count, ir_rxtx_pin_cfg); 1737 /* 1738 * For these boards we need to invert the Tx output via the 1739 * IR controller to have the LED off while idle 1740 */ 1741 v4l2_subdev_call(dev->sd_ir, ir, tx_g_parameters, ¶ms); 1742 params.enable = false; 1743 params.shutdown = false; 1744 params.invert_level = true; 1745 v4l2_subdev_call(dev->sd_ir, ir, tx_s_parameters, ¶ms); 1746 params.shutdown = true; 1747 v4l2_subdev_call(dev->sd_ir, ir, tx_s_parameters, ¶ms); 1748 break; 1749 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL: 1750 case CX23885_BOARD_TEVII_S470: 1751 case CX23885_BOARD_MYGICA_X8507: 1752 case CX23885_BOARD_TBS_6980: 1753 case CX23885_BOARD_TBS_6981: 1754 case CX23885_BOARD_DVBSKY_T9580: 1755 case CX23885_BOARD_DVBSKY_T980C: 1756 case CX23885_BOARD_DVBSKY_S950C: 1757 case CX23885_BOARD_TT_CT2_4500_CI: 1758 case CX23885_BOARD_DVBSKY_S950: 1759 case CX23885_BOARD_DVBSKY_S952: 1760 case CX23885_BOARD_DVBSKY_T982: 1761 if (!enable_885_ir) 1762 break; 1763 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_AV_CORE); 1764 if (dev->sd_ir == NULL) { 1765 ret = -ENODEV; 1766 break; 1767 } 1768 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config, 1769 ir_rx_pin_cfg_count, ir_rx_pin_cfg); 1770 break; 1771 case CX23885_BOARD_HAUPPAUGE_HVR1250: 1772 if (!enable_885_ir) 1773 break; 1774 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_AV_CORE); 1775 if (dev->sd_ir == NULL) { 1776 ret = -ENODEV; 1777 break; 1778 } 1779 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config, 1780 ir_rxtx_pin_cfg_count, ir_rxtx_pin_cfg); 1781 break; 1782 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: 1783 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2: 1784 request_module("ir-kbd-i2c"); 1785 break; 1786 } 1787 1788 return ret; 1789} 1790 1791void cx23885_ir_fini(struct cx23885_dev *dev) 1792{ 1793 switch (dev->board) { 1794 case CX23885_BOARD_HAUPPAUGE_HVR1270: 1795 case CX23885_BOARD_HAUPPAUGE_HVR1850: 1796 case CX23885_BOARD_HAUPPAUGE_HVR1290: 1797 cx23885_irq_remove(dev, PCI_MSK_IR); 1798 cx23888_ir_remove(dev); 1799 dev->sd_ir = NULL; 1800 break; 1801 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL: 1802 case CX23885_BOARD_TEVII_S470: 1803 case CX23885_BOARD_HAUPPAUGE_HVR1250: 1804 case CX23885_BOARD_MYGICA_X8507: 1805 case CX23885_BOARD_TBS_6980: 1806 case CX23885_BOARD_TBS_6981: 1807 case CX23885_BOARD_DVBSKY_T9580: 1808 case CX23885_BOARD_DVBSKY_T980C: 1809 case CX23885_BOARD_DVBSKY_S950C: 1810 case CX23885_BOARD_TT_CT2_4500_CI: 1811 case CX23885_BOARD_DVBSKY_S950: 1812 case CX23885_BOARD_DVBSKY_S952: 1813 case CX23885_BOARD_DVBSKY_T982: 1814 cx23885_irq_remove(dev, PCI_MSK_AV_CORE); 1815 /* sd_ir is a duplicate pointer to the AV Core, just clear it */ 1816 dev->sd_ir = NULL; 1817 break; 1818 } 1819} 1820 1821static int netup_jtag_io(void *device, int tms, int tdi, int read_tdo) 1822{ 1823 int data; 1824 int tdo = 0; 1825 struct cx23885_dev *dev = (struct cx23885_dev *)device; 1826 /*TMS*/ 1827 data = ((cx_read(GP0_IO)) & (~0x00000002)); 1828 data |= (tms ? 0x00020002 : 0x00020000); 1829 cx_write(GP0_IO, data); 1830 1831 /*TDI*/ 1832 data = ((cx_read(MC417_RWD)) & (~0x0000a000)); 1833 data |= (tdi ? 0x00008000 : 0); 1834 cx_write(MC417_RWD, data); 1835 if (read_tdo) 1836 tdo = (data & 0x00004000) ? 1 : 0; /*TDO*/ 1837 1838 cx_write(MC417_RWD, data | 0x00002000); 1839 udelay(1); 1840 /*TCK*/ 1841 cx_write(MC417_RWD, data); 1842 1843 return tdo; 1844} 1845 1846void cx23885_ir_pci_int_enable(struct cx23885_dev *dev) 1847{ 1848 switch (dev->board) { 1849 case CX23885_BOARD_HAUPPAUGE_HVR1270: 1850 case CX23885_BOARD_HAUPPAUGE_HVR1850: 1851 case CX23885_BOARD_HAUPPAUGE_HVR1290: 1852 if (dev->sd_ir) 1853 cx23885_irq_add_enable(dev, PCI_MSK_IR); 1854 break; 1855 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL: 1856 case CX23885_BOARD_TEVII_S470: 1857 case CX23885_BOARD_HAUPPAUGE_HVR1250: 1858 case CX23885_BOARD_MYGICA_X8507: 1859 case CX23885_BOARD_TBS_6980: 1860 case CX23885_BOARD_TBS_6981: 1861 case CX23885_BOARD_DVBSKY_T9580: 1862 case CX23885_BOARD_DVBSKY_T980C: 1863 case CX23885_BOARD_DVBSKY_S950C: 1864 case CX23885_BOARD_TT_CT2_4500_CI: 1865 case CX23885_BOARD_DVBSKY_S950: 1866 case CX23885_BOARD_DVBSKY_S952: 1867 case CX23885_BOARD_DVBSKY_T982: 1868 if (dev->sd_ir) 1869 cx23885_irq_add_enable(dev, PCI_MSK_AV_CORE); 1870 break; 1871 } 1872} 1873 1874void cx23885_card_setup(struct cx23885_dev *dev) 1875{ 1876 struct cx23885_tsport *ts1 = &dev->ts1; 1877 struct cx23885_tsport *ts2 = &dev->ts2; 1878 1879 static u8 eeprom[256]; 1880 1881 if (dev->i2c_bus[0].i2c_rc == 0) { 1882 dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1; 1883 tveeprom_read(&dev->i2c_bus[0].i2c_client, 1884 eeprom, sizeof(eeprom)); 1885 } 1886 1887 switch (dev->board) { 1888 case CX23885_BOARD_HAUPPAUGE_HVR1250: 1889 if (dev->i2c_bus[0].i2c_rc == 0) { 1890 if (eeprom[0x80] != 0x84) 1891 hauppauge_eeprom(dev, eeprom+0xc0); 1892 else 1893 hauppauge_eeprom(dev, eeprom+0x80); 1894 } 1895 break; 1896 case CX23885_BOARD_HAUPPAUGE_HVR1500: 1897 case CX23885_BOARD_HAUPPAUGE_HVR1500Q: 1898 case CX23885_BOARD_HAUPPAUGE_HVR1400: 1899 if (dev->i2c_bus[0].i2c_rc == 0) 1900 hauppauge_eeprom(dev, eeprom+0x80); 1901 break; 1902 case CX23885_BOARD_HAUPPAUGE_HVR1800: 1903 case CX23885_BOARD_HAUPPAUGE_HVR1800lp: 1904 case CX23885_BOARD_HAUPPAUGE_HVR1200: 1905 case CX23885_BOARD_HAUPPAUGE_HVR1700: 1906 case CX23885_BOARD_HAUPPAUGE_HVR1270: 1907 case CX23885_BOARD_HAUPPAUGE_HVR1275: 1908 case CX23885_BOARD_HAUPPAUGE_HVR1255: 1909 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111: 1910 case CX23885_BOARD_HAUPPAUGE_HVR1210: 1911 case CX23885_BOARD_HAUPPAUGE_HVR1850: 1912 case CX23885_BOARD_HAUPPAUGE_HVR1290: 1913 case CX23885_BOARD_HAUPPAUGE_HVR4400: 1914 case CX23885_BOARD_HAUPPAUGE_STARBURST: 1915 case CX23885_BOARD_HAUPPAUGE_IMPACTVCBE: 1916 case CX23885_BOARD_HAUPPAUGE_HVR5525: 1917 if (dev->i2c_bus[0].i2c_rc == 0) 1918 hauppauge_eeprom(dev, eeprom+0xc0); 1919 break; 1920 } 1921 1922 switch (dev->board) { 1923 case CX23885_BOARD_AVERMEDIA_HC81R: 1924 /* Defaults for VID B */ 1925 ts1->gen_ctrl_val = 0x4; /* Parallel */ 1926 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1927 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1928 /* Defaults for VID C */ 1929 /* DREQ_POL, SMODE, PUNC_CLK, MCLK_POL Serial bus + punc clk */ 1930 ts2->gen_ctrl_val = 0x10e; 1931 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1932 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1933 break; 1934 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP: 1935 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: 1936 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2: 1937 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 1938 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1939 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1940 /* break omitted intentionally */ 1941 case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP: 1942 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 1943 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1944 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1945 break; 1946 case CX23885_BOARD_HAUPPAUGE_HVR1850: 1947 case CX23885_BOARD_HAUPPAUGE_HVR1800: 1948 /* Defaults for VID B - Analog encoder */ 1949 /* DREQ_POL, SMODE, PUNC_CLK, MCLK_POL Serial bus + punc clk */ 1950 ts1->gen_ctrl_val = 0x10e; 1951 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1952 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1953 1954 /* APB_TSVALERR_POL (active low)*/ 1955 ts1->vld_misc_val = 0x2000; 1956 ts1->hw_sop_ctrl_val = (0x47 << 16 | 188 << 4 | 0xc); 1957 cx_write(0x130184, 0xc); 1958 1959 /* Defaults for VID C */ 1960 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 1961 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1962 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1963 break; 1964 case CX23885_BOARD_TBS_6920: 1965 ts1->gen_ctrl_val = 0x4; /* Parallel */ 1966 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1967 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1968 break; 1969 case CX23885_BOARD_TEVII_S470: 1970 case CX23885_BOARD_TEVII_S471: 1971 case CX23885_BOARD_DVBWORLD_2005: 1972 case CX23885_BOARD_PROF_8000: 1973 case CX23885_BOARD_DVBSKY_T980C: 1974 case CX23885_BOARD_DVBSKY_S950C: 1975 case CX23885_BOARD_TT_CT2_4500_CI: 1976 case CX23885_BOARD_DVBSKY_S950: 1977 ts1->gen_ctrl_val = 0x5; /* Parallel */ 1978 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1979 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1980 break; 1981 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: 1982 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: 1983 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL: 1984 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 1985 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1986 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1987 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 1988 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1989 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1990 break; 1991 case CX23885_BOARD_TBS_6980: 1992 case CX23885_BOARD_TBS_6981: 1993 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 1994 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1995 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1996 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 1997 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1998 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1999 tbs_card_init(dev); 2000 break; 2001 case CX23885_BOARD_MYGICA_X8506: 2002 case CX23885_BOARD_MAGICPRO_PROHDTVE2: 2003 case CX23885_BOARD_MYGICA_X8507: 2004 ts1->gen_ctrl_val = 0x5; /* Parallel */ 2005 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2006 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2007 break; 2008 case CX23885_BOARD_MYGICA_X8558PRO: 2009 ts1->gen_ctrl_val = 0x5; /* Parallel */ 2010 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2011 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2012 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 2013 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2014 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2015 break; 2016 case CX23885_BOARD_HAUPPAUGE_HVR4400: 2017 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 2018 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2019 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2020 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 2021 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2022 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2023 break; 2024 case CX23885_BOARD_HAUPPAUGE_STARBURST: 2025 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 2026 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2027 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2028 break; 2029 case CX23885_BOARD_DVBSKY_T9580: 2030 case CX23885_BOARD_DVBSKY_T982: 2031 ts1->gen_ctrl_val = 0x5; /* Parallel */ 2032 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2033 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2034 ts2->gen_ctrl_val = 0x8; /* Serial bus */ 2035 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2036 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2037 break; 2038 case CX23885_BOARD_DVBSKY_S952: 2039 ts1->gen_ctrl_val = 0x5; /* Parallel */ 2040 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2041 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2042 ts2->gen_ctrl_val = 0xe; /* Serial bus */ 2043 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2044 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2045 break; 2046 case CX23885_BOARD_HAUPPAUGE_HVR5525: 2047 ts1->gen_ctrl_val = 0x5; /* Parallel */ 2048 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2049 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2050 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 2051 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2052 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2053 break; 2054 case CX23885_BOARD_HAUPPAUGE_HVR1250: 2055 case CX23885_BOARD_HAUPPAUGE_HVR1500: 2056 case CX23885_BOARD_HAUPPAUGE_HVR1500Q: 2057 case CX23885_BOARD_HAUPPAUGE_HVR1800lp: 2058 case CX23885_BOARD_HAUPPAUGE_HVR1200: 2059 case CX23885_BOARD_HAUPPAUGE_HVR1700: 2060 case CX23885_BOARD_HAUPPAUGE_HVR1400: 2061 case CX23885_BOARD_HAUPPAUGE_IMPACTVCBE: 2062 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H: 2063 case CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200: 2064 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000: 2065 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F: 2066 case CX23885_BOARD_HAUPPAUGE_HVR1270: 2067 case CX23885_BOARD_HAUPPAUGE_HVR1275: 2068 case CX23885_BOARD_HAUPPAUGE_HVR1255: 2069 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111: 2070 case CX23885_BOARD_HAUPPAUGE_HVR1210: 2071 case CX23885_BOARD_COMPRO_VIDEOMATE_E800: 2072 case CX23885_BOARD_HAUPPAUGE_HVR1290: 2073 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID: 2074 default: 2075 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 2076 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2077 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2078 } 2079 2080 /* Certain boards support analog, or require the avcore to be 2081 * loaded, ensure this happens. 2082 */ 2083 switch (dev->board) { 2084 case CX23885_BOARD_TEVII_S470: 2085 /* Currently only enabled for the integrated IR controller */ 2086 if (!enable_885_ir) 2087 break; 2088 case CX23885_BOARD_HAUPPAUGE_HVR1250: 2089 case CX23885_BOARD_HAUPPAUGE_HVR1800: 2090 case CX23885_BOARD_HAUPPAUGE_IMPACTVCBE: 2091 case CX23885_BOARD_HAUPPAUGE_HVR1800lp: 2092 case CX23885_BOARD_HAUPPAUGE_HVR1700: 2093 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H: 2094 case CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200: 2095 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000: 2096 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F: 2097 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: 2098 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: 2099 case CX23885_BOARD_COMPRO_VIDEOMATE_E800: 2100 case CX23885_BOARD_HAUPPAUGE_HVR1255: 2101 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111: 2102 case CX23885_BOARD_HAUPPAUGE_HVR1270: 2103 case CX23885_BOARD_HAUPPAUGE_HVR1850: 2104 case CX23885_BOARD_MYGICA_X8506: 2105 case CX23885_BOARD_MAGICPRO_PROHDTVE2: 2106 case CX23885_BOARD_HAUPPAUGE_HVR1290: 2107 case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200: 2108 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID: 2109 case CX23885_BOARD_HAUPPAUGE_HVR1500: 2110 case CX23885_BOARD_MPX885: 2111 case CX23885_BOARD_MYGICA_X8507: 2112 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL: 2113 case CX23885_BOARD_AVERMEDIA_HC81R: 2114 case CX23885_BOARD_TBS_6980: 2115 case CX23885_BOARD_TBS_6981: 2116 case CX23885_BOARD_DVBSKY_T9580: 2117 case CX23885_BOARD_DVBSKY_T980C: 2118 case CX23885_BOARD_DVBSKY_S950C: 2119 case CX23885_BOARD_TT_CT2_4500_CI: 2120 case CX23885_BOARD_DVBSKY_S950: 2121 case CX23885_BOARD_DVBSKY_S952: 2122 case CX23885_BOARD_DVBSKY_T982: 2123 dev->sd_cx25840 = v4l2_i2c_new_subdev(&dev->v4l2_dev, 2124 &dev->i2c_bus[2].i2c_adap, 2125 "cx25840", 0x88 >> 1, NULL); 2126 if (dev->sd_cx25840) { 2127 dev->sd_cx25840->grp_id = CX23885_HW_AV_CORE; 2128 v4l2_subdev_call(dev->sd_cx25840, core, load_fw); 2129 } 2130 break; 2131 } 2132 2133 /* AUX-PLL 27MHz CLK */ 2134 switch (dev->board) { 2135 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: 2136 netup_initialize(dev); 2137 break; 2138 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: { 2139 int ret; 2140 const struct firmware *fw; 2141 const char *filename = "dvb-netup-altera-01.fw"; 2142 char *action = "configure"; 2143 static struct netup_card_info cinfo; 2144 struct altera_config netup_config = { 2145 .dev = dev, 2146 .action = action, 2147 .jtag_io = netup_jtag_io, 2148 }; 2149 2150 netup_initialize(dev); 2151 2152 netup_get_card_info(&dev->i2c_bus[0].i2c_adap, &cinfo); 2153 if (netup_card_rev) 2154 cinfo.rev = netup_card_rev; 2155 2156 switch (cinfo.rev) { 2157 case 0x4: 2158 filename = "dvb-netup-altera-04.fw"; 2159 break; 2160 default: 2161 filename = "dvb-netup-altera-01.fw"; 2162 break; 2163 } 2164 printk(KERN_INFO "NetUP card rev=0x%x fw_filename=%s\n", 2165 cinfo.rev, filename); 2166 2167 ret = request_firmware(&fw, filename, &dev->pci->dev); 2168 if (ret != 0) 2169 printk(KERN_ERR "did not find the firmware file. (%s) " 2170 "Please see linux/Documentation/dvb/ for more details " 2171 "on firmware-problems.", filename); 2172 else 2173 altera_init(&netup_config, fw); 2174 2175 release_firmware(fw); 2176 break; 2177 } 2178 } 2179} 2180