1/* 2 * ov2640 Camera Driver 3 * 4 * Copyright (C) 2010 Alberto Panizzo <maramaopercheseimorto@gmail.com> 5 * 6 * Based on ov772x, ov9640 drivers and previous non merged implementations. 7 * 8 * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved. 9 * Copyright (C) 2006, OmniVision 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 */ 15 16#include <linux/init.h> 17#include <linux/module.h> 18#include <linux/i2c.h> 19#include <linux/slab.h> 20#include <linux/delay.h> 21#include <linux/gpio.h> 22#include <linux/gpio/consumer.h> 23#include <linux/of_gpio.h> 24#include <linux/v4l2-mediabus.h> 25#include <linux/videodev2.h> 26 27#include <media/soc_camera.h> 28#include <media/v4l2-clk.h> 29#include <media/v4l2-subdev.h> 30#include <media/v4l2-ctrls.h> 31#include <media/v4l2-image-sizes.h> 32 33#define VAL_SET(x, mask, rshift, lshift) \ 34 ((((x) >> rshift) & mask) << lshift) 35/* 36 * DSP registers 37 * register offset for BANK_SEL == BANK_SEL_DSP 38 */ 39#define R_BYPASS 0x05 /* Bypass DSP */ 40#define R_BYPASS_DSP_BYPAS 0x01 /* Bypass DSP, sensor out directly */ 41#define R_BYPASS_USE_DSP 0x00 /* Use the internal DSP */ 42#define QS 0x44 /* Quantization Scale Factor */ 43#define CTRLI 0x50 44#define CTRLI_LP_DP 0x80 45#define CTRLI_ROUND 0x40 46#define CTRLI_V_DIV_SET(x) VAL_SET(x, 0x3, 0, 3) 47#define CTRLI_H_DIV_SET(x) VAL_SET(x, 0x3, 0, 0) 48#define HSIZE 0x51 /* H_SIZE[7:0] (real/4) */ 49#define HSIZE_SET(x) VAL_SET(x, 0xFF, 2, 0) 50#define VSIZE 0x52 /* V_SIZE[7:0] (real/4) */ 51#define VSIZE_SET(x) VAL_SET(x, 0xFF, 2, 0) 52#define XOFFL 0x53 /* OFFSET_X[7:0] */ 53#define XOFFL_SET(x) VAL_SET(x, 0xFF, 0, 0) 54#define YOFFL 0x54 /* OFFSET_Y[7:0] */ 55#define YOFFL_SET(x) VAL_SET(x, 0xFF, 0, 0) 56#define VHYX 0x55 /* Offset and size completion */ 57#define VHYX_VSIZE_SET(x) VAL_SET(x, 0x1, (8+2), 7) 58#define VHYX_HSIZE_SET(x) VAL_SET(x, 0x1, (8+2), 3) 59#define VHYX_YOFF_SET(x) VAL_SET(x, 0x3, 8, 4) 60#define VHYX_XOFF_SET(x) VAL_SET(x, 0x3, 8, 0) 61#define DPRP 0x56 62#define TEST 0x57 /* Horizontal size completion */ 63#define TEST_HSIZE_SET(x) VAL_SET(x, 0x1, (9+2), 7) 64#define ZMOW 0x5A /* Zoom: Out Width OUTW[7:0] (real/4) */ 65#define ZMOW_OUTW_SET(x) VAL_SET(x, 0xFF, 2, 0) 66#define ZMOH 0x5B /* Zoom: Out Height OUTH[7:0] (real/4) */ 67#define ZMOH_OUTH_SET(x) VAL_SET(x, 0xFF, 2, 0) 68#define ZMHH 0x5C /* Zoom: Speed and H&W completion */ 69#define ZMHH_ZSPEED_SET(x) VAL_SET(x, 0x0F, 0, 4) 70#define ZMHH_OUTH_SET(x) VAL_SET(x, 0x1, (8+2), 2) 71#define ZMHH_OUTW_SET(x) VAL_SET(x, 0x3, (8+2), 0) 72#define BPADDR 0x7C /* SDE Indirect Register Access: Address */ 73#define BPDATA 0x7D /* SDE Indirect Register Access: Data */ 74#define CTRL2 0x86 /* DSP Module enable 2 */ 75#define CTRL2_DCW_EN 0x20 76#define CTRL2_SDE_EN 0x10 77#define CTRL2_UV_ADJ_EN 0x08 78#define CTRL2_UV_AVG_EN 0x04 79#define CTRL2_CMX_EN 0x01 80#define CTRL3 0x87 /* DSP Module enable 3 */ 81#define CTRL3_BPC_EN 0x80 82#define CTRL3_WPC_EN 0x40 83#define SIZEL 0x8C /* Image Size Completion */ 84#define SIZEL_HSIZE8_11_SET(x) VAL_SET(x, 0x1, 11, 6) 85#define SIZEL_HSIZE8_SET(x) VAL_SET(x, 0x7, 0, 3) 86#define SIZEL_VSIZE8_SET(x) VAL_SET(x, 0x7, 0, 0) 87#define HSIZE8 0xC0 /* Image Horizontal Size HSIZE[10:3] */ 88#define HSIZE8_SET(x) VAL_SET(x, 0xFF, 3, 0) 89#define VSIZE8 0xC1 /* Image Vertical Size VSIZE[10:3] */ 90#define VSIZE8_SET(x) VAL_SET(x, 0xFF, 3, 0) 91#define CTRL0 0xC2 /* DSP Module enable 0 */ 92#define CTRL0_AEC_EN 0x80 93#define CTRL0_AEC_SEL 0x40 94#define CTRL0_STAT_SEL 0x20 95#define CTRL0_VFIRST 0x10 96#define CTRL0_YUV422 0x08 97#define CTRL0_YUV_EN 0x04 98#define CTRL0_RGB_EN 0x02 99#define CTRL0_RAW_EN 0x01 100#define CTRL1 0xC3 /* DSP Module enable 1 */ 101#define CTRL1_CIP 0x80 102#define CTRL1_DMY 0x40 103#define CTRL1_RAW_GMA 0x20 104#define CTRL1_DG 0x10 105#define CTRL1_AWB 0x08 106#define CTRL1_AWB_GAIN 0x04 107#define CTRL1_LENC 0x02 108#define CTRL1_PRE 0x01 109#define R_DVP_SP 0xD3 /* DVP output speed control */ 110#define R_DVP_SP_AUTO_MODE 0x80 111#define R_DVP_SP_DVP_MASK 0x3F /* DVP PCLK = sysclk (48)/[6:0] (YUV0); 112 * = sysclk (48)/(2*[6:0]) (RAW);*/ 113#define IMAGE_MODE 0xDA /* Image Output Format Select */ 114#define IMAGE_MODE_Y8_DVP_EN 0x40 115#define IMAGE_MODE_JPEG_EN 0x10 116#define IMAGE_MODE_YUV422 0x00 117#define IMAGE_MODE_RAW10 0x04 /* (DVP) */ 118#define IMAGE_MODE_RGB565 0x08 119#define IMAGE_MODE_HREF_VSYNC 0x02 /* HREF timing select in DVP JPEG output 120 * mode (0 for HREF is same as sensor) */ 121#define IMAGE_MODE_LBYTE_FIRST 0x01 /* Byte swap enable for DVP 122 * 1: Low byte first UYVY (C2[4] =0) 123 * VYUY (C2[4] =1) 124 * 0: High byte first YUYV (C2[4]=0) 125 * YVYU (C2[4] = 1) */ 126#define RESET 0xE0 /* Reset */ 127#define RESET_MICROC 0x40 128#define RESET_SCCB 0x20 129#define RESET_JPEG 0x10 130#define RESET_DVP 0x04 131#define RESET_IPU 0x02 132#define RESET_CIF 0x01 133#define REGED 0xED /* Register ED */ 134#define REGED_CLK_OUT_DIS 0x10 135#define MS_SP 0xF0 /* SCCB Master Speed */ 136#define SS_ID 0xF7 /* SCCB Slave ID */ 137#define SS_CTRL 0xF8 /* SCCB Slave Control */ 138#define SS_CTRL_ADD_AUTO_INC 0x20 139#define SS_CTRL_EN 0x08 140#define SS_CTRL_DELAY_CLK 0x04 141#define SS_CTRL_ACC_EN 0x02 142#define SS_CTRL_SEN_PASS_THR 0x01 143#define MC_BIST 0xF9 /* Microcontroller misc register */ 144#define MC_BIST_RESET 0x80 /* Microcontroller Reset */ 145#define MC_BIST_BOOT_ROM_SEL 0x40 146#define MC_BIST_12KB_SEL 0x20 147#define MC_BIST_12KB_MASK 0x30 148#define MC_BIST_512KB_SEL 0x08 149#define MC_BIST_512KB_MASK 0x0C 150#define MC_BIST_BUSY_BIT_R 0x02 151#define MC_BIST_MC_RES_ONE_SH_W 0x02 152#define MC_BIST_LAUNCH 0x01 153#define BANK_SEL 0xFF /* Register Bank Select */ 154#define BANK_SEL_DSP 0x00 155#define BANK_SEL_SENS 0x01 156 157/* 158 * Sensor registers 159 * register offset for BANK_SEL == BANK_SEL_SENS 160 */ 161#define GAIN 0x00 /* AGC - Gain control gain setting */ 162#define COM1 0x03 /* Common control 1 */ 163#define COM1_1_DUMMY_FR 0x40 164#define COM1_3_DUMMY_FR 0x80 165#define COM1_7_DUMMY_FR 0xC0 166#define COM1_VWIN_LSB_UXGA 0x0F 167#define COM1_VWIN_LSB_SVGA 0x0A 168#define COM1_VWIN_LSB_CIF 0x06 169#define REG04 0x04 /* Register 04 */ 170#define REG04_DEF 0x20 /* Always set */ 171#define REG04_HFLIP_IMG 0x80 /* Horizontal mirror image ON/OFF */ 172#define REG04_VFLIP_IMG 0x40 /* Vertical flip image ON/OFF */ 173#define REG04_VREF_EN 0x10 174#define REG04_HREF_EN 0x08 175#define REG04_AEC_SET(x) VAL_SET(x, 0x3, 0, 0) 176#define REG08 0x08 /* Frame Exposure One-pin Control Pre-charge Row Num */ 177#define COM2 0x09 /* Common control 2 */ 178#define COM2_SOFT_SLEEP_MODE 0x10 /* Soft sleep mode */ 179 /* Output drive capability */ 180#define COM2_OCAP_Nx_SET(N) (((N) - 1) & 0x03) /* N = [1x .. 4x] */ 181#define PID 0x0A /* Product ID Number MSB */ 182#define VER 0x0B /* Product ID Number LSB */ 183#define COM3 0x0C /* Common control 3 */ 184#define COM3_BAND_50H 0x04 /* 0 For Banding at 60H */ 185#define COM3_BAND_AUTO 0x02 /* Auto Banding */ 186#define COM3_SING_FR_SNAPSH 0x01 /* 0 For enable live video output after the 187 * snapshot sequence*/ 188#define AEC 0x10 /* AEC[9:2] Exposure Value */ 189#define CLKRC 0x11 /* Internal clock */ 190#define CLKRC_EN 0x80 191#define CLKRC_DIV_SET(x) (((x) - 1) & 0x1F) /* CLK = XVCLK/(x) */ 192#define COM7 0x12 /* Common control 7 */ 193#define COM7_SRST 0x80 /* Initiates system reset. All registers are 194 * set to factory default values after which 195 * the chip resumes normal operation */ 196#define COM7_RES_UXGA 0x00 /* Resolution selectors for UXGA */ 197#define COM7_RES_SVGA 0x40 /* SVGA */ 198#define COM7_RES_CIF 0x20 /* CIF */ 199#define COM7_ZOOM_EN 0x04 /* Enable Zoom mode */ 200#define COM7_COLOR_BAR_TEST 0x02 /* Enable Color Bar Test Pattern */ 201#define COM8 0x13 /* Common control 8 */ 202#define COM8_DEF 0xC0 /* Banding filter ON/OFF */ 203#define COM8_BNDF_EN 0x20 /* Banding filter ON/OFF */ 204#define COM8_AGC_EN 0x04 /* AGC Auto/Manual control selection */ 205#define COM8_AEC_EN 0x01 /* Auto/Manual Exposure control */ 206#define COM9 0x14 /* Common control 9 207 * Automatic gain ceiling - maximum AGC value [7:5]*/ 208#define COM9_AGC_GAIN_2x 0x00 /* 000 : 2x */ 209#define COM9_AGC_GAIN_4x 0x20 /* 001 : 4x */ 210#define COM9_AGC_GAIN_8x 0x40 /* 010 : 8x */ 211#define COM9_AGC_GAIN_16x 0x60 /* 011 : 16x */ 212#define COM9_AGC_GAIN_32x 0x80 /* 100 : 32x */ 213#define COM9_AGC_GAIN_64x 0xA0 /* 101 : 64x */ 214#define COM9_AGC_GAIN_128x 0xC0 /* 110 : 128x */ 215#define COM10 0x15 /* Common control 10 */ 216#define COM10_PCLK_HREF 0x20 /* PCLK output qualified by HREF */ 217#define COM10_PCLK_RISE 0x10 /* Data is updated at the rising edge of 218 * PCLK (user can latch data at the next 219 * falling edge of PCLK). 220 * 0 otherwise. */ 221#define COM10_HREF_INV 0x08 /* Invert HREF polarity: 222 * HREF negative for valid data*/ 223#define COM10_VSINC_INV 0x02 /* Invert VSYNC polarity */ 224#define HSTART 0x17 /* Horizontal Window start MSB 8 bit */ 225#define HEND 0x18 /* Horizontal Window end MSB 8 bit */ 226#define VSTART 0x19 /* Vertical Window start MSB 8 bit */ 227#define VEND 0x1A /* Vertical Window end MSB 8 bit */ 228#define MIDH 0x1C /* Manufacturer ID byte - high */ 229#define MIDL 0x1D /* Manufacturer ID byte - low */ 230#define AEW 0x24 /* AGC/AEC - Stable operating region (upper limit) */ 231#define AEB 0x25 /* AGC/AEC - Stable operating region (lower limit) */ 232#define VV 0x26 /* AGC/AEC Fast mode operating region */ 233#define VV_HIGH_TH_SET(x) VAL_SET(x, 0xF, 0, 4) 234#define VV_LOW_TH_SET(x) VAL_SET(x, 0xF, 0, 0) 235#define REG2A 0x2A /* Dummy pixel insert MSB */ 236#define FRARL 0x2B /* Dummy pixel insert LSB */ 237#define ADDVFL 0x2D /* LSB of insert dummy lines in Vertical direction */ 238#define ADDVFH 0x2E /* MSB of insert dummy lines in Vertical direction */ 239#define YAVG 0x2F /* Y/G Channel Average value */ 240#define REG32 0x32 /* Common Control 32 */ 241#define REG32_PCLK_DIV_2 0x80 /* PCLK freq divided by 2 */ 242#define REG32_PCLK_DIV_4 0xC0 /* PCLK freq divided by 4 */ 243#define ARCOM2 0x34 /* Zoom: Horizontal start point */ 244#define REG45 0x45 /* Register 45 */ 245#define FLL 0x46 /* Frame Length Adjustment LSBs */ 246#define FLH 0x47 /* Frame Length Adjustment MSBs */ 247#define COM19 0x48 /* Zoom: Vertical start point */ 248#define ZOOMS 0x49 /* Zoom: Vertical start point */ 249#define COM22 0x4B /* Flash light control */ 250#define COM25 0x4E /* For Banding operations */ 251#define BD50 0x4F /* 50Hz Banding AEC 8 LSBs */ 252#define BD60 0x50 /* 60Hz Banding AEC 8 LSBs */ 253#define REG5D 0x5D /* AVGsel[7:0], 16-zone average weight option */ 254#define REG5E 0x5E /* AVGsel[15:8], 16-zone average weight option */ 255#define REG5F 0x5F /* AVGsel[23:16], 16-zone average weight option */ 256#define REG60 0x60 /* AVGsel[31:24], 16-zone average weight option */ 257#define HISTO_LOW 0x61 /* Histogram Algorithm Low Level */ 258#define HISTO_HIGH 0x62 /* Histogram Algorithm High Level */ 259 260/* 261 * ID 262 */ 263#define MANUFACTURER_ID 0x7FA2 264#define PID_OV2640 0x2642 265#define VERSION(pid, ver) ((pid << 8) | (ver & 0xFF)) 266 267/* 268 * Struct 269 */ 270struct regval_list { 271 u8 reg_num; 272 u8 value; 273}; 274 275struct ov2640_win_size { 276 char *name; 277 u32 width; 278 u32 height; 279 const struct regval_list *regs; 280}; 281 282 283struct ov2640_priv { 284 struct v4l2_subdev subdev; 285 struct v4l2_ctrl_handler hdl; 286 u32 cfmt_code; 287 struct v4l2_clk *clk; 288 const struct ov2640_win_size *win; 289 290 struct soc_camera_subdev_desc ssdd_dt; 291 struct gpio_desc *resetb_gpio; 292 struct gpio_desc *pwdn_gpio; 293}; 294 295/* 296 * Registers settings 297 */ 298 299#define ENDMARKER { 0xff, 0xff } 300 301static const struct regval_list ov2640_init_regs[] = { 302 { BANK_SEL, BANK_SEL_DSP }, 303 { 0x2c, 0xff }, 304 { 0x2e, 0xdf }, 305 { BANK_SEL, BANK_SEL_SENS }, 306 { 0x3c, 0x32 }, 307 { CLKRC, CLKRC_DIV_SET(1) }, 308 { COM2, COM2_OCAP_Nx_SET(3) }, 309 { REG04, REG04_DEF | REG04_HREF_EN }, 310 { COM8, COM8_DEF | COM8_BNDF_EN | COM8_AGC_EN | COM8_AEC_EN }, 311 { COM9, COM9_AGC_GAIN_8x | 0x08}, 312 { 0x2c, 0x0c }, 313 { 0x33, 0x78 }, 314 { 0x3a, 0x33 }, 315 { 0x3b, 0xfb }, 316 { 0x3e, 0x00 }, 317 { 0x43, 0x11 }, 318 { 0x16, 0x10 }, 319 { 0x39, 0x02 }, 320 { 0x35, 0x88 }, 321 { 0x22, 0x0a }, 322 { 0x37, 0x40 }, 323 { 0x23, 0x00 }, 324 { ARCOM2, 0xa0 }, 325 { 0x06, 0x02 }, 326 { 0x06, 0x88 }, 327 { 0x07, 0xc0 }, 328 { 0x0d, 0xb7 }, 329 { 0x0e, 0x01 }, 330 { 0x4c, 0x00 }, 331 { 0x4a, 0x81 }, 332 { 0x21, 0x99 }, 333 { AEW, 0x40 }, 334 { AEB, 0x38 }, 335 { VV, VV_HIGH_TH_SET(0x08) | VV_LOW_TH_SET(0x02) }, 336 { 0x5c, 0x00 }, 337 { 0x63, 0x00 }, 338 { FLL, 0x22 }, 339 { COM3, 0x38 | COM3_BAND_AUTO }, 340 { REG5D, 0x55 }, 341 { REG5E, 0x7d }, 342 { REG5F, 0x7d }, 343 { REG60, 0x55 }, 344 { HISTO_LOW, 0x70 }, 345 { HISTO_HIGH, 0x80 }, 346 { 0x7c, 0x05 }, 347 { 0x20, 0x80 }, 348 { 0x28, 0x30 }, 349 { 0x6c, 0x00 }, 350 { 0x6d, 0x80 }, 351 { 0x6e, 0x00 }, 352 { 0x70, 0x02 }, 353 { 0x71, 0x94 }, 354 { 0x73, 0xc1 }, 355 { 0x3d, 0x34 }, 356 { COM7, COM7_RES_UXGA | COM7_ZOOM_EN }, 357 { 0x5a, 0x57 }, 358 { BD50, 0xbb }, 359 { BD60, 0x9c }, 360 { BANK_SEL, BANK_SEL_DSP }, 361 { 0xe5, 0x7f }, 362 { MC_BIST, MC_BIST_RESET | MC_BIST_BOOT_ROM_SEL }, 363 { 0x41, 0x24 }, 364 { RESET, RESET_JPEG | RESET_DVP }, 365 { 0x76, 0xff }, 366 { 0x33, 0xa0 }, 367 { 0x42, 0x20 }, 368 { 0x43, 0x18 }, 369 { 0x4c, 0x00 }, 370 { CTRL3, CTRL3_BPC_EN | CTRL3_WPC_EN | 0x10 }, 371 { 0x88, 0x3f }, 372 { 0xd7, 0x03 }, 373 { 0xd9, 0x10 }, 374 { R_DVP_SP , R_DVP_SP_AUTO_MODE | 0x2 }, 375 { 0xc8, 0x08 }, 376 { 0xc9, 0x80 }, 377 { BPADDR, 0x00 }, 378 { BPDATA, 0x00 }, 379 { BPADDR, 0x03 }, 380 { BPDATA, 0x48 }, 381 { BPDATA, 0x48 }, 382 { BPADDR, 0x08 }, 383 { BPDATA, 0x20 }, 384 { BPDATA, 0x10 }, 385 { BPDATA, 0x0e }, 386 { 0x90, 0x00 }, 387 { 0x91, 0x0e }, 388 { 0x91, 0x1a }, 389 { 0x91, 0x31 }, 390 { 0x91, 0x5a }, 391 { 0x91, 0x69 }, 392 { 0x91, 0x75 }, 393 { 0x91, 0x7e }, 394 { 0x91, 0x88 }, 395 { 0x91, 0x8f }, 396 { 0x91, 0x96 }, 397 { 0x91, 0xa3 }, 398 { 0x91, 0xaf }, 399 { 0x91, 0xc4 }, 400 { 0x91, 0xd7 }, 401 { 0x91, 0xe8 }, 402 { 0x91, 0x20 }, 403 { 0x92, 0x00 }, 404 { 0x93, 0x06 }, 405 { 0x93, 0xe3 }, 406 { 0x93, 0x03 }, 407 { 0x93, 0x03 }, 408 { 0x93, 0x00 }, 409 { 0x93, 0x02 }, 410 { 0x93, 0x00 }, 411 { 0x93, 0x00 }, 412 { 0x93, 0x00 }, 413 { 0x93, 0x00 }, 414 { 0x93, 0x00 }, 415 { 0x93, 0x00 }, 416 { 0x93, 0x00 }, 417 { 0x96, 0x00 }, 418 { 0x97, 0x08 }, 419 { 0x97, 0x19 }, 420 { 0x97, 0x02 }, 421 { 0x97, 0x0c }, 422 { 0x97, 0x24 }, 423 { 0x97, 0x30 }, 424 { 0x97, 0x28 }, 425 { 0x97, 0x26 }, 426 { 0x97, 0x02 }, 427 { 0x97, 0x98 }, 428 { 0x97, 0x80 }, 429 { 0x97, 0x00 }, 430 { 0x97, 0x00 }, 431 { 0xa4, 0x00 }, 432 { 0xa8, 0x00 }, 433 { 0xc5, 0x11 }, 434 { 0xc6, 0x51 }, 435 { 0xbf, 0x80 }, 436 { 0xc7, 0x10 }, 437 { 0xb6, 0x66 }, 438 { 0xb8, 0xA5 }, 439 { 0xb7, 0x64 }, 440 { 0xb9, 0x7C }, 441 { 0xb3, 0xaf }, 442 { 0xb4, 0x97 }, 443 { 0xb5, 0xFF }, 444 { 0xb0, 0xC5 }, 445 { 0xb1, 0x94 }, 446 { 0xb2, 0x0f }, 447 { 0xc4, 0x5c }, 448 { 0xa6, 0x00 }, 449 { 0xa7, 0x20 }, 450 { 0xa7, 0xd8 }, 451 { 0xa7, 0x1b }, 452 { 0xa7, 0x31 }, 453 { 0xa7, 0x00 }, 454 { 0xa7, 0x18 }, 455 { 0xa7, 0x20 }, 456 { 0xa7, 0xd8 }, 457 { 0xa7, 0x19 }, 458 { 0xa7, 0x31 }, 459 { 0xa7, 0x00 }, 460 { 0xa7, 0x18 }, 461 { 0xa7, 0x20 }, 462 { 0xa7, 0xd8 }, 463 { 0xa7, 0x19 }, 464 { 0xa7, 0x31 }, 465 { 0xa7, 0x00 }, 466 { 0xa7, 0x18 }, 467 { 0x7f, 0x00 }, 468 { 0xe5, 0x1f }, 469 { 0xe1, 0x77 }, 470 { 0xdd, 0x7f }, 471 { CTRL0, CTRL0_YUV422 | CTRL0_YUV_EN | CTRL0_RGB_EN }, 472 ENDMARKER, 473}; 474 475/* 476 * Register settings for window size 477 * The preamble, setup the internal DSP to input an UXGA (1600x1200) image. 478 * Then the different zooming configurations will setup the output image size. 479 */ 480static const struct regval_list ov2640_size_change_preamble_regs[] = { 481 { BANK_SEL, BANK_SEL_DSP }, 482 { RESET, RESET_DVP }, 483 { HSIZE8, HSIZE8_SET(UXGA_WIDTH) }, 484 { VSIZE8, VSIZE8_SET(UXGA_HEIGHT) }, 485 { CTRL2, CTRL2_DCW_EN | CTRL2_SDE_EN | 486 CTRL2_UV_AVG_EN | CTRL2_CMX_EN | CTRL2_UV_ADJ_EN }, 487 { HSIZE, HSIZE_SET(UXGA_WIDTH) }, 488 { VSIZE, VSIZE_SET(UXGA_HEIGHT) }, 489 { XOFFL, XOFFL_SET(0) }, 490 { YOFFL, YOFFL_SET(0) }, 491 { VHYX, VHYX_HSIZE_SET(UXGA_WIDTH) | VHYX_VSIZE_SET(UXGA_HEIGHT) | 492 VHYX_XOFF_SET(0) | VHYX_YOFF_SET(0)}, 493 { TEST, TEST_HSIZE_SET(UXGA_WIDTH) }, 494 ENDMARKER, 495}; 496 497#define PER_SIZE_REG_SEQ(x, y, v_div, h_div, pclk_div) \ 498 { CTRLI, CTRLI_LP_DP | CTRLI_V_DIV_SET(v_div) | \ 499 CTRLI_H_DIV_SET(h_div)}, \ 500 { ZMOW, ZMOW_OUTW_SET(x) }, \ 501 { ZMOH, ZMOH_OUTH_SET(y) }, \ 502 { ZMHH, ZMHH_OUTW_SET(x) | ZMHH_OUTH_SET(y) }, \ 503 { R_DVP_SP, pclk_div }, \ 504 { RESET, 0x00} 505 506static const struct regval_list ov2640_qcif_regs[] = { 507 PER_SIZE_REG_SEQ(QCIF_WIDTH, QCIF_HEIGHT, 3, 3, 4), 508 ENDMARKER, 509}; 510 511static const struct regval_list ov2640_qvga_regs[] = { 512 PER_SIZE_REG_SEQ(QVGA_WIDTH, QVGA_HEIGHT, 2, 2, 4), 513 ENDMARKER, 514}; 515 516static const struct regval_list ov2640_cif_regs[] = { 517 PER_SIZE_REG_SEQ(CIF_WIDTH, CIF_HEIGHT, 2, 2, 8), 518 ENDMARKER, 519}; 520 521static const struct regval_list ov2640_vga_regs[] = { 522 PER_SIZE_REG_SEQ(VGA_WIDTH, VGA_HEIGHT, 0, 0, 2), 523 ENDMARKER, 524}; 525 526static const struct regval_list ov2640_svga_regs[] = { 527 PER_SIZE_REG_SEQ(SVGA_WIDTH, SVGA_HEIGHT, 1, 1, 2), 528 ENDMARKER, 529}; 530 531static const struct regval_list ov2640_xga_regs[] = { 532 PER_SIZE_REG_SEQ(XGA_WIDTH, XGA_HEIGHT, 0, 0, 2), 533 { CTRLI, 0x00}, 534 ENDMARKER, 535}; 536 537static const struct regval_list ov2640_sxga_regs[] = { 538 PER_SIZE_REG_SEQ(SXGA_WIDTH, SXGA_HEIGHT, 0, 0, 2), 539 { CTRLI, 0x00}, 540 { R_DVP_SP, 2 | R_DVP_SP_AUTO_MODE }, 541 ENDMARKER, 542}; 543 544static const struct regval_list ov2640_uxga_regs[] = { 545 PER_SIZE_REG_SEQ(UXGA_WIDTH, UXGA_HEIGHT, 0, 0, 0), 546 { CTRLI, 0x00}, 547 { R_DVP_SP, 0 | R_DVP_SP_AUTO_MODE }, 548 ENDMARKER, 549}; 550 551#define OV2640_SIZE(n, w, h, r) \ 552 {.name = n, .width = w , .height = h, .regs = r } 553 554static const struct ov2640_win_size ov2640_supported_win_sizes[] = { 555 OV2640_SIZE("QCIF", QCIF_WIDTH, QCIF_HEIGHT, ov2640_qcif_regs), 556 OV2640_SIZE("QVGA", QVGA_WIDTH, QVGA_HEIGHT, ov2640_qvga_regs), 557 OV2640_SIZE("CIF", CIF_WIDTH, CIF_HEIGHT, ov2640_cif_regs), 558 OV2640_SIZE("VGA", VGA_WIDTH, VGA_HEIGHT, ov2640_vga_regs), 559 OV2640_SIZE("SVGA", SVGA_WIDTH, SVGA_HEIGHT, ov2640_svga_regs), 560 OV2640_SIZE("XGA", XGA_WIDTH, XGA_HEIGHT, ov2640_xga_regs), 561 OV2640_SIZE("SXGA", SXGA_WIDTH, SXGA_HEIGHT, ov2640_sxga_regs), 562 OV2640_SIZE("UXGA", UXGA_WIDTH, UXGA_HEIGHT, ov2640_uxga_regs), 563}; 564 565/* 566 * Register settings for pixel formats 567 */ 568static const struct regval_list ov2640_format_change_preamble_regs[] = { 569 { BANK_SEL, BANK_SEL_DSP }, 570 { R_BYPASS, R_BYPASS_USE_DSP }, 571 ENDMARKER, 572}; 573 574static const struct regval_list ov2640_yuyv_regs[] = { 575 { IMAGE_MODE, IMAGE_MODE_YUV422 }, 576 { 0xd7, 0x03 }, 577 { 0x33, 0xa0 }, 578 { 0xe5, 0x1f }, 579 { 0xe1, 0x67 }, 580 { RESET, 0x00 }, 581 { R_BYPASS, R_BYPASS_USE_DSP }, 582 ENDMARKER, 583}; 584 585static const struct regval_list ov2640_uyvy_regs[] = { 586 { IMAGE_MODE, IMAGE_MODE_LBYTE_FIRST | IMAGE_MODE_YUV422 }, 587 { 0xd7, 0x01 }, 588 { 0x33, 0xa0 }, 589 { 0xe1, 0x67 }, 590 { RESET, 0x00 }, 591 { R_BYPASS, R_BYPASS_USE_DSP }, 592 ENDMARKER, 593}; 594 595static const struct regval_list ov2640_rgb565_be_regs[] = { 596 { IMAGE_MODE, IMAGE_MODE_RGB565 }, 597 { 0xd7, 0x03 }, 598 { RESET, 0x00 }, 599 { R_BYPASS, R_BYPASS_USE_DSP }, 600 ENDMARKER, 601}; 602 603static const struct regval_list ov2640_rgb565_le_regs[] = { 604 { IMAGE_MODE, IMAGE_MODE_LBYTE_FIRST | IMAGE_MODE_RGB565 }, 605 { 0xd7, 0x03 }, 606 { RESET, 0x00 }, 607 { R_BYPASS, R_BYPASS_USE_DSP }, 608 ENDMARKER, 609}; 610 611static u32 ov2640_codes[] = { 612 MEDIA_BUS_FMT_YUYV8_2X8, 613 MEDIA_BUS_FMT_UYVY8_2X8, 614 MEDIA_BUS_FMT_RGB565_2X8_BE, 615 MEDIA_BUS_FMT_RGB565_2X8_LE, 616}; 617 618/* 619 * General functions 620 */ 621static struct ov2640_priv *to_ov2640(const struct i2c_client *client) 622{ 623 return container_of(i2c_get_clientdata(client), struct ov2640_priv, 624 subdev); 625} 626 627static int ov2640_write_array(struct i2c_client *client, 628 const struct regval_list *vals) 629{ 630 int ret; 631 632 while ((vals->reg_num != 0xff) || (vals->value != 0xff)) { 633 ret = i2c_smbus_write_byte_data(client, 634 vals->reg_num, vals->value); 635 dev_vdbg(&client->dev, "array: 0x%02x, 0x%02x", 636 vals->reg_num, vals->value); 637 638 if (ret < 0) 639 return ret; 640 vals++; 641 } 642 return 0; 643} 644 645static int ov2640_mask_set(struct i2c_client *client, 646 u8 reg, u8 mask, u8 set) 647{ 648 s32 val = i2c_smbus_read_byte_data(client, reg); 649 if (val < 0) 650 return val; 651 652 val &= ~mask; 653 val |= set & mask; 654 655 dev_vdbg(&client->dev, "masks: 0x%02x, 0x%02x", reg, val); 656 657 return i2c_smbus_write_byte_data(client, reg, val); 658} 659 660static int ov2640_reset(struct i2c_client *client) 661{ 662 int ret; 663 const struct regval_list reset_seq[] = { 664 {BANK_SEL, BANK_SEL_SENS}, 665 {COM7, COM7_SRST}, 666 ENDMARKER, 667 }; 668 669 ret = ov2640_write_array(client, reset_seq); 670 if (ret) 671 goto err; 672 673 msleep(5); 674err: 675 dev_dbg(&client->dev, "%s: (ret %d)", __func__, ret); 676 return ret; 677} 678 679/* 680 * soc_camera_ops functions 681 */ 682static int ov2640_s_stream(struct v4l2_subdev *sd, int enable) 683{ 684 return 0; 685} 686 687static int ov2640_s_ctrl(struct v4l2_ctrl *ctrl) 688{ 689 struct v4l2_subdev *sd = 690 &container_of(ctrl->handler, struct ov2640_priv, hdl)->subdev; 691 struct i2c_client *client = v4l2_get_subdevdata(sd); 692 u8 val; 693 int ret; 694 695 ret = i2c_smbus_write_byte_data(client, BANK_SEL, BANK_SEL_SENS); 696 if (ret < 0) 697 return ret; 698 699 switch (ctrl->id) { 700 case V4L2_CID_VFLIP: 701 val = ctrl->val ? REG04_VFLIP_IMG : 0x00; 702 return ov2640_mask_set(client, REG04, REG04_VFLIP_IMG, val); 703 case V4L2_CID_HFLIP: 704 val = ctrl->val ? REG04_HFLIP_IMG : 0x00; 705 return ov2640_mask_set(client, REG04, REG04_HFLIP_IMG, val); 706 } 707 708 return -EINVAL; 709} 710 711#ifdef CONFIG_VIDEO_ADV_DEBUG 712static int ov2640_g_register(struct v4l2_subdev *sd, 713 struct v4l2_dbg_register *reg) 714{ 715 struct i2c_client *client = v4l2_get_subdevdata(sd); 716 int ret; 717 718 reg->size = 1; 719 if (reg->reg > 0xff) 720 return -EINVAL; 721 722 ret = i2c_smbus_read_byte_data(client, reg->reg); 723 if (ret < 0) 724 return ret; 725 726 reg->val = ret; 727 728 return 0; 729} 730 731static int ov2640_s_register(struct v4l2_subdev *sd, 732 const struct v4l2_dbg_register *reg) 733{ 734 struct i2c_client *client = v4l2_get_subdevdata(sd); 735 736 if (reg->reg > 0xff || 737 reg->val > 0xff) 738 return -EINVAL; 739 740 return i2c_smbus_write_byte_data(client, reg->reg, reg->val); 741} 742#endif 743 744static int ov2640_s_power(struct v4l2_subdev *sd, int on) 745{ 746 struct i2c_client *client = v4l2_get_subdevdata(sd); 747 struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client); 748 struct ov2640_priv *priv = to_ov2640(client); 749 750 return soc_camera_set_power(&client->dev, ssdd, priv->clk, on); 751} 752 753/* Select the nearest higher resolution for capture */ 754static const struct ov2640_win_size *ov2640_select_win(u32 *width, u32 *height) 755{ 756 int i, default_size = ARRAY_SIZE(ov2640_supported_win_sizes) - 1; 757 758 for (i = 0; i < ARRAY_SIZE(ov2640_supported_win_sizes); i++) { 759 if (ov2640_supported_win_sizes[i].width >= *width && 760 ov2640_supported_win_sizes[i].height >= *height) { 761 *width = ov2640_supported_win_sizes[i].width; 762 *height = ov2640_supported_win_sizes[i].height; 763 return &ov2640_supported_win_sizes[i]; 764 } 765 } 766 767 *width = ov2640_supported_win_sizes[default_size].width; 768 *height = ov2640_supported_win_sizes[default_size].height; 769 return &ov2640_supported_win_sizes[default_size]; 770} 771 772static int ov2640_set_params(struct i2c_client *client, u32 *width, u32 *height, 773 u32 code) 774{ 775 struct ov2640_priv *priv = to_ov2640(client); 776 const struct regval_list *selected_cfmt_regs; 777 int ret; 778 779 /* select win */ 780 priv->win = ov2640_select_win(width, height); 781 782 /* select format */ 783 priv->cfmt_code = 0; 784 switch (code) { 785 case MEDIA_BUS_FMT_RGB565_2X8_BE: 786 dev_dbg(&client->dev, "%s: Selected cfmt RGB565 BE", __func__); 787 selected_cfmt_regs = ov2640_rgb565_be_regs; 788 break; 789 case MEDIA_BUS_FMT_RGB565_2X8_LE: 790 dev_dbg(&client->dev, "%s: Selected cfmt RGB565 LE", __func__); 791 selected_cfmt_regs = ov2640_rgb565_le_regs; 792 break; 793 case MEDIA_BUS_FMT_YUYV8_2X8: 794 dev_dbg(&client->dev, "%s: Selected cfmt YUYV (YUV422)", __func__); 795 selected_cfmt_regs = ov2640_yuyv_regs; 796 break; 797 default: 798 case MEDIA_BUS_FMT_UYVY8_2X8: 799 dev_dbg(&client->dev, "%s: Selected cfmt UYVY", __func__); 800 selected_cfmt_regs = ov2640_uyvy_regs; 801 } 802 803 /* reset hardware */ 804 ov2640_reset(client); 805 806 /* initialize the sensor with default data */ 807 dev_dbg(&client->dev, "%s: Init default", __func__); 808 ret = ov2640_write_array(client, ov2640_init_regs); 809 if (ret < 0) 810 goto err; 811 812 /* select preamble */ 813 dev_dbg(&client->dev, "%s: Set size to %s", __func__, priv->win->name); 814 ret = ov2640_write_array(client, ov2640_size_change_preamble_regs); 815 if (ret < 0) 816 goto err; 817 818 /* set size win */ 819 ret = ov2640_write_array(client, priv->win->regs); 820 if (ret < 0) 821 goto err; 822 823 /* cfmt preamble */ 824 dev_dbg(&client->dev, "%s: Set cfmt", __func__); 825 ret = ov2640_write_array(client, ov2640_format_change_preamble_regs); 826 if (ret < 0) 827 goto err; 828 829 /* set cfmt */ 830 ret = ov2640_write_array(client, selected_cfmt_regs); 831 if (ret < 0) 832 goto err; 833 834 priv->cfmt_code = code; 835 *width = priv->win->width; 836 *height = priv->win->height; 837 838 return 0; 839 840err: 841 dev_err(&client->dev, "%s: Error %d", __func__, ret); 842 ov2640_reset(client); 843 priv->win = NULL; 844 845 return ret; 846} 847 848static int ov2640_g_fmt(struct v4l2_subdev *sd, 849 struct v4l2_mbus_framefmt *mf) 850{ 851 struct i2c_client *client = v4l2_get_subdevdata(sd); 852 struct ov2640_priv *priv = to_ov2640(client); 853 854 if (!priv->win) { 855 u32 width = SVGA_WIDTH, height = SVGA_HEIGHT; 856 priv->win = ov2640_select_win(&width, &height); 857 priv->cfmt_code = MEDIA_BUS_FMT_UYVY8_2X8; 858 } 859 860 mf->width = priv->win->width; 861 mf->height = priv->win->height; 862 mf->code = priv->cfmt_code; 863 864 switch (mf->code) { 865 case MEDIA_BUS_FMT_RGB565_2X8_BE: 866 case MEDIA_BUS_FMT_RGB565_2X8_LE: 867 mf->colorspace = V4L2_COLORSPACE_SRGB; 868 break; 869 default: 870 case MEDIA_BUS_FMT_YUYV8_2X8: 871 case MEDIA_BUS_FMT_UYVY8_2X8: 872 mf->colorspace = V4L2_COLORSPACE_JPEG; 873 } 874 mf->field = V4L2_FIELD_NONE; 875 876 return 0; 877} 878 879static int ov2640_s_fmt(struct v4l2_subdev *sd, 880 struct v4l2_mbus_framefmt *mf) 881{ 882 struct i2c_client *client = v4l2_get_subdevdata(sd); 883 int ret; 884 885 886 switch (mf->code) { 887 case MEDIA_BUS_FMT_RGB565_2X8_BE: 888 case MEDIA_BUS_FMT_RGB565_2X8_LE: 889 mf->colorspace = V4L2_COLORSPACE_SRGB; 890 break; 891 default: 892 mf->code = MEDIA_BUS_FMT_UYVY8_2X8; 893 case MEDIA_BUS_FMT_YUYV8_2X8: 894 case MEDIA_BUS_FMT_UYVY8_2X8: 895 mf->colorspace = V4L2_COLORSPACE_JPEG; 896 } 897 898 ret = ov2640_set_params(client, &mf->width, &mf->height, mf->code); 899 900 return ret; 901} 902 903static int ov2640_try_fmt(struct v4l2_subdev *sd, 904 struct v4l2_mbus_framefmt *mf) 905{ 906 /* 907 * select suitable win, but don't store it 908 */ 909 ov2640_select_win(&mf->width, &mf->height); 910 911 mf->field = V4L2_FIELD_NONE; 912 913 switch (mf->code) { 914 case MEDIA_BUS_FMT_RGB565_2X8_BE: 915 case MEDIA_BUS_FMT_RGB565_2X8_LE: 916 mf->colorspace = V4L2_COLORSPACE_SRGB; 917 break; 918 default: 919 mf->code = MEDIA_BUS_FMT_UYVY8_2X8; 920 case MEDIA_BUS_FMT_YUYV8_2X8: 921 case MEDIA_BUS_FMT_UYVY8_2X8: 922 mf->colorspace = V4L2_COLORSPACE_JPEG; 923 } 924 925 return 0; 926} 927 928static int ov2640_enum_fmt(struct v4l2_subdev *sd, unsigned int index, 929 u32 *code) 930{ 931 if (index >= ARRAY_SIZE(ov2640_codes)) 932 return -EINVAL; 933 934 *code = ov2640_codes[index]; 935 return 0; 936} 937 938static int ov2640_g_crop(struct v4l2_subdev *sd, struct v4l2_crop *a) 939{ 940 a->c.left = 0; 941 a->c.top = 0; 942 a->c.width = UXGA_WIDTH; 943 a->c.height = UXGA_HEIGHT; 944 a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; 945 946 return 0; 947} 948 949static int ov2640_cropcap(struct v4l2_subdev *sd, struct v4l2_cropcap *a) 950{ 951 a->bounds.left = 0; 952 a->bounds.top = 0; 953 a->bounds.width = UXGA_WIDTH; 954 a->bounds.height = UXGA_HEIGHT; 955 a->defrect = a->bounds; 956 a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; 957 a->pixelaspect.numerator = 1; 958 a->pixelaspect.denominator = 1; 959 960 return 0; 961} 962 963static int ov2640_video_probe(struct i2c_client *client) 964{ 965 struct ov2640_priv *priv = to_ov2640(client); 966 u8 pid, ver, midh, midl; 967 const char *devname; 968 int ret; 969 970 ret = ov2640_s_power(&priv->subdev, 1); 971 if (ret < 0) 972 return ret; 973 974 /* 975 * check and show product ID and manufacturer ID 976 */ 977 i2c_smbus_write_byte_data(client, BANK_SEL, BANK_SEL_SENS); 978 pid = i2c_smbus_read_byte_data(client, PID); 979 ver = i2c_smbus_read_byte_data(client, VER); 980 midh = i2c_smbus_read_byte_data(client, MIDH); 981 midl = i2c_smbus_read_byte_data(client, MIDL); 982 983 switch (VERSION(pid, ver)) { 984 case PID_OV2640: 985 devname = "ov2640"; 986 break; 987 default: 988 dev_err(&client->dev, 989 "Product ID error %x:%x\n", pid, ver); 990 ret = -ENODEV; 991 goto done; 992 } 993 994 dev_info(&client->dev, 995 "%s Product ID %0x:%0x Manufacturer ID %x:%x\n", 996 devname, pid, ver, midh, midl); 997 998 ret = v4l2_ctrl_handler_setup(&priv->hdl); 999 1000done: 1001 ov2640_s_power(&priv->subdev, 0); 1002 return ret; 1003} 1004 1005static const struct v4l2_ctrl_ops ov2640_ctrl_ops = { 1006 .s_ctrl = ov2640_s_ctrl, 1007}; 1008 1009static struct v4l2_subdev_core_ops ov2640_subdev_core_ops = { 1010#ifdef CONFIG_VIDEO_ADV_DEBUG 1011 .g_register = ov2640_g_register, 1012 .s_register = ov2640_s_register, 1013#endif 1014 .s_power = ov2640_s_power, 1015}; 1016 1017static int ov2640_g_mbus_config(struct v4l2_subdev *sd, 1018 struct v4l2_mbus_config *cfg) 1019{ 1020 struct i2c_client *client = v4l2_get_subdevdata(sd); 1021 struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client); 1022 1023 cfg->flags = V4L2_MBUS_PCLK_SAMPLE_RISING | V4L2_MBUS_MASTER | 1024 V4L2_MBUS_VSYNC_ACTIVE_HIGH | V4L2_MBUS_HSYNC_ACTIVE_HIGH | 1025 V4L2_MBUS_DATA_ACTIVE_HIGH; 1026 cfg->type = V4L2_MBUS_PARALLEL; 1027 cfg->flags = soc_camera_apply_board_flags(ssdd, cfg); 1028 1029 return 0; 1030} 1031 1032static struct v4l2_subdev_video_ops ov2640_subdev_video_ops = { 1033 .s_stream = ov2640_s_stream, 1034 .g_mbus_fmt = ov2640_g_fmt, 1035 .s_mbus_fmt = ov2640_s_fmt, 1036 .try_mbus_fmt = ov2640_try_fmt, 1037 .cropcap = ov2640_cropcap, 1038 .g_crop = ov2640_g_crop, 1039 .enum_mbus_fmt = ov2640_enum_fmt, 1040 .g_mbus_config = ov2640_g_mbus_config, 1041}; 1042 1043static struct v4l2_subdev_ops ov2640_subdev_ops = { 1044 .core = &ov2640_subdev_core_ops, 1045 .video = &ov2640_subdev_video_ops, 1046}; 1047 1048/* OF probe functions */ 1049static int ov2640_hw_power(struct device *dev, int on) 1050{ 1051 struct i2c_client *client = to_i2c_client(dev); 1052 struct ov2640_priv *priv = to_ov2640(client); 1053 1054 dev_dbg(&client->dev, "%s: %s the camera\n", 1055 __func__, on ? "ENABLE" : "DISABLE"); 1056 1057 if (priv->pwdn_gpio) 1058 gpiod_direction_output(priv->pwdn_gpio, !on); 1059 1060 return 0; 1061} 1062 1063static int ov2640_hw_reset(struct device *dev) 1064{ 1065 struct i2c_client *client = to_i2c_client(dev); 1066 struct ov2640_priv *priv = to_ov2640(client); 1067 1068 if (priv->resetb_gpio) { 1069 /* Active the resetb pin to perform a reset pulse */ 1070 gpiod_direction_output(priv->resetb_gpio, 1); 1071 usleep_range(3000, 5000); 1072 gpiod_direction_output(priv->resetb_gpio, 0); 1073 } 1074 1075 return 0; 1076} 1077 1078static int ov2640_probe_dt(struct i2c_client *client, 1079 struct ov2640_priv *priv) 1080{ 1081 /* Request the reset GPIO deasserted */ 1082 priv->resetb_gpio = devm_gpiod_get_optional(&client->dev, "resetb", 1083 GPIOD_OUT_LOW); 1084 if (!priv->resetb_gpio) 1085 dev_dbg(&client->dev, "resetb gpio is not assigned!\n"); 1086 else if (IS_ERR(priv->resetb_gpio)) 1087 return PTR_ERR(priv->resetb_gpio); 1088 1089 /* Request the power down GPIO asserted */ 1090 priv->pwdn_gpio = devm_gpiod_get_optional(&client->dev, "pwdn", 1091 GPIOD_OUT_HIGH); 1092 if (!priv->pwdn_gpio) 1093 dev_dbg(&client->dev, "pwdn gpio is not assigned!\n"); 1094 else if (IS_ERR(priv->pwdn_gpio)) 1095 return PTR_ERR(priv->pwdn_gpio); 1096 1097 /* Initialize the soc_camera_subdev_desc */ 1098 priv->ssdd_dt.power = ov2640_hw_power; 1099 priv->ssdd_dt.reset = ov2640_hw_reset; 1100 client->dev.platform_data = &priv->ssdd_dt; 1101 1102 return 0; 1103} 1104 1105/* 1106 * i2c_driver functions 1107 */ 1108static int ov2640_probe(struct i2c_client *client, 1109 const struct i2c_device_id *did) 1110{ 1111 struct ov2640_priv *priv; 1112 struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client); 1113 struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent); 1114 int ret; 1115 1116 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) { 1117 dev_err(&adapter->dev, 1118 "OV2640: I2C-Adapter doesn't support SMBUS\n"); 1119 return -EIO; 1120 } 1121 1122 priv = devm_kzalloc(&client->dev, sizeof(struct ov2640_priv), GFP_KERNEL); 1123 if (!priv) { 1124 dev_err(&adapter->dev, 1125 "Failed to allocate memory for private data!\n"); 1126 return -ENOMEM; 1127 } 1128 1129 priv->clk = v4l2_clk_get(&client->dev, "xvclk"); 1130 if (IS_ERR(priv->clk)) 1131 return -EPROBE_DEFER; 1132 1133 if (!ssdd && !client->dev.of_node) { 1134 dev_err(&client->dev, "Missing platform_data for driver\n"); 1135 ret = -EINVAL; 1136 goto err_clk; 1137 } 1138 1139 if (!ssdd) { 1140 ret = ov2640_probe_dt(client, priv); 1141 if (ret) 1142 goto err_clk; 1143 } 1144 1145 v4l2_i2c_subdev_init(&priv->subdev, client, &ov2640_subdev_ops); 1146 v4l2_ctrl_handler_init(&priv->hdl, 2); 1147 v4l2_ctrl_new_std(&priv->hdl, &ov2640_ctrl_ops, 1148 V4L2_CID_VFLIP, 0, 1, 1, 0); 1149 v4l2_ctrl_new_std(&priv->hdl, &ov2640_ctrl_ops, 1150 V4L2_CID_HFLIP, 0, 1, 1, 0); 1151 priv->subdev.ctrl_handler = &priv->hdl; 1152 if (priv->hdl.error) { 1153 ret = priv->hdl.error; 1154 goto err_clk; 1155 } 1156 1157 ret = ov2640_video_probe(client); 1158 if (ret < 0) 1159 goto err_videoprobe; 1160 1161 ret = v4l2_async_register_subdev(&priv->subdev); 1162 if (ret < 0) 1163 goto err_videoprobe; 1164 1165 dev_info(&adapter->dev, "OV2640 Probed\n"); 1166 1167 return 0; 1168 1169err_videoprobe: 1170 v4l2_ctrl_handler_free(&priv->hdl); 1171err_clk: 1172 v4l2_clk_put(priv->clk); 1173 return ret; 1174} 1175 1176static int ov2640_remove(struct i2c_client *client) 1177{ 1178 struct ov2640_priv *priv = to_ov2640(client); 1179 1180 v4l2_async_unregister_subdev(&priv->subdev); 1181 v4l2_clk_put(priv->clk); 1182 v4l2_device_unregister_subdev(&priv->subdev); 1183 v4l2_ctrl_handler_free(&priv->hdl); 1184 return 0; 1185} 1186 1187static const struct i2c_device_id ov2640_id[] = { 1188 { "ov2640", 0 }, 1189 { } 1190}; 1191MODULE_DEVICE_TABLE(i2c, ov2640_id); 1192 1193static const struct of_device_id ov2640_of_match[] = { 1194 {.compatible = "ovti,ov2640", }, 1195 {}, 1196}; 1197MODULE_DEVICE_TABLE(of, ov2640_of_match); 1198 1199static struct i2c_driver ov2640_i2c_driver = { 1200 .driver = { 1201 .name = "ov2640", 1202 .of_match_table = of_match_ptr(ov2640_of_match), 1203 }, 1204 .probe = ov2640_probe, 1205 .remove = ov2640_remove, 1206 .id_table = ov2640_id, 1207}; 1208 1209module_i2c_driver(ov2640_i2c_driver); 1210 1211MODULE_DESCRIPTION("SoC Camera driver for Omni Vision 2640 sensor"); 1212MODULE_AUTHOR("Alberto Panizzo"); 1213MODULE_LICENSE("GPL v2"); 1214