1/* 2 * Copyright (C) 2003 ATI Inc. <hyu@ati.com> 3 * Copyright (C) 2004,2007 Bartlomiej Zolnierkiewicz 4 */ 5 6#include <linux/types.h> 7#include <linux/module.h> 8#include <linux/kernel.h> 9#include <linux/pci.h> 10#include <linux/ide.h> 11#include <linux/init.h> 12 13#define DRV_NAME "atiixp" 14 15#define ATIIXP_IDE_PIO_TIMING 0x40 16#define ATIIXP_IDE_MDMA_TIMING 0x44 17#define ATIIXP_IDE_PIO_CONTROL 0x48 18#define ATIIXP_IDE_PIO_MODE 0x4a 19#define ATIIXP_IDE_UDMA_CONTROL 0x54 20#define ATIIXP_IDE_UDMA_MODE 0x56 21 22struct atiixp_ide_timing { 23 u8 command_width; 24 u8 recover_width; 25}; 26 27static struct atiixp_ide_timing pio_timing[] = { 28 { 0x05, 0x0d }, 29 { 0x04, 0x07 }, 30 { 0x03, 0x04 }, 31 { 0x02, 0x02 }, 32 { 0x02, 0x00 }, 33}; 34 35static struct atiixp_ide_timing mdma_timing[] = { 36 { 0x07, 0x07 }, 37 { 0x02, 0x01 }, 38 { 0x02, 0x00 }, 39}; 40 41static DEFINE_SPINLOCK(atiixp_lock); 42 43/** 44 * atiixp_set_pio_mode - set host controller for PIO mode 45 * @hwif: port 46 * @drive: drive 47 * 48 * Set the interface PIO mode. 49 */ 50 51static void atiixp_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) 52{ 53 struct pci_dev *dev = to_pci_dev(hwif->dev); 54 unsigned long flags; 55 int timing_shift = (drive->dn ^ 1) * 8; 56 u32 pio_timing_data; 57 u16 pio_mode_data; 58 const u8 pio = drive->pio_mode - XFER_PIO_0; 59 60 spin_lock_irqsave(&atiixp_lock, flags); 61 62 pci_read_config_word(dev, ATIIXP_IDE_PIO_MODE, &pio_mode_data); 63 pio_mode_data &= ~(0x07 << (drive->dn * 4)); 64 pio_mode_data |= (pio << (drive->dn * 4)); 65 pci_write_config_word(dev, ATIIXP_IDE_PIO_MODE, pio_mode_data); 66 67 pci_read_config_dword(dev, ATIIXP_IDE_PIO_TIMING, &pio_timing_data); 68 pio_timing_data &= ~(0xff << timing_shift); 69 pio_timing_data |= (pio_timing[pio].recover_width << timing_shift) | 70 (pio_timing[pio].command_width << (timing_shift + 4)); 71 pci_write_config_dword(dev, ATIIXP_IDE_PIO_TIMING, pio_timing_data); 72 73 spin_unlock_irqrestore(&atiixp_lock, flags); 74} 75 76/** 77 * atiixp_set_dma_mode - set host controller for DMA mode 78 * @hwif: port 79 * @drive: drive 80 * 81 * Set a ATIIXP host controller to the desired DMA mode. This involves 82 * programming the right timing data into the PCI configuration space. 83 */ 84 85static void atiixp_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive) 86{ 87 struct pci_dev *dev = to_pci_dev(hwif->dev); 88 unsigned long flags; 89 int timing_shift = (drive->dn ^ 1) * 8; 90 u32 tmp32; 91 u16 tmp16; 92 u16 udma_ctl = 0; 93 const u8 speed = drive->dma_mode; 94 95 spin_lock_irqsave(&atiixp_lock, flags); 96 97 pci_read_config_word(dev, ATIIXP_IDE_UDMA_CONTROL, &udma_ctl); 98 99 if (speed >= XFER_UDMA_0) { 100 pci_read_config_word(dev, ATIIXP_IDE_UDMA_MODE, &tmp16); 101 tmp16 &= ~(0x07 << (drive->dn * 4)); 102 tmp16 |= ((speed & 0x07) << (drive->dn * 4)); 103 pci_write_config_word(dev, ATIIXP_IDE_UDMA_MODE, tmp16); 104 105 udma_ctl |= (1 << drive->dn); 106 } else if (speed >= XFER_MW_DMA_0) { 107 u8 i = speed & 0x03; 108 109 pci_read_config_dword(dev, ATIIXP_IDE_MDMA_TIMING, &tmp32); 110 tmp32 &= ~(0xff << timing_shift); 111 tmp32 |= (mdma_timing[i].recover_width << timing_shift) | 112 (mdma_timing[i].command_width << (timing_shift + 4)); 113 pci_write_config_dword(dev, ATIIXP_IDE_MDMA_TIMING, tmp32); 114 115 udma_ctl &= ~(1 << drive->dn); 116 } 117 118 pci_write_config_word(dev, ATIIXP_IDE_UDMA_CONTROL, udma_ctl); 119 120 spin_unlock_irqrestore(&atiixp_lock, flags); 121} 122 123static u8 atiixp_cable_detect(ide_hwif_t *hwif) 124{ 125 struct pci_dev *pdev = to_pci_dev(hwif->dev); 126 u8 udma_mode = 0, ch = hwif->channel; 127 128 pci_read_config_byte(pdev, ATIIXP_IDE_UDMA_MODE + ch, &udma_mode); 129 130 if ((udma_mode & 0x07) >= 0x04 || (udma_mode & 0x70) >= 0x40) 131 return ATA_CBL_PATA80; 132 else 133 return ATA_CBL_PATA40; 134} 135 136static const struct ide_port_ops atiixp_port_ops = { 137 .set_pio_mode = atiixp_set_pio_mode, 138 .set_dma_mode = atiixp_set_dma_mode, 139 .cable_detect = atiixp_cable_detect, 140}; 141 142static const struct ide_port_info atiixp_pci_info[] = { 143 { /* 0: IXP200/300/400/700 */ 144 .name = DRV_NAME, 145 .enablebits = {{0x48,0x01,0x00}, {0x48,0x08,0x00}}, 146 .port_ops = &atiixp_port_ops, 147 .pio_mask = ATA_PIO4, 148 .mwdma_mask = ATA_MWDMA2, 149 .udma_mask = ATA_UDMA5, 150 }, 151 { /* 1: IXP600 */ 152 .name = DRV_NAME, 153 .enablebits = {{0x48,0x01,0x00}, {0x00,0x00,0x00}}, 154 .port_ops = &atiixp_port_ops, 155 .host_flags = IDE_HFLAG_SINGLE, 156 .pio_mask = ATA_PIO4, 157 .mwdma_mask = ATA_MWDMA2, 158 .udma_mask = ATA_UDMA5, 159 }, 160}; 161 162/** 163 * atiixp_init_one - called when a ATIIXP is found 164 * @dev: the atiixp device 165 * @id: the matching pci id 166 * 167 * Called when the PCI registration layer (or the IDE initialization) 168 * finds a device matching our IDE device tables. 169 */ 170 171static int atiixp_init_one(struct pci_dev *dev, const struct pci_device_id *id) 172{ 173 return ide_pci_init_one(dev, &atiixp_pci_info[id->driver_data], NULL); 174} 175 176static const struct pci_device_id atiixp_pci_tbl[] = { 177 { PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP200_IDE), 0 }, 178 { PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP300_IDE), 0 }, 179 { PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP400_IDE), 0 }, 180 { PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP600_IDE), 1 }, 181 { PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP700_IDE), 0 }, 182 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_HUDSON2_IDE), 0 }, 183 { 0, }, 184}; 185MODULE_DEVICE_TABLE(pci, atiixp_pci_tbl); 186 187static struct pci_driver atiixp_pci_driver = { 188 .name = "ATIIXP_IDE", 189 .id_table = atiixp_pci_tbl, 190 .probe = atiixp_init_one, 191 .remove = ide_pci_remove, 192 .suspend = ide_pci_suspend, 193 .resume = ide_pci_resume, 194}; 195 196static int __init atiixp_ide_init(void) 197{ 198 return ide_pci_register_driver(&atiixp_pci_driver); 199} 200 201static void __exit atiixp_ide_exit(void) 202{ 203 pci_unregister_driver(&atiixp_pci_driver); 204} 205 206module_init(atiixp_ide_init); 207module_exit(atiixp_ide_exit); 208 209MODULE_AUTHOR("HUI YU"); 210MODULE_DESCRIPTION("PCI driver module for ATI IXP IDE"); 211MODULE_LICENSE("GPL"); 212