1/********************************************************** 2 * Copyright 1998-2009 VMware, Inc. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person 5 * obtaining a copy of this software and associated documentation 6 * files (the "Software"), to deal in the Software without 7 * restriction, including without limitation the rights to use, copy, 8 * modify, merge, publish, distribute, sublicense, and/or sell copies 9 * of the Software, and to permit persons to whom the Software is 10 * furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be 13 * included in all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 * SOFTWARE. 23 * 24 **********************************************************/ 25 26/* 27 * svga_reg.h -- 28 * 29 * Virtual hardware definitions for the VMware SVGA II device. 30 */ 31 32#ifndef _SVGA_REG_H_ 33#define _SVGA_REG_H_ 34 35/* 36 * PCI device IDs. 37 */ 38#define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405 39 40/* 41 * SVGA_REG_ENABLE bit definitions. 42 */ 43#define SVGA_REG_ENABLE_DISABLE 0 44#define SVGA_REG_ENABLE_ENABLE 1 45#define SVGA_REG_ENABLE_HIDE 2 46#define SVGA_REG_ENABLE_ENABLE_HIDE (SVGA_REG_ENABLE_ENABLE |\ 47 SVGA_REG_ENABLE_HIDE) 48 49/* 50 * Legal values for the SVGA_REG_CURSOR_ON register in old-fashioned 51 * cursor bypass mode. This is still supported, but no new guest 52 * drivers should use it. 53 */ 54#define SVGA_CURSOR_ON_HIDE 0x0 /* Must be 0 to maintain backward compatibility */ 55#define SVGA_CURSOR_ON_SHOW 0x1 /* Must be 1 to maintain backward compatibility */ 56#define SVGA_CURSOR_ON_REMOVE_FROM_FB 0x2 /* Remove the cursor from the framebuffer because we need to see what's under it */ 57#define SVGA_CURSOR_ON_RESTORE_TO_FB 0x3 /* Put the cursor back in the framebuffer so the user can see it */ 58 59/* 60 * The maximum framebuffer size that can traced for e.g. guests in VESA mode. 61 * The changeMap in the monitor is proportional to this number. Therefore, we'd 62 * like to keep it as small as possible to reduce monitor overhead (using 63 * SVGA_VRAM_MAX_SIZE for this increases the size of the shared area by over 64 * 4k!). 65 * 66 * NB: For compatibility reasons, this value must be greater than 0xff0000. 67 * See bug 335072. 68 */ 69#define SVGA_FB_MAX_TRACEABLE_SIZE 0x1000000 70 71#define SVGA_MAX_PSEUDOCOLOR_DEPTH 8 72#define SVGA_MAX_PSEUDOCOLORS (1 << SVGA_MAX_PSEUDOCOLOR_DEPTH) 73#define SVGA_NUM_PALETTE_REGS (3 * SVGA_MAX_PSEUDOCOLORS) 74 75#define SVGA_MAGIC 0x900000UL 76#define SVGA_MAKE_ID(ver) (SVGA_MAGIC << 8 | (ver)) 77 78/* Version 2 let the address of the frame buffer be unsigned on Win32 */ 79#define SVGA_VERSION_2 2 80#define SVGA_ID_2 SVGA_MAKE_ID(SVGA_VERSION_2) 81 82/* Version 1 has new registers starting with SVGA_REG_CAPABILITIES so 83 PALETTE_BASE has moved */ 84#define SVGA_VERSION_1 1 85#define SVGA_ID_1 SVGA_MAKE_ID(SVGA_VERSION_1) 86 87/* Version 0 is the initial version */ 88#define SVGA_VERSION_0 0 89#define SVGA_ID_0 SVGA_MAKE_ID(SVGA_VERSION_0) 90 91/* "Invalid" value for all SVGA IDs. (Version ID, screen object ID, surface ID...) */ 92#define SVGA_ID_INVALID 0xFFFFFFFF 93 94/* Port offsets, relative to BAR0 */ 95#define SVGA_INDEX_PORT 0x0 96#define SVGA_VALUE_PORT 0x1 97#define SVGA_BIOS_PORT 0x2 98#define SVGA_IRQSTATUS_PORT 0x8 99 100/* 101 * Interrupt source flags for IRQSTATUS_PORT and IRQMASK. 102 * 103 * Interrupts are only supported when the 104 * SVGA_CAP_IRQMASK capability is present. 105 */ 106#define SVGA_IRQFLAG_ANY_FENCE 0x1 /* Any fence was passed */ 107#define SVGA_IRQFLAG_FIFO_PROGRESS 0x2 /* Made forward progress in the FIFO */ 108#define SVGA_IRQFLAG_FENCE_GOAL 0x4 /* SVGA_FIFO_FENCE_GOAL reached */ 109 110/* 111 * Registers 112 */ 113 114enum { 115 SVGA_REG_ID = 0, 116 SVGA_REG_ENABLE = 1, 117 SVGA_REG_WIDTH = 2, 118 SVGA_REG_HEIGHT = 3, 119 SVGA_REG_MAX_WIDTH = 4, 120 SVGA_REG_MAX_HEIGHT = 5, 121 SVGA_REG_DEPTH = 6, 122 SVGA_REG_BITS_PER_PIXEL = 7, /* Current bpp in the guest */ 123 SVGA_REG_PSEUDOCOLOR = 8, 124 SVGA_REG_RED_MASK = 9, 125 SVGA_REG_GREEN_MASK = 10, 126 SVGA_REG_BLUE_MASK = 11, 127 SVGA_REG_BYTES_PER_LINE = 12, 128 SVGA_REG_FB_START = 13, /* (Deprecated) */ 129 SVGA_REG_FB_OFFSET = 14, 130 SVGA_REG_VRAM_SIZE = 15, 131 SVGA_REG_FB_SIZE = 16, 132 133 /* ID 0 implementation only had the above registers, then the palette */ 134 135 SVGA_REG_CAPABILITIES = 17, 136 SVGA_REG_MEM_START = 18, /* (Deprecated) */ 137 SVGA_REG_MEM_SIZE = 19, 138 SVGA_REG_CONFIG_DONE = 20, /* Set when memory area configured */ 139 SVGA_REG_SYNC = 21, /* See "FIFO Synchronization Registers" */ 140 SVGA_REG_BUSY = 22, /* See "FIFO Synchronization Registers" */ 141 SVGA_REG_GUEST_ID = 23, /* Set guest OS identifier */ 142 SVGA_REG_CURSOR_ID = 24, /* (Deprecated) */ 143 SVGA_REG_CURSOR_X = 25, /* (Deprecated) */ 144 SVGA_REG_CURSOR_Y = 26, /* (Deprecated) */ 145 SVGA_REG_CURSOR_ON = 27, /* (Deprecated) */ 146 SVGA_REG_HOST_BITS_PER_PIXEL = 28, /* (Deprecated) */ 147 SVGA_REG_SCRATCH_SIZE = 29, /* Number of scratch registers */ 148 SVGA_REG_MEM_REGS = 30, /* Number of FIFO registers */ 149 SVGA_REG_NUM_DISPLAYS = 31, /* (Deprecated) */ 150 SVGA_REG_PITCHLOCK = 32, /* Fixed pitch for all modes */ 151 SVGA_REG_IRQMASK = 33, /* Interrupt mask */ 152 153 /* Legacy multi-monitor support */ 154 SVGA_REG_NUM_GUEST_DISPLAYS = 34,/* Number of guest displays in X/Y direction */ 155 SVGA_REG_DISPLAY_ID = 35, /* Display ID for the following display attributes */ 156 SVGA_REG_DISPLAY_IS_PRIMARY = 36,/* Whether this is a primary display */ 157 SVGA_REG_DISPLAY_POSITION_X = 37,/* The display position x */ 158 SVGA_REG_DISPLAY_POSITION_Y = 38,/* The display position y */ 159 SVGA_REG_DISPLAY_WIDTH = 39, /* The display's width */ 160 SVGA_REG_DISPLAY_HEIGHT = 40, /* The display's height */ 161 162 /* See "Guest memory regions" below. */ 163 SVGA_REG_GMR_ID = 41, 164 SVGA_REG_GMR_DESCRIPTOR = 42, 165 SVGA_REG_GMR_MAX_IDS = 43, 166 SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH = 44, 167 168 SVGA_REG_TRACES = 45, /* Enable trace-based updates even when FIFO is on */ 169 SVGA_REG_GMRS_MAX_PAGES = 46, /* Maximum number of 4KB pages for all GMRs */ 170 SVGA_REG_MEMORY_SIZE = 47, /* Total dedicated device memory excluding FIFO */ 171 SVGA_REG_COMMAND_LOW = 48, /* Lower 32 bits and submits commands */ 172 SVGA_REG_COMMAND_HIGH = 49, /* Upper 32 bits of command buffer PA */ 173 SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM = 50, /* Max primary memory */ 174 SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB = 51, /* Suggested limit on mob mem */ 175 SVGA_REG_DEV_CAP = 52, /* Write dev cap index, read value */ 176 SVGA_REG_CMD_PREPEND_LOW = 53, 177 SVGA_REG_CMD_PREPEND_HIGH = 54, 178 SVGA_REG_SCREENTARGET_MAX_WIDTH = 55, 179 SVGA_REG_SCREENTARGET_MAX_HEIGHT = 56, 180 SVGA_REG_MOB_MAX_SIZE = 57, 181 SVGA_REG_TOP = 58, /* Must be 1 more than the last register */ 182 183 SVGA_PALETTE_BASE = 1024, /* Base of SVGA color map */ 184 /* Next 768 (== 256*3) registers exist for colormap */ 185 186 SVGA_SCRATCH_BASE = SVGA_PALETTE_BASE + SVGA_NUM_PALETTE_REGS 187 /* Base of scratch registers */ 188 /* Next reg[SVGA_REG_SCRATCH_SIZE] registers exist for scratch usage: 189 First 4 are reserved for VESA BIOS Extension; any remaining are for 190 the use of the current SVGA driver. */ 191}; 192 193 194/* 195 * Guest memory regions (GMRs): 196 * 197 * This is a new memory mapping feature available in SVGA devices 198 * which have the SVGA_CAP_GMR bit set. Previously, there were two 199 * fixed memory regions available with which to share data between the 200 * device and the driver: the FIFO ('MEM') and the framebuffer. GMRs 201 * are our name for an extensible way of providing arbitrary DMA 202 * buffers for use between the driver and the SVGA device. They are a 203 * new alternative to framebuffer memory, usable for both 2D and 3D 204 * graphics operations. 205 * 206 * Since GMR mapping must be done synchronously with guest CPU 207 * execution, we use a new pair of SVGA registers: 208 * 209 * SVGA_REG_GMR_ID -- 210 * 211 * Read/write. 212 * This register holds the 32-bit ID (a small positive integer) 213 * of a GMR to create, delete, or redefine. Writing this register 214 * has no side-effects. 215 * 216 * SVGA_REG_GMR_DESCRIPTOR -- 217 * 218 * Write-only. 219 * Writing this register will create, delete, or redefine the GMR 220 * specified by the above ID register. If this register is zero, 221 * the GMR is deleted. Any pointers into this GMR (including those 222 * currently being processed by FIFO commands) will be 223 * synchronously invalidated. 224 * 225 * If this register is nonzero, it must be the physical page 226 * number (PPN) of a data structure which describes the physical 227 * layout of the memory region this GMR should describe. The 228 * descriptor structure will be read synchronously by the SVGA 229 * device when this register is written. The descriptor need not 230 * remain allocated for the lifetime of the GMR. 231 * 232 * The guest driver should write SVGA_REG_GMR_ID first, then 233 * SVGA_REG_GMR_DESCRIPTOR. 234 * 235 * SVGA_REG_GMR_MAX_IDS -- 236 * 237 * Read-only. 238 * The SVGA device may choose to support a maximum number of 239 * user-defined GMR IDs. This register holds the number of supported 240 * IDs. (The maximum supported ID plus 1) 241 * 242 * SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH -- 243 * 244 * Read-only. 245 * The SVGA device may choose to put a limit on the total number 246 * of SVGAGuestMemDescriptor structures it will read when defining 247 * a single GMR. 248 * 249 * The descriptor structure is an array of SVGAGuestMemDescriptor 250 * structures. Each structure may do one of three things: 251 * 252 * - Terminate the GMR descriptor list. 253 * (ppn==0, numPages==0) 254 * 255 * - Add a PPN or range of PPNs to the GMR's virtual address space. 256 * (ppn != 0, numPages != 0) 257 * 258 * - Provide the PPN of the next SVGAGuestMemDescriptor, in order to 259 * support multi-page GMR descriptor tables without forcing the 260 * driver to allocate physically contiguous memory. 261 * (ppn != 0, numPages == 0) 262 * 263 * Note that each physical page of SVGAGuestMemDescriptor structures 264 * can describe at least 2MB of guest memory. If the driver needs to 265 * use more than one page of descriptor structures, it must use one of 266 * its SVGAGuestMemDescriptors to point to an additional page. The 267 * device will never automatically cross a page boundary. 268 * 269 * Once the driver has described a GMR, it is immediately available 270 * for use via any FIFO command that uses an SVGAGuestPtr structure. 271 * These pointers include a GMR identifier plus an offset into that 272 * GMR. 273 * 274 * The driver must check the SVGA_CAP_GMR bit before using the GMR 275 * registers. 276 */ 277 278/* 279 * Special GMR IDs, allowing SVGAGuestPtrs to point to framebuffer 280 * memory as well. In the future, these IDs could even be used to 281 * allow legacy memory regions to be redefined by the guest as GMRs. 282 * 283 * Using the guest framebuffer (GFB) at BAR1 for general purpose DMA 284 * is being phased out. Please try to use user-defined GMRs whenever 285 * possible. 286 */ 287#define SVGA_GMR_NULL ((uint32) -1) 288#define SVGA_GMR_FRAMEBUFFER ((uint32) -2) /* Guest Framebuffer (GFB) */ 289 290typedef 291struct SVGAGuestMemDescriptor { 292 uint32 ppn; 293 uint32 numPages; 294} SVGAGuestMemDescriptor; 295 296typedef 297struct SVGAGuestPtr { 298 uint32 gmrId; 299 uint32 offset; 300} SVGAGuestPtr; 301 302 303/* 304 * SVGAGMRImageFormat -- 305 * 306 * This is a packed representation of the source 2D image format 307 * for a GMR-to-screen blit. Currently it is defined as an encoding 308 * of the screen's color depth and bits-per-pixel, however, 16 bits 309 * are reserved for future use to identify other encodings (such as 310 * RGBA or higher-precision images). 311 * 312 * Currently supported formats: 313 * 314 * bpp depth Format Name 315 * --- ----- ----------- 316 * 32 24 32-bit BGRX 317 * 24 24 24-bit BGR 318 * 16 16 RGB 5-6-5 319 * 16 15 RGB 5-5-5 320 * 321 */ 322 323typedef 324struct SVGAGMRImageFormat { 325 union { 326 struct { 327 uint32 bitsPerPixel : 8; 328 uint32 colorDepth : 8; 329 uint32 reserved : 16; /* Must be zero */ 330 }; 331 332 uint32 value; 333 }; 334} SVGAGMRImageFormat; 335 336typedef 337struct SVGAGuestImage { 338 SVGAGuestPtr ptr; 339 340 /* 341 * A note on interpretation of pitch: This value of pitch is the 342 * number of bytes between vertically adjacent image 343 * blocks. Normally this is the number of bytes between the first 344 * pixel of two adjacent scanlines. With compressed textures, 345 * however, this may represent the number of bytes between 346 * compression blocks rather than between rows of pixels. 347 * 348 * XXX: Compressed textures currently must be tightly packed in guest memory. 349 * 350 * If the image is 1-dimensional, pitch is ignored. 351 * 352 * If 'pitch' is zero, the SVGA3D device calculates a pitch value 353 * assuming each row of blocks is tightly packed. 354 */ 355 uint32 pitch; 356} SVGAGuestImage; 357 358/* 359 * SVGAColorBGRX -- 360 * 361 * A 24-bit color format (BGRX), which does not depend on the 362 * format of the legacy guest framebuffer (GFB) or the current 363 * GMRFB state. 364 */ 365 366typedef 367struct SVGAColorBGRX { 368 union { 369 struct { 370 uint32 b : 8; 371 uint32 g : 8; 372 uint32 r : 8; 373 uint32 x : 8; /* Unused */ 374 }; 375 376 uint32 value; 377 }; 378} SVGAColorBGRX; 379 380 381/* 382 * SVGASignedRect -- 383 * SVGASignedPoint -- 384 * 385 * Signed rectangle and point primitives. These are used by the new 386 * 2D primitives for drawing to Screen Objects, which can occupy a 387 * signed virtual coordinate space. 388 * 389 * SVGASignedRect specifies a half-open interval: the (left, top) 390 * pixel is part of the rectangle, but the (right, bottom) pixel is 391 * not. 392 */ 393 394typedef 395struct SVGASignedRect { 396 int32 left; 397 int32 top; 398 int32 right; 399 int32 bottom; 400} SVGASignedRect; 401 402typedef 403struct SVGASignedPoint { 404 int32 x; 405 int32 y; 406} SVGASignedPoint; 407 408 409/* 410 * Capabilities 411 * 412 * Note the holes in the bitfield. Missing bits have been deprecated, 413 * and must not be reused. Those capabilities will never be reported 414 * by new versions of the SVGA device. 415 * 416 * SVGA_CAP_GMR2 -- 417 * Provides asynchronous commands to define and remap guest memory 418 * regions. Adds device registers SVGA_REG_GMRS_MAX_PAGES and 419 * SVGA_REG_MEMORY_SIZE. 420 * 421 * SVGA_CAP_SCREEN_OBJECT_2 -- 422 * Allow screen object support, and require backing stores from the 423 * guest for each screen object. 424 */ 425 426#define SVGA_CAP_NONE 0x00000000 427#define SVGA_CAP_RECT_COPY 0x00000002 428#define SVGA_CAP_CURSOR 0x00000020 429#define SVGA_CAP_CURSOR_BYPASS 0x00000040 /* Legacy (Use Cursor Bypass 3 instead) */ 430#define SVGA_CAP_CURSOR_BYPASS_2 0x00000080 /* Legacy (Use Cursor Bypass 3 instead) */ 431#define SVGA_CAP_8BIT_EMULATION 0x00000100 432#define SVGA_CAP_ALPHA_CURSOR 0x00000200 433#define SVGA_CAP_3D 0x00004000 434#define SVGA_CAP_EXTENDED_FIFO 0x00008000 435#define SVGA_CAP_MULTIMON 0x00010000 /* Legacy multi-monitor support */ 436#define SVGA_CAP_PITCHLOCK 0x00020000 437#define SVGA_CAP_IRQMASK 0x00040000 438#define SVGA_CAP_DISPLAY_TOPOLOGY 0x00080000 /* Legacy multi-monitor support */ 439#define SVGA_CAP_GMR 0x00100000 440#define SVGA_CAP_TRACES 0x00200000 441#define SVGA_CAP_GMR2 0x00400000 442#define SVGA_CAP_SCREEN_OBJECT_2 0x00800000 443#define SVGA_CAP_COMMAND_BUFFERS 0x01000000 444#define SVGA_CAP_DEAD1 0x02000000 445#define SVGA_CAP_CMD_BUFFERS_2 0x04000000 446#define SVGA_CAP_GBOBJECTS 0x08000000 447 448/* 449 * FIFO register indices. 450 * 451 * The FIFO is a chunk of device memory mapped into guest physmem. It 452 * is always treated as 32-bit words. 453 * 454 * The guest driver gets to decide how to partition it between 455 * - FIFO registers (there are always at least 4, specifying where the 456 * following data area is and how much data it contains; there may be 457 * more registers following these, depending on the FIFO protocol 458 * version in use) 459 * - FIFO data, written by the guest and slurped out by the VMX. 460 * These indices are 32-bit word offsets into the FIFO. 461 */ 462 463enum { 464 /* 465 * Block 1 (basic registers): The originally defined FIFO registers. 466 * These exist and are valid for all versions of the FIFO protocol. 467 */ 468 469 SVGA_FIFO_MIN = 0, 470 SVGA_FIFO_MAX, /* The distance from MIN to MAX must be at least 10K */ 471 SVGA_FIFO_NEXT_CMD, 472 SVGA_FIFO_STOP, 473 474 /* 475 * Block 2 (extended registers): Mandatory registers for the extended 476 * FIFO. These exist if the SVGA caps register includes 477 * SVGA_CAP_EXTENDED_FIFO; some of them are valid only if their 478 * associated capability bit is enabled. 479 * 480 * Note that when originally defined, SVGA_CAP_EXTENDED_FIFO implied 481 * support only for (FIFO registers) CAPABILITIES, FLAGS, and FENCE. 482 * This means that the guest has to test individually (in most cases 483 * using FIFO caps) for the presence of registers after this; the VMX 484 * can define "extended FIFO" to mean whatever it wants, and currently 485 * won't enable it unless there's room for that set and much more. 486 */ 487 488 SVGA_FIFO_CAPABILITIES = 4, 489 SVGA_FIFO_FLAGS, 490 /* Valid with SVGA_FIFO_CAP_FENCE: */ 491 SVGA_FIFO_FENCE, 492 493 /* 494 * Block 3a (optional extended registers): Additional registers for the 495 * extended FIFO, whose presence isn't actually implied by 496 * SVGA_CAP_EXTENDED_FIFO; these exist if SVGA_FIFO_MIN is high enough to 497 * leave room for them. 498 * 499 * These in block 3a, the VMX currently considers mandatory for the 500 * extended FIFO. 501 */ 502 503 /* Valid if exists (i.e. if extended FIFO enabled): */ 504 SVGA_FIFO_3D_HWVERSION, /* See SVGA3dHardwareVersion in svga3d_reg.h */ 505 /* Valid with SVGA_FIFO_CAP_PITCHLOCK: */ 506 SVGA_FIFO_PITCHLOCK, 507 508 /* Valid with SVGA_FIFO_CAP_CURSOR_BYPASS_3: */ 509 SVGA_FIFO_CURSOR_ON, /* Cursor bypass 3 show/hide register */ 510 SVGA_FIFO_CURSOR_X, /* Cursor bypass 3 x register */ 511 SVGA_FIFO_CURSOR_Y, /* Cursor bypass 3 y register */ 512 SVGA_FIFO_CURSOR_COUNT, /* Incremented when any of the other 3 change */ 513 SVGA_FIFO_CURSOR_LAST_UPDATED,/* Last time the host updated the cursor */ 514 515 /* Valid with SVGA_FIFO_CAP_RESERVE: */ 516 SVGA_FIFO_RESERVED, /* Bytes past NEXT_CMD with real contents */ 517 518 /* 519 * Valid with SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2: 520 * 521 * By default this is SVGA_ID_INVALID, to indicate that the cursor 522 * coordinates are specified relative to the virtual root. If this 523 * is set to a specific screen ID, cursor position is reinterpreted 524 * as a signed offset relative to that screen's origin. 525 */ 526 SVGA_FIFO_CURSOR_SCREEN_ID, 527 528 /* 529 * Valid with SVGA_FIFO_CAP_DEAD 530 * 531 * An arbitrary value written by the host, drivers should not use it. 532 */ 533 SVGA_FIFO_DEAD, 534 535 /* 536 * Valid with SVGA_FIFO_CAP_3D_HWVERSION_REVISED: 537 * 538 * Contains 3D HWVERSION (see SVGA3dHardwareVersion in svga3d_reg.h) 539 * on platforms that can enforce graphics resource limits. 540 */ 541 SVGA_FIFO_3D_HWVERSION_REVISED, 542 543 /* 544 * XXX: The gap here, up until SVGA_FIFO_3D_CAPS, can be used for new 545 * registers, but this must be done carefully and with judicious use of 546 * capability bits, since comparisons based on SVGA_FIFO_MIN aren't 547 * enough to tell you whether the register exists: we've shipped drivers 548 * and products that used SVGA_FIFO_3D_CAPS but didn't know about some of 549 * the earlier ones. The actual order of introduction was: 550 * - PITCHLOCK 551 * - 3D_CAPS 552 * - CURSOR_* (cursor bypass 3) 553 * - RESERVED 554 * So, code that wants to know whether it can use any of the 555 * aforementioned registers, or anything else added after PITCHLOCK and 556 * before 3D_CAPS, needs to reason about something other than 557 * SVGA_FIFO_MIN. 558 */ 559 560 /* 561 * 3D caps block space; valid with 3D hardware version >= 562 * SVGA3D_HWVERSION_WS6_B1. 563 */ 564 SVGA_FIFO_3D_CAPS = 32, 565 SVGA_FIFO_3D_CAPS_LAST = 32 + 255, 566 567 /* 568 * End of VMX's current definition of "extended-FIFO registers". 569 * Registers before here are always enabled/disabled as a block; either 570 * the extended FIFO is enabled and includes all preceding registers, or 571 * it's disabled entirely. 572 * 573 * Block 3b (truly optional extended registers): Additional registers for 574 * the extended FIFO, which the VMX already knows how to enable and 575 * disable with correct granularity. 576 * 577 * Registers after here exist if and only if the guest SVGA driver 578 * sets SVGA_FIFO_MIN high enough to leave room for them. 579 */ 580 581 /* Valid if register exists: */ 582 SVGA_FIFO_GUEST_3D_HWVERSION, /* Guest driver's 3D version */ 583 SVGA_FIFO_FENCE_GOAL, /* Matching target for SVGA_IRQFLAG_FENCE_GOAL */ 584 SVGA_FIFO_BUSY, /* See "FIFO Synchronization Registers" */ 585 586 /* 587 * Always keep this last. This defines the maximum number of 588 * registers we know about. At power-on, this value is placed in 589 * the SVGA_REG_MEM_REGS register, and we expect the guest driver 590 * to allocate this much space in FIFO memory for registers. 591 */ 592 SVGA_FIFO_NUM_REGS 593}; 594 595 596/* 597 * Definition of registers included in extended FIFO support. 598 * 599 * The guest SVGA driver gets to allocate the FIFO between registers 600 * and data. It must always allocate at least 4 registers, but old 601 * drivers stopped there. 602 * 603 * The VMX will enable extended FIFO support if and only if the guest 604 * left enough room for all registers defined as part of the mandatory 605 * set for the extended FIFO. 606 * 607 * Note that the guest drivers typically allocate the FIFO only at 608 * initialization time, not at mode switches, so it's likely that the 609 * number of FIFO registers won't change without a reboot. 610 * 611 * All registers less than this value are guaranteed to be present if 612 * svgaUser->fifo.extended is set. Any later registers must be tested 613 * individually for compatibility at each use (in the VMX). 614 * 615 * This value is used only by the VMX, so it can change without 616 * affecting driver compatibility; keep it that way? 617 */ 618#define SVGA_FIFO_EXTENDED_MANDATORY_REGS (SVGA_FIFO_3D_CAPS_LAST + 1) 619 620 621/* 622 * FIFO Synchronization Registers 623 * 624 * This explains the relationship between the various FIFO 625 * sync-related registers in IOSpace and in FIFO space. 626 * 627 * SVGA_REG_SYNC -- 628 * 629 * The SYNC register can be used in two different ways by the guest: 630 * 631 * 1. If the guest wishes to fully sync (drain) the FIFO, 632 * it will write once to SYNC then poll on the BUSY 633 * register. The FIFO is sync'ed once BUSY is zero. 634 * 635 * 2. If the guest wants to asynchronously wake up the host, 636 * it will write once to SYNC without polling on BUSY. 637 * Ideally it will do this after some new commands have 638 * been placed in the FIFO, and after reading a zero 639 * from SVGA_FIFO_BUSY. 640 * 641 * (1) is the original behaviour that SYNC was designed to 642 * support. Originally, a write to SYNC would implicitly 643 * trigger a read from BUSY. This causes us to synchronously 644 * process the FIFO. 645 * 646 * This behaviour has since been changed so that writing SYNC 647 * will *not* implicitly cause a read from BUSY. Instead, it 648 * makes a channel call which asynchronously wakes up the MKS 649 * thread. 650 * 651 * New guests can use this new behaviour to implement (2) 652 * efficiently. This lets guests get the host's attention 653 * without waiting for the MKS to poll, which gives us much 654 * better CPU utilization on SMP hosts and on UP hosts while 655 * we're blocked on the host GPU. 656 * 657 * Old guests shouldn't notice the behaviour change. SYNC was 658 * never guaranteed to process the entire FIFO, since it was 659 * bounded to a particular number of CPU cycles. Old guests will 660 * still loop on the BUSY register until the FIFO is empty. 661 * 662 * Writing to SYNC currently has the following side-effects: 663 * 664 * - Sets SVGA_REG_BUSY to TRUE (in the monitor) 665 * - Asynchronously wakes up the MKS thread for FIFO processing 666 * - The value written to SYNC is recorded as a "reason", for 667 * stats purposes. 668 * 669 * If SVGA_FIFO_BUSY is available, drivers are advised to only 670 * write to SYNC if SVGA_FIFO_BUSY is FALSE. Drivers should set 671 * SVGA_FIFO_BUSY to TRUE after writing to SYNC. The MKS will 672 * eventually set SVGA_FIFO_BUSY on its own, but this approach 673 * lets the driver avoid sending multiple asynchronous wakeup 674 * messages to the MKS thread. 675 * 676 * SVGA_REG_BUSY -- 677 * 678 * This register is set to TRUE when SVGA_REG_SYNC is written, 679 * and it reads as FALSE when the FIFO has been completely 680 * drained. 681 * 682 * Every read from this register causes us to synchronously 683 * process FIFO commands. There is no guarantee as to how many 684 * commands each read will process. 685 * 686 * CPU time spent processing FIFO commands will be billed to 687 * the guest. 688 * 689 * New drivers should avoid using this register unless they 690 * need to guarantee that the FIFO is completely drained. It 691 * is overkill for performing a sync-to-fence. Older drivers 692 * will use this register for any type of synchronization. 693 * 694 * SVGA_FIFO_BUSY -- 695 * 696 * This register is a fast way for the guest driver to check 697 * whether the FIFO is already being processed. It reads and 698 * writes at normal RAM speeds, with no monitor intervention. 699 * 700 * If this register reads as TRUE, the host is guaranteeing that 701 * any new commands written into the FIFO will be noticed before 702 * the MKS goes back to sleep. 703 * 704 * If this register reads as FALSE, no such guarantee can be 705 * made. 706 * 707 * The guest should use this register to quickly determine 708 * whether or not it needs to wake up the host. If the guest 709 * just wrote a command or group of commands that it would like 710 * the host to begin processing, it should: 711 * 712 * 1. Read SVGA_FIFO_BUSY. If it reads as TRUE, no further 713 * action is necessary. 714 * 715 * 2. Write TRUE to SVGA_FIFO_BUSY. This informs future guest 716 * code that we've already sent a SYNC to the host and we 717 * don't need to send a duplicate. 718 * 719 * 3. Write a reason to SVGA_REG_SYNC. This will send an 720 * asynchronous wakeup to the MKS thread. 721 */ 722 723 724/* 725 * FIFO Capabilities 726 * 727 * Fence -- Fence register and command are supported 728 * Accel Front -- Front buffer only commands are supported 729 * Pitch Lock -- Pitch lock register is supported 730 * Video -- SVGA Video overlay units are supported 731 * Escape -- Escape command is supported 732 * 733 * XXX: Add longer descriptions for each capability, including a list 734 * of the new features that each capability provides. 735 * 736 * SVGA_FIFO_CAP_SCREEN_OBJECT -- 737 * 738 * Provides dynamic multi-screen rendering, for improved Unity and 739 * multi-monitor modes. With Screen Object, the guest can 740 * dynamically create and destroy 'screens', which can represent 741 * Unity windows or virtual monitors. Screen Object also provides 742 * strong guarantees that DMA operations happen only when 743 * guest-initiated. Screen Object deprecates the BAR1 guest 744 * framebuffer (GFB) and all commands that work only with the GFB. 745 * 746 * New registers: 747 * FIFO_CURSOR_SCREEN_ID, VIDEO_DATA_GMRID, VIDEO_DST_SCREEN_ID 748 * 749 * New 2D commands: 750 * DEFINE_SCREEN, DESTROY_SCREEN, DEFINE_GMRFB, BLIT_GMRFB_TO_SCREEN, 751 * BLIT_SCREEN_TO_GMRFB, ANNOTATION_FILL, ANNOTATION_COPY 752 * 753 * New 3D commands: 754 * BLIT_SURFACE_TO_SCREEN 755 * 756 * New guarantees: 757 * 758 * - The host will not read or write guest memory, including the GFB, 759 * except when explicitly initiated by a DMA command. 760 * 761 * - All DMA, including legacy DMA like UPDATE and PRESENT_READBACK, 762 * is guaranteed to complete before any subsequent FENCEs. 763 * 764 * - All legacy commands which affect a Screen (UPDATE, PRESENT, 765 * PRESENT_READBACK) as well as new Screen blit commands will 766 * all behave consistently as blits, and memory will be read 767 * or written in FIFO order. 768 * 769 * For example, if you PRESENT from one SVGA3D surface to multiple 770 * places on the screen, the data copied will always be from the 771 * SVGA3D surface at the time the PRESENT was issued in the FIFO. 772 * This was not necessarily true on devices without Screen Object. 773 * 774 * This means that on devices that support Screen Object, the 775 * PRESENT_READBACK command should not be necessary unless you 776 * actually want to read back the results of 3D rendering into 777 * system memory. (And for that, the BLIT_SCREEN_TO_GMRFB 778 * command provides a strict superset of functionality.) 779 * 780 * - When a screen is resized, either using Screen Object commands or 781 * legacy multimon registers, its contents are preserved. 782 * 783 * SVGA_FIFO_CAP_GMR2 -- 784 * 785 * Provides new commands to define and remap guest memory regions (GMR). 786 * 787 * New 2D commands: 788 * DEFINE_GMR2, REMAP_GMR2. 789 * 790 * SVGA_FIFO_CAP_3D_HWVERSION_REVISED -- 791 * 792 * Indicates new register SVGA_FIFO_3D_HWVERSION_REVISED exists. 793 * This register may replace SVGA_FIFO_3D_HWVERSION on platforms 794 * that enforce graphics resource limits. This allows the platform 795 * to clear SVGA_FIFO_3D_HWVERSION and disable 3D in legacy guest 796 * drivers that do not limit their resources. 797 * 798 * Note this is an alias to SVGA_FIFO_CAP_GMR2 because these indicators 799 * are codependent (and thus we use a single capability bit). 800 * 801 * SVGA_FIFO_CAP_SCREEN_OBJECT_2 -- 802 * 803 * Modifies the DEFINE_SCREEN command to include a guest provided 804 * backing store in GMR memory and the bytesPerLine for the backing 805 * store. This capability requires the use of a backing store when 806 * creating screen objects. However if SVGA_FIFO_CAP_SCREEN_OBJECT 807 * is present then backing stores are optional. 808 * 809 * SVGA_FIFO_CAP_DEAD -- 810 * 811 * Drivers should not use this cap bit. This cap bit can not be 812 * reused since some hosts already expose it. 813 */ 814 815#define SVGA_FIFO_CAP_NONE 0 816#define SVGA_FIFO_CAP_FENCE (1<<0) 817#define SVGA_FIFO_CAP_ACCELFRONT (1<<1) 818#define SVGA_FIFO_CAP_PITCHLOCK (1<<2) 819#define SVGA_FIFO_CAP_VIDEO (1<<3) 820#define SVGA_FIFO_CAP_CURSOR_BYPASS_3 (1<<4) 821#define SVGA_FIFO_CAP_ESCAPE (1<<5) 822#define SVGA_FIFO_CAP_RESERVE (1<<6) 823#define SVGA_FIFO_CAP_SCREEN_OBJECT (1<<7) 824#define SVGA_FIFO_CAP_GMR2 (1<<8) 825#define SVGA_FIFO_CAP_3D_HWVERSION_REVISED SVGA_FIFO_CAP_GMR2 826#define SVGA_FIFO_CAP_SCREEN_OBJECT_2 (1<<9) 827#define SVGA_FIFO_CAP_DEAD (1<<10) 828 829 830/* 831 * FIFO Flags 832 * 833 * Accel Front -- Driver should use front buffer only commands 834 */ 835 836#define SVGA_FIFO_FLAG_NONE 0 837#define SVGA_FIFO_FLAG_ACCELFRONT (1<<0) 838#define SVGA_FIFO_FLAG_RESERVED (1<<31) /* Internal use only */ 839 840/* 841 * FIFO reservation sentinel value 842 */ 843 844#define SVGA_FIFO_RESERVED_UNKNOWN 0xffffffff 845 846 847/* 848 * Video overlay support 849 */ 850 851#define SVGA_NUM_OVERLAY_UNITS 32 852 853 854/* 855 * Video capabilities that the guest is currently using 856 */ 857 858#define SVGA_VIDEO_FLAG_COLORKEY 0x0001 859 860 861/* 862 * Offsets for the video overlay registers 863 */ 864 865enum { 866 SVGA_VIDEO_ENABLED = 0, 867 SVGA_VIDEO_FLAGS, 868 SVGA_VIDEO_DATA_OFFSET, 869 SVGA_VIDEO_FORMAT, 870 SVGA_VIDEO_COLORKEY, 871 SVGA_VIDEO_SIZE, /* Deprecated */ 872 SVGA_VIDEO_WIDTH, 873 SVGA_VIDEO_HEIGHT, 874 SVGA_VIDEO_SRC_X, 875 SVGA_VIDEO_SRC_Y, 876 SVGA_VIDEO_SRC_WIDTH, 877 SVGA_VIDEO_SRC_HEIGHT, 878 SVGA_VIDEO_DST_X, /* Signed int32 */ 879 SVGA_VIDEO_DST_Y, /* Signed int32 */ 880 SVGA_VIDEO_DST_WIDTH, 881 SVGA_VIDEO_DST_HEIGHT, 882 SVGA_VIDEO_PITCH_1, 883 SVGA_VIDEO_PITCH_2, 884 SVGA_VIDEO_PITCH_3, 885 SVGA_VIDEO_DATA_GMRID, /* Optional, defaults to SVGA_GMR_FRAMEBUFFER */ 886 SVGA_VIDEO_DST_SCREEN_ID, /* Optional, defaults to virtual coords (SVGA_ID_INVALID) */ 887 SVGA_VIDEO_NUM_REGS 888}; 889 890 891/* 892 * SVGA Overlay Units 893 * 894 * width and height relate to the entire source video frame. 895 * srcX, srcY, srcWidth and srcHeight represent subset of the source 896 * video frame to be displayed. 897 */ 898 899typedef struct SVGAOverlayUnit { 900 uint32 enabled; 901 uint32 flags; 902 uint32 dataOffset; 903 uint32 format; 904 uint32 colorKey; 905 uint32 size; 906 uint32 width; 907 uint32 height; 908 uint32 srcX; 909 uint32 srcY; 910 uint32 srcWidth; 911 uint32 srcHeight; 912 int32 dstX; 913 int32 dstY; 914 uint32 dstWidth; 915 uint32 dstHeight; 916 uint32 pitches[3]; 917 uint32 dataGMRId; 918 uint32 dstScreenId; 919} SVGAOverlayUnit; 920 921 922/* 923 * SVGAScreenObject -- 924 * 925 * This is a new way to represent a guest's multi-monitor screen or 926 * Unity window. Screen objects are only supported if the 927 * SVGA_FIFO_CAP_SCREEN_OBJECT capability bit is set. 928 * 929 * If Screen Objects are supported, they can be used to fully 930 * replace the functionality provided by the framebuffer registers 931 * (SVGA_REG_WIDTH, HEIGHT, etc.) and by SVGA_CAP_DISPLAY_TOPOLOGY. 932 * 933 * The screen object is a struct with guaranteed binary 934 * compatibility. New flags can be added, and the struct may grow, 935 * but existing fields must retain their meaning. 936 * 937 * Added with SVGA_FIFO_CAP_SCREEN_OBJECT_2 are required fields of 938 * a SVGAGuestPtr that is used to back the screen contents. This 939 * memory must come from the GFB. The guest is not allowed to 940 * access the memory and doing so will have undefined results. The 941 * backing store is required to be page aligned and the size is 942 * padded to the next page boundry. The number of pages is: 943 * (bytesPerLine * size.width * 4 + PAGE_SIZE - 1) / PAGE_SIZE 944 * 945 * The pitch in the backingStore is required to be at least large 946 * enough to hold a 32bbp scanline. It is recommended that the 947 * driver pad bytesPerLine for a potential performance win. 948 * 949 * The cloneCount field is treated as a hint from the guest that 950 * the user wants this display to be cloned, countCount times. A 951 * value of zero means no cloning should happen. 952 */ 953 954#define SVGA_SCREEN_MUST_BE_SET (1 << 0) /* Must be set or results undefined */ 955#define SVGA_SCREEN_HAS_ROOT SVGA_SCREEN_MUST_BE_SET /* Deprecated */ 956#define SVGA_SCREEN_IS_PRIMARY (1 << 1) /* Guest considers this screen to be 'primary' */ 957#define SVGA_SCREEN_FULLSCREEN_HINT (1 << 2) /* Guest is running a fullscreen app here */ 958 959/* 960 * Added with SVGA_FIFO_CAP_SCREEN_OBJECT_2. When the screen is 961 * deactivated the base layer is defined to lose all contents and 962 * become black. When a screen is deactivated the backing store is 963 * optional. When set backingPtr and bytesPerLine will be ignored. 964 */ 965#define SVGA_SCREEN_DEACTIVATE (1 << 3) 966 967/* 968 * Added with SVGA_FIFO_CAP_SCREEN_OBJECT_2. When this flag is set 969 * the screen contents will be outputted as all black to the user 970 * though the base layer contents is preserved. The screen base layer 971 * can still be read and written to like normal though the no visible 972 * effect will be seen by the user. When the flag is changed the 973 * screen will be blanked or redrawn to the current contents as needed 974 * without any extra commands from the driver. This flag only has an 975 * effect when the screen is not deactivated. 976 */ 977#define SVGA_SCREEN_BLANKING (1 << 4) 978 979typedef 980struct SVGAScreenObject { 981 uint32 structSize; /* sizeof(SVGAScreenObject) */ 982 uint32 id; 983 uint32 flags; 984 struct { 985 uint32 width; 986 uint32 height; 987 } size; 988 struct { 989 int32 x; 990 int32 y; 991 } root; 992 993 /* 994 * Added and required by SVGA_FIFO_CAP_SCREEN_OBJECT_2, optional 995 * with SVGA_FIFO_CAP_SCREEN_OBJECT. 996 */ 997 SVGAGuestImage backingStore; 998 uint32 cloneCount; 999} SVGAScreenObject; 1000 1001 1002/* 1003 * Commands in the command FIFO: 1004 * 1005 * Command IDs defined below are used for the traditional 2D FIFO 1006 * communication (not all commands are available for all versions of the 1007 * SVGA FIFO protocol). 1008 * 1009 * Note the holes in the command ID numbers: These commands have been 1010 * deprecated, and the old IDs must not be reused. 1011 * 1012 * Command IDs from 1000 to 1999 are reserved for use by the SVGA3D 1013 * protocol. 1014 * 1015 * Each command's parameters are described by the comments and 1016 * structs below. 1017 */ 1018 1019typedef enum { 1020 SVGA_CMD_INVALID_CMD = 0, 1021 SVGA_CMD_UPDATE = 1, 1022 SVGA_CMD_RECT_COPY = 3, 1023 SVGA_CMD_DEFINE_CURSOR = 19, 1024 SVGA_CMD_DEFINE_ALPHA_CURSOR = 22, 1025 SVGA_CMD_UPDATE_VERBOSE = 25, 1026 SVGA_CMD_FRONT_ROP_FILL = 29, 1027 SVGA_CMD_FENCE = 30, 1028 SVGA_CMD_ESCAPE = 33, 1029 SVGA_CMD_DEFINE_SCREEN = 34, 1030 SVGA_CMD_DESTROY_SCREEN = 35, 1031 SVGA_CMD_DEFINE_GMRFB = 36, 1032 SVGA_CMD_BLIT_GMRFB_TO_SCREEN = 37, 1033 SVGA_CMD_BLIT_SCREEN_TO_GMRFB = 38, 1034 SVGA_CMD_ANNOTATION_FILL = 39, 1035 SVGA_CMD_ANNOTATION_COPY = 40, 1036 SVGA_CMD_DEFINE_GMR2 = 41, 1037 SVGA_CMD_REMAP_GMR2 = 42, 1038 SVGA_CMD_MAX 1039} SVGAFifoCmdId; 1040 1041#define SVGA_CMD_MAX_ARGS 64 1042 1043 1044/* 1045 * SVGA_CMD_UPDATE -- 1046 * 1047 * This is a DMA transfer which copies from the Guest Framebuffer 1048 * (GFB) at BAR1 + SVGA_REG_FB_OFFSET to any screens which 1049 * intersect with the provided virtual rectangle. 1050 * 1051 * This command does not support using arbitrary guest memory as a 1052 * data source- it only works with the pre-defined GFB memory. 1053 * This command also does not support signed virtual coordinates. 1054 * If you have defined screens (using SVGA_CMD_DEFINE_SCREEN) with 1055 * negative root x/y coordinates, the negative portion of those 1056 * screens will not be reachable by this command. 1057 * 1058 * This command is not necessary when using framebuffer 1059 * traces. Traces are automatically enabled if the SVGA FIFO is 1060 * disabled, and you may explicitly enable/disable traces using 1061 * SVGA_REG_TRACES. With traces enabled, any write to the GFB will 1062 * automatically act as if a subsequent SVGA_CMD_UPDATE was issued. 1063 * 1064 * Traces and SVGA_CMD_UPDATE are the only supported ways to render 1065 * pseudocolor screen updates. The newer Screen Object commands 1066 * only support true color formats. 1067 * 1068 * Availability: 1069 * Always available. 1070 */ 1071 1072typedef 1073struct SVGAFifoCmdUpdate { 1074 uint32 x; 1075 uint32 y; 1076 uint32 width; 1077 uint32 height; 1078} SVGAFifoCmdUpdate; 1079 1080 1081/* 1082 * SVGA_CMD_RECT_COPY -- 1083 * 1084 * Perform a rectangular DMA transfer from one area of the GFB to 1085 * another, and copy the result to any screens which intersect it. 1086 * 1087 * Availability: 1088 * SVGA_CAP_RECT_COPY 1089 */ 1090 1091typedef 1092struct SVGAFifoCmdRectCopy { 1093 uint32 srcX; 1094 uint32 srcY; 1095 uint32 destX; 1096 uint32 destY; 1097 uint32 width; 1098 uint32 height; 1099} SVGAFifoCmdRectCopy; 1100 1101 1102/* 1103 * SVGA_CMD_DEFINE_CURSOR -- 1104 * 1105 * Provide a new cursor image, as an AND/XOR mask. 1106 * 1107 * The recommended way to position the cursor overlay is by using 1108 * the SVGA_FIFO_CURSOR_* registers, supported by the 1109 * SVGA_FIFO_CAP_CURSOR_BYPASS_3 capability. 1110 * 1111 * Availability: 1112 * SVGA_CAP_CURSOR 1113 */ 1114 1115typedef 1116struct SVGAFifoCmdDefineCursor { 1117 uint32 id; /* Reserved, must be zero. */ 1118 uint32 hotspotX; 1119 uint32 hotspotY; 1120 uint32 width; 1121 uint32 height; 1122 uint32 andMaskDepth; /* Value must be 1 or equal to BITS_PER_PIXEL */ 1123 uint32 xorMaskDepth; /* Value must be 1 or equal to BITS_PER_PIXEL */ 1124 /* 1125 * Followed by scanline data for AND mask, then XOR mask. 1126 * Each scanline is padded to a 32-bit boundary. 1127 */ 1128} SVGAFifoCmdDefineCursor; 1129 1130 1131/* 1132 * SVGA_CMD_DEFINE_ALPHA_CURSOR -- 1133 * 1134 * Provide a new cursor image, in 32-bit BGRA format. 1135 * 1136 * The recommended way to position the cursor overlay is by using 1137 * the SVGA_FIFO_CURSOR_* registers, supported by the 1138 * SVGA_FIFO_CAP_CURSOR_BYPASS_3 capability. 1139 * 1140 * Availability: 1141 * SVGA_CAP_ALPHA_CURSOR 1142 */ 1143 1144typedef 1145struct SVGAFifoCmdDefineAlphaCursor { 1146 uint32 id; /* Reserved, must be zero. */ 1147 uint32 hotspotX; 1148 uint32 hotspotY; 1149 uint32 width; 1150 uint32 height; 1151 /* Followed by scanline data */ 1152} SVGAFifoCmdDefineAlphaCursor; 1153 1154 1155/* 1156 * SVGA_CMD_UPDATE_VERBOSE -- 1157 * 1158 * Just like SVGA_CMD_UPDATE, but also provide a per-rectangle 1159 * 'reason' value, an opaque cookie which is used by internal 1160 * debugging tools. Third party drivers should not use this 1161 * command. 1162 * 1163 * Availability: 1164 * SVGA_CAP_EXTENDED_FIFO 1165 */ 1166 1167typedef 1168struct SVGAFifoCmdUpdateVerbose { 1169 uint32 x; 1170 uint32 y; 1171 uint32 width; 1172 uint32 height; 1173 uint32 reason; 1174} SVGAFifoCmdUpdateVerbose; 1175 1176 1177/* 1178 * SVGA_CMD_FRONT_ROP_FILL -- 1179 * 1180 * This is a hint which tells the SVGA device that the driver has 1181 * just filled a rectangular region of the GFB with a solid 1182 * color. Instead of reading these pixels from the GFB, the device 1183 * can assume that they all equal 'color'. This is primarily used 1184 * for remote desktop protocols. 1185 * 1186 * Availability: 1187 * SVGA_FIFO_CAP_ACCELFRONT 1188 */ 1189 1190#define SVGA_ROP_COPY 0x03 1191 1192typedef 1193struct SVGAFifoCmdFrontRopFill { 1194 uint32 color; /* In the same format as the GFB */ 1195 uint32 x; 1196 uint32 y; 1197 uint32 width; 1198 uint32 height; 1199 uint32 rop; /* Must be SVGA_ROP_COPY */ 1200} SVGAFifoCmdFrontRopFill; 1201 1202 1203/* 1204 * SVGA_CMD_FENCE -- 1205 * 1206 * Insert a synchronization fence. When the SVGA device reaches 1207 * this command, it will copy the 'fence' value into the 1208 * SVGA_FIFO_FENCE register. It will also compare the fence against 1209 * SVGA_FIFO_FENCE_GOAL. If the fence matches the goal and the 1210 * SVGA_IRQFLAG_FENCE_GOAL interrupt is enabled, the device will 1211 * raise this interrupt. 1212 * 1213 * Availability: 1214 * SVGA_FIFO_FENCE for this command, 1215 * SVGA_CAP_IRQMASK for SVGA_FIFO_FENCE_GOAL. 1216 */ 1217 1218typedef 1219struct { 1220 uint32 fence; 1221} SVGAFifoCmdFence; 1222 1223 1224/* 1225 * SVGA_CMD_ESCAPE -- 1226 * 1227 * Send an extended or vendor-specific variable length command. 1228 * This is used for video overlay, third party plugins, and 1229 * internal debugging tools. See svga_escape.h 1230 * 1231 * Availability: 1232 * SVGA_FIFO_CAP_ESCAPE 1233 */ 1234 1235typedef 1236struct SVGAFifoCmdEscape { 1237 uint32 nsid; 1238 uint32 size; 1239 /* followed by 'size' bytes of data */ 1240} SVGAFifoCmdEscape; 1241 1242 1243/* 1244 * SVGA_CMD_DEFINE_SCREEN -- 1245 * 1246 * Define or redefine an SVGAScreenObject. See the description of 1247 * SVGAScreenObject above. The video driver is responsible for 1248 * generating new screen IDs. They should be small positive 1249 * integers. The virtual device will have an implementation 1250 * specific upper limit on the number of screen IDs 1251 * supported. Drivers are responsible for recycling IDs. The first 1252 * valid ID is zero. 1253 * 1254 * - Interaction with other registers: 1255 * 1256 * For backwards compatibility, when the GFB mode registers (WIDTH, 1257 * HEIGHT, PITCHLOCK, BITS_PER_PIXEL) are modified, the SVGA device 1258 * deletes all screens other than screen #0, and redefines screen 1259 * #0 according to the specified mode. Drivers that use 1260 * SVGA_CMD_DEFINE_SCREEN should destroy or redefine screen #0. 1261 * 1262 * If you use screen objects, do not use the legacy multi-mon 1263 * registers (SVGA_REG_NUM_GUEST_DISPLAYS, SVGA_REG_DISPLAY_*). 1264 * 1265 * Availability: 1266 * SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2 1267 */ 1268 1269typedef 1270struct { 1271 SVGAScreenObject screen; /* Variable-length according to version */ 1272} SVGAFifoCmdDefineScreen; 1273 1274 1275/* 1276 * SVGA_CMD_DESTROY_SCREEN -- 1277 * 1278 * Destroy an SVGAScreenObject. Its ID is immediately available for 1279 * re-use. 1280 * 1281 * Availability: 1282 * SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2 1283 */ 1284 1285typedef 1286struct { 1287 uint32 screenId; 1288} SVGAFifoCmdDestroyScreen; 1289 1290 1291/* 1292 * SVGA_CMD_DEFINE_GMRFB -- 1293 * 1294 * This command sets a piece of SVGA device state called the 1295 * Guest Memory Region Framebuffer, or GMRFB. The GMRFB is a 1296 * piece of light-weight state which identifies the location and 1297 * format of an image in guest memory or in BAR1. The GMRFB has 1298 * an arbitrary size, and it doesn't need to match the geometry 1299 * of the GFB or any screen object. 1300 * 1301 * The GMRFB can be redefined as often as you like. You could 1302 * always use the same GMRFB, you could redefine it before 1303 * rendering from a different guest screen, or you could even 1304 * redefine it before every blit. 1305 * 1306 * There are multiple ways to use this command. The simplest way is 1307 * to use it to move the framebuffer either to elsewhere in the GFB 1308 * (BAR1) memory region, or to a user-defined GMR. This lets a 1309 * driver use a framebuffer allocated entirely out of normal system 1310 * memory, which we encourage. 1311 * 1312 * Another way to use this command is to set up a ring buffer of 1313 * updates in GFB memory. If a driver wants to ensure that no 1314 * frames are skipped by the SVGA device, it is important that the 1315 * driver not modify the source data for a blit until the device is 1316 * done processing the command. One efficient way to accomplish 1317 * this is to use a ring of small DMA buffers. Each buffer is used 1318 * for one blit, then we move on to the next buffer in the 1319 * ring. The FENCE mechanism is used to protect each buffer from 1320 * re-use until the device is finished with that buffer's 1321 * corresponding blit. 1322 * 1323 * This command does not affect the meaning of SVGA_CMD_UPDATE. 1324 * UPDATEs always occur from the legacy GFB memory area. This 1325 * command has no support for pseudocolor GMRFBs. Currently only 1326 * true-color 15, 16, and 24-bit depths are supported. Future 1327 * devices may expose capabilities for additional framebuffer 1328 * formats. 1329 * 1330 * The default GMRFB value is undefined. Drivers must always send 1331 * this command at least once before performing any blit from the 1332 * GMRFB. 1333 * 1334 * Availability: 1335 * SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2 1336 */ 1337 1338typedef 1339struct { 1340 SVGAGuestPtr ptr; 1341 uint32 bytesPerLine; 1342 SVGAGMRImageFormat format; 1343} SVGAFifoCmdDefineGMRFB; 1344 1345 1346/* 1347 * SVGA_CMD_BLIT_GMRFB_TO_SCREEN -- 1348 * 1349 * This is a guest-to-host blit. It performs a DMA operation to 1350 * copy a rectangular region of pixels from the current GMRFB to 1351 * one or more Screen Objects. 1352 * 1353 * The destination coordinate may be specified relative to a 1354 * screen's origin (if a screen ID is specified) or relative to the 1355 * virtual coordinate system's origin (if the screen ID is 1356 * SVGA_ID_INVALID). The actual destination may span zero or more 1357 * screens, in the case of a virtual destination rect or a rect 1358 * which extends off the edge of the specified screen. 1359 * 1360 * This command writes to the screen's "base layer": the underlying 1361 * framebuffer which exists below any cursor or video overlays. No 1362 * action is necessary to explicitly hide or update any overlays 1363 * which exist on top of the updated region. 1364 * 1365 * The SVGA device is guaranteed to finish reading from the GMRFB 1366 * by the time any subsequent FENCE commands are reached. 1367 * 1368 * This command consumes an annotation. See the 1369 * SVGA_CMD_ANNOTATION_* commands for details. 1370 * 1371 * Availability: 1372 * SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2 1373 */ 1374 1375typedef 1376struct { 1377 SVGASignedPoint srcOrigin; 1378 SVGASignedRect destRect; 1379 uint32 destScreenId; 1380} SVGAFifoCmdBlitGMRFBToScreen; 1381 1382 1383/* 1384 * SVGA_CMD_BLIT_SCREEN_TO_GMRFB -- 1385 * 1386 * This is a host-to-guest blit. It performs a DMA operation to 1387 * copy a rectangular region of pixels from a single Screen Object 1388 * back to the current GMRFB. 1389 * 1390 * Usage note: This command should be used rarely. It will 1391 * typically be inefficient, but it is necessary for some types of 1392 * synchronization between 3D (GPU) and 2D (CPU) rendering into 1393 * overlapping areas of a screen. 1394 * 1395 * The source coordinate is specified relative to a screen's 1396 * origin. The provided screen ID must be valid. If any parameters 1397 * are invalid, the resulting pixel values are undefined. 1398 * 1399 * This command reads the screen's "base layer". Overlays like 1400 * video and cursor are not included, but any data which was sent 1401 * using a blit-to-screen primitive will be available, no matter 1402 * whether the data's original source was the GMRFB or the 3D 1403 * acceleration hardware. 1404 * 1405 * Note that our guest-to-host blits and host-to-guest blits aren't 1406 * symmetric in their current implementation. While the parameters 1407 * are identical, host-to-guest blits are a lot less featureful. 1408 * They do not support clipping: If the source parameters don't 1409 * fully fit within a screen, the blit fails. They must originate 1410 * from exactly one screen. Virtual coordinates are not directly 1411 * supported. 1412 * 1413 * Host-to-guest blits do support the same set of GMRFB formats 1414 * offered by guest-to-host blits. 1415 * 1416 * The SVGA device is guaranteed to finish writing to the GMRFB by 1417 * the time any subsequent FENCE commands are reached. 1418 * 1419 * Availability: 1420 * SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2 1421 */ 1422 1423typedef 1424struct { 1425 SVGASignedPoint destOrigin; 1426 SVGASignedRect srcRect; 1427 uint32 srcScreenId; 1428} SVGAFifoCmdBlitScreenToGMRFB; 1429 1430 1431/* 1432 * SVGA_CMD_ANNOTATION_FILL -- 1433 * 1434 * This is a blit annotation. This command stores a small piece of 1435 * device state which is consumed by the next blit-to-screen 1436 * command. The state is only cleared by commands which are 1437 * specifically documented as consuming an annotation. Other 1438 * commands (such as ESCAPEs for debugging) may intervene between 1439 * the annotation and its associated blit. 1440 * 1441 * This annotation is a promise about the contents of the next 1442 * blit: The video driver is guaranteeing that all pixels in that 1443 * blit will have the same value, specified here as a color in 1444 * SVGAColorBGRX format. 1445 * 1446 * The SVGA device can still render the blit correctly even if it 1447 * ignores this annotation, but the annotation may allow it to 1448 * perform the blit more efficiently, for example by ignoring the 1449 * source data and performing a fill in hardware. 1450 * 1451 * This annotation is most important for performance when the 1452 * user's display is being remoted over a network connection. 1453 * 1454 * Availability: 1455 * SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2 1456 */ 1457 1458typedef 1459struct { 1460 SVGAColorBGRX color; 1461} SVGAFifoCmdAnnotationFill; 1462 1463 1464/* 1465 * SVGA_CMD_ANNOTATION_COPY -- 1466 * 1467 * This is a blit annotation. See SVGA_CMD_ANNOTATION_FILL for more 1468 * information about annotations. 1469 * 1470 * This annotation is a promise about the contents of the next 1471 * blit: The video driver is guaranteeing that all pixels in that 1472 * blit will have the same value as those which already exist at an 1473 * identically-sized region on the same or a different screen. 1474 * 1475 * Note that the source pixels for the COPY in this annotation are 1476 * sampled before applying the anqnotation's associated blit. They 1477 * are allowed to overlap with the blit's destination pixels. 1478 * 1479 * The copy source rectangle is specified the same way as the blit 1480 * destination: it can be a rectangle which spans zero or more 1481 * screens, specified relative to either a screen or to the virtual 1482 * coordinate system's origin. If the source rectangle includes 1483 * pixels which are not from exactly one screen, the results are 1484 * undefined. 1485 * 1486 * Availability: 1487 * SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2 1488 */ 1489 1490typedef 1491struct { 1492 SVGASignedPoint srcOrigin; 1493 uint32 srcScreenId; 1494} SVGAFifoCmdAnnotationCopy; 1495 1496 1497/* 1498 * SVGA_CMD_DEFINE_GMR2 -- 1499 * 1500 * Define guest memory region v2. See the description of GMRs above. 1501 * 1502 * Availability: 1503 * SVGA_CAP_GMR2 1504 */ 1505 1506typedef 1507struct { 1508 uint32 gmrId; 1509 uint32 numPages; 1510} SVGAFifoCmdDefineGMR2; 1511 1512 1513/* 1514 * SVGA_CMD_REMAP_GMR2 -- 1515 * 1516 * Remap guest memory region v2. See the description of GMRs above. 1517 * 1518 * This command allows guest to modify a portion of an existing GMR by 1519 * invalidating it or reassigning it to different guest physical pages. 1520 * The pages are identified by physical page number (PPN). The pages 1521 * are assumed to be pinned and valid for DMA operations. 1522 * 1523 * Description of command flags: 1524 * 1525 * SVGA_REMAP_GMR2_VIA_GMR: If enabled, references a PPN list in a GMR. 1526 * The PPN list must not overlap with the remap region (this can be 1527 * handled trivially by referencing a separate GMR). If flag is 1528 * disabled, PPN list is appended to SVGARemapGMR command. 1529 * 1530 * SVGA_REMAP_GMR2_PPN64: If set, PPN list is in PPN64 format, otherwise 1531 * it is in PPN32 format. 1532 * 1533 * SVGA_REMAP_GMR2_SINGLE_PPN: If set, PPN list contains a single entry. 1534 * A single PPN can be used to invalidate a portion of a GMR or 1535 * map it to to a single guest scratch page. 1536 * 1537 * Availability: 1538 * SVGA_CAP_GMR2 1539 */ 1540 1541typedef enum { 1542 SVGA_REMAP_GMR2_PPN32 = 0, 1543 SVGA_REMAP_GMR2_VIA_GMR = (1 << 0), 1544 SVGA_REMAP_GMR2_PPN64 = (1 << 1), 1545 SVGA_REMAP_GMR2_SINGLE_PPN = (1 << 2), 1546} SVGARemapGMR2Flags; 1547 1548typedef 1549struct { 1550 uint32 gmrId; 1551 SVGARemapGMR2Flags flags; 1552 uint32 offsetPages; /* offset in pages to begin remap */ 1553 uint32 numPages; /* number of pages to remap */ 1554 /* 1555 * Followed by additional data depending on SVGARemapGMR2Flags. 1556 * 1557 * If flag SVGA_REMAP_GMR2_VIA_GMR is set, single SVGAGuestPtr follows. 1558 * Otherwise an array of page descriptors in PPN32 or PPN64 format 1559 * (according to flag SVGA_REMAP_GMR2_PPN64) follows. If flag 1560 * SVGA_REMAP_GMR2_SINGLE_PPN is set, array contains a single entry. 1561 */ 1562} SVGAFifoCmdRemapGMR2; 1563 1564#endif 1565