1/* 2 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd 3 * Author:Mark Yao <mark.yao@rock-chips.com> 4 * 5 * This software is licensed under the terms of the GNU General Public 6 * License version 2, as published by the Free Software Foundation, and 7 * may be copied, distributed, and modified under those terms. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 15#ifndef _ROCKCHIP_DRM_VOP_H 16#define _ROCKCHIP_DRM_VOP_H 17 18/* register definition */ 19#define REG_CFG_DONE 0x0000 20#define VERSION_INFO 0x0004 21#define SYS_CTRL 0x0008 22#define SYS_CTRL1 0x000c 23#define DSP_CTRL0 0x0010 24#define DSP_CTRL1 0x0014 25#define DSP_BG 0x0018 26#define MCU_CTRL 0x001c 27#define INTR_CTRL0 0x0020 28#define INTR_CTRL1 0x0024 29#define WIN0_CTRL0 0x0030 30#define WIN0_CTRL1 0x0034 31#define WIN0_COLOR_KEY 0x0038 32#define WIN0_VIR 0x003c 33#define WIN0_YRGB_MST 0x0040 34#define WIN0_CBR_MST 0x0044 35#define WIN0_ACT_INFO 0x0048 36#define WIN0_DSP_INFO 0x004c 37#define WIN0_DSP_ST 0x0050 38#define WIN0_SCL_FACTOR_YRGB 0x0054 39#define WIN0_SCL_FACTOR_CBR 0x0058 40#define WIN0_SCL_OFFSET 0x005c 41#define WIN0_SRC_ALPHA_CTRL 0x0060 42#define WIN0_DST_ALPHA_CTRL 0x0064 43#define WIN0_FADING_CTRL 0x0068 44/* win1 register */ 45#define WIN1_CTRL0 0x0070 46#define WIN1_CTRL1 0x0074 47#define WIN1_COLOR_KEY 0x0078 48#define WIN1_VIR 0x007c 49#define WIN1_YRGB_MST 0x0080 50#define WIN1_CBR_MST 0x0084 51#define WIN1_ACT_INFO 0x0088 52#define WIN1_DSP_INFO 0x008c 53#define WIN1_DSP_ST 0x0090 54#define WIN1_SCL_FACTOR_YRGB 0x0094 55#define WIN1_SCL_FACTOR_CBR 0x0098 56#define WIN1_SCL_OFFSET 0x009c 57#define WIN1_SRC_ALPHA_CTRL 0x00a0 58#define WIN1_DST_ALPHA_CTRL 0x00a4 59#define WIN1_FADING_CTRL 0x00a8 60/* win2 register */ 61#define WIN2_CTRL0 0x00b0 62#define WIN2_CTRL1 0x00b4 63#define WIN2_VIR0_1 0x00b8 64#define WIN2_VIR2_3 0x00bc 65#define WIN2_MST0 0x00c0 66#define WIN2_DSP_INFO0 0x00c4 67#define WIN2_DSP_ST0 0x00c8 68#define WIN2_COLOR_KEY 0x00cc 69#define WIN2_MST1 0x00d0 70#define WIN2_DSP_INFO1 0x00d4 71#define WIN2_DSP_ST1 0x00d8 72#define WIN2_SRC_ALPHA_CTRL 0x00dc 73#define WIN2_MST2 0x00e0 74#define WIN2_DSP_INFO2 0x00e4 75#define WIN2_DSP_ST2 0x00e8 76#define WIN2_DST_ALPHA_CTRL 0x00ec 77#define WIN2_MST3 0x00f0 78#define WIN2_DSP_INFO3 0x00f4 79#define WIN2_DSP_ST3 0x00f8 80#define WIN2_FADING_CTRL 0x00fc 81/* win3 register */ 82#define WIN3_CTRL0 0x0100 83#define WIN3_CTRL1 0x0104 84#define WIN3_VIR0_1 0x0108 85#define WIN3_VIR2_3 0x010c 86#define WIN3_MST0 0x0110 87#define WIN3_DSP_INFO0 0x0114 88#define WIN3_DSP_ST0 0x0118 89#define WIN3_COLOR_KEY 0x011c 90#define WIN3_MST1 0x0120 91#define WIN3_DSP_INFO1 0x0124 92#define WIN3_DSP_ST1 0x0128 93#define WIN3_SRC_ALPHA_CTRL 0x012c 94#define WIN3_MST2 0x0130 95#define WIN3_DSP_INFO2 0x0134 96#define WIN3_DSP_ST2 0x0138 97#define WIN3_DST_ALPHA_CTRL 0x013c 98#define WIN3_MST3 0x0140 99#define WIN3_DSP_INFO3 0x0144 100#define WIN3_DSP_ST3 0x0148 101#define WIN3_FADING_CTRL 0x014c 102/* hwc register */ 103#define HWC_CTRL0 0x0150 104#define HWC_CTRL1 0x0154 105#define HWC_MST 0x0158 106#define HWC_DSP_ST 0x015c 107#define HWC_SRC_ALPHA_CTRL 0x0160 108#define HWC_DST_ALPHA_CTRL 0x0164 109#define HWC_FADING_CTRL 0x0168 110/* post process register */ 111#define POST_DSP_HACT_INFO 0x0170 112#define POST_DSP_VACT_INFO 0x0174 113#define POST_SCL_FACTOR_YRGB 0x0178 114#define POST_SCL_CTRL 0x0180 115#define POST_DSP_VACT_INFO_F1 0x0184 116#define DSP_HTOTAL_HS_END 0x0188 117#define DSP_HACT_ST_END 0x018c 118#define DSP_VTOTAL_VS_END 0x0190 119#define DSP_VACT_ST_END 0x0194 120#define DSP_VS_ST_END_F1 0x0198 121#define DSP_VACT_ST_END_F1 0x019c 122/* register definition end */ 123 124/* interrupt define */ 125#define DSP_HOLD_VALID_INTR (1 << 0) 126#define FS_INTR (1 << 1) 127#define LINE_FLAG_INTR (1 << 2) 128#define BUS_ERROR_INTR (1 << 3) 129 130#define INTR_MASK (DSP_HOLD_VALID_INTR | FS_INTR | \ 131 LINE_FLAG_INTR | BUS_ERROR_INTR) 132 133#define DSP_HOLD_VALID_INTR_EN(x) ((x) << 4) 134#define FS_INTR_EN(x) ((x) << 5) 135#define LINE_FLAG_INTR_EN(x) ((x) << 6) 136#define BUS_ERROR_INTR_EN(x) ((x) << 7) 137#define DSP_HOLD_VALID_INTR_MASK (1 << 4) 138#define FS_INTR_MASK (1 << 5) 139#define LINE_FLAG_INTR_MASK (1 << 6) 140#define BUS_ERROR_INTR_MASK (1 << 7) 141 142#define INTR_CLR_SHIFT 8 143#define DSP_HOLD_VALID_INTR_CLR (1 << (INTR_CLR_SHIFT + 0)) 144#define FS_INTR_CLR (1 << (INTR_CLR_SHIFT + 1)) 145#define LINE_FLAG_INTR_CLR (1 << (INTR_CLR_SHIFT + 2)) 146#define BUS_ERROR_INTR_CLR (1 << (INTR_CLR_SHIFT + 3)) 147 148#define DSP_LINE_NUM(x) (((x) & 0x1fff) << 12) 149#define DSP_LINE_NUM_MASK (0x1fff << 12) 150 151/* src alpha ctrl define */ 152#define SRC_FADING_VALUE(x) (((x) & 0xff) << 24) 153#define SRC_GLOBAL_ALPHA(x) (((x) & 0xff) << 16) 154#define SRC_FACTOR_M0(x) (((x) & 0x7) << 6) 155#define SRC_ALPHA_CAL_M0(x) (((x) & 0x1) << 5) 156#define SRC_BLEND_M0(x) (((x) & 0x3) << 3) 157#define SRC_ALPHA_M0(x) (((x) & 0x1) << 2) 158#define SRC_COLOR_M0(x) (((x) & 0x1) << 1) 159#define SRC_ALPHA_EN(x) (((x) & 0x1) << 0) 160/* dst alpha ctrl define */ 161#define DST_FACTOR_M0(x) (((x) & 0x7) << 6) 162 163/* 164 * display output interface supported by rockchip lcdc 165 */ 166#define ROCKCHIP_OUT_MODE_P888 0 167#define ROCKCHIP_OUT_MODE_P666 1 168#define ROCKCHIP_OUT_MODE_P565 2 169/* for use special outface */ 170#define ROCKCHIP_OUT_MODE_AAAA 15 171 172enum alpha_mode { 173 ALPHA_STRAIGHT, 174 ALPHA_INVERSE, 175}; 176 177enum global_blend_mode { 178 ALPHA_GLOBAL, 179 ALPHA_PER_PIX, 180 ALPHA_PER_PIX_GLOBAL, 181}; 182 183enum alpha_cal_mode { 184 ALPHA_SATURATION, 185 ALPHA_NO_SATURATION, 186}; 187 188enum color_mode { 189 ALPHA_SRC_PRE_MUL, 190 ALPHA_SRC_NO_PRE_MUL, 191}; 192 193enum factor_mode { 194 ALPHA_ZERO, 195 ALPHA_ONE, 196 ALPHA_SRC, 197 ALPHA_SRC_INVERSE, 198 ALPHA_SRC_GLOBAL, 199}; 200 201#endif /* _ROCKCHIP_DRM_VOP_H */ 202