1/* 2 * rcar_du_regs.h -- R-Car Display Unit Registers Definitions 3 * 4 * Copyright (C) 2013 Renesas Electronics Corporation 5 * 6 * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com) 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 10 * as published by the Free Software Foundation. 11 */ 12 13#ifndef __RCAR_DU_REGS_H__ 14#define __RCAR_DU_REGS_H__ 15 16#define DU0_REG_OFFSET 0x00000 17#define DU1_REG_OFFSET 0x30000 18#define DU2_REG_OFFSET 0x40000 19 20/* ----------------------------------------------------------------------------- 21 * Display Control Registers 22 */ 23 24#define DSYSR 0x00000 /* display 1 */ 25#define DSYSR_ILTS (1 << 29) 26#define DSYSR_DSEC (1 << 20) 27#define DSYSR_IUPD (1 << 16) 28#define DSYSR_DRES (1 << 9) 29#define DSYSR_DEN (1 << 8) 30#define DSYSR_TVM_MASTER (0 << 6) 31#define DSYSR_TVM_SWITCH (1 << 6) 32#define DSYSR_TVM_TVSYNC (2 << 6) 33#define DSYSR_TVM_MASK (3 << 6) 34#define DSYSR_SCM_INT_NONE (0 << 4) 35#define DSYSR_SCM_INT_SYNC (2 << 4) 36#define DSYSR_SCM_INT_VIDEO (3 << 4) 37#define DSYSR_SCM_MASK (3 << 4) 38 39#define DSMR 0x00004 40#define DSMR_VSPM (1 << 28) 41#define DSMR_ODPM (1 << 27) 42#define DSMR_DIPM_DISP (0 << 25) 43#define DSMR_DIPM_CSYNC (1 << 25) 44#define DSMR_DIPM_DE (3 << 25) 45#define DSMR_DIPM_MASK (3 << 25) 46#define DSMR_CSPM (1 << 24) 47#define DSMR_DIL (1 << 19) 48#define DSMR_VSL (1 << 18) 49#define DSMR_HSL (1 << 17) 50#define DSMR_DDIS (1 << 16) 51#define DSMR_CDEL (1 << 15) 52#define DSMR_CDEM_CDE (0 << 13) 53#define DSMR_CDEM_LOW (2 << 13) 54#define DSMR_CDEM_HIGH (3 << 13) 55#define DSMR_CDEM_MASK (3 << 13) 56#define DSMR_CDED (1 << 12) 57#define DSMR_ODEV (1 << 8) 58#define DSMR_CSY_VH_OR (0 << 6) 59#define DSMR_CSY_333 (2 << 6) 60#define DSMR_CSY_222 (3 << 6) 61#define DSMR_CSY_MASK (3 << 6) 62 63#define DSSR 0x00008 64#define DSSR_VC1FB_DSA0 (0 << 30) 65#define DSSR_VC1FB_DSA1 (1 << 30) 66#define DSSR_VC1FB_DSA2 (2 << 30) 67#define DSSR_VC1FB_INIT (3 << 30) 68#define DSSR_VC1FB_MASK (3 << 30) 69#define DSSR_VC0FB_DSA0 (0 << 28) 70#define DSSR_VC0FB_DSA1 (1 << 28) 71#define DSSR_VC0FB_DSA2 (2 << 28) 72#define DSSR_VC0FB_INIT (3 << 28) 73#define DSSR_VC0FB_MASK (3 << 28) 74#define DSSR_DFB(n) (1 << ((n)+15)) 75#define DSSR_TVR (1 << 15) 76#define DSSR_FRM (1 << 14) 77#define DSSR_VBK (1 << 11) 78#define DSSR_RINT (1 << 9) 79#define DSSR_HBK (1 << 8) 80#define DSSR_ADC(n) (1 << ((n)-1)) 81 82#define DSRCR 0x0000c 83#define DSRCR_TVCL (1 << 15) 84#define DSRCR_FRCL (1 << 14) 85#define DSRCR_VBCL (1 << 11) 86#define DSRCR_RICL (1 << 9) 87#define DSRCR_HBCL (1 << 8) 88#define DSRCR_ADCL(n) (1 << ((n)-1)) 89#define DSRCR_MASK 0x0000cbff 90 91#define DIER 0x00010 92#define DIER_TVE (1 << 15) 93#define DIER_FRE (1 << 14) 94#define DIER_VBE (1 << 11) 95#define DIER_RIE (1 << 9) 96#define DIER_HBE (1 << 8) 97#define DIER_ADCE(n) (1 << ((n)-1)) 98 99#define CPCR 0x00014 100#define CPCR_CP4CE (1 << 19) 101#define CPCR_CP3CE (1 << 18) 102#define CPCR_CP2CE (1 << 17) 103#define CPCR_CP1CE (1 << 16) 104 105#define DPPR 0x00018 106#define DPPR_DPE(n) (1 << ((n)*4-1)) 107#define DPPR_DPS(n, p) (((p)-1) << DPPR_DPS_SHIFT(n)) 108#define DPPR_DPS_SHIFT(n) (((n)-1)*4) 109#define DPPR_BPP16 (DPPR_DPE(8) | DPPR_DPS(8, 1)) /* plane1 */ 110#define DPPR_BPP32_P1 (DPPR_DPE(7) | DPPR_DPS(7, 1)) 111#define DPPR_BPP32_P2 (DPPR_DPE(8) | DPPR_DPS(8, 2)) 112#define DPPR_BPP32 (DPPR_BPP32_P1 | DPPR_BPP32_P2) /* plane1 & 2 */ 113 114#define DEFR 0x00020 115#define DEFR_CODE (0x7773 << 16) 116#define DEFR_EXSL (1 << 12) 117#define DEFR_EXVL (1 << 11) 118#define DEFR_EXUP (1 << 5) 119#define DEFR_VCUP (1 << 4) 120#define DEFR_DEFE (1 << 0) 121 122#define DAPCR 0x00024 123#define DAPCR_CODE (0x7773 << 16) 124#define DAPCR_AP2E (1 << 4) 125#define DAPCR_AP1E (1 << 0) 126 127#define DCPCR 0x00028 128#define DCPCR_CODE (0x7773 << 16) 129#define DCPCR_CA2B (1 << 13) 130#define DCPCR_CD2F (1 << 12) 131#define DCPCR_DC2E (1 << 8) 132#define DCPCR_CAB (1 << 5) 133#define DCPCR_CDF (1 << 4) 134#define DCPCR_DCE (1 << 0) 135 136#define DEFR2 0x00034 137#define DEFR2_CODE (0x7775 << 16) 138#define DEFR2_DEFE2G (1 << 0) 139 140#define DEFR3 0x00038 141#define DEFR3_CODE (0x7776 << 16) 142#define DEFR3_EVDA (1 << 14) 143#define DEFR3_EVDM_1 (1 << 12) 144#define DEFR3_EVDM_2 (2 << 12) 145#define DEFR3_EVDM_3 (3 << 12) 146#define DEFR3_VMSM2_EMA (1 << 6) 147#define DEFR3_VMSM1_ENA (1 << 4) 148#define DEFR3_DEFE3 (1 << 0) 149 150#define DEFR4 0x0003c 151#define DEFR4_CODE (0x7777 << 16) 152#define DEFR4_LRUO (1 << 5) 153#define DEFR4_SPCE (1 << 4) 154 155#define DVCSR 0x000d0 156#define DVCSR_VCnFB2_DSA0(n) (0 << ((n)*2+16)) 157#define DVCSR_VCnFB2_DSA1(n) (1 << ((n)*2+16)) 158#define DVCSR_VCnFB2_DSA2(n) (2 << ((n)*2+16)) 159#define DVCSR_VCnFB2_INIT(n) (3 << ((n)*2+16)) 160#define DVCSR_VCnFB2_MASK(n) (3 << ((n)*2+16)) 161#define DVCSR_VCnFB_DSA0(n) (0 << ((n)*2)) 162#define DVCSR_VCnFB_DSA1(n) (1 << ((n)*2)) 163#define DVCSR_VCnFB_DSA2(n) (2 << ((n)*2)) 164#define DVCSR_VCnFB_INIT(n) (3 << ((n)*2)) 165#define DVCSR_VCnFB_MASK(n) (3 << ((n)*2)) 166 167#define DEFR5 0x000e0 168#define DEFR5_CODE (0x66 << 24) 169#define DEFR5_YCRGB2_DIS (0 << 14) 170#define DEFR5_YCRGB2_PRI1 (1 << 14) 171#define DEFR5_YCRGB2_PRI2 (2 << 14) 172#define DEFR5_YCRGB2_PRI3 (3 << 14) 173#define DEFR5_YCRGB2_MASK (3 << 14) 174#define DEFR5_YCRGB1_DIS (0 << 12) 175#define DEFR5_YCRGB1_PRI1 (1 << 12) 176#define DEFR5_YCRGB1_PRI2 (2 << 12) 177#define DEFR5_YCRGB1_PRI3 (3 << 12) 178#define DEFR5_YCRGB1_MASK (3 << 12) 179#define DEFR5_DEFE5 (1 << 0) 180 181#define DDLTR 0x000e4 182#define DDLTR_CODE (0x7766 << 16) 183#define DDLTR_DLAR2 (1 << 6) 184#define DDLTR_DLAY2 (1 << 5) 185#define DDLTR_DLAY1 (1 << 1) 186 187#define DEFR6 0x000e8 188#define DEFR6_CODE (0x7778 << 16) 189#define DEFR6_ODPM22_D2SMR (0 << 10) 190#define DEFR6_ODPM22_DISP (2 << 10) 191#define DEFR6_ODPM22_CDE (3 << 10) 192#define DEFR6_ODPM22_MASK (3 << 10) 193#define DEFR6_ODPM12_DSMR (0 << 8) 194#define DEFR6_ODPM12_DISP (2 << 8) 195#define DEFR6_ODPM12_CDE (3 << 8) 196#define DEFR6_ODPM12_MASK (3 << 8) 197#define DEFR6_TCNE2 (1 << 6) 198#define DEFR6_MLOS1 (1 << 2) 199#define DEFR6_DEFAULT (DEFR6_CODE | DEFR6_TCNE2) 200 201/* ----------------------------------------------------------------------------- 202 * R8A7790-only Control Registers 203 */ 204 205#define DD1SSR 0x20008 206#define DD1SSR_TVR (1 << 15) 207#define DD1SSR_FRM (1 << 14) 208#define DD1SSR_BUF (1 << 12) 209#define DD1SSR_VBK (1 << 11) 210#define DD1SSR_RINT (1 << 9) 211#define DD1SSR_HBK (1 << 8) 212#define DD1SSR_ADC(n) (1 << ((n)-1)) 213 214#define DD1SRCR 0x2000c 215#define DD1SRCR_TVR (1 << 15) 216#define DD1SRCR_FRM (1 << 14) 217#define DD1SRCR_BUF (1 << 12) 218#define DD1SRCR_VBK (1 << 11) 219#define DD1SRCR_RINT (1 << 9) 220#define DD1SRCR_HBK (1 << 8) 221#define DD1SRCR_ADC(n) (1 << ((n)-1)) 222 223#define DD1IER 0x20010 224#define DD1IER_TVR (1 << 15) 225#define DD1IER_FRM (1 << 14) 226#define DD1IER_BUF (1 << 12) 227#define DD1IER_VBK (1 << 11) 228#define DD1IER_RINT (1 << 9) 229#define DD1IER_HBK (1 << 8) 230#define DD1IER_ADC(n) (1 << ((n)-1)) 231 232#define DEFR8 0x20020 233#define DEFR8_CODE (0x7790 << 16) 234#define DEFR8_VSCS (1 << 6) 235#define DEFR8_DRGBS_DU(n) ((n) << 4) 236#define DEFR8_DRGBS_MASK (3 << 4) 237#define DEFR8_DEFE8 (1 << 0) 238 239#define DOFLR 0x20024 240#define DOFLR_CODE (0x7790 << 16) 241#define DOFLR_HSYCFL1 (1 << 13) 242#define DOFLR_VSYCFL1 (1 << 12) 243#define DOFLR_ODDFL1 (1 << 11) 244#define DOFLR_DISPFL1 (1 << 10) 245#define DOFLR_CDEFL1 (1 << 9) 246#define DOFLR_RGBFL1 (1 << 8) 247#define DOFLR_HSYCFL0 (1 << 5) 248#define DOFLR_VSYCFL0 (1 << 4) 249#define DOFLR_ODDFL0 (1 << 3) 250#define DOFLR_DISPFL0 (1 << 2) 251#define DOFLR_CDEFL0 (1 << 1) 252#define DOFLR_RGBFL0 (1 << 0) 253 254#define DIDSR 0x20028 255#define DIDSR_CODE (0x7790 << 16) 256#define DIDSR_LCDS_DCLKIN(n) (0 << (8 + (n) * 2)) 257#define DIDSR_LCDS_LVDS0(n) (2 << (8 + (n) * 2)) 258#define DIDSR_LCDS_LVDS1(n) (3 << (8 + (n) * 2)) 259#define DIDSR_LCDS_MASK(n) (3 << (8 + (n) * 2)) 260#define DIDSR_PDCS_CLK(n, clk) (clk << ((n) * 2)) 261#define DIDSR_PDCS_MASK(n) (3 << ((n) * 2)) 262 263/* ----------------------------------------------------------------------------- 264 * Display Timing Generation Registers 265 */ 266 267#define HDSR 0x00040 268#define HDER 0x00044 269#define VDSR 0x00048 270#define VDER 0x0004c 271#define HCR 0x00050 272#define HSWR 0x00054 273#define VCR 0x00058 274#define VSPR 0x0005c 275#define EQWR 0x00060 276#define SPWR 0x00064 277#define CLAMPSR 0x00070 278#define CLAMPWR 0x00074 279#define DESR 0x00078 280#define DEWR 0x0007c 281 282/* ----------------------------------------------------------------------------- 283 * Display Attribute Registers 284 */ 285 286#define CP1TR 0x00080 287#define CP2TR 0x00084 288#define CP3TR 0x00088 289#define CP4TR 0x0008c 290 291#define DOOR 0x00090 292#define DOOR_RGB(r, g, b) (((r) << 18) | ((g) << 10) | ((b) << 2)) 293#define CDER 0x00094 294#define CDER_RGB(r, g, b) (((r) << 18) | ((g) << 10) | ((b) << 2)) 295#define BPOR 0x00098 296#define BPOR_RGB(r, g, b) (((r) << 18) | ((g) << 10) | ((b) << 2)) 297 298#define RINTOFSR 0x0009c 299 300#define DSHPR 0x000c8 301#define DSHPR_CODE (0x7776 << 16) 302#define DSHPR_PRIH (0xa << 4) 303#define DSHPR_PRIL_BPP16 (0x8 << 0) 304#define DSHPR_PRIL_BPP32 (0x9 << 0) 305 306/* ----------------------------------------------------------------------------- 307 * Display Plane Registers 308 */ 309 310#define PLANE_OFF 0x00100 311 312#define PnMR 0x00100 /* plane 1 */ 313#define PnMR_VISL_VIN0 (0 << 26) /* use Video Input 0 */ 314#define PnMR_VISL_VIN1 (1 << 26) /* use Video Input 1 */ 315#define PnMR_VISL_VIN2 (2 << 26) /* use Video Input 2 */ 316#define PnMR_VISL_VIN3 (3 << 26) /* use Video Input 3 */ 317#define PnMR_YCDF_YUYV (1 << 20) /* YUYV format */ 318#define PnMR_TC_R (0 << 17) /* Tranparent color is PnTC1R */ 319#define PnMR_TC_CP (1 << 17) /* Tranparent color is color palette */ 320#define PnMR_WAE (1 << 16) /* Wrap around Enable */ 321#define PnMR_SPIM_TP (0 << 12) /* Transparent Color */ 322#define PnMR_SPIM_ALP (1 << 12) /* Alpha Blending */ 323#define PnMR_SPIM_EOR (2 << 12) /* EOR */ 324#define PnMR_SPIM_TP_OFF (1 << 14) /* No Transparent Color */ 325#define PnMR_CPSL_CP1 (0 << 8) /* Color Palette selected 1 */ 326#define PnMR_CPSL_CP2 (1 << 8) /* Color Palette selected 2 */ 327#define PnMR_CPSL_CP3 (2 << 8) /* Color Palette selected 3 */ 328#define PnMR_CPSL_CP4 (3 << 8) /* Color Palette selected 4 */ 329#define PnMR_DC (1 << 7) /* Display Area Change */ 330#define PnMR_BM_MD (0 << 4) /* Manual Display Change Mode */ 331#define PnMR_BM_AR (1 << 4) /* Auto Rendering Mode */ 332#define PnMR_BM_AD (2 << 4) /* Auto Display Change Mode */ 333#define PnMR_BM_VC (3 << 4) /* Video Capture Mode */ 334#define PnMR_DDDF_8BPP (0 << 0) /* 8bit */ 335#define PnMR_DDDF_16BPP (1 << 0) /* 16bit or 32bit */ 336#define PnMR_DDDF_ARGB (2 << 0) /* ARGB */ 337#define PnMR_DDDF_YC (3 << 0) /* YC */ 338#define PnMR_DDDF_MASK (3 << 0) 339 340#define PnMWR 0x00104 341 342#define PnALPHAR 0x00108 343#define PnALPHAR_ABIT_1 (0 << 12) 344#define PnALPHAR_ABIT_0 (1 << 12) 345#define PnALPHAR_ABIT_X (2 << 12) 346 347#define PnDSXR 0x00110 348#define PnDSYR 0x00114 349#define PnDPXR 0x00118 350#define PnDPYR 0x0011c 351 352#define PnDSA0R 0x00120 353#define PnDSA1R 0x00124 354#define PnDSA2R 0x00128 355#define PnDSA_MASK 0xfffffff0 356 357#define PnSPXR 0x00130 358#define PnSPYR 0x00134 359#define PnWASPR 0x00138 360#define PnWAMWR 0x0013c 361 362#define PnBTR 0x00140 363 364#define PnTC1R 0x00144 365#define PnTC2R 0x00148 366#define PnTC3R 0x0014c 367#define PnTC3R_CODE (0x66 << 24) 368 369#define PnMLR 0x00150 370 371#define PnSWAPR 0x00180 372#define PnSWAPR_DIGN (1 << 4) 373#define PnSWAPR_SPQW (1 << 3) 374#define PnSWAPR_SPLW (1 << 2) 375#define PnSWAPR_SPWD (1 << 1) 376#define PnSWAPR_SPBY (1 << 0) 377 378#define PnDDCR 0x00184 379#define PnDDCR_CODE (0x7775 << 16) 380#define PnDDCR_LRGB1 (1 << 11) 381#define PnDDCR_LRGB0 (1 << 10) 382 383#define PnDDCR2 0x00188 384#define PnDDCR2_CODE (0x7776 << 16) 385#define PnDDCR2_NV21 (1 << 5) 386#define PnDDCR2_Y420 (1 << 4) 387#define PnDDCR2_DIVU (1 << 1) 388#define PnDDCR2_DIVY (1 << 0) 389 390#define PnDDCR4 0x00190 391#define PnDDCR4_CODE (0x7766 << 16) 392#define PnDDCR4_SDFS_RGB (0 << 4) 393#define PnDDCR4_SDFS_YC (5 << 4) 394#define PnDDCR4_SDFS_MASK (7 << 4) 395#define PnDDCR4_EDF_NONE (0 << 0) 396#define PnDDCR4_EDF_ARGB8888 (1 << 0) 397#define PnDDCR4_EDF_RGB888 (2 << 0) 398#define PnDDCR4_EDF_RGB666 (3 << 0) 399#define PnDDCR4_EDF_MASK (7 << 0) 400 401#define APnMR 0x0a100 402#define APnMR_WAE (1 << 16) /* Wrap around Enable */ 403#define APnMR_DC (1 << 7) /* Display Area Change */ 404#define APnMR_BM_MD (0 << 4) /* Manual Display Change Mode */ 405#define APnMR_BM_AD (2 << 4) /* Auto Display Change Mode */ 406 407#define APnMWR 0x0a104 408 409#define APnDSXR 0x0a110 410#define APnDSYR 0x0a114 411#define APnDPXR 0x0a118 412#define APnDPYR 0x0a11c 413 414#define APnDSA0R 0x0a120 415#define APnDSA1R 0x0a124 416#define APnDSA2R 0x0a128 417 418#define APnSPXR 0x0a130 419#define APnSPYR 0x0a134 420#define APnWASPR 0x0a138 421#define APnWAMWR 0x0a13c 422 423#define APnBTR 0x0a140 424 425#define APnMLR 0x0a150 426#define APnSWAPR 0x0a180 427 428/* ----------------------------------------------------------------------------- 429 * Display Capture Registers 430 */ 431 432#define DCMR 0x0c100 433#define DCMWR 0x0c104 434#define DCSAR 0x0c120 435#define DCMLR 0x0c150 436 437/* ----------------------------------------------------------------------------- 438 * Color Palette Registers 439 */ 440 441#define CP1_000R 0x01000 442#define CP1_255R 0x013fc 443#define CP2_000R 0x02000 444#define CP2_255R 0x023fc 445#define CP3_000R 0x03000 446#define CP3_255R 0x033fc 447#define CP4_000R 0x04000 448#define CP4_255R 0x043fc 449 450/* ----------------------------------------------------------------------------- 451 * External Synchronization Control Registers 452 */ 453 454#define ESCR 0x10000 455#define ESCR2 0x31000 456#define ESCR_DCLKOINV (1 << 25) 457#define ESCR_DCLKSEL_DCLKIN (0 << 20) 458#define ESCR_DCLKSEL_CLKS (1 << 20) 459#define ESCR_DCLKSEL_MASK (1 << 20) 460#define ESCR_DCLKDIS (1 << 16) 461#define ESCR_SYNCSEL_OFF (0 << 8) 462#define ESCR_SYNCSEL_EXVSYNC (2 << 8) 463#define ESCR_SYNCSEL_EXHSYNC (3 << 8) 464#define ESCR_FRQSEL_MASK (0x3f << 0) 465 466#define OTAR 0x10004 467#define OTAR2 0x31004 468 469/* ----------------------------------------------------------------------------- 470 * Dual Display Output Control Registers 471 */ 472 473#define DORCR 0x11000 474#define DORCR_PG2T (1 << 30) 475#define DORCR_DK2S (1 << 28) 476#define DORCR_PG2D_DS1 (0 << 24) 477#define DORCR_PG2D_DS2 (1 << 24) 478#define DORCR_PG2D_FIX0 (2 << 24) 479#define DORCR_PG2D_DOOR (3 << 24) 480#define DORCR_PG2D_MASK (3 << 24) 481#define DORCR_DR1D (1 << 21) 482#define DORCR_PG1D_DS1 (0 << 16) 483#define DORCR_PG1D_DS2 (1 << 16) 484#define DORCR_PG1D_FIX0 (2 << 16) 485#define DORCR_PG1D_DOOR (3 << 16) 486#define DORCR_PG1D_MASK (3 << 16) 487#define DORCR_RGPV (1 << 4) 488#define DORCR_DPRS (1 << 0) 489 490#define DPTSR 0x11004 491#define DPTSR_PnDK(n) (1 << ((n) + 16)) 492#define DPTSR_PnTS(n) (1 << (n)) 493 494#define DAPTSR 0x11008 495#define DAPTSR_APnDK(n) (1 << ((n) + 16)) 496#define DAPTSR_APnTS(n) (1 << (n)) 497 498#define DS1PR 0x11020 499#define DS2PR 0x11024 500 501/* ----------------------------------------------------------------------------- 502 * YC-RGB Conversion Coefficient Registers 503 */ 504 505#define YNCR 0x11080 506#define YNOR 0x11084 507#define CRNOR 0x11088 508#define CBNOR 0x1108c 509#define RCRCR 0x11090 510#define GCRCR 0x11094 511#define GCBCR 0x11098 512#define BCBCR 0x1109c 513 514#endif /* __RCAR_DU_REGS_H__ */ 515