1/* 2 * Copyright (c) 2015, The Linux Foundation. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 and 6 * only version 2 as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14#include <linux/clk.h> 15#include <linux/delay.h> 16#include <linux/err.h> 17#include <linux/gpio.h> 18#include <linux/interrupt.h> 19#include <linux/of_device.h> 20#include <linux/of_gpio.h> 21#include <linux/of_irq.h> 22#include <linux/regulator/consumer.h> 23#include <linux/spinlock.h> 24#include <video/mipi_display.h> 25 26#include "dsi.h" 27#include "dsi.xml.h" 28 29#define MSM_DSI_VER_MAJOR_V2 0x02 30#define MSM_DSI_VER_MAJOR_6G 0x03 31#define MSM_DSI_6G_VER_MINOR_V1_0 0x10000000 32#define MSM_DSI_6G_VER_MINOR_V1_1 0x10010000 33#define MSM_DSI_6G_VER_MINOR_V1_1_1 0x10010001 34#define MSM_DSI_6G_VER_MINOR_V1_2 0x10020000 35#define MSM_DSI_6G_VER_MINOR_V1_3_1 0x10030001 36 37#define DSI_6G_REG_SHIFT 4 38 39#define DSI_REGULATOR_MAX 8 40struct dsi_reg_entry { 41 char name[32]; 42 int min_voltage; 43 int max_voltage; 44 int enable_load; 45 int disable_load; 46}; 47 48struct dsi_reg_config { 49 int num; 50 struct dsi_reg_entry regs[DSI_REGULATOR_MAX]; 51}; 52 53struct dsi_config { 54 u32 major; 55 u32 minor; 56 u32 io_offset; 57 enum msm_dsi_phy_type phy_type; 58 struct dsi_reg_config reg_cfg; 59}; 60 61static const struct dsi_config dsi_cfgs[] = { 62 {MSM_DSI_VER_MAJOR_V2, 0, 0, MSM_DSI_PHY_UNKNOWN}, 63 { /* 8974 v1 */ 64 .major = MSM_DSI_VER_MAJOR_6G, 65 .minor = MSM_DSI_6G_VER_MINOR_V1_0, 66 .io_offset = DSI_6G_REG_SHIFT, 67 .phy_type = MSM_DSI_PHY_28NM, 68 .reg_cfg = { 69 .num = 4, 70 .regs = { 71 {"gdsc", -1, -1, -1, -1}, 72 {"vdd", 3000000, 3000000, 150000, 100}, 73 {"vdda", 1200000, 1200000, 100000, 100}, 74 {"vddio", 1800000, 1800000, 100000, 100}, 75 }, 76 }, 77 }, 78 { /* 8974 v2 */ 79 .major = MSM_DSI_VER_MAJOR_6G, 80 .minor = MSM_DSI_6G_VER_MINOR_V1_1, 81 .io_offset = DSI_6G_REG_SHIFT, 82 .phy_type = MSM_DSI_PHY_28NM, 83 .reg_cfg = { 84 .num = 4, 85 .regs = { 86 {"gdsc", -1, -1, -1, -1}, 87 {"vdd", 3000000, 3000000, 150000, 100}, 88 {"vdda", 1200000, 1200000, 100000, 100}, 89 {"vddio", 1800000, 1800000, 100000, 100}, 90 }, 91 }, 92 }, 93 { /* 8974 v3 */ 94 .major = MSM_DSI_VER_MAJOR_6G, 95 .minor = MSM_DSI_6G_VER_MINOR_V1_1_1, 96 .io_offset = DSI_6G_REG_SHIFT, 97 .phy_type = MSM_DSI_PHY_28NM, 98 .reg_cfg = { 99 .num = 4, 100 .regs = { 101 {"gdsc", -1, -1, -1, -1}, 102 {"vdd", 3000000, 3000000, 150000, 100}, 103 {"vdda", 1200000, 1200000, 100000, 100}, 104 {"vddio", 1800000, 1800000, 100000, 100}, 105 }, 106 }, 107 }, 108 { /* 8084 */ 109 .major = MSM_DSI_VER_MAJOR_6G, 110 .minor = MSM_DSI_6G_VER_MINOR_V1_2, 111 .io_offset = DSI_6G_REG_SHIFT, 112 .phy_type = MSM_DSI_PHY_28NM, 113 .reg_cfg = { 114 .num = 4, 115 .regs = { 116 {"gdsc", -1, -1, -1, -1}, 117 {"vdd", 3000000, 3000000, 150000, 100}, 118 {"vdda", 1200000, 1200000, 100000, 100}, 119 {"vddio", 1800000, 1800000, 100000, 100}, 120 }, 121 }, 122 }, 123 { /* 8916 */ 124 .major = MSM_DSI_VER_MAJOR_6G, 125 .minor = MSM_DSI_6G_VER_MINOR_V1_3_1, 126 .io_offset = DSI_6G_REG_SHIFT, 127 .phy_type = MSM_DSI_PHY_28NM, 128 .reg_cfg = { 129 .num = 4, 130 .regs = { 131 {"gdsc", -1, -1, -1, -1}, 132 {"vdd", 2850000, 2850000, 100000, 100}, 133 {"vdda", 1200000, 1200000, 100000, 100}, 134 {"vddio", 1800000, 1800000, 100000, 100}, 135 }, 136 }, 137 }, 138}; 139 140static int dsi_get_version(const void __iomem *base, u32 *major, u32 *minor) 141{ 142 u32 ver; 143 u32 ver_6g; 144 145 if (!major || !minor) 146 return -EINVAL; 147 148 /* From DSI6G(v3), addition of a 6G_HW_VERSION register at offset 0 149 * makes all other registers 4-byte shifted down. 150 */ 151 ver_6g = msm_readl(base + REG_DSI_6G_HW_VERSION); 152 if (ver_6g == 0) { 153 ver = msm_readl(base + REG_DSI_VERSION); 154 ver = FIELD(ver, DSI_VERSION_MAJOR); 155 if (ver <= MSM_DSI_VER_MAJOR_V2) { 156 /* old versions */ 157 *major = ver; 158 *minor = 0; 159 return 0; 160 } else { 161 return -EINVAL; 162 } 163 } else { 164 ver = msm_readl(base + DSI_6G_REG_SHIFT + REG_DSI_VERSION); 165 ver = FIELD(ver, DSI_VERSION_MAJOR); 166 if (ver == MSM_DSI_VER_MAJOR_6G) { 167 /* 6G version */ 168 *major = ver; 169 *minor = ver_6g; 170 return 0; 171 } else { 172 return -EINVAL; 173 } 174 } 175} 176 177#define DSI_ERR_STATE_ACK 0x0000 178#define DSI_ERR_STATE_TIMEOUT 0x0001 179#define DSI_ERR_STATE_DLN0_PHY 0x0002 180#define DSI_ERR_STATE_FIFO 0x0004 181#define DSI_ERR_STATE_MDP_FIFO_UNDERFLOW 0x0008 182#define DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION 0x0010 183#define DSI_ERR_STATE_PLL_UNLOCKED 0x0020 184 185#define DSI_CLK_CTRL_ENABLE_CLKS \ 186 (DSI_CLK_CTRL_AHBS_HCLK_ON | DSI_CLK_CTRL_AHBM_SCLK_ON | \ 187 DSI_CLK_CTRL_PCLK_ON | DSI_CLK_CTRL_DSICLK_ON | \ 188 DSI_CLK_CTRL_BYTECLK_ON | DSI_CLK_CTRL_ESCCLK_ON | \ 189 DSI_CLK_CTRL_FORCE_ON_DYN_AHBM_HCLK) 190 191struct msm_dsi_host { 192 struct mipi_dsi_host base; 193 194 struct platform_device *pdev; 195 struct drm_device *dev; 196 197 int id; 198 199 void __iomem *ctrl_base; 200 struct regulator_bulk_data supplies[DSI_REGULATOR_MAX]; 201 struct clk *mdp_core_clk; 202 struct clk *ahb_clk; 203 struct clk *axi_clk; 204 struct clk *mmss_misc_ahb_clk; 205 struct clk *byte_clk; 206 struct clk *esc_clk; 207 struct clk *pixel_clk; 208 u32 byte_clk_rate; 209 210 struct gpio_desc *disp_en_gpio; 211 struct gpio_desc *te_gpio; 212 213 const struct dsi_config *cfg; 214 215 struct completion dma_comp; 216 struct completion video_comp; 217 struct mutex dev_mutex; 218 struct mutex cmd_mutex; 219 struct mutex clk_mutex; 220 spinlock_t intr_lock; /* Protect interrupt ctrl register */ 221 222 u32 err_work_state; 223 struct work_struct err_work; 224 struct workqueue_struct *workqueue; 225 226 struct drm_gem_object *tx_gem_obj; 227 u8 *rx_buf; 228 229 struct drm_display_mode *mode; 230 231 /* Panel info */ 232 struct device_node *panel_node; 233 unsigned int channel; 234 unsigned int lanes; 235 enum mipi_dsi_pixel_format format; 236 unsigned long mode_flags; 237 238 u32 dma_cmd_ctrl_restore; 239 240 bool registered; 241 bool power_on; 242 int irq; 243}; 244 245static u32 dsi_get_bpp(const enum mipi_dsi_pixel_format fmt) 246{ 247 switch (fmt) { 248 case MIPI_DSI_FMT_RGB565: return 16; 249 case MIPI_DSI_FMT_RGB666_PACKED: return 18; 250 case MIPI_DSI_FMT_RGB666: 251 case MIPI_DSI_FMT_RGB888: 252 default: return 24; 253 } 254} 255 256static inline u32 dsi_read(struct msm_dsi_host *msm_host, u32 reg) 257{ 258 return msm_readl(msm_host->ctrl_base + msm_host->cfg->io_offset + reg); 259} 260static inline void dsi_write(struct msm_dsi_host *msm_host, u32 reg, u32 data) 261{ 262 msm_writel(data, msm_host->ctrl_base + msm_host->cfg->io_offset + reg); 263} 264 265static int dsi_host_regulator_enable(struct msm_dsi_host *msm_host); 266static void dsi_host_regulator_disable(struct msm_dsi_host *msm_host); 267 268static const struct dsi_config *dsi_get_config(struct msm_dsi_host *msm_host) 269{ 270 const struct dsi_config *cfg; 271 struct regulator *gdsc_reg; 272 int i, ret; 273 u32 major = 0, minor = 0; 274 275 gdsc_reg = regulator_get(&msm_host->pdev->dev, "gdsc"); 276 if (IS_ERR_OR_NULL(gdsc_reg)) { 277 pr_err("%s: cannot get gdsc\n", __func__); 278 goto fail; 279 } 280 ret = regulator_enable(gdsc_reg); 281 if (ret) { 282 pr_err("%s: unable to enable gdsc\n", __func__); 283 regulator_put(gdsc_reg); 284 goto fail; 285 } 286 ret = clk_prepare_enable(msm_host->ahb_clk); 287 if (ret) { 288 pr_err("%s: unable to enable ahb_clk\n", __func__); 289 regulator_disable(gdsc_reg); 290 regulator_put(gdsc_reg); 291 goto fail; 292 } 293 294 ret = dsi_get_version(msm_host->ctrl_base, &major, &minor); 295 296 clk_disable_unprepare(msm_host->ahb_clk); 297 regulator_disable(gdsc_reg); 298 regulator_put(gdsc_reg); 299 if (ret) { 300 pr_err("%s: Invalid version\n", __func__); 301 goto fail; 302 } 303 304 for (i = 0; i < ARRAY_SIZE(dsi_cfgs); i++) { 305 cfg = dsi_cfgs + i; 306 if ((cfg->major == major) && (cfg->minor == minor)) 307 return cfg; 308 } 309 pr_err("%s: Version %x:%x not support\n", __func__, major, minor); 310 311fail: 312 return NULL; 313} 314 315static inline struct msm_dsi_host *to_msm_dsi_host(struct mipi_dsi_host *host) 316{ 317 return container_of(host, struct msm_dsi_host, base); 318} 319 320static void dsi_host_regulator_disable(struct msm_dsi_host *msm_host) 321{ 322 struct regulator_bulk_data *s = msm_host->supplies; 323 const struct dsi_reg_entry *regs = msm_host->cfg->reg_cfg.regs; 324 int num = msm_host->cfg->reg_cfg.num; 325 int i; 326 327 DBG(""); 328 for (i = num - 1; i >= 0; i--) 329 if (regs[i].disable_load >= 0) 330 regulator_set_load(s[i].consumer, 331 regs[i].disable_load); 332 333 regulator_bulk_disable(num, s); 334} 335 336static int dsi_host_regulator_enable(struct msm_dsi_host *msm_host) 337{ 338 struct regulator_bulk_data *s = msm_host->supplies; 339 const struct dsi_reg_entry *regs = msm_host->cfg->reg_cfg.regs; 340 int num = msm_host->cfg->reg_cfg.num; 341 int ret, i; 342 343 DBG(""); 344 for (i = 0; i < num; i++) { 345 if (regs[i].enable_load >= 0) { 346 ret = regulator_set_load(s[i].consumer, 347 regs[i].enable_load); 348 if (ret < 0) { 349 pr_err("regulator %d set op mode failed, %d\n", 350 i, ret); 351 goto fail; 352 } 353 } 354 } 355 356 ret = regulator_bulk_enable(num, s); 357 if (ret < 0) { 358 pr_err("regulator enable failed, %d\n", ret); 359 goto fail; 360 } 361 362 return 0; 363 364fail: 365 for (i--; i >= 0; i--) 366 regulator_set_load(s[i].consumer, regs[i].disable_load); 367 return ret; 368} 369 370static int dsi_regulator_init(struct msm_dsi_host *msm_host) 371{ 372 struct regulator_bulk_data *s = msm_host->supplies; 373 const struct dsi_reg_entry *regs = msm_host->cfg->reg_cfg.regs; 374 int num = msm_host->cfg->reg_cfg.num; 375 int i, ret; 376 377 for (i = 0; i < num; i++) 378 s[i].supply = regs[i].name; 379 380 ret = devm_regulator_bulk_get(&msm_host->pdev->dev, num, s); 381 if (ret < 0) { 382 pr_err("%s: failed to init regulator, ret=%d\n", 383 __func__, ret); 384 return ret; 385 } 386 387 for (i = 0; i < num; i++) { 388 if ((regs[i].min_voltage >= 0) && (regs[i].max_voltage >= 0)) { 389 ret = regulator_set_voltage(s[i].consumer, 390 regs[i].min_voltage, regs[i].max_voltage); 391 if (ret < 0) { 392 pr_err("regulator %d set voltage failed, %d\n", 393 i, ret); 394 return ret; 395 } 396 } 397 } 398 399 return 0; 400} 401 402static int dsi_clk_init(struct msm_dsi_host *msm_host) 403{ 404 struct device *dev = &msm_host->pdev->dev; 405 int ret = 0; 406 407 msm_host->mdp_core_clk = devm_clk_get(dev, "mdp_core_clk"); 408 if (IS_ERR(msm_host->mdp_core_clk)) { 409 ret = PTR_ERR(msm_host->mdp_core_clk); 410 pr_err("%s: Unable to get mdp core clk. ret=%d\n", 411 __func__, ret); 412 goto exit; 413 } 414 415 msm_host->ahb_clk = devm_clk_get(dev, "iface_clk"); 416 if (IS_ERR(msm_host->ahb_clk)) { 417 ret = PTR_ERR(msm_host->ahb_clk); 418 pr_err("%s: Unable to get mdss ahb clk. ret=%d\n", 419 __func__, ret); 420 goto exit; 421 } 422 423 msm_host->axi_clk = devm_clk_get(dev, "bus_clk"); 424 if (IS_ERR(msm_host->axi_clk)) { 425 ret = PTR_ERR(msm_host->axi_clk); 426 pr_err("%s: Unable to get axi bus clk. ret=%d\n", 427 __func__, ret); 428 goto exit; 429 } 430 431 msm_host->mmss_misc_ahb_clk = devm_clk_get(dev, "core_mmss_clk"); 432 if (IS_ERR(msm_host->mmss_misc_ahb_clk)) { 433 ret = PTR_ERR(msm_host->mmss_misc_ahb_clk); 434 pr_err("%s: Unable to get mmss misc ahb clk. ret=%d\n", 435 __func__, ret); 436 goto exit; 437 } 438 439 msm_host->byte_clk = devm_clk_get(dev, "byte_clk"); 440 if (IS_ERR(msm_host->byte_clk)) { 441 ret = PTR_ERR(msm_host->byte_clk); 442 pr_err("%s: can't find dsi_byte_clk. ret=%d\n", 443 __func__, ret); 444 msm_host->byte_clk = NULL; 445 goto exit; 446 } 447 448 msm_host->pixel_clk = devm_clk_get(dev, "pixel_clk"); 449 if (IS_ERR(msm_host->pixel_clk)) { 450 ret = PTR_ERR(msm_host->pixel_clk); 451 pr_err("%s: can't find dsi_pixel_clk. ret=%d\n", 452 __func__, ret); 453 msm_host->pixel_clk = NULL; 454 goto exit; 455 } 456 457 msm_host->esc_clk = devm_clk_get(dev, "core_clk"); 458 if (IS_ERR(msm_host->esc_clk)) { 459 ret = PTR_ERR(msm_host->esc_clk); 460 pr_err("%s: can't find dsi_esc_clk. ret=%d\n", 461 __func__, ret); 462 msm_host->esc_clk = NULL; 463 goto exit; 464 } 465 466exit: 467 return ret; 468} 469 470static int dsi_bus_clk_enable(struct msm_dsi_host *msm_host) 471{ 472 int ret; 473 474 DBG("id=%d", msm_host->id); 475 476 ret = clk_prepare_enable(msm_host->mdp_core_clk); 477 if (ret) { 478 pr_err("%s: failed to enable mdp_core_clock, %d\n", 479 __func__, ret); 480 goto core_clk_err; 481 } 482 483 ret = clk_prepare_enable(msm_host->ahb_clk); 484 if (ret) { 485 pr_err("%s: failed to enable ahb clock, %d\n", __func__, ret); 486 goto ahb_clk_err; 487 } 488 489 ret = clk_prepare_enable(msm_host->axi_clk); 490 if (ret) { 491 pr_err("%s: failed to enable ahb clock, %d\n", __func__, ret); 492 goto axi_clk_err; 493 } 494 495 ret = clk_prepare_enable(msm_host->mmss_misc_ahb_clk); 496 if (ret) { 497 pr_err("%s: failed to enable mmss misc ahb clk, %d\n", 498 __func__, ret); 499 goto misc_ahb_clk_err; 500 } 501 502 return 0; 503 504misc_ahb_clk_err: 505 clk_disable_unprepare(msm_host->axi_clk); 506axi_clk_err: 507 clk_disable_unprepare(msm_host->ahb_clk); 508ahb_clk_err: 509 clk_disable_unprepare(msm_host->mdp_core_clk); 510core_clk_err: 511 return ret; 512} 513 514static void dsi_bus_clk_disable(struct msm_dsi_host *msm_host) 515{ 516 DBG(""); 517 clk_disable_unprepare(msm_host->mmss_misc_ahb_clk); 518 clk_disable_unprepare(msm_host->axi_clk); 519 clk_disable_unprepare(msm_host->ahb_clk); 520 clk_disable_unprepare(msm_host->mdp_core_clk); 521} 522 523static int dsi_link_clk_enable(struct msm_dsi_host *msm_host) 524{ 525 int ret; 526 527 DBG("Set clk rates: pclk=%d, byteclk=%d", 528 msm_host->mode->clock, msm_host->byte_clk_rate); 529 530 ret = clk_set_rate(msm_host->byte_clk, msm_host->byte_clk_rate); 531 if (ret) { 532 pr_err("%s: Failed to set rate byte clk, %d\n", __func__, ret); 533 goto error; 534 } 535 536 ret = clk_set_rate(msm_host->pixel_clk, msm_host->mode->clock * 1000); 537 if (ret) { 538 pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret); 539 goto error; 540 } 541 542 ret = clk_prepare_enable(msm_host->esc_clk); 543 if (ret) { 544 pr_err("%s: Failed to enable dsi esc clk\n", __func__); 545 goto error; 546 } 547 548 ret = clk_prepare_enable(msm_host->byte_clk); 549 if (ret) { 550 pr_err("%s: Failed to enable dsi byte clk\n", __func__); 551 goto byte_clk_err; 552 } 553 554 ret = clk_prepare_enable(msm_host->pixel_clk); 555 if (ret) { 556 pr_err("%s: Failed to enable dsi pixel clk\n", __func__); 557 goto pixel_clk_err; 558 } 559 560 return 0; 561 562pixel_clk_err: 563 clk_disable_unprepare(msm_host->byte_clk); 564byte_clk_err: 565 clk_disable_unprepare(msm_host->esc_clk); 566error: 567 return ret; 568} 569 570static void dsi_link_clk_disable(struct msm_dsi_host *msm_host) 571{ 572 clk_disable_unprepare(msm_host->esc_clk); 573 clk_disable_unprepare(msm_host->pixel_clk); 574 clk_disable_unprepare(msm_host->byte_clk); 575} 576 577static int dsi_clk_ctrl(struct msm_dsi_host *msm_host, bool enable) 578{ 579 int ret = 0; 580 581 mutex_lock(&msm_host->clk_mutex); 582 if (enable) { 583 ret = dsi_bus_clk_enable(msm_host); 584 if (ret) { 585 pr_err("%s: Can not enable bus clk, %d\n", 586 __func__, ret); 587 goto unlock_ret; 588 } 589 ret = dsi_link_clk_enable(msm_host); 590 if (ret) { 591 pr_err("%s: Can not enable link clk, %d\n", 592 __func__, ret); 593 dsi_bus_clk_disable(msm_host); 594 goto unlock_ret; 595 } 596 } else { 597 dsi_link_clk_disable(msm_host); 598 dsi_bus_clk_disable(msm_host); 599 } 600 601unlock_ret: 602 mutex_unlock(&msm_host->clk_mutex); 603 return ret; 604} 605 606static int dsi_calc_clk_rate(struct msm_dsi_host *msm_host) 607{ 608 struct drm_display_mode *mode = msm_host->mode; 609 u8 lanes = msm_host->lanes; 610 u32 bpp = dsi_get_bpp(msm_host->format); 611 u32 pclk_rate; 612 613 if (!mode) { 614 pr_err("%s: mode not set\n", __func__); 615 return -EINVAL; 616 } 617 618 pclk_rate = mode->clock * 1000; 619 if (lanes > 0) { 620 msm_host->byte_clk_rate = (pclk_rate * bpp) / (8 * lanes); 621 } else { 622 pr_err("%s: forcing mdss_dsi lanes to 1\n", __func__); 623 msm_host->byte_clk_rate = (pclk_rate * bpp) / 8; 624 } 625 626 DBG("pclk=%d, bclk=%d", pclk_rate, msm_host->byte_clk_rate); 627 628 return 0; 629} 630 631static void dsi_phy_sw_reset(struct msm_dsi_host *msm_host) 632{ 633 DBG(""); 634 dsi_write(msm_host, REG_DSI_PHY_RESET, DSI_PHY_RESET_RESET); 635 /* Make sure fully reset */ 636 wmb(); 637 udelay(1000); 638 dsi_write(msm_host, REG_DSI_PHY_RESET, 0); 639 udelay(100); 640} 641 642static void dsi_intr_ctrl(struct msm_dsi_host *msm_host, u32 mask, int enable) 643{ 644 u32 intr; 645 unsigned long flags; 646 647 spin_lock_irqsave(&msm_host->intr_lock, flags); 648 intr = dsi_read(msm_host, REG_DSI_INTR_CTRL); 649 650 if (enable) 651 intr |= mask; 652 else 653 intr &= ~mask; 654 655 DBG("intr=%x enable=%d", intr, enable); 656 657 dsi_write(msm_host, REG_DSI_INTR_CTRL, intr); 658 spin_unlock_irqrestore(&msm_host->intr_lock, flags); 659} 660 661static inline enum dsi_traffic_mode dsi_get_traffic_mode(const u32 mode_flags) 662{ 663 if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 664 return BURST_MODE; 665 else if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 666 return NON_BURST_SYNCH_PULSE; 667 668 return NON_BURST_SYNCH_EVENT; 669} 670 671static inline enum dsi_vid_dst_format dsi_get_vid_fmt( 672 const enum mipi_dsi_pixel_format mipi_fmt) 673{ 674 switch (mipi_fmt) { 675 case MIPI_DSI_FMT_RGB888: return VID_DST_FORMAT_RGB888; 676 case MIPI_DSI_FMT_RGB666: return VID_DST_FORMAT_RGB666_LOOSE; 677 case MIPI_DSI_FMT_RGB666_PACKED: return VID_DST_FORMAT_RGB666; 678 case MIPI_DSI_FMT_RGB565: return VID_DST_FORMAT_RGB565; 679 default: return VID_DST_FORMAT_RGB888; 680 } 681} 682 683static inline enum dsi_cmd_dst_format dsi_get_cmd_fmt( 684 const enum mipi_dsi_pixel_format mipi_fmt) 685{ 686 switch (mipi_fmt) { 687 case MIPI_DSI_FMT_RGB888: return CMD_DST_FORMAT_RGB888; 688 case MIPI_DSI_FMT_RGB666_PACKED: 689 case MIPI_DSI_FMT_RGB666: return VID_DST_FORMAT_RGB666; 690 case MIPI_DSI_FMT_RGB565: return CMD_DST_FORMAT_RGB565; 691 default: return CMD_DST_FORMAT_RGB888; 692 } 693} 694 695static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable, 696 u32 clk_pre, u32 clk_post) 697{ 698 u32 flags = msm_host->mode_flags; 699 enum mipi_dsi_pixel_format mipi_fmt = msm_host->format; 700 u32 data = 0; 701 702 if (!enable) { 703 dsi_write(msm_host, REG_DSI_CTRL, 0); 704 return; 705 } 706 707 if (flags & MIPI_DSI_MODE_VIDEO) { 708 if (flags & MIPI_DSI_MODE_VIDEO_HSE) 709 data |= DSI_VID_CFG0_PULSE_MODE_HSA_HE; 710 if (flags & MIPI_DSI_MODE_VIDEO_HFP) 711 data |= DSI_VID_CFG0_HFP_POWER_STOP; 712 if (flags & MIPI_DSI_MODE_VIDEO_HBP) 713 data |= DSI_VID_CFG0_HBP_POWER_STOP; 714 if (flags & MIPI_DSI_MODE_VIDEO_HSA) 715 data |= DSI_VID_CFG0_HSA_POWER_STOP; 716 /* Always set low power stop mode for BLLP 717 * to let command engine send packets 718 */ 719 data |= DSI_VID_CFG0_EOF_BLLP_POWER_STOP | 720 DSI_VID_CFG0_BLLP_POWER_STOP; 721 data |= DSI_VID_CFG0_TRAFFIC_MODE(dsi_get_traffic_mode(flags)); 722 data |= DSI_VID_CFG0_DST_FORMAT(dsi_get_vid_fmt(mipi_fmt)); 723 data |= DSI_VID_CFG0_VIRT_CHANNEL(msm_host->channel); 724 dsi_write(msm_host, REG_DSI_VID_CFG0, data); 725 726 /* Do not swap RGB colors */ 727 data = DSI_VID_CFG1_RGB_SWAP(SWAP_RGB); 728 dsi_write(msm_host, REG_DSI_VID_CFG1, 0); 729 } else { 730 /* Do not swap RGB colors */ 731 data = DSI_CMD_CFG0_RGB_SWAP(SWAP_RGB); 732 data |= DSI_CMD_CFG0_DST_FORMAT(dsi_get_cmd_fmt(mipi_fmt)); 733 dsi_write(msm_host, REG_DSI_CMD_CFG0, data); 734 735 data = DSI_CMD_CFG1_WR_MEM_START(MIPI_DCS_WRITE_MEMORY_START) | 736 DSI_CMD_CFG1_WR_MEM_CONTINUE( 737 MIPI_DCS_WRITE_MEMORY_CONTINUE); 738 /* Always insert DCS command */ 739 data |= DSI_CMD_CFG1_INSERT_DCS_COMMAND; 740 dsi_write(msm_host, REG_DSI_CMD_CFG1, data); 741 } 742 743 dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL, 744 DSI_CMD_DMA_CTRL_FROM_FRAME_BUFFER | 745 DSI_CMD_DMA_CTRL_LOW_POWER); 746 747 data = 0; 748 /* Always assume dedicated TE pin */ 749 data |= DSI_TRIG_CTRL_TE; 750 data |= DSI_TRIG_CTRL_MDP_TRIGGER(TRIGGER_NONE); 751 data |= DSI_TRIG_CTRL_DMA_TRIGGER(TRIGGER_SW); 752 data |= DSI_TRIG_CTRL_STREAM(msm_host->channel); 753 if ((msm_host->cfg->major == MSM_DSI_VER_MAJOR_6G) && 754 (msm_host->cfg->minor >= MSM_DSI_6G_VER_MINOR_V1_2)) 755 data |= DSI_TRIG_CTRL_BLOCK_DMA_WITHIN_FRAME; 756 dsi_write(msm_host, REG_DSI_TRIG_CTRL, data); 757 758 data = DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(clk_post) | 759 DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(clk_pre); 760 dsi_write(msm_host, REG_DSI_CLKOUT_TIMING_CTRL, data); 761 762 data = 0; 763 if (!(flags & MIPI_DSI_MODE_EOT_PACKET)) 764 data |= DSI_EOT_PACKET_CTRL_TX_EOT_APPEND; 765 dsi_write(msm_host, REG_DSI_EOT_PACKET_CTRL, data); 766 767 /* allow only ack-err-status to generate interrupt */ 768 dsi_write(msm_host, REG_DSI_ERR_INT_MASK0, 0x13ff3fe0); 769 770 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1); 771 772 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS); 773 774 data = DSI_CTRL_CLK_EN; 775 776 DBG("lane number=%d", msm_host->lanes); 777 if (msm_host->lanes == 2) { 778 data |= DSI_CTRL_LANE1 | DSI_CTRL_LANE2; 779 /* swap lanes for 2-lane panel for better performance */ 780 dsi_write(msm_host, REG_DSI_LANE_SWAP_CTRL, 781 DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(LANE_SWAP_1230)); 782 } else { 783 /* Take 4 lanes as default */ 784 data |= DSI_CTRL_LANE0 | DSI_CTRL_LANE1 | DSI_CTRL_LANE2 | 785 DSI_CTRL_LANE3; 786 /* Do not swap lanes for 4-lane panel */ 787 dsi_write(msm_host, REG_DSI_LANE_SWAP_CTRL, 788 DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(LANE_SWAP_0123)); 789 } 790 data |= DSI_CTRL_ENABLE; 791 792 dsi_write(msm_host, REG_DSI_CTRL, data); 793} 794 795static void dsi_timing_setup(struct msm_dsi_host *msm_host) 796{ 797 struct drm_display_mode *mode = msm_host->mode; 798 u32 hs_start = 0, vs_start = 0; /* take sync start as 0 */ 799 u32 h_total = mode->htotal; 800 u32 v_total = mode->vtotal; 801 u32 hs_end = mode->hsync_end - mode->hsync_start; 802 u32 vs_end = mode->vsync_end - mode->vsync_start; 803 u32 ha_start = h_total - mode->hsync_start; 804 u32 ha_end = ha_start + mode->hdisplay; 805 u32 va_start = v_total - mode->vsync_start; 806 u32 va_end = va_start + mode->vdisplay; 807 u32 wc; 808 809 DBG(""); 810 811 if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) { 812 dsi_write(msm_host, REG_DSI_ACTIVE_H, 813 DSI_ACTIVE_H_START(ha_start) | 814 DSI_ACTIVE_H_END(ha_end)); 815 dsi_write(msm_host, REG_DSI_ACTIVE_V, 816 DSI_ACTIVE_V_START(va_start) | 817 DSI_ACTIVE_V_END(va_end)); 818 dsi_write(msm_host, REG_DSI_TOTAL, 819 DSI_TOTAL_H_TOTAL(h_total - 1) | 820 DSI_TOTAL_V_TOTAL(v_total - 1)); 821 822 dsi_write(msm_host, REG_DSI_ACTIVE_HSYNC, 823 DSI_ACTIVE_HSYNC_START(hs_start) | 824 DSI_ACTIVE_HSYNC_END(hs_end)); 825 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_HPOS, 0); 826 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_VPOS, 827 DSI_ACTIVE_VSYNC_VPOS_START(vs_start) | 828 DSI_ACTIVE_VSYNC_VPOS_END(vs_end)); 829 } else { /* command mode */ 830 /* image data and 1 byte write_memory_start cmd */ 831 wc = mode->hdisplay * dsi_get_bpp(msm_host->format) / 8 + 1; 832 833 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM_CTRL, 834 DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT(wc) | 835 DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL( 836 msm_host->channel) | 837 DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE( 838 MIPI_DSI_DCS_LONG_WRITE)); 839 840 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM_TOTAL, 841 DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL(mode->hdisplay) | 842 DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL(mode->vdisplay)); 843 } 844} 845 846static void dsi_sw_reset(struct msm_dsi_host *msm_host) 847{ 848 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS); 849 wmb(); /* clocks need to be enabled before reset */ 850 851 dsi_write(msm_host, REG_DSI_RESET, 1); 852 wmb(); /* make sure reset happen */ 853 dsi_write(msm_host, REG_DSI_RESET, 0); 854} 855 856static void dsi_op_mode_config(struct msm_dsi_host *msm_host, 857 bool video_mode, bool enable) 858{ 859 u32 dsi_ctrl; 860 861 dsi_ctrl = dsi_read(msm_host, REG_DSI_CTRL); 862 863 if (!enable) { 864 dsi_ctrl &= ~(DSI_CTRL_ENABLE | DSI_CTRL_VID_MODE_EN | 865 DSI_CTRL_CMD_MODE_EN); 866 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE | 867 DSI_IRQ_MASK_VIDEO_DONE, 0); 868 } else { 869 if (video_mode) { 870 dsi_ctrl |= DSI_CTRL_VID_MODE_EN; 871 } else { /* command mode */ 872 dsi_ctrl |= DSI_CTRL_CMD_MODE_EN; 873 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE, 1); 874 } 875 dsi_ctrl |= DSI_CTRL_ENABLE; 876 } 877 878 dsi_write(msm_host, REG_DSI_CTRL, dsi_ctrl); 879} 880 881static void dsi_set_tx_power_mode(int mode, struct msm_dsi_host *msm_host) 882{ 883 u32 data; 884 885 data = dsi_read(msm_host, REG_DSI_CMD_DMA_CTRL); 886 887 if (mode == 0) 888 data &= ~DSI_CMD_DMA_CTRL_LOW_POWER; 889 else 890 data |= DSI_CMD_DMA_CTRL_LOW_POWER; 891 892 dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL, data); 893} 894 895static void dsi_wait4video_done(struct msm_dsi_host *msm_host) 896{ 897 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 1); 898 899 reinit_completion(&msm_host->video_comp); 900 901 wait_for_completion_timeout(&msm_host->video_comp, 902 msecs_to_jiffies(70)); 903 904 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 0); 905} 906 907static void dsi_wait4video_eng_busy(struct msm_dsi_host *msm_host) 908{ 909 if (!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO)) 910 return; 911 912 if (msm_host->power_on) { 913 dsi_wait4video_done(msm_host); 914 /* delay 4 ms to skip BLLP */ 915 usleep_range(2000, 4000); 916 } 917} 918 919/* dsi_cmd */ 920static int dsi_tx_buf_alloc(struct msm_dsi_host *msm_host, int size) 921{ 922 struct drm_device *dev = msm_host->dev; 923 int ret; 924 u32 iova; 925 926 mutex_lock(&dev->struct_mutex); 927 msm_host->tx_gem_obj = msm_gem_new(dev, size, MSM_BO_UNCACHED); 928 if (IS_ERR(msm_host->tx_gem_obj)) { 929 ret = PTR_ERR(msm_host->tx_gem_obj); 930 pr_err("%s: failed to allocate gem, %d\n", __func__, ret); 931 msm_host->tx_gem_obj = NULL; 932 mutex_unlock(&dev->struct_mutex); 933 return ret; 934 } 935 936 ret = msm_gem_get_iova_locked(msm_host->tx_gem_obj, 0, &iova); 937 if (ret) { 938 pr_err("%s: failed to get iova, %d\n", __func__, ret); 939 return ret; 940 } 941 mutex_unlock(&dev->struct_mutex); 942 943 if (iova & 0x07) { 944 pr_err("%s: buf NOT 8 bytes aligned\n", __func__); 945 return -EINVAL; 946 } 947 948 return 0; 949} 950 951static void dsi_tx_buf_free(struct msm_dsi_host *msm_host) 952{ 953 struct drm_device *dev = msm_host->dev; 954 955 if (msm_host->tx_gem_obj) { 956 msm_gem_put_iova(msm_host->tx_gem_obj, 0); 957 mutex_lock(&dev->struct_mutex); 958 msm_gem_free_object(msm_host->tx_gem_obj); 959 msm_host->tx_gem_obj = NULL; 960 mutex_unlock(&dev->struct_mutex); 961 } 962} 963 964/* 965 * prepare cmd buffer to be txed 966 */ 967static int dsi_cmd_dma_add(struct drm_gem_object *tx_gem, 968 const struct mipi_dsi_msg *msg) 969{ 970 struct mipi_dsi_packet packet; 971 int len; 972 int ret; 973 u8 *data; 974 975 ret = mipi_dsi_create_packet(&packet, msg); 976 if (ret) { 977 pr_err("%s: create packet failed, %d\n", __func__, ret); 978 return ret; 979 } 980 len = (packet.size + 3) & (~0x3); 981 982 if (len > tx_gem->size) { 983 pr_err("%s: packet size is too big\n", __func__); 984 return -EINVAL; 985 } 986 987 data = msm_gem_vaddr(tx_gem); 988 989 if (IS_ERR(data)) { 990 ret = PTR_ERR(data); 991 pr_err("%s: get vaddr failed, %d\n", __func__, ret); 992 return ret; 993 } 994 995 /* MSM specific command format in memory */ 996 data[0] = packet.header[1]; 997 data[1] = packet.header[2]; 998 data[2] = packet.header[0]; 999 data[3] = BIT(7); /* Last packet */ 1000 if (mipi_dsi_packet_format_is_long(msg->type)) 1001 data[3] |= BIT(6); 1002 if (msg->rx_buf && msg->rx_len) 1003 data[3] |= BIT(5); 1004 1005 /* Long packet */ 1006 if (packet.payload && packet.payload_length) 1007 memcpy(data + 4, packet.payload, packet.payload_length); 1008 1009 /* Append 0xff to the end */ 1010 if (packet.size < len) 1011 memset(data + packet.size, 0xff, len - packet.size); 1012 1013 return len; 1014} 1015 1016/* 1017 * dsi_short_read1_resp: 1 parameter 1018 */ 1019static int dsi_short_read1_resp(u8 *buf, const struct mipi_dsi_msg *msg) 1020{ 1021 u8 *data = msg->rx_buf; 1022 if (data && (msg->rx_len >= 1)) { 1023 *data = buf[1]; /* strip out dcs type */ 1024 return 1; 1025 } else { 1026 pr_err("%s: read data does not match with rx_buf len %zu\n", 1027 __func__, msg->rx_len); 1028 return -EINVAL; 1029 } 1030} 1031 1032/* 1033 * dsi_short_read2_resp: 2 parameter 1034 */ 1035static int dsi_short_read2_resp(u8 *buf, const struct mipi_dsi_msg *msg) 1036{ 1037 u8 *data = msg->rx_buf; 1038 if (data && (msg->rx_len >= 2)) { 1039 data[0] = buf[1]; /* strip out dcs type */ 1040 data[1] = buf[2]; 1041 return 2; 1042 } else { 1043 pr_err("%s: read data does not match with rx_buf len %zu\n", 1044 __func__, msg->rx_len); 1045 return -EINVAL; 1046 } 1047} 1048 1049static int dsi_long_read_resp(u8 *buf, const struct mipi_dsi_msg *msg) 1050{ 1051 /* strip out 4 byte dcs header */ 1052 if (msg->rx_buf && msg->rx_len) 1053 memcpy(msg->rx_buf, buf + 4, msg->rx_len); 1054 1055 return msg->rx_len; 1056} 1057 1058 1059static int dsi_cmd_dma_tx(struct msm_dsi_host *msm_host, int len) 1060{ 1061 int ret; 1062 u32 iova; 1063 bool triggered; 1064 1065 ret = msm_gem_get_iova(msm_host->tx_gem_obj, 0, &iova); 1066 if (ret) { 1067 pr_err("%s: failed to get iova: %d\n", __func__, ret); 1068 return ret; 1069 } 1070 1071 reinit_completion(&msm_host->dma_comp); 1072 1073 dsi_wait4video_eng_busy(msm_host); 1074 1075 triggered = msm_dsi_manager_cmd_xfer_trigger( 1076 msm_host->id, iova, len); 1077 if (triggered) { 1078 ret = wait_for_completion_timeout(&msm_host->dma_comp, 1079 msecs_to_jiffies(200)); 1080 DBG("ret=%d", ret); 1081 if (ret == 0) 1082 ret = -ETIMEDOUT; 1083 else 1084 ret = len; 1085 } else 1086 ret = len; 1087 1088 return ret; 1089} 1090 1091static int dsi_cmd_dma_rx(struct msm_dsi_host *msm_host, 1092 u8 *buf, int rx_byte, int pkt_size) 1093{ 1094 u32 *lp, *temp, data; 1095 int i, j = 0, cnt; 1096 u32 read_cnt; 1097 u8 reg[16]; 1098 int repeated_bytes = 0; 1099 int buf_offset = buf - msm_host->rx_buf; 1100 1101 lp = (u32 *)buf; 1102 temp = (u32 *)reg; 1103 cnt = (rx_byte + 3) >> 2; 1104 if (cnt > 4) 1105 cnt = 4; /* 4 x 32 bits registers only */ 1106 1107 if (rx_byte == 4) 1108 read_cnt = 4; 1109 else 1110 read_cnt = pkt_size + 6; 1111 1112 /* 1113 * In case of multiple reads from the panel, after the first read, there 1114 * is possibility that there are some bytes in the payload repeating in 1115 * the RDBK_DATA registers. Since we read all the parameters from the 1116 * panel right from the first byte for every pass. We need to skip the 1117 * repeating bytes and then append the new parameters to the rx buffer. 1118 */ 1119 if (read_cnt > 16) { 1120 int bytes_shifted; 1121 /* Any data more than 16 bytes will be shifted out. 1122 * The temp read buffer should already contain these bytes. 1123 * The remaining bytes in read buffer are the repeated bytes. 1124 */ 1125 bytes_shifted = read_cnt - 16; 1126 repeated_bytes = buf_offset - bytes_shifted; 1127 } 1128 1129 for (i = cnt - 1; i >= 0; i--) { 1130 data = dsi_read(msm_host, REG_DSI_RDBK_DATA(i)); 1131 *temp++ = ntohl(data); /* to host byte order */ 1132 DBG("data = 0x%x and ntohl(data) = 0x%x", data, ntohl(data)); 1133 } 1134 1135 for (i = repeated_bytes; i < 16; i++) 1136 buf[j++] = reg[i]; 1137 1138 return j; 1139} 1140 1141static int dsi_cmds2buf_tx(struct msm_dsi_host *msm_host, 1142 const struct mipi_dsi_msg *msg) 1143{ 1144 int len, ret; 1145 int bllp_len = msm_host->mode->hdisplay * 1146 dsi_get_bpp(msm_host->format) / 8; 1147 1148 len = dsi_cmd_dma_add(msm_host->tx_gem_obj, msg); 1149 if (!len) { 1150 pr_err("%s: failed to add cmd type = 0x%x\n", 1151 __func__, msg->type); 1152 return -EINVAL; 1153 } 1154 1155 /* for video mode, do not send cmds more than 1156 * one pixel line, since it only transmit it 1157 * during BLLP. 1158 */ 1159 /* TODO: if the command is sent in LP mode, the bit rate is only 1160 * half of esc clk rate. In this case, if the video is already 1161 * actively streaming, we need to check more carefully if the 1162 * command can be fit into one BLLP. 1163 */ 1164 if ((msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) && (len > bllp_len)) { 1165 pr_err("%s: cmd cannot fit into BLLP period, len=%d\n", 1166 __func__, len); 1167 return -EINVAL; 1168 } 1169 1170 ret = dsi_cmd_dma_tx(msm_host, len); 1171 if (ret < len) { 1172 pr_err("%s: cmd dma tx failed, type=0x%x, data0=0x%x, len=%d\n", 1173 __func__, msg->type, (*(u8 *)(msg->tx_buf)), len); 1174 return -ECOMM; 1175 } 1176 1177 return len; 1178} 1179 1180static void dsi_sw_reset_restore(struct msm_dsi_host *msm_host) 1181{ 1182 u32 data0, data1; 1183 1184 data0 = dsi_read(msm_host, REG_DSI_CTRL); 1185 data1 = data0; 1186 data1 &= ~DSI_CTRL_ENABLE; 1187 dsi_write(msm_host, REG_DSI_CTRL, data1); 1188 /* 1189 * dsi controller need to be disabled before 1190 * clocks turned on 1191 */ 1192 wmb(); 1193 1194 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS); 1195 wmb(); /* make sure clocks enabled */ 1196 1197 /* dsi controller can only be reset while clocks are running */ 1198 dsi_write(msm_host, REG_DSI_RESET, 1); 1199 wmb(); /* make sure reset happen */ 1200 dsi_write(msm_host, REG_DSI_RESET, 0); 1201 wmb(); /* controller out of reset */ 1202 dsi_write(msm_host, REG_DSI_CTRL, data0); 1203 wmb(); /* make sure dsi controller enabled again */ 1204} 1205 1206static void dsi_err_worker(struct work_struct *work) 1207{ 1208 struct msm_dsi_host *msm_host = 1209 container_of(work, struct msm_dsi_host, err_work); 1210 u32 status = msm_host->err_work_state; 1211 1212 pr_err_ratelimited("%s: status=%x\n", __func__, status); 1213 if (status & DSI_ERR_STATE_MDP_FIFO_UNDERFLOW) 1214 dsi_sw_reset_restore(msm_host); 1215 1216 /* It is safe to clear here because error irq is disabled. */ 1217 msm_host->err_work_state = 0; 1218 1219 /* enable dsi error interrupt */ 1220 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1); 1221} 1222 1223static void dsi_ack_err_status(struct msm_dsi_host *msm_host) 1224{ 1225 u32 status; 1226 1227 status = dsi_read(msm_host, REG_DSI_ACK_ERR_STATUS); 1228 1229 if (status) { 1230 dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, status); 1231 /* Writing of an extra 0 needed to clear error bits */ 1232 dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, 0); 1233 msm_host->err_work_state |= DSI_ERR_STATE_ACK; 1234 } 1235} 1236 1237static void dsi_timeout_status(struct msm_dsi_host *msm_host) 1238{ 1239 u32 status; 1240 1241 status = dsi_read(msm_host, REG_DSI_TIMEOUT_STATUS); 1242 1243 if (status) { 1244 dsi_write(msm_host, REG_DSI_TIMEOUT_STATUS, status); 1245 msm_host->err_work_state |= DSI_ERR_STATE_TIMEOUT; 1246 } 1247} 1248 1249static void dsi_dln0_phy_err(struct msm_dsi_host *msm_host) 1250{ 1251 u32 status; 1252 1253 status = dsi_read(msm_host, REG_DSI_DLN0_PHY_ERR); 1254 1255 if (status) { 1256 dsi_write(msm_host, REG_DSI_DLN0_PHY_ERR, status); 1257 msm_host->err_work_state |= DSI_ERR_STATE_DLN0_PHY; 1258 } 1259} 1260 1261static void dsi_fifo_status(struct msm_dsi_host *msm_host) 1262{ 1263 u32 status; 1264 1265 status = dsi_read(msm_host, REG_DSI_FIFO_STATUS); 1266 1267 /* fifo underflow, overflow */ 1268 if (status) { 1269 dsi_write(msm_host, REG_DSI_FIFO_STATUS, status); 1270 msm_host->err_work_state |= DSI_ERR_STATE_FIFO; 1271 if (status & DSI_FIFO_STATUS_CMD_MDP_FIFO_UNDERFLOW) 1272 msm_host->err_work_state |= 1273 DSI_ERR_STATE_MDP_FIFO_UNDERFLOW; 1274 } 1275} 1276 1277static void dsi_status(struct msm_dsi_host *msm_host) 1278{ 1279 u32 status; 1280 1281 status = dsi_read(msm_host, REG_DSI_STATUS0); 1282 1283 if (status & DSI_STATUS0_INTERLEAVE_OP_CONTENTION) { 1284 dsi_write(msm_host, REG_DSI_STATUS0, status); 1285 msm_host->err_work_state |= 1286 DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION; 1287 } 1288} 1289 1290static void dsi_clk_status(struct msm_dsi_host *msm_host) 1291{ 1292 u32 status; 1293 1294 status = dsi_read(msm_host, REG_DSI_CLK_STATUS); 1295 1296 if (status & DSI_CLK_STATUS_PLL_UNLOCKED) { 1297 dsi_write(msm_host, REG_DSI_CLK_STATUS, status); 1298 msm_host->err_work_state |= DSI_ERR_STATE_PLL_UNLOCKED; 1299 } 1300} 1301 1302static void dsi_error(struct msm_dsi_host *msm_host) 1303{ 1304 /* disable dsi error interrupt */ 1305 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 0); 1306 1307 dsi_clk_status(msm_host); 1308 dsi_fifo_status(msm_host); 1309 dsi_ack_err_status(msm_host); 1310 dsi_timeout_status(msm_host); 1311 dsi_status(msm_host); 1312 dsi_dln0_phy_err(msm_host); 1313 1314 queue_work(msm_host->workqueue, &msm_host->err_work); 1315} 1316 1317static irqreturn_t dsi_host_irq(int irq, void *ptr) 1318{ 1319 struct msm_dsi_host *msm_host = ptr; 1320 u32 isr; 1321 unsigned long flags; 1322 1323 if (!msm_host->ctrl_base) 1324 return IRQ_HANDLED; 1325 1326 spin_lock_irqsave(&msm_host->intr_lock, flags); 1327 isr = dsi_read(msm_host, REG_DSI_INTR_CTRL); 1328 dsi_write(msm_host, REG_DSI_INTR_CTRL, isr); 1329 spin_unlock_irqrestore(&msm_host->intr_lock, flags); 1330 1331 DBG("isr=0x%x, id=%d", isr, msm_host->id); 1332 1333 if (isr & DSI_IRQ_ERROR) 1334 dsi_error(msm_host); 1335 1336 if (isr & DSI_IRQ_VIDEO_DONE) 1337 complete(&msm_host->video_comp); 1338 1339 if (isr & DSI_IRQ_CMD_DMA_DONE) 1340 complete(&msm_host->dma_comp); 1341 1342 return IRQ_HANDLED; 1343} 1344 1345static int dsi_host_init_panel_gpios(struct msm_dsi_host *msm_host, 1346 struct device *panel_device) 1347{ 1348 int ret; 1349 1350 msm_host->disp_en_gpio = devm_gpiod_get(panel_device, 1351 "disp-enable"); 1352 if (IS_ERR(msm_host->disp_en_gpio)) { 1353 DBG("cannot get disp-enable-gpios %ld", 1354 PTR_ERR(msm_host->disp_en_gpio)); 1355 msm_host->disp_en_gpio = NULL; 1356 } 1357 if (msm_host->disp_en_gpio) { 1358 ret = gpiod_direction_output(msm_host->disp_en_gpio, 0); 1359 if (ret) { 1360 pr_err("cannot set dir to disp-en-gpios %d\n", ret); 1361 return ret; 1362 } 1363 } 1364 1365 msm_host->te_gpio = devm_gpiod_get(panel_device, "disp-te"); 1366 if (IS_ERR(msm_host->te_gpio)) { 1367 DBG("cannot get disp-te-gpios %ld", PTR_ERR(msm_host->te_gpio)); 1368 msm_host->te_gpio = NULL; 1369 } 1370 1371 if (msm_host->te_gpio) { 1372 ret = gpiod_direction_input(msm_host->te_gpio); 1373 if (ret) { 1374 pr_err("%s: cannot set dir to disp-te-gpios, %d\n", 1375 __func__, ret); 1376 return ret; 1377 } 1378 } 1379 1380 return 0; 1381} 1382 1383static int dsi_host_attach(struct mipi_dsi_host *host, 1384 struct mipi_dsi_device *dsi) 1385{ 1386 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1387 int ret; 1388 1389 msm_host->channel = dsi->channel; 1390 msm_host->lanes = dsi->lanes; 1391 msm_host->format = dsi->format; 1392 msm_host->mode_flags = dsi->mode_flags; 1393 1394 msm_host->panel_node = dsi->dev.of_node; 1395 1396 /* Some gpios defined in panel DT need to be controlled by host */ 1397 ret = dsi_host_init_panel_gpios(msm_host, &dsi->dev); 1398 if (ret) 1399 return ret; 1400 1401 DBG("id=%d", msm_host->id); 1402 if (msm_host->dev) 1403 drm_helper_hpd_irq_event(msm_host->dev); 1404 1405 return 0; 1406} 1407 1408static int dsi_host_detach(struct mipi_dsi_host *host, 1409 struct mipi_dsi_device *dsi) 1410{ 1411 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1412 1413 msm_host->panel_node = NULL; 1414 1415 DBG("id=%d", msm_host->id); 1416 if (msm_host->dev) 1417 drm_helper_hpd_irq_event(msm_host->dev); 1418 1419 return 0; 1420} 1421 1422static ssize_t dsi_host_transfer(struct mipi_dsi_host *host, 1423 const struct mipi_dsi_msg *msg) 1424{ 1425 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1426 int ret; 1427 1428 if (!msg || !msm_host->power_on) 1429 return -EINVAL; 1430 1431 mutex_lock(&msm_host->cmd_mutex); 1432 ret = msm_dsi_manager_cmd_xfer(msm_host->id, msg); 1433 mutex_unlock(&msm_host->cmd_mutex); 1434 1435 return ret; 1436} 1437 1438static struct mipi_dsi_host_ops dsi_host_ops = { 1439 .attach = dsi_host_attach, 1440 .detach = dsi_host_detach, 1441 .transfer = dsi_host_transfer, 1442}; 1443 1444int msm_dsi_host_init(struct msm_dsi *msm_dsi) 1445{ 1446 struct msm_dsi_host *msm_host = NULL; 1447 struct platform_device *pdev = msm_dsi->pdev; 1448 int ret; 1449 1450 msm_host = devm_kzalloc(&pdev->dev, sizeof(*msm_host), GFP_KERNEL); 1451 if (!msm_host) { 1452 pr_err("%s: FAILED: cannot alloc dsi host\n", 1453 __func__); 1454 ret = -ENOMEM; 1455 goto fail; 1456 } 1457 1458 ret = of_property_read_u32(pdev->dev.of_node, 1459 "qcom,dsi-host-index", &msm_host->id); 1460 if (ret) { 1461 dev_err(&pdev->dev, 1462 "%s: host index not specified, ret=%d\n", 1463 __func__, ret); 1464 goto fail; 1465 } 1466 msm_host->pdev = pdev; 1467 1468 ret = dsi_clk_init(msm_host); 1469 if (ret) { 1470 pr_err("%s: unable to initialize dsi clks\n", __func__); 1471 goto fail; 1472 } 1473 1474 msm_host->ctrl_base = msm_ioremap(pdev, "dsi_ctrl", "DSI CTRL"); 1475 if (IS_ERR(msm_host->ctrl_base)) { 1476 pr_err("%s: unable to map Dsi ctrl base\n", __func__); 1477 ret = PTR_ERR(msm_host->ctrl_base); 1478 goto fail; 1479 } 1480 1481 msm_host->cfg = dsi_get_config(msm_host); 1482 if (!msm_host->cfg) { 1483 ret = -EINVAL; 1484 pr_err("%s: get config failed\n", __func__); 1485 goto fail; 1486 } 1487 1488 ret = dsi_regulator_init(msm_host); 1489 if (ret) { 1490 pr_err("%s: regulator init failed\n", __func__); 1491 goto fail; 1492 } 1493 1494 msm_host->rx_buf = devm_kzalloc(&pdev->dev, SZ_4K, GFP_KERNEL); 1495 if (!msm_host->rx_buf) { 1496 pr_err("%s: alloc rx temp buf failed\n", __func__); 1497 goto fail; 1498 } 1499 1500 init_completion(&msm_host->dma_comp); 1501 init_completion(&msm_host->video_comp); 1502 mutex_init(&msm_host->dev_mutex); 1503 mutex_init(&msm_host->cmd_mutex); 1504 mutex_init(&msm_host->clk_mutex); 1505 spin_lock_init(&msm_host->intr_lock); 1506 1507 /* setup workqueue */ 1508 msm_host->workqueue = alloc_ordered_workqueue("dsi_drm_work", 0); 1509 INIT_WORK(&msm_host->err_work, dsi_err_worker); 1510 1511 msm_dsi->phy = msm_dsi_phy_init(pdev, msm_host->cfg->phy_type, 1512 msm_host->id); 1513 if (!msm_dsi->phy) { 1514 ret = -EINVAL; 1515 pr_err("%s: phy init failed\n", __func__); 1516 goto fail; 1517 } 1518 msm_dsi->host = &msm_host->base; 1519 msm_dsi->id = msm_host->id; 1520 1521 DBG("Dsi Host %d initialized", msm_host->id); 1522 return 0; 1523 1524fail: 1525 return ret; 1526} 1527 1528void msm_dsi_host_destroy(struct mipi_dsi_host *host) 1529{ 1530 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1531 1532 DBG(""); 1533 dsi_tx_buf_free(msm_host); 1534 if (msm_host->workqueue) { 1535 flush_workqueue(msm_host->workqueue); 1536 destroy_workqueue(msm_host->workqueue); 1537 msm_host->workqueue = NULL; 1538 } 1539 1540 mutex_destroy(&msm_host->clk_mutex); 1541 mutex_destroy(&msm_host->cmd_mutex); 1542 mutex_destroy(&msm_host->dev_mutex); 1543} 1544 1545int msm_dsi_host_modeset_init(struct mipi_dsi_host *host, 1546 struct drm_device *dev) 1547{ 1548 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1549 struct platform_device *pdev = msm_host->pdev; 1550 int ret; 1551 1552 msm_host->irq = irq_of_parse_and_map(pdev->dev.of_node, 0); 1553 if (msm_host->irq < 0) { 1554 ret = msm_host->irq; 1555 dev_err(dev->dev, "failed to get irq: %d\n", ret); 1556 return ret; 1557 } 1558 1559 ret = devm_request_irq(&pdev->dev, msm_host->irq, 1560 dsi_host_irq, IRQF_TRIGGER_HIGH | IRQF_ONESHOT, 1561 "dsi_isr", msm_host); 1562 if (ret < 0) { 1563 dev_err(&pdev->dev, "failed to request IRQ%u: %d\n", 1564 msm_host->irq, ret); 1565 return ret; 1566 } 1567 1568 msm_host->dev = dev; 1569 ret = dsi_tx_buf_alloc(msm_host, SZ_4K); 1570 if (ret) { 1571 pr_err("%s: alloc tx gem obj failed, %d\n", __func__, ret); 1572 return ret; 1573 } 1574 1575 return 0; 1576} 1577 1578int msm_dsi_host_register(struct mipi_dsi_host *host, bool check_defer) 1579{ 1580 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1581 struct device_node *node; 1582 int ret; 1583 1584 /* Register mipi dsi host */ 1585 if (!msm_host->registered) { 1586 host->dev = &msm_host->pdev->dev; 1587 host->ops = &dsi_host_ops; 1588 ret = mipi_dsi_host_register(host); 1589 if (ret) 1590 return ret; 1591 1592 msm_host->registered = true; 1593 1594 /* If the panel driver has not been probed after host register, 1595 * we should defer the host's probe. 1596 * It makes sure panel is connected when fbcon detects 1597 * connector status and gets the proper display mode to 1598 * create framebuffer. 1599 */ 1600 if (check_defer) { 1601 node = of_get_child_by_name(msm_host->pdev->dev.of_node, 1602 "panel"); 1603 if (node) { 1604 if (!of_drm_find_panel(node)) 1605 return -EPROBE_DEFER; 1606 } 1607 } 1608 } 1609 1610 return 0; 1611} 1612 1613void msm_dsi_host_unregister(struct mipi_dsi_host *host) 1614{ 1615 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1616 1617 if (msm_host->registered) { 1618 mipi_dsi_host_unregister(host); 1619 host->dev = NULL; 1620 host->ops = NULL; 1621 msm_host->registered = false; 1622 } 1623} 1624 1625int msm_dsi_host_xfer_prepare(struct mipi_dsi_host *host, 1626 const struct mipi_dsi_msg *msg) 1627{ 1628 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1629 1630 /* TODO: make sure dsi_cmd_mdp is idle. 1631 * Since DSI6G v1.2.0, we can set DSI_TRIG_CTRL.BLOCK_DMA_WITHIN_FRAME 1632 * to ask H/W to wait until cmd mdp is idle. S/W wait is not needed. 1633 * How to handle the old versions? Wait for mdp cmd done? 1634 */ 1635 1636 /* 1637 * mdss interrupt is generated in mdp core clock domain 1638 * mdp clock need to be enabled to receive dsi interrupt 1639 */ 1640 dsi_clk_ctrl(msm_host, 1); 1641 1642 /* TODO: vote for bus bandwidth */ 1643 1644 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM)) 1645 dsi_set_tx_power_mode(0, msm_host); 1646 1647 msm_host->dma_cmd_ctrl_restore = dsi_read(msm_host, REG_DSI_CTRL); 1648 dsi_write(msm_host, REG_DSI_CTRL, 1649 msm_host->dma_cmd_ctrl_restore | 1650 DSI_CTRL_CMD_MODE_EN | 1651 DSI_CTRL_ENABLE); 1652 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 1); 1653 1654 return 0; 1655} 1656 1657void msm_dsi_host_xfer_restore(struct mipi_dsi_host *host, 1658 const struct mipi_dsi_msg *msg) 1659{ 1660 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1661 1662 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 0); 1663 dsi_write(msm_host, REG_DSI_CTRL, msm_host->dma_cmd_ctrl_restore); 1664 1665 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM)) 1666 dsi_set_tx_power_mode(1, msm_host); 1667 1668 /* TODO: unvote for bus bandwidth */ 1669 1670 dsi_clk_ctrl(msm_host, 0); 1671} 1672 1673int msm_dsi_host_cmd_tx(struct mipi_dsi_host *host, 1674 const struct mipi_dsi_msg *msg) 1675{ 1676 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1677 1678 return dsi_cmds2buf_tx(msm_host, msg); 1679} 1680 1681int msm_dsi_host_cmd_rx(struct mipi_dsi_host *host, 1682 const struct mipi_dsi_msg *msg) 1683{ 1684 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1685 int data_byte, rx_byte, dlen, end; 1686 int short_response, diff, pkt_size, ret = 0; 1687 char cmd; 1688 int rlen = msg->rx_len; 1689 u8 *buf; 1690 1691 if (rlen <= 2) { 1692 short_response = 1; 1693 pkt_size = rlen; 1694 rx_byte = 4; 1695 } else { 1696 short_response = 0; 1697 data_byte = 10; /* first read */ 1698 if (rlen < data_byte) 1699 pkt_size = rlen; 1700 else 1701 pkt_size = data_byte; 1702 rx_byte = data_byte + 6; /* 4 header + 2 crc */ 1703 } 1704 1705 buf = msm_host->rx_buf; 1706 end = 0; 1707 while (!end) { 1708 u8 tx[2] = {pkt_size & 0xff, pkt_size >> 8}; 1709 struct mipi_dsi_msg max_pkt_size_msg = { 1710 .channel = msg->channel, 1711 .type = MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, 1712 .tx_len = 2, 1713 .tx_buf = tx, 1714 }; 1715 1716 DBG("rlen=%d pkt_size=%d rx_byte=%d", 1717 rlen, pkt_size, rx_byte); 1718 1719 ret = dsi_cmds2buf_tx(msm_host, &max_pkt_size_msg); 1720 if (ret < 2) { 1721 pr_err("%s: Set max pkt size failed, %d\n", 1722 __func__, ret); 1723 return -EINVAL; 1724 } 1725 1726 if ((msm_host->cfg->major == MSM_DSI_VER_MAJOR_6G) && 1727 (msm_host->cfg->minor >= MSM_DSI_6G_VER_MINOR_V1_1)) { 1728 /* Clear the RDBK_DATA registers */ 1729 dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL, 1730 DSI_RDBK_DATA_CTRL_CLR); 1731 wmb(); /* make sure the RDBK registers are cleared */ 1732 dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL, 0); 1733 wmb(); /* release cleared status before transfer */ 1734 } 1735 1736 ret = dsi_cmds2buf_tx(msm_host, msg); 1737 if (ret < msg->tx_len) { 1738 pr_err("%s: Read cmd Tx failed, %d\n", __func__, ret); 1739 return ret; 1740 } 1741 1742 /* 1743 * once cmd_dma_done interrupt received, 1744 * return data from client is ready and stored 1745 * at RDBK_DATA register already 1746 * since rx fifo is 16 bytes, dcs header is kept at first loop, 1747 * after that dcs header lost during shift into registers 1748 */ 1749 dlen = dsi_cmd_dma_rx(msm_host, buf, rx_byte, pkt_size); 1750 1751 if (dlen <= 0) 1752 return 0; 1753 1754 if (short_response) 1755 break; 1756 1757 if (rlen <= data_byte) { 1758 diff = data_byte - rlen; 1759 end = 1; 1760 } else { 1761 diff = 0; 1762 rlen -= data_byte; 1763 } 1764 1765 if (!end) { 1766 dlen -= 2; /* 2 crc */ 1767 dlen -= diff; 1768 buf += dlen; /* next start position */ 1769 data_byte = 14; /* NOT first read */ 1770 if (rlen < data_byte) 1771 pkt_size += rlen; 1772 else 1773 pkt_size += data_byte; 1774 DBG("buf=%p dlen=%d diff=%d", buf, dlen, diff); 1775 } 1776 } 1777 1778 /* 1779 * For single Long read, if the requested rlen < 10, 1780 * we need to shift the start position of rx 1781 * data buffer to skip the bytes which are not 1782 * updated. 1783 */ 1784 if (pkt_size < 10 && !short_response) 1785 buf = msm_host->rx_buf + (10 - rlen); 1786 else 1787 buf = msm_host->rx_buf; 1788 1789 cmd = buf[0]; 1790 switch (cmd) { 1791 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT: 1792 pr_err("%s: rx ACK_ERR_PACLAGE\n", __func__); 1793 ret = 0; 1794 break; 1795 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE: 1796 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE: 1797 ret = dsi_short_read1_resp(buf, msg); 1798 break; 1799 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE: 1800 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE: 1801 ret = dsi_short_read2_resp(buf, msg); 1802 break; 1803 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE: 1804 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE: 1805 ret = dsi_long_read_resp(buf, msg); 1806 break; 1807 default: 1808 pr_warn("%s:Invalid response cmd\n", __func__); 1809 ret = 0; 1810 } 1811 1812 return ret; 1813} 1814 1815void msm_dsi_host_cmd_xfer_commit(struct mipi_dsi_host *host, u32 iova, u32 len) 1816{ 1817 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1818 1819 dsi_write(msm_host, REG_DSI_DMA_BASE, iova); 1820 dsi_write(msm_host, REG_DSI_DMA_LEN, len); 1821 dsi_write(msm_host, REG_DSI_TRIG_DMA, 1); 1822 1823 /* Make sure trigger happens */ 1824 wmb(); 1825} 1826 1827int msm_dsi_host_enable(struct mipi_dsi_host *host) 1828{ 1829 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1830 1831 dsi_op_mode_config(msm_host, 1832 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), true); 1833 1834 /* TODO: clock should be turned off for command mode, 1835 * and only turned on before MDP START. 1836 * This part of code should be enabled once mdp driver support it. 1837 */ 1838 /* if (msm_panel->mode == MSM_DSI_CMD_MODE) 1839 dsi_clk_ctrl(msm_host, 0); */ 1840 1841 return 0; 1842} 1843 1844int msm_dsi_host_disable(struct mipi_dsi_host *host) 1845{ 1846 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1847 1848 dsi_op_mode_config(msm_host, 1849 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), false); 1850 1851 /* Since we have disabled INTF, the video engine won't stop so that 1852 * the cmd engine will be blocked. 1853 * Reset to disable video engine so that we can send off cmd. 1854 */ 1855 dsi_sw_reset(msm_host); 1856 1857 return 0; 1858} 1859 1860int msm_dsi_host_power_on(struct mipi_dsi_host *host) 1861{ 1862 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1863 u32 clk_pre = 0, clk_post = 0; 1864 int ret = 0; 1865 1866 mutex_lock(&msm_host->dev_mutex); 1867 if (msm_host->power_on) { 1868 DBG("dsi host already on"); 1869 goto unlock_ret; 1870 } 1871 1872 ret = dsi_calc_clk_rate(msm_host); 1873 if (ret) { 1874 pr_err("%s: unable to calc clk rate, %d\n", __func__, ret); 1875 goto unlock_ret; 1876 } 1877 1878 ret = dsi_host_regulator_enable(msm_host); 1879 if (ret) { 1880 pr_err("%s:Failed to enable vregs.ret=%d\n", 1881 __func__, ret); 1882 goto unlock_ret; 1883 } 1884 1885 ret = dsi_bus_clk_enable(msm_host); 1886 if (ret) { 1887 pr_err("%s: failed to enable bus clocks, %d\n", __func__, ret); 1888 goto fail_disable_reg; 1889 } 1890 1891 dsi_phy_sw_reset(msm_host); 1892 ret = msm_dsi_manager_phy_enable(msm_host->id, 1893 msm_host->byte_clk_rate * 8, 1894 clk_get_rate(msm_host->esc_clk), 1895 &clk_pre, &clk_post); 1896 dsi_bus_clk_disable(msm_host); 1897 if (ret) { 1898 pr_err("%s: failed to enable phy, %d\n", __func__, ret); 1899 goto fail_disable_reg; 1900 } 1901 1902 ret = dsi_clk_ctrl(msm_host, 1); 1903 if (ret) { 1904 pr_err("%s: failed to enable clocks. ret=%d\n", __func__, ret); 1905 goto fail_disable_reg; 1906 } 1907 1908 dsi_timing_setup(msm_host); 1909 dsi_sw_reset(msm_host); 1910 dsi_ctrl_config(msm_host, true, clk_pre, clk_post); 1911 1912 if (msm_host->disp_en_gpio) 1913 gpiod_set_value(msm_host->disp_en_gpio, 1); 1914 1915 msm_host->power_on = true; 1916 mutex_unlock(&msm_host->dev_mutex); 1917 1918 return 0; 1919 1920fail_disable_reg: 1921 dsi_host_regulator_disable(msm_host); 1922unlock_ret: 1923 mutex_unlock(&msm_host->dev_mutex); 1924 return ret; 1925} 1926 1927int msm_dsi_host_power_off(struct mipi_dsi_host *host) 1928{ 1929 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1930 1931 mutex_lock(&msm_host->dev_mutex); 1932 if (!msm_host->power_on) { 1933 DBG("dsi host already off"); 1934 goto unlock_ret; 1935 } 1936 1937 dsi_ctrl_config(msm_host, false, 0, 0); 1938 1939 if (msm_host->disp_en_gpio) 1940 gpiod_set_value(msm_host->disp_en_gpio, 0); 1941 1942 msm_dsi_manager_phy_disable(msm_host->id); 1943 1944 dsi_clk_ctrl(msm_host, 0); 1945 1946 dsi_host_regulator_disable(msm_host); 1947 1948 DBG("-"); 1949 1950 msm_host->power_on = false; 1951 1952unlock_ret: 1953 mutex_unlock(&msm_host->dev_mutex); 1954 return 0; 1955} 1956 1957int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host, 1958 struct drm_display_mode *mode) 1959{ 1960 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1961 1962 if (msm_host->mode) { 1963 drm_mode_destroy(msm_host->dev, msm_host->mode); 1964 msm_host->mode = NULL; 1965 } 1966 1967 msm_host->mode = drm_mode_duplicate(msm_host->dev, mode); 1968 if (IS_ERR(msm_host->mode)) { 1969 pr_err("%s: cannot duplicate mode\n", __func__); 1970 return PTR_ERR(msm_host->mode); 1971 } 1972 1973 return 0; 1974} 1975 1976struct drm_panel *msm_dsi_host_get_panel(struct mipi_dsi_host *host, 1977 unsigned long *panel_flags) 1978{ 1979 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1980 struct drm_panel *panel; 1981 1982 panel = of_drm_find_panel(msm_host->panel_node); 1983 if (panel_flags) 1984 *panel_flags = msm_host->mode_flags; 1985 1986 return panel; 1987} 1988 1989