1/*
2 * Copyright (C) 2009 Francisco Jerez.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 *
25 */
26
27#ifndef __DRM_I2C_CH7006_PRIV_H__
28#define __DRM_I2C_CH7006_PRIV_H__
29
30#include <drm/drmP.h>
31#include <drm/drm_crtc_helper.h>
32#include <drm/drm_encoder_slave.h>
33#include <drm/i2c/ch7006.h>
34
35typedef int64_t fixed;
36#define fixed1 (1LL << 32)
37
38enum ch7006_tv_norm {
39	TV_NORM_PAL,
40	TV_NORM_PAL_M,
41	TV_NORM_PAL_N,
42	TV_NORM_PAL_NC,
43	TV_NORM_PAL_60,
44	TV_NORM_NTSC_M,
45	TV_NORM_NTSC_J,
46	NUM_TV_NORMS
47};
48
49struct ch7006_tv_norm_info {
50	fixed vrefresh;
51	int vdisplay;
52	int vtotal;
53	int hvirtual;
54
55	fixed subc_freq;
56	fixed black_level;
57
58	uint32_t dispmode;
59	int voffset;
60};
61
62struct ch7006_mode {
63	struct drm_display_mode mode;
64
65	int enc_hdisp;
66	int enc_vdisp;
67
68	fixed subc_coeff;
69	uint32_t dispmode;
70
71	uint32_t valid_scales;
72	uint32_t valid_norms;
73};
74
75struct ch7006_state {
76	uint8_t regs[0x26];
77};
78
79struct ch7006_priv {
80	struct ch7006_encoder_params params;
81	struct ch7006_mode *mode;
82
83	struct ch7006_state state;
84	struct ch7006_state saved_state;
85
86	struct drm_property *scale_property;
87
88	int select_subconnector;
89	int subconnector;
90	int hmargin;
91	int vmargin;
92	enum ch7006_tv_norm norm;
93	int brightness;
94	int contrast;
95	int flicker;
96	int scale;
97
98	int chip_version;
99	int last_dpms;
100};
101
102#define to_ch7006_priv(x) \
103	((struct ch7006_priv *)to_encoder_slave(x)->slave_priv)
104
105extern int ch7006_debug;
106extern char *ch7006_tv_norm;
107extern int ch7006_scale;
108
109extern char *ch7006_tv_norm_names[];
110extern struct ch7006_tv_norm_info ch7006_tv_norms[];
111extern struct ch7006_mode ch7006_modes[];
112
113struct ch7006_mode *ch7006_lookup_mode(struct drm_encoder *encoder,
114				       const struct drm_display_mode *drm_mode);
115
116void ch7006_setup_levels(struct drm_encoder *encoder);
117void ch7006_setup_subcarrier(struct drm_encoder *encoder);
118void ch7006_setup_pll(struct drm_encoder *encoder);
119void ch7006_setup_power_state(struct drm_encoder *encoder);
120void ch7006_setup_properties(struct drm_encoder *encoder);
121
122void ch7006_write(struct i2c_client *client, uint8_t addr, uint8_t val);
123uint8_t ch7006_read(struct i2c_client *client, uint8_t addr);
124
125void ch7006_state_load(struct i2c_client *client,
126		       struct ch7006_state *state);
127void ch7006_state_save(struct i2c_client *client,
128		       struct ch7006_state *state);
129
130/* Some helper macros */
131
132#define ch7006_dbg(client, format, ...) do {				\
133		if (ch7006_debug)					\
134			dev_printk(KERN_DEBUG, &client->dev,		\
135				   "%s: " format, __func__, ## __VA_ARGS__); \
136	} while (0)
137#define ch7006_info(client, format, ...) \
138				dev_info(&client->dev, format, __VA_ARGS__)
139#define ch7006_err(client, format, ...) \
140				dev_err(&client->dev, format, __VA_ARGS__)
141
142#define __mask(src, bitfield) \
143		(((2 << (1 ? bitfield)) - 1) & ~((1 << (0 ? bitfield)) - 1))
144#define mask(bitfield) __mask(bitfield)
145
146#define __bitf(src, bitfield, x) \
147		(((x) >> (src) << (0 ? bitfield)) &  __mask(src, bitfield))
148#define bitf(bitfield, x) __bitf(bitfield, x)
149#define bitfs(bitfield, s) __bitf(bitfield, bitfield##_##s)
150#define setbitf(state, reg, bitfield, x)				\
151	state->regs[reg] = (state->regs[reg] & ~mask(reg##_##bitfield))	\
152		| bitf(reg##_##bitfield, x)
153
154#define __unbitf(src, bitfield, x) \
155		((x & __mask(src, bitfield)) >> (0 ? bitfield) << (src))
156#define unbitf(bitfield, x) __unbitf(bitfield, x)
157
158static inline int interpolate(int y0, int y1, int y2, int x)
159{
160	return y1 + (x < 50 ? y1 - y0 : y2 - y1) * (x - 50) / 50;
161}
162
163static inline int32_t round_fixed(fixed x)
164{
165	return (x + fixed1/2) >> 32;
166}
167
168#define ch7006_load_reg(client, state, reg) ch7006_write(client, reg, state->regs[reg])
169#define ch7006_save_reg(client, state, reg) state->regs[reg] = ch7006_read(client, reg)
170
171/* Fixed hardware specs */
172
173#define CH7006_FREQ0				14318
174#define CH7006_MAXN				650
175#define CH7006_MAXM				315
176
177/* Register definitions */
178
179#define CH7006_DISPMODE				0x00
180#define CH7006_DISPMODE_INPUT_RES		0, 7:5
181#define CH7006_DISPMODE_INPUT_RES_512x384	0x0
182#define CH7006_DISPMODE_INPUT_RES_720x400	0x1
183#define CH7006_DISPMODE_INPUT_RES_640x400	0x2
184#define CH7006_DISPMODE_INPUT_RES_640x480	0x3
185#define CH7006_DISPMODE_INPUT_RES_800x600	0x4
186#define CH7006_DISPMODE_INPUT_RES_NATIVE	0x5
187#define CH7006_DISPMODE_OUTPUT_STD		0, 4:3
188#define CH7006_DISPMODE_OUTPUT_STD_PAL		0x0
189#define CH7006_DISPMODE_OUTPUT_STD_NTSC		0x1
190#define CH7006_DISPMODE_OUTPUT_STD_PAL_M	0x2
191#define CH7006_DISPMODE_OUTPUT_STD_NTSC_J	0x3
192#define CH7006_DISPMODE_SCALING_RATIO		0, 2:0
193#define CH7006_DISPMODE_SCALING_RATIO_5_4	0x0
194#define CH7006_DISPMODE_SCALING_RATIO_1_1	0x1
195#define CH7006_DISPMODE_SCALING_RATIO_7_8	0x2
196#define CH7006_DISPMODE_SCALING_RATIO_5_6	0x3
197#define CH7006_DISPMODE_SCALING_RATIO_3_4	0x4
198#define CH7006_DISPMODE_SCALING_RATIO_7_10	0x5
199
200#define CH7006_FFILTER				0x01
201#define CH7006_FFILTER_TEXT			0, 5:4
202#define CH7006_FFILTER_LUMA			0, 3:2
203#define CH7006_FFILTER_CHROMA			0, 1:0
204#define CH7006_FFILTER_CHROMA_NO_DCRAWL		0x3
205
206#define CH7006_BWIDTH				0x03
207#define CH7006_BWIDTH_5L_FFILER			(1 << 7)
208#define CH7006_BWIDTH_CVBS_NO_CHROMA		(1 << 6)
209#define CH7006_BWIDTH_CHROMA			0, 5:4
210#define CH7006_BWIDTH_SVIDEO_YPEAK		(1 << 3)
211#define CH7006_BWIDTH_SVIDEO_LUMA		0, 2:1
212#define CH7006_BWIDTH_CVBS_LUMA			0, 0:0
213
214#define CH7006_INPUT_FORMAT			0x04
215#define CH7006_INPUT_FORMAT_DAC_GAIN		(1 << 6)
216#define CH7006_INPUT_FORMAT_RGB_PASS_THROUGH	(1 << 5)
217#define CH7006_INPUT_FORMAT_FORMAT		0, 3:0
218#define CH7006_INPUT_FORMAT_FORMAT_RGB16	0x0
219#define CH7006_INPUT_FORMAT_FORMAT_YCrCb24m16	0x1
220#define CH7006_INPUT_FORMAT_FORMAT_RGB24m16	0x2
221#define CH7006_INPUT_FORMAT_FORMAT_RGB15	0x3
222#define CH7006_INPUT_FORMAT_FORMAT_RGB24m12C	0x4
223#define CH7006_INPUT_FORMAT_FORMAT_RGB24m12I	0x5
224#define CH7006_INPUT_FORMAT_FORMAT_RGB24m8	0x6
225#define CH7006_INPUT_FORMAT_FORMAT_RGB16m8	0x7
226#define CH7006_INPUT_FORMAT_FORMAT_RGB15m8	0x8
227#define CH7006_INPUT_FORMAT_FORMAT_YCrCb24m8	0x9
228
229#define CH7006_CLKMODE				0x06
230#define CH7006_CLKMODE_SUBC_LOCK		(1 << 7)
231#define CH7006_CLKMODE_MASTER			(1 << 6)
232#define CH7006_CLKMODE_POS_EDGE			(1 << 4)
233#define CH7006_CLKMODE_XCM			0, 3:2
234#define CH7006_CLKMODE_PCM			0, 1:0
235
236#define CH7006_START_ACTIVE			0x07
237#define CH7006_START_ACTIVE_0			0, 7:0
238
239#define CH7006_POV				0x08
240#define CH7006_POV_START_ACTIVE_8		8, 2:2
241#define CH7006_POV_HPOS_8			8, 1:1
242#define CH7006_POV_VPOS_8			8, 0:0
243
244#define CH7006_BLACK_LEVEL			0x09
245#define CH7006_BLACK_LEVEL_0			0, 7:0
246
247#define CH7006_HPOS				0x0a
248#define CH7006_HPOS_0				0, 7:0
249
250#define CH7006_VPOS				0x0b
251#define CH7006_VPOS_0				0, 7:0
252
253#define CH7006_INPUT_SYNC			0x0d
254#define CH7006_INPUT_SYNC_EMBEDDED		(1 << 3)
255#define CH7006_INPUT_SYNC_OUTPUT		(1 << 2)
256#define CH7006_INPUT_SYNC_PVSYNC		(1 << 1)
257#define CH7006_INPUT_SYNC_PHSYNC		(1 << 0)
258
259#define CH7006_POWER				0x0e
260#define CH7006_POWER_SCART			(1 << 4)
261#define CH7006_POWER_RESET			(1 << 3)
262#define CH7006_POWER_LEVEL			0, 2:0
263#define CH7006_POWER_LEVEL_CVBS_OFF		0x0
264#define CH7006_POWER_LEVEL_POWER_OFF		0x1
265#define CH7006_POWER_LEVEL_SVIDEO_OFF		0x2
266#define CH7006_POWER_LEVEL_NORMAL		0x3
267#define CH7006_POWER_LEVEL_FULL_POWER_OFF	0x4
268
269#define CH7006_DETECT				0x10
270#define CH7006_DETECT_SVIDEO_Y_TEST		(1 << 3)
271#define CH7006_DETECT_SVIDEO_C_TEST		(1 << 2)
272#define CH7006_DETECT_CVBS_TEST			(1 << 1)
273#define CH7006_DETECT_SENSE			(1 << 0)
274
275#define CH7006_CONTRAST				0x11
276#define CH7006_CONTRAST_0			0, 2:0
277
278#define CH7006_PLLOV	 			0x13
279#define CH7006_PLLOV_N_8	 		8, 2:1
280#define CH7006_PLLOV_M_8	 		8, 0:0
281
282#define CH7006_PLLM	 			0x14
283#define CH7006_PLLM_0	 			0, 7:0
284
285#define CH7006_PLLN	 			0x15
286#define CH7006_PLLN_0	 			0, 7:0
287
288#define CH7006_BCLKOUT	 			0x17
289
290#define CH7006_SUBC_INC0			0x18
291#define CH7006_SUBC_INC0_28			28, 3:0
292
293#define CH7006_SUBC_INC1			0x19
294#define CH7006_SUBC_INC1_24			24, 3:0
295
296#define CH7006_SUBC_INC2			0x1a
297#define CH7006_SUBC_INC2_20			20, 3:0
298
299#define CH7006_SUBC_INC3			0x1b
300#define CH7006_SUBC_INC3_GPIO1_VAL		(1 << 7)
301#define CH7006_SUBC_INC3_GPIO0_VAL		(1 << 6)
302#define CH7006_SUBC_INC3_POUT_3_3V		(1 << 5)
303#define CH7006_SUBC_INC3_POUT_INV		(1 << 4)
304#define CH7006_SUBC_INC3_16			16, 3:0
305
306#define CH7006_SUBC_INC4			0x1c
307#define CH7006_SUBC_INC4_GPIO1_IN		(1 << 7)
308#define CH7006_SUBC_INC4_GPIO0_IN		(1 << 6)
309#define CH7006_SUBC_INC4_DS_INPUT		(1 << 4)
310#define CH7006_SUBC_INC4_12			12, 3:0
311
312#define CH7006_SUBC_INC5			0x1d
313#define CH7006_SUBC_INC5_8			8, 3:0
314
315#define CH7006_SUBC_INC6			0x1e
316#define CH7006_SUBC_INC6_4			4, 3:0
317
318#define CH7006_SUBC_INC7			0x1f
319#define CH7006_SUBC_INC7_0			0, 3:0
320
321#define CH7006_PLL_CONTROL			0x20
322#define CH7006_PLL_CONTROL_CPI			(1 << 5)
323#define CH7006_PLL_CONTROL_CAPACITOR		(1 << 4)
324#define CH7006_PLL_CONTROL_7STAGES		(1 << 3)
325#define CH7006_PLL_CONTROL_DIGITAL_5V		(1 << 2)
326#define CH7006_PLL_CONTROL_ANALOG_5V		(1 << 1)
327#define CH7006_PLL_CONTROL_MEMORY_5V		(1 << 0)
328
329#define CH7006_CALC_SUBC_INC0			0x21
330#define CH7006_CALC_SUBC_INC0_24		24, 4:3
331#define CH7006_CALC_SUBC_INC0_HYST		0, 2:1
332#define CH7006_CALC_SUBC_INC0_AUTO		(1 << 0)
333
334#define CH7006_CALC_SUBC_INC1			0x22
335#define CH7006_CALC_SUBC_INC1_16		16, 7:0
336
337#define CH7006_CALC_SUBC_INC2			0x23
338#define CH7006_CALC_SUBC_INC2_8			8, 7:0
339
340#define CH7006_CALC_SUBC_INC3			0x24
341#define CH7006_CALC_SUBC_INC3_0			0, 7:0
342
343#define CH7006_VERSION_ID			0x25
344
345#endif
346