1/*
2 * Copyright (C) 2013 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include <linux/clk.h>
10#include <linux/cpu.h>
11#include <linux/cpufreq.h>
12#include <linux/err.h>
13#include <linux/module.h>
14#include <linux/of.h>
15#include <linux/pm_opp.h>
16#include <linux/platform_device.h>
17#include <linux/regulator/consumer.h>
18
19#define PU_SOC_VOLTAGE_NORMAL	1250000
20#define PU_SOC_VOLTAGE_HIGH	1275000
21#define FREQ_1P2_GHZ		1200000000
22
23static struct regulator *arm_reg;
24static struct regulator *pu_reg;
25static struct regulator *soc_reg;
26
27static struct clk *arm_clk;
28static struct clk *pll1_sys_clk;
29static struct clk *pll1_sw_clk;
30static struct clk *step_clk;
31static struct clk *pll2_pfd2_396m_clk;
32
33static struct device *cpu_dev;
34static bool free_opp;
35static struct cpufreq_frequency_table *freq_table;
36static unsigned int transition_latency;
37
38static u32 *imx6_soc_volt;
39static u32 soc_opp_count;
40
41static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
42{
43	struct dev_pm_opp *opp;
44	unsigned long freq_hz, volt, volt_old;
45	unsigned int old_freq, new_freq;
46	int ret;
47
48	new_freq = freq_table[index].frequency;
49	freq_hz = new_freq * 1000;
50	old_freq = clk_get_rate(arm_clk) / 1000;
51
52	rcu_read_lock();
53	opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz);
54	if (IS_ERR(opp)) {
55		rcu_read_unlock();
56		dev_err(cpu_dev, "failed to find OPP for %ld\n", freq_hz);
57		return PTR_ERR(opp);
58	}
59
60	volt = dev_pm_opp_get_voltage(opp);
61	rcu_read_unlock();
62	volt_old = regulator_get_voltage(arm_reg);
63
64	dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n",
65		old_freq / 1000, volt_old / 1000,
66		new_freq / 1000, volt / 1000);
67
68	/* scaling up?  scale voltage before frequency */
69	if (new_freq > old_freq) {
70		if (!IS_ERR(pu_reg)) {
71			ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0);
72			if (ret) {
73				dev_err(cpu_dev, "failed to scale vddpu up: %d\n", ret);
74				return ret;
75			}
76		}
77		ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0);
78		if (ret) {
79			dev_err(cpu_dev, "failed to scale vddsoc up: %d\n", ret);
80			return ret;
81		}
82		ret = regulator_set_voltage_tol(arm_reg, volt, 0);
83		if (ret) {
84			dev_err(cpu_dev,
85				"failed to scale vddarm up: %d\n", ret);
86			return ret;
87		}
88	}
89
90	/*
91	 * The setpoints are selected per PLL/PDF frequencies, so we need to
92	 * reprogram PLL for frequency scaling.  The procedure of reprogramming
93	 * PLL1 is as below.
94	 *
95	 *  - Enable pll2_pfd2_396m_clk and reparent pll1_sw_clk to it
96	 *  - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it
97	 *  - Disable pll2_pfd2_396m_clk
98	 */
99	clk_set_parent(step_clk, pll2_pfd2_396m_clk);
100	clk_set_parent(pll1_sw_clk, step_clk);
101	if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk)) {
102		clk_set_rate(pll1_sys_clk, new_freq * 1000);
103		clk_set_parent(pll1_sw_clk, pll1_sys_clk);
104	}
105
106	/* Ensure the arm clock divider is what we expect */
107	ret = clk_set_rate(arm_clk, new_freq * 1000);
108	if (ret) {
109		dev_err(cpu_dev, "failed to set clock rate: %d\n", ret);
110		regulator_set_voltage_tol(arm_reg, volt_old, 0);
111		return ret;
112	}
113
114	/* scaling down?  scale voltage after frequency */
115	if (new_freq < old_freq) {
116		ret = regulator_set_voltage_tol(arm_reg, volt, 0);
117		if (ret) {
118			dev_warn(cpu_dev,
119				 "failed to scale vddarm down: %d\n", ret);
120			ret = 0;
121		}
122		ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0);
123		if (ret) {
124			dev_warn(cpu_dev, "failed to scale vddsoc down: %d\n", ret);
125			ret = 0;
126		}
127		if (!IS_ERR(pu_reg)) {
128			ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0);
129			if (ret) {
130				dev_warn(cpu_dev, "failed to scale vddpu down: %d\n", ret);
131				ret = 0;
132			}
133		}
134	}
135
136	return 0;
137}
138
139static int imx6q_cpufreq_init(struct cpufreq_policy *policy)
140{
141	policy->clk = arm_clk;
142	return cpufreq_generic_init(policy, freq_table, transition_latency);
143}
144
145static struct cpufreq_driver imx6q_cpufreq_driver = {
146	.flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK,
147	.verify = cpufreq_generic_frequency_table_verify,
148	.target_index = imx6q_set_target,
149	.get = cpufreq_generic_get,
150	.init = imx6q_cpufreq_init,
151	.name = "imx6q-cpufreq",
152	.attr = cpufreq_generic_attr,
153};
154
155static int imx6q_cpufreq_probe(struct platform_device *pdev)
156{
157	struct device_node *np;
158	struct dev_pm_opp *opp;
159	unsigned long min_volt, max_volt;
160	int num, ret;
161	const struct property *prop;
162	const __be32 *val;
163	u32 nr, i, j;
164
165	cpu_dev = get_cpu_device(0);
166	if (!cpu_dev) {
167		pr_err("failed to get cpu0 device\n");
168		return -ENODEV;
169	}
170
171	np = of_node_get(cpu_dev->of_node);
172	if (!np) {
173		dev_err(cpu_dev, "failed to find cpu0 node\n");
174		return -ENOENT;
175	}
176
177	arm_clk = clk_get(cpu_dev, "arm");
178	pll1_sys_clk = clk_get(cpu_dev, "pll1_sys");
179	pll1_sw_clk = clk_get(cpu_dev, "pll1_sw");
180	step_clk = clk_get(cpu_dev, "step");
181	pll2_pfd2_396m_clk = clk_get(cpu_dev, "pll2_pfd2_396m");
182	if (IS_ERR(arm_clk) || IS_ERR(pll1_sys_clk) || IS_ERR(pll1_sw_clk) ||
183	    IS_ERR(step_clk) || IS_ERR(pll2_pfd2_396m_clk)) {
184		dev_err(cpu_dev, "failed to get clocks\n");
185		ret = -ENOENT;
186		goto put_clk;
187	}
188
189	arm_reg = regulator_get(cpu_dev, "arm");
190	pu_reg = regulator_get_optional(cpu_dev, "pu");
191	soc_reg = regulator_get(cpu_dev, "soc");
192	if (IS_ERR(arm_reg) || IS_ERR(soc_reg)) {
193		dev_err(cpu_dev, "failed to get regulators\n");
194		ret = -ENOENT;
195		goto put_reg;
196	}
197
198	/*
199	 * We expect an OPP table supplied by platform.
200	 * Just, incase the platform did not supply the OPP
201	 * table, it will try to get it.
202	 */
203	num = dev_pm_opp_get_opp_count(cpu_dev);
204	if (num < 0) {
205		ret = of_init_opp_table(cpu_dev);
206		if (ret < 0) {
207			dev_err(cpu_dev, "failed to init OPP table: %d\n", ret);
208			goto put_reg;
209		}
210
211		/* Because we have added the OPPs here, we must free them */
212		free_opp = true;
213
214		num = dev_pm_opp_get_opp_count(cpu_dev);
215		if (num < 0) {
216			ret = num;
217			dev_err(cpu_dev, "no OPP table is found: %d\n", ret);
218			goto out_free_opp;
219		}
220	}
221
222	ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table);
223	if (ret) {
224		dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret);
225		goto put_reg;
226	}
227
228	/* Make imx6_soc_volt array's size same as arm opp number */
229	imx6_soc_volt = devm_kzalloc(cpu_dev, sizeof(*imx6_soc_volt) * num, GFP_KERNEL);
230	if (imx6_soc_volt == NULL) {
231		ret = -ENOMEM;
232		goto free_freq_table;
233	}
234
235	prop = of_find_property(np, "fsl,soc-operating-points", NULL);
236	if (!prop || !prop->value)
237		goto soc_opp_out;
238
239	/*
240	 * Each OPP is a set of tuples consisting of frequency and
241	 * voltage like <freq-kHz vol-uV>.
242	 */
243	nr = prop->length / sizeof(u32);
244	if (nr % 2 || (nr / 2) < num)
245		goto soc_opp_out;
246
247	for (j = 0; j < num; j++) {
248		val = prop->value;
249		for (i = 0; i < nr / 2; i++) {
250			unsigned long freq = be32_to_cpup(val++);
251			unsigned long volt = be32_to_cpup(val++);
252			if (freq_table[j].frequency == freq) {
253				imx6_soc_volt[soc_opp_count++] = volt;
254				break;
255			}
256		}
257	}
258
259soc_opp_out:
260	/* use fixed soc opp volt if no valid soc opp info found in dtb */
261	if (soc_opp_count != num) {
262		dev_warn(cpu_dev, "can NOT find valid fsl,soc-operating-points property in dtb, use default value!\n");
263		for (j = 0; j < num; j++)
264			imx6_soc_volt[j] = PU_SOC_VOLTAGE_NORMAL;
265		if (freq_table[num - 1].frequency * 1000 == FREQ_1P2_GHZ)
266			imx6_soc_volt[num - 1] = PU_SOC_VOLTAGE_HIGH;
267	}
268
269	if (of_property_read_u32(np, "clock-latency", &transition_latency))
270		transition_latency = CPUFREQ_ETERNAL;
271
272	/*
273	 * Calculate the ramp time for max voltage change in the
274	 * VDDSOC and VDDPU regulators.
275	 */
276	ret = regulator_set_voltage_time(soc_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]);
277	if (ret > 0)
278		transition_latency += ret * 1000;
279	if (!IS_ERR(pu_reg)) {
280		ret = regulator_set_voltage_time(pu_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]);
281		if (ret > 0)
282			transition_latency += ret * 1000;
283	}
284
285	/*
286	 * OPP is maintained in order of increasing frequency, and
287	 * freq_table initialised from OPP is therefore sorted in the
288	 * same order.
289	 */
290	rcu_read_lock();
291	opp = dev_pm_opp_find_freq_exact(cpu_dev,
292				  freq_table[0].frequency * 1000, true);
293	min_volt = dev_pm_opp_get_voltage(opp);
294	opp = dev_pm_opp_find_freq_exact(cpu_dev,
295				  freq_table[--num].frequency * 1000, true);
296	max_volt = dev_pm_opp_get_voltage(opp);
297	rcu_read_unlock();
298	ret = regulator_set_voltage_time(arm_reg, min_volt, max_volt);
299	if (ret > 0)
300		transition_latency += ret * 1000;
301
302	ret = cpufreq_register_driver(&imx6q_cpufreq_driver);
303	if (ret) {
304		dev_err(cpu_dev, "failed register driver: %d\n", ret);
305		goto free_freq_table;
306	}
307
308	of_node_put(np);
309	return 0;
310
311free_freq_table:
312	dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
313out_free_opp:
314	if (free_opp)
315		of_free_opp_table(cpu_dev);
316put_reg:
317	if (!IS_ERR(arm_reg))
318		regulator_put(arm_reg);
319	if (!IS_ERR(pu_reg))
320		regulator_put(pu_reg);
321	if (!IS_ERR(soc_reg))
322		regulator_put(soc_reg);
323put_clk:
324	if (!IS_ERR(arm_clk))
325		clk_put(arm_clk);
326	if (!IS_ERR(pll1_sys_clk))
327		clk_put(pll1_sys_clk);
328	if (!IS_ERR(pll1_sw_clk))
329		clk_put(pll1_sw_clk);
330	if (!IS_ERR(step_clk))
331		clk_put(step_clk);
332	if (!IS_ERR(pll2_pfd2_396m_clk))
333		clk_put(pll2_pfd2_396m_clk);
334	of_node_put(np);
335	return ret;
336}
337
338static int imx6q_cpufreq_remove(struct platform_device *pdev)
339{
340	cpufreq_unregister_driver(&imx6q_cpufreq_driver);
341	dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
342	if (free_opp)
343		of_free_opp_table(cpu_dev);
344	regulator_put(arm_reg);
345	if (!IS_ERR(pu_reg))
346		regulator_put(pu_reg);
347	regulator_put(soc_reg);
348	clk_put(arm_clk);
349	clk_put(pll1_sys_clk);
350	clk_put(pll1_sw_clk);
351	clk_put(step_clk);
352	clk_put(pll2_pfd2_396m_clk);
353
354	return 0;
355}
356
357static struct platform_driver imx6q_cpufreq_platdrv = {
358	.driver = {
359		.name	= "imx6q-cpufreq",
360	},
361	.probe		= imx6q_cpufreq_probe,
362	.remove		= imx6q_cpufreq_remove,
363};
364module_platform_driver(imx6q_cpufreq_platdrv);
365
366MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
367MODULE_DESCRIPTION("Freescale i.MX6Q cpufreq driver");
368MODULE_LICENSE("GPL");
369