1/* 2 * AM43XX Clock init 3 * 4 * Copyright (C) 2013 Texas Instruments, Inc 5 * Tero Kristo (t-kristo@ti.com) 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation version 2. 10 * 11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 12 * kind, whether express or implied; without even the implied warranty 13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 */ 16 17#include <linux/kernel.h> 18#include <linux/list.h> 19#include <linux/clk-provider.h> 20#include <linux/clk/ti.h> 21 22static struct ti_dt_clk am43xx_clks[] = { 23 DT_CLK(NULL, "clk_32768_ck", "clk_32768_ck"), 24 DT_CLK(NULL, "clk_rc32k_ck", "clk_rc32k_ck"), 25 DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"), 26 DT_CLK(NULL, "virt_24000000_ck", "virt_24000000_ck"), 27 DT_CLK(NULL, "virt_25000000_ck", "virt_25000000_ck"), 28 DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"), 29 DT_CLK(NULL, "sys_clkin_ck", "sys_clkin_ck"), 30 DT_CLK(NULL, "tclkin_ck", "tclkin_ck"), 31 DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"), 32 DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"), 33 DT_CLK(NULL, "dpll_core_m4_ck", "dpll_core_m4_ck"), 34 DT_CLK(NULL, "dpll_core_m5_ck", "dpll_core_m5_ck"), 35 DT_CLK(NULL, "dpll_core_m6_ck", "dpll_core_m6_ck"), 36 DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"), 37 DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"), 38 DT_CLK(NULL, "dpll_ddr_ck", "dpll_ddr_ck"), 39 DT_CLK(NULL, "dpll_ddr_m2_ck", "dpll_ddr_m2_ck"), 40 DT_CLK(NULL, "dpll_disp_ck", "dpll_disp_ck"), 41 DT_CLK(NULL, "dpll_disp_m2_ck", "dpll_disp_m2_ck"), 42 DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"), 43 DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"), 44 DT_CLK(NULL, "dpll_per_m2_div4_wkupdm_ck", "dpll_per_m2_div4_wkupdm_ck"), 45 DT_CLK(NULL, "dpll_per_m2_div4_ck", "dpll_per_m2_div4_ck"), 46 DT_CLK(NULL, "adc_tsc_fck", "adc_tsc_fck"), 47 DT_CLK(NULL, "clkdiv32k_ck", "clkdiv32k_ck"), 48 DT_CLK(NULL, "clkdiv32k_ick", "clkdiv32k_ick"), 49 DT_CLK(NULL, "dcan0_fck", "dcan0_fck"), 50 DT_CLK(NULL, "dcan1_fck", "dcan1_fck"), 51 DT_CLK(NULL, "pruss_ocp_gclk", "pruss_ocp_gclk"), 52 DT_CLK(NULL, "mcasp0_fck", "mcasp0_fck"), 53 DT_CLK(NULL, "mcasp1_fck", "mcasp1_fck"), 54 DT_CLK(NULL, "smartreflex0_fck", "smartreflex0_fck"), 55 DT_CLK(NULL, "smartreflex1_fck", "smartreflex1_fck"), 56 DT_CLK(NULL, "sha0_fck", "sha0_fck"), 57 DT_CLK(NULL, "aes0_fck", "aes0_fck"), 58 DT_CLK(NULL, "timer1_fck", "timer1_fck"), 59 DT_CLK(NULL, "timer2_fck", "timer2_fck"), 60 DT_CLK(NULL, "timer3_fck", "timer3_fck"), 61 DT_CLK(NULL, "timer4_fck", "timer4_fck"), 62 DT_CLK(NULL, "timer5_fck", "timer5_fck"), 63 DT_CLK(NULL, "timer6_fck", "timer6_fck"), 64 DT_CLK(NULL, "timer7_fck", "timer7_fck"), 65 DT_CLK(NULL, "wdt1_fck", "wdt1_fck"), 66 DT_CLK(NULL, "l3_gclk", "l3_gclk"), 67 DT_CLK(NULL, "dpll_core_m4_div2_ck", "dpll_core_m4_div2_ck"), 68 DT_CLK(NULL, "l4hs_gclk", "l4hs_gclk"), 69 DT_CLK(NULL, "l3s_gclk", "l3s_gclk"), 70 DT_CLK(NULL, "l4ls_gclk", "l4ls_gclk"), 71 DT_CLK(NULL, "clk_24mhz", "clk_24mhz"), 72 DT_CLK(NULL, "cpsw_125mhz_gclk", "cpsw_125mhz_gclk"), 73 DT_CLK(NULL, "cpsw_cpts_rft_clk", "cpsw_cpts_rft_clk"), 74 DT_CLK(NULL, "gpio0_dbclk_mux_ck", "gpio0_dbclk_mux_ck"), 75 DT_CLK(NULL, "gpio0_dbclk", "gpio0_dbclk"), 76 DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"), 77 DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"), 78 DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"), 79 DT_CLK(NULL, "gpio4_dbclk", "gpio4_dbclk"), 80 DT_CLK(NULL, "gpio5_dbclk", "gpio5_dbclk"), 81 DT_CLK(NULL, "mmc_clk", "mmc_clk"), 82 DT_CLK(NULL, "gfx_fclk_clksel_ck", "gfx_fclk_clksel_ck"), 83 DT_CLK(NULL, "gfx_fck_div_ck", "gfx_fck_div_ck"), 84 DT_CLK(NULL, "timer_32k_ck", "clkdiv32k_ick"), 85 DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"), 86 DT_CLK(NULL, "sysclk_div", "sysclk_div"), 87 DT_CLK(NULL, "disp_clk", "disp_clk"), 88 DT_CLK(NULL, "clk_32k_mosc_ck", "clk_32k_mosc_ck"), 89 DT_CLK(NULL, "clk_32k_tpm_ck", "clk_32k_tpm_ck"), 90 DT_CLK(NULL, "dpll_extdev_ck", "dpll_extdev_ck"), 91 DT_CLK(NULL, "dpll_extdev_m2_ck", "dpll_extdev_m2_ck"), 92 DT_CLK(NULL, "mux_synctimer32k_ck", "mux_synctimer32k_ck"), 93 DT_CLK(NULL, "synctimer_32kclk", "synctimer_32kclk"), 94 DT_CLK(NULL, "timer8_fck", "timer8_fck"), 95 DT_CLK(NULL, "timer9_fck", "timer9_fck"), 96 DT_CLK(NULL, "timer10_fck", "timer10_fck"), 97 DT_CLK(NULL, "timer11_fck", "timer11_fck"), 98 DT_CLK(NULL, "cpsw_50m_clkdiv", "cpsw_50m_clkdiv"), 99 DT_CLK(NULL, "cpsw_5m_clkdiv", "cpsw_5m_clkdiv"), 100 DT_CLK(NULL, "dpll_ddr_x2_ck", "dpll_ddr_x2_ck"), 101 DT_CLK(NULL, "dpll_ddr_m4_ck", "dpll_ddr_m4_ck"), 102 DT_CLK(NULL, "dpll_per_clkdcoldo", "dpll_per_clkdcoldo"), 103 DT_CLK(NULL, "dll_aging_clk_div", "dll_aging_clk_div"), 104 DT_CLK(NULL, "div_core_25m_ck", "div_core_25m_ck"), 105 DT_CLK(NULL, "func_12m_clk", "func_12m_clk"), 106 DT_CLK(NULL, "vtp_clk_div", "vtp_clk_div"), 107 DT_CLK(NULL, "usbphy_32khz_clkmux", "usbphy_32khz_clkmux"), 108 DT_CLK("48300200.ehrpwm", "tbclk", "ehrpwm0_tbclk"), 109 DT_CLK("48302200.ehrpwm", "tbclk", "ehrpwm1_tbclk"), 110 DT_CLK("48304200.ehrpwm", "tbclk", "ehrpwm2_tbclk"), 111 DT_CLK("48306200.ehrpwm", "tbclk", "ehrpwm3_tbclk"), 112 DT_CLK("48308200.ehrpwm", "tbclk", "ehrpwm4_tbclk"), 113 DT_CLK("4830a200.ehrpwm", "tbclk", "ehrpwm5_tbclk"), 114 { .node_name = NULL }, 115}; 116 117int __init am43xx_dt_clk_init(void) 118{ 119 struct clk *clk1, *clk2; 120 121 ti_dt_clocks_register(am43xx_clks); 122 123 omap2_clk_disable_autoidle_all(); 124 125 /* 126 * cpsw_cpts_rft_clk has got the choice of 3 clocksources 127 * dpll_core_m4_ck, dpll_core_m5_ck and dpll_disp_m2_ck. 128 * By default dpll_core_m4_ck is selected, witn this as clock 129 * source the CPTS doesnot work properly. It gives clockcheck errors 130 * while running PTP. 131 * clockcheck: clock jumped backward or running slower than expected! 132 * By selecting dpll_core_m5_ck as the clocksource fixes this issue. 133 * In AM335x dpll_core_m5_ck is the default clocksource. 134 */ 135 clk1 = clk_get_sys(NULL, "cpsw_cpts_rft_clk"); 136 clk2 = clk_get_sys(NULL, "dpll_core_m5_ck"); 137 clk_set_parent(clk1, clk2); 138 139 return 0; 140} 141