1/*
2 * Copyright (c) 2012, 2013, NVIDIA CORPORATION.  All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <linux/io.h>
18#include <linux/clk.h>
19#include <linux/clk-provider.h>
20#include <linux/clkdev.h>
21#include <linux/of.h>
22#include <linux/of_address.h>
23#include <linux/delay.h>
24#include <linux/export.h>
25#include <linux/clk/tegra.h>
26
27#include "clk.h"
28#include "clk-id.h"
29
30#define PMC_CLK_OUT_CNTRL 0x1a8
31#define PMC_DPD_PADS_ORIDE 0x1c
32#define PMC_DPD_PADS_ORIDE_BLINK_ENB 20
33#define PMC_CTRL 0
34#define PMC_CTRL_BLINK_ENB 7
35#define PMC_BLINK_TIMER 0x40
36
37struct pmc_clk_init_data {
38	char *mux_name;
39	char *gate_name;
40	const char **parents;
41	int num_parents;
42	int mux_id;
43	int gate_id;
44	char *dev_name;
45	u8 mux_shift;
46	u8 gate_shift;
47};
48
49#define PMC_CLK(_num, _mux_shift, _gate_shift)\
50	{\
51		.mux_name = "clk_out_" #_num "_mux",\
52		.gate_name = "clk_out_" #_num,\
53		.parents = clk_out ##_num ##_parents,\
54		.num_parents = ARRAY_SIZE(clk_out ##_num ##_parents),\
55		.mux_id = tegra_clk_clk_out_ ##_num ##_mux,\
56		.gate_id = tegra_clk_clk_out_ ##_num,\
57		.dev_name = "extern" #_num,\
58		.mux_shift = _mux_shift,\
59		.gate_shift = _gate_shift,\
60	}
61
62static DEFINE_SPINLOCK(clk_out_lock);
63
64static const char *clk_out1_parents[] = { "clk_m", "clk_m_div2",
65	"clk_m_div4", "extern1",
66};
67
68static const char *clk_out2_parents[] = { "clk_m", "clk_m_div2",
69	"clk_m_div4", "extern2",
70};
71
72static const char *clk_out3_parents[] = { "clk_m", "clk_m_div2",
73	"clk_m_div4", "extern3",
74};
75
76static struct pmc_clk_init_data pmc_clks[] = {
77	PMC_CLK(1, 6, 2),
78	PMC_CLK(2, 14, 10),
79	PMC_CLK(3, 22, 18),
80};
81
82void __init tegra_pmc_clk_init(void __iomem *pmc_base,
83				struct tegra_clk *tegra_clks)
84{
85	struct clk *clk;
86	struct clk **dt_clk;
87	int i;
88
89	for (i = 0; i < ARRAY_SIZE(pmc_clks); i++) {
90		struct pmc_clk_init_data *data;
91
92		data = pmc_clks + i;
93
94		dt_clk = tegra_lookup_dt_id(data->mux_id, tegra_clks);
95		if (!dt_clk)
96			continue;
97
98		clk = clk_register_mux(NULL, data->mux_name, data->parents,
99				data->num_parents, CLK_SET_RATE_NO_REPARENT,
100				pmc_base + PMC_CLK_OUT_CNTRL, data->mux_shift,
101				3, 0, &clk_out_lock);
102		*dt_clk = clk;
103
104
105		dt_clk = tegra_lookup_dt_id(data->gate_id, tegra_clks);
106		if (!dt_clk)
107			continue;
108
109		clk = clk_register_gate(NULL, data->gate_name, data->mux_name,
110					0, pmc_base + PMC_CLK_OUT_CNTRL,
111					data->gate_shift, 0, &clk_out_lock);
112		*dt_clk = clk;
113		clk_register_clkdev(clk, data->dev_name, data->gate_name);
114	}
115
116	/* blink */
117	writel_relaxed(0, pmc_base + PMC_BLINK_TIMER);
118	clk = clk_register_gate(NULL, "blink_override", "clk_32k", 0,
119				pmc_base + PMC_DPD_PADS_ORIDE,
120				PMC_DPD_PADS_ORIDE_BLINK_ENB, 0, NULL);
121
122	dt_clk = tegra_lookup_dt_id(tegra_clk_blink, tegra_clks);
123	if (!dt_clk)
124		return;
125
126	clk = clk_register_gate(NULL, "blink", "blink_override", 0,
127				pmc_base + PMC_CTRL,
128				PMC_CTRL_BLINK_ENB, 0, NULL);
129	clk_register_clkdev(clk, "blink", NULL);
130	*dt_clk = clk;
131}
132
133