1/*
2 * Copyright 2013 Emilio López
3 * Emilio López <emilio@elopez.com.ar>
4 *
5 * Copyright 2013 Chen-Yu Tsai
6 * Chen-Yu Tsai <wens@csie.org>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16 * GNU General Public License for more details.
17 */
18
19#include <linux/clk-provider.h>
20#include <linux/clkdev.h>
21#include <linux/of.h>
22#include <linux/of_address.h>
23#include <linux/slab.h>
24
25static DEFINE_SPINLOCK(gmac_lock);
26
27/**
28 * sun7i_a20_gmac_clk_setup - Setup function for A20/A31 GMAC clock module
29 *
30 * This clock looks something like this
31 *                               ________________________
32 *  MII TX clock from PHY >-----|___________    _________|----> to GMAC core
33 *  GMAC Int. RGMII TX clk >----|___________\__/__gate---|----> to PHY
34 *  Ext. 125MHz RGMII TX clk >--|__divider__/            |
35 *                              |________________________|
36 *
37 * The external 125 MHz reference is optional, i.e. GMAC can use its
38 * internal TX clock just fine. The A31 GMAC clock module does not have
39 * the divider controls for the external reference.
40 *
41 * To keep it simple, let the GMAC use either the MII TX clock for MII mode,
42 * and its internal TX clock for GMII and RGMII modes. The GMAC driver should
43 * select the appropriate source and gate/ungate the output to the PHY.
44 *
45 * Only the GMAC should use this clock. Altering the clock so that it doesn't
46 * match the GMAC's operation parameters will result in the GMAC not being
47 * able to send traffic out. The GMAC driver should set the clock rate and
48 * enable/disable this clock to configure the required state. The clock
49 * driver then responds by auto-reparenting the clock.
50 */
51
52#define SUN7I_A20_GMAC_GPIT	2
53#define SUN7I_A20_GMAC_MASK	0x3
54#define SUN7I_A20_GMAC_PARENTS	2
55
56static u32 sun7i_a20_gmac_mux_table[SUN7I_A20_GMAC_PARENTS] = {
57	0x00, /* Select mii_phy_tx_clk */
58	0x02, /* Select gmac_int_tx_clk */
59};
60
61static void __init sun7i_a20_gmac_clk_setup(struct device_node *node)
62{
63	struct clk *clk;
64	struct clk_mux *mux;
65	struct clk_gate *gate;
66	const char *clk_name = node->name;
67	const char *parents[SUN7I_A20_GMAC_PARENTS];
68	void __iomem *reg;
69
70	if (of_property_read_string(node, "clock-output-names", &clk_name))
71		return;
72
73	/* allocate mux and gate clock structs */
74	mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL);
75	if (!mux)
76		return;
77
78	gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
79	if (!gate)
80		goto free_mux;
81
82	/* gmac clock requires exactly 2 parents */
83	parents[0] = of_clk_get_parent_name(node, 0);
84	parents[1] = of_clk_get_parent_name(node, 1);
85	if (!parents[0] || !parents[1])
86		goto free_gate;
87
88	reg = of_iomap(node, 0);
89	if (!reg)
90		goto free_gate;
91
92	/* set up gate and fixed rate properties */
93	gate->reg = reg;
94	gate->bit_idx = SUN7I_A20_GMAC_GPIT;
95	gate->lock = &gmac_lock;
96	mux->reg = reg;
97	mux->mask = SUN7I_A20_GMAC_MASK;
98	mux->table = sun7i_a20_gmac_mux_table;
99	mux->lock = &gmac_lock;
100
101	clk = clk_register_composite(NULL, clk_name,
102			parents, SUN7I_A20_GMAC_PARENTS,
103			&mux->hw, &clk_mux_ops,
104			NULL, NULL,
105			&gate->hw, &clk_gate_ops,
106			0);
107
108	if (IS_ERR(clk))
109		goto iounmap_reg;
110
111	of_clk_add_provider(node, of_clk_src_simple_get, clk);
112	clk_register_clkdev(clk, clk_name, NULL);
113
114	return;
115
116iounmap_reg:
117	iounmap(reg);
118free_gate:
119	kfree(gate);
120free_mux:
121	kfree(mux);
122}
123CLK_OF_DECLARE(sun7i_a20_gmac, "allwinner,sun7i-a20-gmac-clk",
124		sun7i_a20_gmac_clk_setup);
125