1/*
2 * Hisilicon Hi3620 clock gate driver
3 *
4 * Copyright (c) 2012-2013 Hisilicon Limited.
5 * Copyright (c) 2012-2013 Linaro Limited.
6 *
7 * Author: Haojian Zhuang <haojian.zhuang@linaro.org>
8 *	   Xin Li <li.xin@linaro.org>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, write to the Free Software Foundation, Inc.,
22 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
23 *
24 */
25
26#ifndef	__HISI_CLK_H
27#define	__HISI_CLK_H
28
29#include <linux/clk-provider.h>
30#include <linux/io.h>
31#include <linux/spinlock.h>
32
33struct hisi_clock_data {
34	struct clk_onecell_data	clk_data;
35	void __iomem		*base;
36};
37
38struct hisi_fixed_rate_clock {
39	unsigned int		id;
40	char			*name;
41	const char		*parent_name;
42	unsigned long		flags;
43	unsigned long		fixed_rate;
44};
45
46struct hisi_fixed_factor_clock {
47	unsigned int		id;
48	char			*name;
49	const char		*parent_name;
50	unsigned long		mult;
51	unsigned long		div;
52	unsigned long		flags;
53};
54
55struct hisi_mux_clock {
56	unsigned int		id;
57	const char		*name;
58	const char		**parent_names;
59	u8			num_parents;
60	unsigned long		flags;
61	unsigned long		offset;
62	u8			shift;
63	u8			width;
64	u8			mux_flags;
65	u32			*table;
66	const char		*alias;
67};
68
69struct hisi_divider_clock {
70	unsigned int		id;
71	const char		*name;
72	const char		*parent_name;
73	unsigned long		flags;
74	unsigned long		offset;
75	u8			shift;
76	u8			width;
77	u8			div_flags;
78	struct clk_div_table	*table;
79	const char		*alias;
80};
81
82struct hisi_gate_clock {
83	unsigned int		id;
84	const char		*name;
85	const char		*parent_name;
86	unsigned long		flags;
87	unsigned long		offset;
88	u8			bit_idx;
89	u8			gate_flags;
90	const char		*alias;
91};
92
93struct clk *hisi_register_clkgate_sep(struct device *, const char *,
94				const char *, unsigned long,
95				void __iomem *, u8,
96				u8, spinlock_t *);
97
98struct hisi_clock_data __init *hisi_clk_init(struct device_node *, int);
99void __init hisi_clk_register_fixed_rate(struct hisi_fixed_rate_clock *,
100					int, struct hisi_clock_data *);
101void __init hisi_clk_register_fixed_factor(struct hisi_fixed_factor_clock *,
102					int, struct hisi_clock_data *);
103void __init hisi_clk_register_mux(struct hisi_mux_clock *, int,
104				struct hisi_clock_data *);
105void __init hisi_clk_register_divider(struct hisi_divider_clock *,
106				int, struct hisi_clock_data *);
107void __init hisi_clk_register_gate(struct hisi_gate_clock *,
108					int, struct hisi_clock_data *);
109void __init hisi_clk_register_gate_sep(struct hisi_gate_clock *,
110					int, struct hisi_clock_data *);
111#endif	/* __HISI_CLK_H */
112