1/* 2 * ahci.c - AHCI SATA support 3 * 4 * Maintained by: Tejun Heo <tj@kernel.org> 5 * Please ALWAYS copy linux-ide@vger.kernel.org 6 * on emails. 7 * 8 * Copyright 2004-2005 Red Hat, Inc. 9 * 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2, or (at your option) 14 * any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; see the file COPYING. If not, write to 23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 24 * 25 * 26 * libata documentation is available via 'make {ps|pdf}docs', 27 * as Documentation/DocBook/libata.* 28 * 29 * AHCI hardware documentation: 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf 32 * 33 */ 34 35#include <linux/kernel.h> 36#include <linux/module.h> 37#include <linux/pci.h> 38#include <linux/blkdev.h> 39#include <linux/delay.h> 40#include <linux/interrupt.h> 41#include <linux/dma-mapping.h> 42#include <linux/device.h> 43#include <linux/dmi.h> 44#include <linux/gfp.h> 45#include <scsi/scsi_host.h> 46#include <scsi/scsi_cmnd.h> 47#include <linux/libata.h> 48#include "ahci.h" 49 50#define DRV_NAME "ahci" 51#define DRV_VERSION "3.0" 52 53enum { 54 AHCI_PCI_BAR_STA2X11 = 0, 55 AHCI_PCI_BAR_ENMOTUS = 2, 56 AHCI_PCI_BAR_STANDARD = 5, 57}; 58 59enum board_ids { 60 /* board IDs by feature in alphabetical order */ 61 board_ahci, 62 board_ahci_ign_iferr, 63 board_ahci_nomsi, 64 board_ahci_noncq, 65 board_ahci_nosntf, 66 board_ahci_yes_fbs, 67 68 /* board IDs for specific chipsets in alphabetical order */ 69 board_ahci_avn, 70 board_ahci_mcp65, 71 board_ahci_mcp77, 72 board_ahci_mcp89, 73 board_ahci_mv, 74 board_ahci_sb600, 75 board_ahci_sb700, /* for SB700 and SB800 */ 76 board_ahci_vt8251, 77 78 /* aliases */ 79 board_ahci_mcp_linux = board_ahci_mcp65, 80 board_ahci_mcp67 = board_ahci_mcp65, 81 board_ahci_mcp73 = board_ahci_mcp65, 82 board_ahci_mcp79 = board_ahci_mcp77, 83}; 84 85static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); 86static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class, 87 unsigned long deadline); 88static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class, 89 unsigned long deadline); 90static void ahci_mcp89_apple_enable(struct pci_dev *pdev); 91static bool is_mcp89_apple(struct pci_dev *pdev); 92static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class, 93 unsigned long deadline); 94#ifdef CONFIG_PM 95static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg); 96static int ahci_pci_device_resume(struct pci_dev *pdev); 97#endif 98 99static struct scsi_host_template ahci_sht = { 100 AHCI_SHT("ahci"), 101}; 102 103static struct ata_port_operations ahci_vt8251_ops = { 104 .inherits = &ahci_ops, 105 .hardreset = ahci_vt8251_hardreset, 106}; 107 108static struct ata_port_operations ahci_p5wdh_ops = { 109 .inherits = &ahci_ops, 110 .hardreset = ahci_p5wdh_hardreset, 111}; 112 113static struct ata_port_operations ahci_avn_ops = { 114 .inherits = &ahci_ops, 115 .hardreset = ahci_avn_hardreset, 116}; 117 118static const struct ata_port_info ahci_port_info[] = { 119 /* by features */ 120 [board_ahci] = { 121 .flags = AHCI_FLAG_COMMON, 122 .pio_mask = ATA_PIO4, 123 .udma_mask = ATA_UDMA6, 124 .port_ops = &ahci_ops, 125 }, 126 [board_ahci_ign_iferr] = { 127 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR), 128 .flags = AHCI_FLAG_COMMON, 129 .pio_mask = ATA_PIO4, 130 .udma_mask = ATA_UDMA6, 131 .port_ops = &ahci_ops, 132 }, 133 [board_ahci_nomsi] = { 134 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI), 135 .flags = AHCI_FLAG_COMMON, 136 .pio_mask = ATA_PIO4, 137 .udma_mask = ATA_UDMA6, 138 .port_ops = &ahci_ops, 139 }, 140 [board_ahci_noncq] = { 141 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ), 142 .flags = AHCI_FLAG_COMMON, 143 .pio_mask = ATA_PIO4, 144 .udma_mask = ATA_UDMA6, 145 .port_ops = &ahci_ops, 146 }, 147 [board_ahci_nosntf] = { 148 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF), 149 .flags = AHCI_FLAG_COMMON, 150 .pio_mask = ATA_PIO4, 151 .udma_mask = ATA_UDMA6, 152 .port_ops = &ahci_ops, 153 }, 154 [board_ahci_yes_fbs] = { 155 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS), 156 .flags = AHCI_FLAG_COMMON, 157 .pio_mask = ATA_PIO4, 158 .udma_mask = ATA_UDMA6, 159 .port_ops = &ahci_ops, 160 }, 161 /* by chipsets */ 162 [board_ahci_avn] = { 163 .flags = AHCI_FLAG_COMMON, 164 .pio_mask = ATA_PIO4, 165 .udma_mask = ATA_UDMA6, 166 .port_ops = &ahci_avn_ops, 167 }, 168 [board_ahci_mcp65] = { 169 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP | 170 AHCI_HFLAG_YES_NCQ), 171 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM, 172 .pio_mask = ATA_PIO4, 173 .udma_mask = ATA_UDMA6, 174 .port_ops = &ahci_ops, 175 }, 176 [board_ahci_mcp77] = { 177 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP), 178 .flags = AHCI_FLAG_COMMON, 179 .pio_mask = ATA_PIO4, 180 .udma_mask = ATA_UDMA6, 181 .port_ops = &ahci_ops, 182 }, 183 [board_ahci_mcp89] = { 184 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA), 185 .flags = AHCI_FLAG_COMMON, 186 .pio_mask = ATA_PIO4, 187 .udma_mask = ATA_UDMA6, 188 .port_ops = &ahci_ops, 189 }, 190 [board_ahci_mv] = { 191 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI | 192 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP), 193 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA, 194 .pio_mask = ATA_PIO4, 195 .udma_mask = ATA_UDMA6, 196 .port_ops = &ahci_ops, 197 }, 198 [board_ahci_sb600] = { 199 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL | 200 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 | 201 AHCI_HFLAG_32BIT_ONLY), 202 .flags = AHCI_FLAG_COMMON, 203 .pio_mask = ATA_PIO4, 204 .udma_mask = ATA_UDMA6, 205 .port_ops = &ahci_pmp_retry_srst_ops, 206 }, 207 [board_ahci_sb700] = { /* for SB700 and SB800 */ 208 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL), 209 .flags = AHCI_FLAG_COMMON, 210 .pio_mask = ATA_PIO4, 211 .udma_mask = ATA_UDMA6, 212 .port_ops = &ahci_pmp_retry_srst_ops, 213 }, 214 [board_ahci_vt8251] = { 215 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP), 216 .flags = AHCI_FLAG_COMMON, 217 .pio_mask = ATA_PIO4, 218 .udma_mask = ATA_UDMA6, 219 .port_ops = &ahci_vt8251_ops, 220 }, 221}; 222 223static const struct pci_device_id ahci_pci_tbl[] = { 224 /* Intel */ 225 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */ 226 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */ 227 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */ 228 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */ 229 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */ 230 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */ 231 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */ 232 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */ 233 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */ 234 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */ 235 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */ 236 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */ 237 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */ 238 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */ 239 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */ 240 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */ 241 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */ 242 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */ 243 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */ 244 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */ 245 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */ 246 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */ 247 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */ 248 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */ 249 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */ 250 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */ 251 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */ 252 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */ 253 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */ 254 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */ 255 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */ 256 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */ 257 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */ 258 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */ 259 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */ 260 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */ 261 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */ 262 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */ 263 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */ 264 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */ 265 { PCI_VDEVICE(INTEL, 0x19b0), board_ahci }, /* DNV AHCI */ 266 { PCI_VDEVICE(INTEL, 0x19b1), board_ahci }, /* DNV AHCI */ 267 { PCI_VDEVICE(INTEL, 0x19b2), board_ahci }, /* DNV AHCI */ 268 { PCI_VDEVICE(INTEL, 0x19b3), board_ahci }, /* DNV AHCI */ 269 { PCI_VDEVICE(INTEL, 0x19b4), board_ahci }, /* DNV AHCI */ 270 { PCI_VDEVICE(INTEL, 0x19b5), board_ahci }, /* DNV AHCI */ 271 { PCI_VDEVICE(INTEL, 0x19b6), board_ahci }, /* DNV AHCI */ 272 { PCI_VDEVICE(INTEL, 0x19b7), board_ahci }, /* DNV AHCI */ 273 { PCI_VDEVICE(INTEL, 0x19bE), board_ahci }, /* DNV AHCI */ 274 { PCI_VDEVICE(INTEL, 0x19bF), board_ahci }, /* DNV AHCI */ 275 { PCI_VDEVICE(INTEL, 0x19c0), board_ahci }, /* DNV AHCI */ 276 { PCI_VDEVICE(INTEL, 0x19c1), board_ahci }, /* DNV AHCI */ 277 { PCI_VDEVICE(INTEL, 0x19c2), board_ahci }, /* DNV AHCI */ 278 { PCI_VDEVICE(INTEL, 0x19c3), board_ahci }, /* DNV AHCI */ 279 { PCI_VDEVICE(INTEL, 0x19c4), board_ahci }, /* DNV AHCI */ 280 { PCI_VDEVICE(INTEL, 0x19c5), board_ahci }, /* DNV AHCI */ 281 { PCI_VDEVICE(INTEL, 0x19c6), board_ahci }, /* DNV AHCI */ 282 { PCI_VDEVICE(INTEL, 0x19c7), board_ahci }, /* DNV AHCI */ 283 { PCI_VDEVICE(INTEL, 0x19cE), board_ahci }, /* DNV AHCI */ 284 { PCI_VDEVICE(INTEL, 0x19cF), board_ahci }, /* DNV AHCI */ 285 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */ 286 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */ 287 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */ 288 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */ 289 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */ 290 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */ 291 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */ 292 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */ 293 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */ 294 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */ 295 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */ 296 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */ 297 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */ 298 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */ 299 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */ 300 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */ 301 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */ 302 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */ 303 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */ 304 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */ 305 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */ 306 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */ 307 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */ 308 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */ 309 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */ 310 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */ 311 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */ 312 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */ 313 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */ 314 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */ 315 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */ 316 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */ 317 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */ 318 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */ 319 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */ 320 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */ 321 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */ 322 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */ 323 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */ 324 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */ 325 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */ 326 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */ 327 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */ 328 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */ 329 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */ 330 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */ 331 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */ 332 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */ 333 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */ 334 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */ 335 { PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/ 336 { PCI_VDEVICE(INTEL, 0xa202), board_ahci }, /* Lewisburg AHCI*/ 337 { PCI_VDEVICE(INTEL, 0xa184), board_ahci }, /* Lewisburg RAID*/ 338 { PCI_VDEVICE(INTEL, 0xa204), board_ahci }, /* Lewisburg RAID*/ 339 { PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/ 340 { PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/ 341 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* Lewisburg RAID*/ 342 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* Lewisburg RAID*/ 343 { PCI_VDEVICE(INTEL, 0xa18e), board_ahci }, /* Lewisburg RAID*/ 344 { PCI_VDEVICE(INTEL, 0xa20e), board_ahci }, /* Lewisburg RAID*/ 345 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */ 346 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */ 347 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */ 348 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */ 349 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */ 350 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */ 351 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */ 352 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */ 353 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */ 354 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */ 355 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */ 356 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci }, /* Wildcat Point-LP AHCI */ 357 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci }, /* Wildcat Point-LP RAID */ 358 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci }, /* Wildcat Point-LP RAID */ 359 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci }, /* Wildcat Point-LP RAID */ 360 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */ 361 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci }, /* 9 Series AHCI */ 362 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */ 363 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci }, /* 9 Series RAID */ 364 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */ 365 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci }, /* 9 Series RAID */ 366 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */ 367 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci }, /* 9 Series RAID */ 368 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci }, /* Sunrise Point-LP AHCI */ 369 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci }, /* Sunrise Point-LP RAID */ 370 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci }, /* Sunrise Point-LP RAID */ 371 { PCI_VDEVICE(INTEL, 0xa103), board_ahci }, /* Sunrise Point-H AHCI */ 372 { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */ 373 { PCI_VDEVICE(INTEL, 0xa107), board_ahci }, /* Sunrise Point-H RAID */ 374 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */ 375 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* Lewisburg RAID*/ 376 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Lewisburg AHCI*/ 377 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* Lewisburg RAID*/ 378 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Lewisburg RAID*/ 379 { PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/ 380 { PCI_VDEVICE(INTEL, 0xa184), board_ahci }, /* Lewisburg RAID*/ 381 { PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/ 382 { PCI_VDEVICE(INTEL, 0xa18e), board_ahci }, /* Lewisburg RAID*/ 383 { PCI_VDEVICE(INTEL, 0xa1d2), board_ahci }, /* Lewisburg RAID*/ 384 { PCI_VDEVICE(INTEL, 0xa1d6), board_ahci }, /* Lewisburg RAID*/ 385 { PCI_VDEVICE(INTEL, 0xa202), board_ahci }, /* Lewisburg AHCI*/ 386 { PCI_VDEVICE(INTEL, 0xa204), board_ahci }, /* Lewisburg RAID*/ 387 { PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/ 388 { PCI_VDEVICE(INTEL, 0xa20e), board_ahci }, /* Lewisburg RAID*/ 389 { PCI_VDEVICE(INTEL, 0xa252), board_ahci }, /* Lewisburg RAID*/ 390 { PCI_VDEVICE(INTEL, 0xa256), board_ahci }, /* Lewisburg RAID*/ 391 392 /* JMicron 360/1/3/5/6, match class to avoid IDE function */ 393 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 394 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr }, 395 /* JMicron 362B and 362C have an AHCI function with IDE class code */ 396 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr }, 397 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr }, 398 /* May need to update quirk_jmicron_async_suspend() for additions */ 399 400 /* ATI */ 401 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */ 402 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */ 403 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */ 404 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */ 405 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */ 406 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */ 407 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */ 408 409 /* AMD */ 410 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */ 411 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */ 412 /* AMD is using RAID class only for ahci controllers */ 413 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 414 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci }, 415 416 /* VIA */ 417 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */ 418 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */ 419 420 /* NVIDIA */ 421 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */ 422 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */ 423 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */ 424 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */ 425 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */ 426 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */ 427 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */ 428 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */ 429 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */ 430 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */ 431 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */ 432 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */ 433 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */ 434 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */ 435 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */ 436 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */ 437 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */ 438 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */ 439 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */ 440 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */ 441 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */ 442 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */ 443 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */ 444 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */ 445 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */ 446 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */ 447 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */ 448 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */ 449 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */ 450 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */ 451 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */ 452 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */ 453 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */ 454 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */ 455 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */ 456 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */ 457 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */ 458 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */ 459 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */ 460 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */ 461 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */ 462 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */ 463 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */ 464 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */ 465 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */ 466 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */ 467 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */ 468 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */ 469 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */ 470 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */ 471 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */ 472 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */ 473 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */ 474 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */ 475 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */ 476 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */ 477 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */ 478 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */ 479 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */ 480 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */ 481 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */ 482 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */ 483 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */ 484 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */ 485 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */ 486 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */ 487 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */ 488 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */ 489 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */ 490 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */ 491 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */ 492 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */ 493 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */ 494 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */ 495 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */ 496 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */ 497 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */ 498 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */ 499 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */ 500 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */ 501 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */ 502 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */ 503 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */ 504 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */ 505 506 /* SiS */ 507 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */ 508 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */ 509 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */ 510 511 /* ST Microelectronics */ 512 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */ 513 514 /* Marvell */ 515 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */ 516 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */ 517 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123), 518 .class = PCI_CLASS_STORAGE_SATA_AHCI, 519 .class_mask = 0xffffff, 520 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */ 521 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125), 522 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */ 523 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178, 524 PCI_VENDOR_ID_MARVELL_EXT, 0x9170), 525 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */ 526 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a), 527 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */ 528 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172), 529 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */ 530 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182), 531 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */ 532 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192), 533 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */ 534 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0), 535 .driver_data = board_ahci_yes_fbs }, 536 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3), 537 .driver_data = board_ahci_yes_fbs }, 538 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230), 539 .driver_data = board_ahci_yes_fbs }, 540 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642), 541 .driver_data = board_ahci_yes_fbs }, 542 543 /* Promise */ 544 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */ 545 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */ 546 547 /* Asmedia */ 548 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */ 549 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */ 550 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */ 551 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */ 552 553 /* 554 * Samsung SSDs found on some macbooks. NCQ times out if MSI is 555 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731 556 */ 557 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi }, 558 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi }, 559 560 /* Enmotus */ 561 { PCI_DEVICE(0x1c44, 0x8000), board_ahci }, 562 563 /* Generic, PCI class code for AHCI */ 564 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 565 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci }, 566 567 { } /* terminate list */ 568}; 569 570 571static struct pci_driver ahci_pci_driver = { 572 .name = DRV_NAME, 573 .id_table = ahci_pci_tbl, 574 .probe = ahci_init_one, 575 .remove = ata_pci_remove_one, 576#ifdef CONFIG_PM 577 .suspend = ahci_pci_device_suspend, 578 .resume = ahci_pci_device_resume, 579#endif 580}; 581 582#if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE) 583static int marvell_enable; 584#else 585static int marvell_enable = 1; 586#endif 587module_param(marvell_enable, int, 0644); 588MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)"); 589 590 591static void ahci_pci_save_initial_config(struct pci_dev *pdev, 592 struct ahci_host_priv *hpriv) 593{ 594 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) { 595 dev_info(&pdev->dev, "JMB361 has only one port\n"); 596 hpriv->force_port_map = 1; 597 } 598 599 /* 600 * Temporary Marvell 6145 hack: PATA port presence 601 * is asserted through the standard AHCI port 602 * presence register, as bit 4 (counting from 0) 603 */ 604 if (hpriv->flags & AHCI_HFLAG_MV_PATA) { 605 if (pdev->device == 0x6121) 606 hpriv->mask_port_map = 0x3; 607 else 608 hpriv->mask_port_map = 0xf; 609 dev_info(&pdev->dev, 610 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n"); 611 } 612 613 ahci_save_initial_config(&pdev->dev, hpriv); 614} 615 616static int ahci_pci_reset_controller(struct ata_host *host) 617{ 618 struct pci_dev *pdev = to_pci_dev(host->dev); 619 620 ahci_reset_controller(host); 621 622 if (pdev->vendor == PCI_VENDOR_ID_INTEL) { 623 struct ahci_host_priv *hpriv = host->private_data; 624 u16 tmp16; 625 626 /* configure PCS */ 627 pci_read_config_word(pdev, 0x92, &tmp16); 628 if ((tmp16 & hpriv->port_map) != hpriv->port_map) { 629 tmp16 |= hpriv->port_map; 630 pci_write_config_word(pdev, 0x92, tmp16); 631 } 632 } 633 634 return 0; 635} 636 637static void ahci_pci_init_controller(struct ata_host *host) 638{ 639 struct ahci_host_priv *hpriv = host->private_data; 640 struct pci_dev *pdev = to_pci_dev(host->dev); 641 void __iomem *port_mmio; 642 u32 tmp; 643 int mv; 644 645 if (hpriv->flags & AHCI_HFLAG_MV_PATA) { 646 if (pdev->device == 0x6121) 647 mv = 2; 648 else 649 mv = 4; 650 port_mmio = __ahci_port_base(host, mv); 651 652 writel(0, port_mmio + PORT_IRQ_MASK); 653 654 /* clear port IRQ */ 655 tmp = readl(port_mmio + PORT_IRQ_STAT); 656 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); 657 if (tmp) 658 writel(tmp, port_mmio + PORT_IRQ_STAT); 659 } 660 661 ahci_init_controller(host); 662} 663 664static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class, 665 unsigned long deadline) 666{ 667 struct ata_port *ap = link->ap; 668 struct ahci_host_priv *hpriv = ap->host->private_data; 669 bool online; 670 int rc; 671 672 DPRINTK("ENTER\n"); 673 674 ahci_stop_engine(ap); 675 676 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context), 677 deadline, &online, NULL); 678 679 hpriv->start_engine(ap); 680 681 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); 682 683 /* vt8251 doesn't clear BSY on signature FIS reception, 684 * request follow-up softreset. 685 */ 686 return online ? -EAGAIN : rc; 687} 688 689static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class, 690 unsigned long deadline) 691{ 692 struct ata_port *ap = link->ap; 693 struct ahci_port_priv *pp = ap->private_data; 694 struct ahci_host_priv *hpriv = ap->host->private_data; 695 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; 696 struct ata_taskfile tf; 697 bool online; 698 int rc; 699 700 ahci_stop_engine(ap); 701 702 /* clear D2H reception area to properly wait for D2H FIS */ 703 ata_tf_init(link->device, &tf); 704 tf.command = ATA_BUSY; 705 ata_tf_to_fis(&tf, 0, 0, d2h_fis); 706 707 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context), 708 deadline, &online, NULL); 709 710 hpriv->start_engine(ap); 711 712 /* The pseudo configuration device on SIMG4726 attached to 713 * ASUS P5W-DH Deluxe doesn't send signature FIS after 714 * hardreset if no device is attached to the first downstream 715 * port && the pseudo device locks up on SRST w/ PMP==0. To 716 * work around this, wait for !BSY only briefly. If BSY isn't 717 * cleared, perform CLO and proceed to IDENTIFY (achieved by 718 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA). 719 * 720 * Wait for two seconds. Devices attached to downstream port 721 * which can't process the following IDENTIFY after this will 722 * have to be reset again. For most cases, this should 723 * suffice while making probing snappish enough. 724 */ 725 if (online) { 726 rc = ata_wait_after_reset(link, jiffies + 2 * HZ, 727 ahci_check_ready); 728 if (rc) 729 ahci_kick_engine(ap); 730 } 731 return rc; 732} 733 734/* 735 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports. 736 * 737 * It has been observed with some SSDs that the timing of events in the 738 * link synchronization phase can leave the port in a state that can not 739 * be recovered by a SATA-hard-reset alone. The failing signature is 740 * SStatus.DET stuck at 1 ("Device presence detected but Phy 741 * communication not established"). It was found that unloading and 742 * reloading the driver when this problem occurs allows the drive 743 * connection to be recovered (DET advanced to 0x3). The critical 744 * component of reloading the driver is that the port state machines are 745 * reset by bouncing "port enable" in the AHCI PCS configuration 746 * register. So, reproduce that effect by bouncing a port whenever we 747 * see DET==1 after a reset. 748 */ 749static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class, 750 unsigned long deadline) 751{ 752 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context); 753 struct ata_port *ap = link->ap; 754 struct ahci_port_priv *pp = ap->private_data; 755 struct ahci_host_priv *hpriv = ap->host->private_data; 756 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; 757 unsigned long tmo = deadline - jiffies; 758 struct ata_taskfile tf; 759 bool online; 760 int rc, i; 761 762 DPRINTK("ENTER\n"); 763 764 ahci_stop_engine(ap); 765 766 for (i = 0; i < 2; i++) { 767 u16 val; 768 u32 sstatus; 769 int port = ap->port_no; 770 struct ata_host *host = ap->host; 771 struct pci_dev *pdev = to_pci_dev(host->dev); 772 773 /* clear D2H reception area to properly wait for D2H FIS */ 774 ata_tf_init(link->device, &tf); 775 tf.command = ATA_BUSY; 776 ata_tf_to_fis(&tf, 0, 0, d2h_fis); 777 778 rc = sata_link_hardreset(link, timing, deadline, &online, 779 ahci_check_ready); 780 781 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 || 782 (sstatus & 0xf) != 1) 783 break; 784 785 ata_link_printk(link, KERN_INFO, "avn bounce port%d\n", 786 port); 787 788 pci_read_config_word(pdev, 0x92, &val); 789 val &= ~(1 << port); 790 pci_write_config_word(pdev, 0x92, val); 791 ata_msleep(ap, 1000); 792 val |= 1 << port; 793 pci_write_config_word(pdev, 0x92, val); 794 deadline += tmo; 795 } 796 797 hpriv->start_engine(ap); 798 799 if (online) 800 *class = ahci_dev_classify(ap); 801 802 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); 803 return rc; 804} 805 806 807#ifdef CONFIG_PM 808static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg) 809{ 810 struct ata_host *host = pci_get_drvdata(pdev); 811 struct ahci_host_priv *hpriv = host->private_data; 812 void __iomem *mmio = hpriv->mmio; 813 u32 ctl; 814 815 if (mesg.event & PM_EVENT_SUSPEND && 816 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) { 817 dev_err(&pdev->dev, 818 "BIOS update required for suspend/resume\n"); 819 return -EIO; 820 } 821 822 if (mesg.event & PM_EVENT_SLEEP) { 823 /* AHCI spec rev1.1 section 8.3.3: 824 * Software must disable interrupts prior to requesting a 825 * transition of the HBA to D3 state. 826 */ 827 ctl = readl(mmio + HOST_CTL); 828 ctl &= ~HOST_IRQ_EN; 829 writel(ctl, mmio + HOST_CTL); 830 readl(mmio + HOST_CTL); /* flush */ 831 } 832 833 return ata_pci_device_suspend(pdev, mesg); 834} 835 836static int ahci_pci_device_resume(struct pci_dev *pdev) 837{ 838 struct ata_host *host = pci_get_drvdata(pdev); 839 int rc; 840 841 rc = ata_pci_device_do_resume(pdev); 842 if (rc) 843 return rc; 844 845 /* Apple BIOS helpfully mangles the registers on resume */ 846 if (is_mcp89_apple(pdev)) 847 ahci_mcp89_apple_enable(pdev); 848 849 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) { 850 rc = ahci_pci_reset_controller(host); 851 if (rc) 852 return rc; 853 854 ahci_pci_init_controller(host); 855 } 856 857 ata_host_resume(host); 858 859 return 0; 860} 861#endif 862 863static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac) 864{ 865 int rc; 866 867 /* 868 * If the device fixup already set the dma_mask to some non-standard 869 * value, don't extend it here. This happens on STA2X11, for example. 870 */ 871 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32)) 872 return 0; 873 874 if (using_dac && 875 !dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) { 876 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64)); 877 if (rc) { 878 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); 879 if (rc) { 880 dev_err(&pdev->dev, 881 "64-bit DMA enable failed\n"); 882 return rc; 883 } 884 } 885 } else { 886 rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); 887 if (rc) { 888 dev_err(&pdev->dev, "32-bit DMA enable failed\n"); 889 return rc; 890 } 891 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); 892 if (rc) { 893 dev_err(&pdev->dev, 894 "32-bit consistent DMA enable failed\n"); 895 return rc; 896 } 897 } 898 return 0; 899} 900 901static void ahci_pci_print_info(struct ata_host *host) 902{ 903 struct pci_dev *pdev = to_pci_dev(host->dev); 904 u16 cc; 905 const char *scc_s; 906 907 pci_read_config_word(pdev, 0x0a, &cc); 908 if (cc == PCI_CLASS_STORAGE_IDE) 909 scc_s = "IDE"; 910 else if (cc == PCI_CLASS_STORAGE_SATA) 911 scc_s = "SATA"; 912 else if (cc == PCI_CLASS_STORAGE_RAID) 913 scc_s = "RAID"; 914 else 915 scc_s = "unknown"; 916 917 ahci_print_info(host, scc_s); 918} 919 920/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is 921 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't 922 * support PMP and the 4726 either directly exports the device 923 * attached to the first downstream port or acts as a hardware storage 924 * controller and emulate a single ATA device (can be RAID 0/1 or some 925 * other configuration). 926 * 927 * When there's no device attached to the first downstream port of the 928 * 4726, "Config Disk" appears, which is a pseudo ATA device to 929 * configure the 4726. However, ATA emulation of the device is very 930 * lame. It doesn't send signature D2H Reg FIS after the initial 931 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues. 932 * 933 * The following function works around the problem by always using 934 * hardreset on the port and not depending on receiving signature FIS 935 * afterward. If signature FIS isn't received soon, ATA class is 936 * assumed without follow-up softreset. 937 */ 938static void ahci_p5wdh_workaround(struct ata_host *host) 939{ 940 static const struct dmi_system_id sysids[] = { 941 { 942 .ident = "P5W DH Deluxe", 943 .matches = { 944 DMI_MATCH(DMI_SYS_VENDOR, 945 "ASUSTEK COMPUTER INC"), 946 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"), 947 }, 948 }, 949 { } 950 }; 951 struct pci_dev *pdev = to_pci_dev(host->dev); 952 953 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) && 954 dmi_check_system(sysids)) { 955 struct ata_port *ap = host->ports[1]; 956 957 dev_info(&pdev->dev, 958 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n"); 959 960 ap->ops = &ahci_p5wdh_ops; 961 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA; 962 } 963} 964 965/* 966 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when 967 * booting in BIOS compatibility mode. We restore the registers but not ID. 968 */ 969static void ahci_mcp89_apple_enable(struct pci_dev *pdev) 970{ 971 u32 val; 972 973 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n"); 974 975 pci_read_config_dword(pdev, 0xf8, &val); 976 val |= 1 << 0x1b; 977 /* the following changes the device ID, but appears not to affect function */ 978 /* val = (val & ~0xf0000000) | 0x80000000; */ 979 pci_write_config_dword(pdev, 0xf8, val); 980 981 pci_read_config_dword(pdev, 0x54c, &val); 982 val |= 1 << 0xc; 983 pci_write_config_dword(pdev, 0x54c, val); 984 985 pci_read_config_dword(pdev, 0x4a4, &val); 986 val &= 0xff; 987 val |= 0x01060100; 988 pci_write_config_dword(pdev, 0x4a4, val); 989 990 pci_read_config_dword(pdev, 0x54c, &val); 991 val &= ~(1 << 0xc); 992 pci_write_config_dword(pdev, 0x54c, val); 993 994 pci_read_config_dword(pdev, 0xf8, &val); 995 val &= ~(1 << 0x1b); 996 pci_write_config_dword(pdev, 0xf8, val); 997} 998 999static bool is_mcp89_apple(struct pci_dev *pdev) 1000{ 1001 return pdev->vendor == PCI_VENDOR_ID_NVIDIA && 1002 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA && 1003 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE && 1004 pdev->subsystem_device == 0xcb89; 1005} 1006 1007/* only some SB600 ahci controllers can do 64bit DMA */ 1008static bool ahci_sb600_enable_64bit(struct pci_dev *pdev) 1009{ 1010 static const struct dmi_system_id sysids[] = { 1011 /* 1012 * The oldest version known to be broken is 0901 and 1013 * working is 1501 which was released on 2007-10-26. 1014 * Enable 64bit DMA on 1501 and anything newer. 1015 * 1016 * Please read bko#9412 for more info. 1017 */ 1018 { 1019 .ident = "ASUS M2A-VM", 1020 .matches = { 1021 DMI_MATCH(DMI_BOARD_VENDOR, 1022 "ASUSTeK Computer INC."), 1023 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"), 1024 }, 1025 .driver_data = "20071026", /* yyyymmdd */ 1026 }, 1027 /* 1028 * All BIOS versions for the MSI K9A2 Platinum (MS-7376) 1029 * support 64bit DMA. 1030 * 1031 * BIOS versions earlier than 1.5 had the Manufacturer DMI 1032 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD". 1033 * This spelling mistake was fixed in BIOS version 1.5, so 1034 * 1.5 and later have the Manufacturer as 1035 * "MICRO-STAR INTERNATIONAL CO.,LTD". 1036 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER". 1037 * 1038 * BIOS versions earlier than 1.9 had a Board Product Name 1039 * DMI field of "MS-7376". This was changed to be 1040 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still 1041 * match on DMI_BOARD_NAME of "MS-7376". 1042 */ 1043 { 1044 .ident = "MSI K9A2 Platinum", 1045 .matches = { 1046 DMI_MATCH(DMI_BOARD_VENDOR, 1047 "MICRO-STAR INTER"), 1048 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"), 1049 }, 1050 }, 1051 /* 1052 * All BIOS versions for the MSI K9AGM2 (MS-7327) support 1053 * 64bit DMA. 1054 * 1055 * This board also had the typo mentioned above in the 1056 * Manufacturer DMI field (fixed in BIOS version 1.5), so 1057 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again. 1058 */ 1059 { 1060 .ident = "MSI K9AGM2", 1061 .matches = { 1062 DMI_MATCH(DMI_BOARD_VENDOR, 1063 "MICRO-STAR INTER"), 1064 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"), 1065 }, 1066 }, 1067 /* 1068 * All BIOS versions for the Asus M3A support 64bit DMA. 1069 * (all release versions from 0301 to 1206 were tested) 1070 */ 1071 { 1072 .ident = "ASUS M3A", 1073 .matches = { 1074 DMI_MATCH(DMI_BOARD_VENDOR, 1075 "ASUSTeK Computer INC."), 1076 DMI_MATCH(DMI_BOARD_NAME, "M3A"), 1077 }, 1078 }, 1079 { } 1080 }; 1081 const struct dmi_system_id *match; 1082 int year, month, date; 1083 char buf[9]; 1084 1085 match = dmi_first_match(sysids); 1086 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) || 1087 !match) 1088 return false; 1089 1090 if (!match->driver_data) 1091 goto enable_64bit; 1092 1093 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date); 1094 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date); 1095 1096 if (strcmp(buf, match->driver_data) >= 0) 1097 goto enable_64bit; 1098 else { 1099 dev_warn(&pdev->dev, 1100 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n", 1101 match->ident); 1102 return false; 1103 } 1104 1105enable_64bit: 1106 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident); 1107 return true; 1108} 1109 1110static bool ahci_broken_system_poweroff(struct pci_dev *pdev) 1111{ 1112 static const struct dmi_system_id broken_systems[] = { 1113 { 1114 .ident = "HP Compaq nx6310", 1115 .matches = { 1116 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1117 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"), 1118 }, 1119 /* PCI slot number of the controller */ 1120 .driver_data = (void *)0x1FUL, 1121 }, 1122 { 1123 .ident = "HP Compaq 6720s", 1124 .matches = { 1125 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1126 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"), 1127 }, 1128 /* PCI slot number of the controller */ 1129 .driver_data = (void *)0x1FUL, 1130 }, 1131 1132 { } /* terminate list */ 1133 }; 1134 const struct dmi_system_id *dmi = dmi_first_match(broken_systems); 1135 1136 if (dmi) { 1137 unsigned long slot = (unsigned long)dmi->driver_data; 1138 /* apply the quirk only to on-board controllers */ 1139 return slot == PCI_SLOT(pdev->devfn); 1140 } 1141 1142 return false; 1143} 1144 1145static bool ahci_broken_suspend(struct pci_dev *pdev) 1146{ 1147 static const struct dmi_system_id sysids[] = { 1148 /* 1149 * On HP dv[4-6] and HDX18 with earlier BIOSen, link 1150 * to the harddisk doesn't become online after 1151 * resuming from STR. Warn and fail suspend. 1152 * 1153 * http://bugzilla.kernel.org/show_bug.cgi?id=12276 1154 * 1155 * Use dates instead of versions to match as HP is 1156 * apparently recycling both product and version 1157 * strings. 1158 * 1159 * http://bugzilla.kernel.org/show_bug.cgi?id=15462 1160 */ 1161 { 1162 .ident = "dv4", 1163 .matches = { 1164 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1165 DMI_MATCH(DMI_PRODUCT_NAME, 1166 "HP Pavilion dv4 Notebook PC"), 1167 }, 1168 .driver_data = "20090105", /* F.30 */ 1169 }, 1170 { 1171 .ident = "dv5", 1172 .matches = { 1173 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1174 DMI_MATCH(DMI_PRODUCT_NAME, 1175 "HP Pavilion dv5 Notebook PC"), 1176 }, 1177 .driver_data = "20090506", /* F.16 */ 1178 }, 1179 { 1180 .ident = "dv6", 1181 .matches = { 1182 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1183 DMI_MATCH(DMI_PRODUCT_NAME, 1184 "HP Pavilion dv6 Notebook PC"), 1185 }, 1186 .driver_data = "20090423", /* F.21 */ 1187 }, 1188 { 1189 .ident = "HDX18", 1190 .matches = { 1191 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1192 DMI_MATCH(DMI_PRODUCT_NAME, 1193 "HP HDX18 Notebook PC"), 1194 }, 1195 .driver_data = "20090430", /* F.23 */ 1196 }, 1197 /* 1198 * Acer eMachines G725 has the same problem. BIOS 1199 * V1.03 is known to be broken. V3.04 is known to 1200 * work. Between, there are V1.06, V2.06 and V3.03 1201 * that we don't have much idea about. For now, 1202 * blacklist anything older than V3.04. 1203 * 1204 * http://bugzilla.kernel.org/show_bug.cgi?id=15104 1205 */ 1206 { 1207 .ident = "G725", 1208 .matches = { 1209 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"), 1210 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"), 1211 }, 1212 .driver_data = "20091216", /* V3.04 */ 1213 }, 1214 { } /* terminate list */ 1215 }; 1216 const struct dmi_system_id *dmi = dmi_first_match(sysids); 1217 int year, month, date; 1218 char buf[9]; 1219 1220 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2)) 1221 return false; 1222 1223 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date); 1224 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date); 1225 1226 return strcmp(buf, dmi->driver_data) < 0; 1227} 1228 1229static bool ahci_broken_online(struct pci_dev *pdev) 1230{ 1231#define ENCODE_BUSDEVFN(bus, slot, func) \ 1232 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func))) 1233 static const struct dmi_system_id sysids[] = { 1234 /* 1235 * There are several gigabyte boards which use 1236 * SIMG5723s configured as hardware RAID. Certain 1237 * 5723 firmware revisions shipped there keep the link 1238 * online but fail to answer properly to SRST or 1239 * IDENTIFY when no device is attached downstream 1240 * causing libata to retry quite a few times leading 1241 * to excessive detection delay. 1242 * 1243 * As these firmwares respond to the second reset try 1244 * with invalid device signature, considering unknown 1245 * sig as offline works around the problem acceptably. 1246 */ 1247 { 1248 .ident = "EP45-DQ6", 1249 .matches = { 1250 DMI_MATCH(DMI_BOARD_VENDOR, 1251 "Gigabyte Technology Co., Ltd."), 1252 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"), 1253 }, 1254 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0), 1255 }, 1256 { 1257 .ident = "EP45-DS5", 1258 .matches = { 1259 DMI_MATCH(DMI_BOARD_VENDOR, 1260 "Gigabyte Technology Co., Ltd."), 1261 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"), 1262 }, 1263 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0), 1264 }, 1265 { } /* terminate list */ 1266 }; 1267#undef ENCODE_BUSDEVFN 1268 const struct dmi_system_id *dmi = dmi_first_match(sysids); 1269 unsigned int val; 1270 1271 if (!dmi) 1272 return false; 1273 1274 val = (unsigned long)dmi->driver_data; 1275 1276 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff); 1277} 1278 1279static bool ahci_broken_devslp(struct pci_dev *pdev) 1280{ 1281 /* device with broken DEVSLP but still showing SDS capability */ 1282 static const struct pci_device_id ids[] = { 1283 { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */ 1284 {} 1285 }; 1286 1287 return pci_match_id(ids, pdev); 1288} 1289 1290#ifdef CONFIG_ATA_ACPI 1291static void ahci_gtf_filter_workaround(struct ata_host *host) 1292{ 1293 static const struct dmi_system_id sysids[] = { 1294 /* 1295 * Aspire 3810T issues a bunch of SATA enable commands 1296 * via _GTF including an invalid one and one which is 1297 * rejected by the device. Among the successful ones 1298 * is FPDMA non-zero offset enable which when enabled 1299 * only on the drive side leads to NCQ command 1300 * failures. Filter it out. 1301 */ 1302 { 1303 .ident = "Aspire 3810T", 1304 .matches = { 1305 DMI_MATCH(DMI_SYS_VENDOR, "Acer"), 1306 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"), 1307 }, 1308 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET, 1309 }, 1310 { } 1311 }; 1312 const struct dmi_system_id *dmi = dmi_first_match(sysids); 1313 unsigned int filter; 1314 int i; 1315 1316 if (!dmi) 1317 return; 1318 1319 filter = (unsigned long)dmi->driver_data; 1320 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n", 1321 filter, dmi->ident); 1322 1323 for (i = 0; i < host->n_ports; i++) { 1324 struct ata_port *ap = host->ports[i]; 1325 struct ata_link *link; 1326 struct ata_device *dev; 1327 1328 ata_for_each_link(link, ap, EDGE) 1329 ata_for_each_dev(dev, link, ALL) 1330 dev->gtf_filter |= filter; 1331 } 1332} 1333#else 1334static inline void ahci_gtf_filter_workaround(struct ata_host *host) 1335{} 1336#endif 1337 1338static int ahci_init_interrupts(struct pci_dev *pdev, unsigned int n_ports, 1339 struct ahci_host_priv *hpriv) 1340{ 1341 int rc, nvec; 1342 1343 if (hpriv->flags & AHCI_HFLAG_NO_MSI) 1344 goto intx; 1345 1346 nvec = pci_msi_vec_count(pdev); 1347 if (nvec < 0) 1348 goto intx; 1349 1350 /* 1351 * If number of MSIs is less than number of ports then Sharing Last 1352 * Message mode could be enforced. In this case assume that advantage 1353 * of multipe MSIs is negated and use single MSI mode instead. 1354 */ 1355 if (nvec < n_ports) 1356 goto single_msi; 1357 1358 rc = pci_enable_msi_exact(pdev, nvec); 1359 if (rc == -ENOSPC) 1360 goto single_msi; 1361 else if (rc < 0) 1362 goto intx; 1363 1364 /* fallback to single MSI mode if the controller enforced MRSM mode */ 1365 if (readl(hpriv->mmio + HOST_CTL) & HOST_MRSM) { 1366 pci_disable_msi(pdev); 1367 printk(KERN_INFO "ahci: MRSM is on, fallback to single MSI\n"); 1368 goto single_msi; 1369 } 1370 1371 if (nvec > 1) 1372 hpriv->flags |= AHCI_HFLAG_MULTI_MSI; 1373 1374 return nvec; 1375 1376single_msi: 1377 if (pci_enable_msi(pdev)) 1378 goto intx; 1379 return 1; 1380 1381intx: 1382 pci_intx(pdev, 1); 1383 return 0; 1384} 1385 1386static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 1387{ 1388 unsigned int board_id = ent->driver_data; 1389 struct ata_port_info pi = ahci_port_info[board_id]; 1390 const struct ata_port_info *ppi[] = { &pi, NULL }; 1391 struct device *dev = &pdev->dev; 1392 struct ahci_host_priv *hpriv; 1393 struct ata_host *host; 1394 int n_ports, i, rc; 1395 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD; 1396 1397 VPRINTK("ENTER\n"); 1398 1399 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS); 1400 1401 ata_print_version_once(&pdev->dev, DRV_VERSION); 1402 1403 /* The AHCI driver can only drive the SATA ports, the PATA driver 1404 can drive them all so if both drivers are selected make sure 1405 AHCI stays out of the way */ 1406 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable) 1407 return -ENODEV; 1408 1409 /* Apple BIOS on MCP89 prevents us using AHCI */ 1410 if (is_mcp89_apple(pdev)) 1411 ahci_mcp89_apple_enable(pdev); 1412 1413 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode. 1414 * At the moment, we can only use the AHCI mode. Let the users know 1415 * that for SAS drives they're out of luck. 1416 */ 1417 if (pdev->vendor == PCI_VENDOR_ID_PROMISE) 1418 dev_info(&pdev->dev, 1419 "PDC42819 can only drive SATA devices with this driver\n"); 1420 1421 /* Both Connext and Enmotus devices use non-standard BARs */ 1422 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06) 1423 ahci_pci_bar = AHCI_PCI_BAR_STA2X11; 1424 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000) 1425 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS; 1426 1427 /* acquire resources */ 1428 rc = pcim_enable_device(pdev); 1429 if (rc) 1430 return rc; 1431 1432 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 1433 (pdev->device == 0x2652 || pdev->device == 0x2653)) { 1434 u8 map; 1435 1436 /* ICH6s share the same PCI ID for both piix and ahci 1437 * modes. Enabling ahci mode while MAP indicates 1438 * combined mode is a bad idea. Yield to ata_piix. 1439 */ 1440 pci_read_config_byte(pdev, ICH_MAP, &map); 1441 if (map & 0x3) { 1442 dev_info(&pdev->dev, 1443 "controller is in combined mode, can't enable AHCI mode\n"); 1444 return -ENODEV; 1445 } 1446 } 1447 1448 /* AHCI controllers often implement SFF compatible interface. 1449 * Grab all PCI BARs just in case. 1450 */ 1451 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME); 1452 if (rc == -EBUSY) 1453 pcim_pin_device(pdev); 1454 if (rc) 1455 return rc; 1456 1457 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); 1458 if (!hpriv) 1459 return -ENOMEM; 1460 hpriv->flags |= (unsigned long)pi.private_data; 1461 1462 /* MCP65 revision A1 and A2 can't do MSI */ 1463 if (board_id == board_ahci_mcp65 && 1464 (pdev->revision == 0xa1 || pdev->revision == 0xa2)) 1465 hpriv->flags |= AHCI_HFLAG_NO_MSI; 1466 1467 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */ 1468 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40) 1469 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL; 1470 1471 /* only some SB600s can do 64bit DMA */ 1472 if (ahci_sb600_enable_64bit(pdev)) 1473 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY; 1474 1475 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar]; 1476 1477 /* must set flag prior to save config in order to take effect */ 1478 if (ahci_broken_devslp(pdev)) 1479 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP; 1480 1481 /* save initial config */ 1482 ahci_pci_save_initial_config(pdev, hpriv); 1483 1484 /* prepare host */ 1485 if (hpriv->cap & HOST_CAP_NCQ) { 1486 pi.flags |= ATA_FLAG_NCQ; 1487 /* 1488 * Auto-activate optimization is supposed to be 1489 * supported on all AHCI controllers indicating NCQ 1490 * capability, but it seems to be broken on some 1491 * chipsets including NVIDIAs. 1492 */ 1493 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA)) 1494 pi.flags |= ATA_FLAG_FPDMA_AA; 1495 1496 /* 1497 * All AHCI controllers should be forward-compatible 1498 * with the new auxiliary field. This code should be 1499 * conditionalized if any buggy AHCI controllers are 1500 * encountered. 1501 */ 1502 pi.flags |= ATA_FLAG_FPDMA_AUX; 1503 } 1504 1505 if (hpriv->cap & HOST_CAP_PMP) 1506 pi.flags |= ATA_FLAG_PMP; 1507 1508 ahci_set_em_messages(hpriv, &pi); 1509 1510 if (ahci_broken_system_poweroff(pdev)) { 1511 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN; 1512 dev_info(&pdev->dev, 1513 "quirky BIOS, skipping spindown on poweroff\n"); 1514 } 1515 1516 if (ahci_broken_suspend(pdev)) { 1517 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND; 1518 dev_warn(&pdev->dev, 1519 "BIOS update required for suspend/resume\n"); 1520 } 1521 1522 if (ahci_broken_online(pdev)) { 1523 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE; 1524 dev_info(&pdev->dev, 1525 "online status unreliable, applying workaround\n"); 1526 } 1527 1528 /* CAP.NP sometimes indicate the index of the last enabled 1529 * port, at other times, that of the last possible port, so 1530 * determining the maximum port number requires looking at 1531 * both CAP.NP and port_map. 1532 */ 1533 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map)); 1534 1535 ahci_init_interrupts(pdev, n_ports, hpriv); 1536 1537 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 1538 if (!host) 1539 return -ENOMEM; 1540 host->private_data = hpriv; 1541 1542 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss) 1543 host->flags |= ATA_HOST_PARALLEL_SCAN; 1544 else 1545 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n"); 1546 1547 if (pi.flags & ATA_FLAG_EM) 1548 ahci_reset_em(host); 1549 1550 for (i = 0; i < host->n_ports; i++) { 1551 struct ata_port *ap = host->ports[i]; 1552 1553 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar"); 1554 ata_port_pbar_desc(ap, ahci_pci_bar, 1555 0x100 + ap->port_no * 0x80, "port"); 1556 1557 /* set enclosure management message type */ 1558 if (ap->flags & ATA_FLAG_EM) 1559 ap->em_message_type = hpriv->em_msg_type; 1560 1561 1562 /* disabled/not-implemented port */ 1563 if (!(hpriv->port_map & (1 << i))) 1564 ap->ops = &ata_dummy_port_ops; 1565 } 1566 1567 /* apply workaround for ASUS P5W DH Deluxe mainboard */ 1568 ahci_p5wdh_workaround(host); 1569 1570 /* apply gtf filter quirk */ 1571 ahci_gtf_filter_workaround(host); 1572 1573 /* initialize adapter */ 1574 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64); 1575 if (rc) 1576 return rc; 1577 1578 rc = ahci_pci_reset_controller(host); 1579 if (rc) 1580 return rc; 1581 1582 ahci_pci_init_controller(host); 1583 ahci_pci_print_info(host); 1584 1585 pci_set_master(pdev); 1586 1587 return ahci_host_activate(host, pdev->irq, &ahci_sht); 1588} 1589 1590module_pci_driver(ahci_pci_driver); 1591 1592MODULE_AUTHOR("Jeff Garzik"); 1593MODULE_DESCRIPTION("AHCI SATA low-level driver"); 1594MODULE_LICENSE("GPL"); 1595MODULE_DEVICE_TABLE(pci, ahci_pci_tbl); 1596MODULE_VERSION(DRV_VERSION); 1597