1/*
2 * arch/xtensa/include/asm/traps.h
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License.  See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2012 Tensilica Inc.
9 */
10#ifndef _XTENSA_TRAPS_H
11#define _XTENSA_TRAPS_H
12
13#include <asm/ptrace.h>
14
15/*
16 * handler must be either of the following:
17 *  void (*)(struct pt_regs *regs);
18 *  void (*)(struct pt_regs *regs, unsigned long exccause);
19 */
20extern void * __init trap_set_handler(int cause, void *handler);
21extern void do_unhandled(struct pt_regs *regs, unsigned long exccause);
22void secondary_trap_init(void);
23
24static inline void spill_registers(void)
25{
26#if XCHAL_NUM_AREGS > 16
27	__asm__ __volatile__ (
28		"	call8	1f\n"
29		"	_j	2f\n"
30		"	retw\n"
31		"	.align	4\n"
32		"1:\n"
33#if XCHAL_NUM_AREGS == 32
34		"	_entry	a1, 32\n"
35		"	addi	a8, a0, 3\n"
36		"	_entry	a1, 16\n"
37		"	mov	a12, a12\n"
38		"	retw\n"
39#else
40		"	_entry	a1, 48\n"
41		"	call12	1f\n"
42		"	retw\n"
43		"	.align	4\n"
44		"1:\n"
45		"	.rept	(" __stringify(XCHAL_NUM_AREGS) " - 16) / 12\n"
46		"	_entry	a1, 48\n"
47		"	mov	a12, a0\n"
48		"	.endr\n"
49		"	_entry	a1, 16\n"
50#if XCHAL_NUM_AREGS % 12 == 0
51		"	mov	a12, a12\n"
52#elif XCHAL_NUM_AREGS % 12 == 4
53		"	mov	a4, a4\n"
54#elif XCHAL_NUM_AREGS % 12 == 8
55		"	mov	a8, a8\n"
56#endif
57		"	retw\n"
58#endif
59		"2:\n"
60		: : : "a8", "a9", "memory");
61#else
62	__asm__ __volatile__ (
63		"	mov	a12, a12\n"
64		: : : "memory");
65#endif
66}
67
68#endif /* _XTENSA_TRAPS_H */
69