1/*
2 * mfld.c: Intel Medfield platform setup code
3 *
4 * (C) Copyright 2013 Intel Corporation
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; version 2
9 * of the License.
10 */
11
12#include <linux/init.h>
13
14#include <asm/apic.h>
15#include <asm/intel-mid.h>
16#include <asm/intel_mid_vrtc.h>
17
18#include "intel_mid_weak_decls.h"
19
20static void penwell_arch_setup(void);
21/* penwell arch ops */
22static struct intel_mid_ops penwell_ops = {
23	.arch_setup = penwell_arch_setup,
24};
25
26static void mfld_power_off(void)
27{
28}
29
30static unsigned long __init mfld_calibrate_tsc(void)
31{
32	unsigned long fast_calibrate;
33	u32 lo, hi, ratio, fsb;
34
35	rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
36	pr_debug("IA32 perf status is 0x%x, 0x%0x\n", lo, hi);
37	ratio = (hi >> 8) & 0x1f;
38	pr_debug("ratio is %d\n", ratio);
39	if (!ratio) {
40		pr_err("read a zero ratio, should be incorrect!\n");
41		pr_err("force tsc ratio to 16 ...\n");
42		ratio = 16;
43	}
44	rdmsr(MSR_FSB_FREQ, lo, hi);
45	if ((lo & 0x7) == 0x7)
46		fsb = FSB_FREQ_83SKU;
47	else
48		fsb = FSB_FREQ_100SKU;
49	fast_calibrate = ratio * fsb;
50	pr_debug("read penwell tsc %lu khz\n", fast_calibrate);
51	lapic_timer_frequency = fsb * 1000 / HZ;
52	/* mark tsc clocksource as reliable */
53	set_cpu_cap(&boot_cpu_data, X86_FEATURE_TSC_RELIABLE);
54
55	if (fast_calibrate)
56		return fast_calibrate;
57
58	return 0;
59}
60
61static void __init penwell_arch_setup(void)
62{
63	x86_platform.calibrate_tsc = mfld_calibrate_tsc;
64	pm_power_off = mfld_power_off;
65}
66
67void *get_penwell_ops(void)
68{
69	return &penwell_ops;
70}
71
72void *get_cloverview_ops(void)
73{
74	return &penwell_ops;
75}
76