1/*
2 * irq_comm.c: Common API for in kernel interrupt controller
3 * Copyright (c) 2007, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
16 * Place - Suite 330, Boston, MA 02111-1307 USA.
17 * Authors:
18 *   Yaozu (Eddie) Dong <Eddie.dong@intel.com>
19 *
20 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
21 */
22
23#include <linux/kvm_host.h>
24#include <linux/slab.h>
25#include <linux/export.h>
26#include <trace/events/kvm.h>
27
28#include <asm/msidef.h>
29
30#include "irq.h"
31
32#include "ioapic.h"
33
34static int kvm_set_pic_irq(struct kvm_kernel_irq_routing_entry *e,
35			   struct kvm *kvm, int irq_source_id, int level,
36			   bool line_status)
37{
38	struct kvm_pic *pic = pic_irqchip(kvm);
39	return kvm_pic_set_irq(pic, e->irqchip.pin, irq_source_id, level);
40}
41
42static int kvm_set_ioapic_irq(struct kvm_kernel_irq_routing_entry *e,
43			      struct kvm *kvm, int irq_source_id, int level,
44			      bool line_status)
45{
46	struct kvm_ioapic *ioapic = kvm->arch.vioapic;
47	return kvm_ioapic_set_irq(ioapic, e->irqchip.pin, irq_source_id, level,
48				line_status);
49}
50
51inline static bool kvm_is_dm_lowest_prio(struct kvm_lapic_irq *irq)
52{
53	return irq->delivery_mode == APIC_DM_LOWEST;
54}
55
56int kvm_irq_delivery_to_apic(struct kvm *kvm, struct kvm_lapic *src,
57		struct kvm_lapic_irq *irq, unsigned long *dest_map)
58{
59	int i, r = -1;
60	struct kvm_vcpu *vcpu, *lowest = NULL;
61
62	if (irq->dest_mode == 0 && irq->dest_id == 0xff &&
63			kvm_is_dm_lowest_prio(irq)) {
64		printk(KERN_INFO "kvm: apic: phys broadcast and lowest prio\n");
65		irq->delivery_mode = APIC_DM_FIXED;
66	}
67
68	if (kvm_irq_delivery_to_apic_fast(kvm, src, irq, &r, dest_map))
69		return r;
70
71	kvm_for_each_vcpu(i, vcpu, kvm) {
72		if (!kvm_apic_present(vcpu))
73			continue;
74
75		if (!kvm_apic_match_dest(vcpu, src, irq->shorthand,
76					irq->dest_id, irq->dest_mode))
77			continue;
78
79		if (!kvm_is_dm_lowest_prio(irq)) {
80			if (r < 0)
81				r = 0;
82			r += kvm_apic_set_irq(vcpu, irq, dest_map);
83		} else if (kvm_lapic_enabled(vcpu)) {
84			if (!lowest)
85				lowest = vcpu;
86			else if (kvm_apic_compare_prio(vcpu, lowest) < 0)
87				lowest = vcpu;
88		}
89	}
90
91	if (lowest)
92		r = kvm_apic_set_irq(lowest, irq, dest_map);
93
94	return r;
95}
96
97static inline void kvm_set_msi_irq(struct kvm_kernel_irq_routing_entry *e,
98				   struct kvm_lapic_irq *irq)
99{
100	trace_kvm_msi_set_irq(e->msi.address_lo, e->msi.data);
101
102	irq->dest_id = (e->msi.address_lo &
103			MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT;
104	irq->vector = (e->msi.data &
105			MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT;
106	irq->dest_mode = (1 << MSI_ADDR_DEST_MODE_SHIFT) & e->msi.address_lo;
107	irq->trig_mode = (1 << MSI_DATA_TRIGGER_SHIFT) & e->msi.data;
108	irq->delivery_mode = e->msi.data & 0x700;
109	irq->level = 1;
110	irq->shorthand = 0;
111	/* TODO Deal with RH bit of MSI message address */
112}
113
114int kvm_set_msi(struct kvm_kernel_irq_routing_entry *e,
115		struct kvm *kvm, int irq_source_id, int level, bool line_status)
116{
117	struct kvm_lapic_irq irq;
118
119	if (!level)
120		return -1;
121
122	kvm_set_msi_irq(e, &irq);
123
124	return kvm_irq_delivery_to_apic(kvm, NULL, &irq, NULL);
125}
126
127
128static int kvm_set_msi_inatomic(struct kvm_kernel_irq_routing_entry *e,
129			 struct kvm *kvm)
130{
131	struct kvm_lapic_irq irq;
132	int r;
133
134	kvm_set_msi_irq(e, &irq);
135
136	if (kvm_irq_delivery_to_apic_fast(kvm, NULL, &irq, &r, NULL))
137		return r;
138	else
139		return -EWOULDBLOCK;
140}
141
142/*
143 * Deliver an IRQ in an atomic context if we can, or return a failure,
144 * user can retry in a process context.
145 * Return value:
146 *  -EWOULDBLOCK - Can't deliver in atomic context: retry in a process context.
147 *  Other values - No need to retry.
148 */
149int kvm_set_irq_inatomic(struct kvm *kvm, int irq_source_id, u32 irq, int level)
150{
151	struct kvm_kernel_irq_routing_entry entries[KVM_NR_IRQCHIPS];
152	struct kvm_kernel_irq_routing_entry *e;
153	int ret = -EINVAL;
154	int idx;
155
156	trace_kvm_set_irq(irq, level, irq_source_id);
157
158	/*
159	 * Injection into either PIC or IOAPIC might need to scan all CPUs,
160	 * which would need to be retried from thread context;  when same GSI
161	 * is connected to both PIC and IOAPIC, we'd have to report a
162	 * partial failure here.
163	 * Since there's no easy way to do this, we only support injecting MSI
164	 * which is limited to 1:1 GSI mapping.
165	 */
166	idx = srcu_read_lock(&kvm->irq_srcu);
167	if (kvm_irq_map_gsi(kvm, entries, irq) > 0) {
168		e = &entries[0];
169		if (likely(e->type == KVM_IRQ_ROUTING_MSI))
170			ret = kvm_set_msi_inatomic(e, kvm);
171		else
172			ret = -EWOULDBLOCK;
173	}
174	srcu_read_unlock(&kvm->irq_srcu, idx);
175	return ret;
176}
177
178int kvm_request_irq_source_id(struct kvm *kvm)
179{
180	unsigned long *bitmap = &kvm->arch.irq_sources_bitmap;
181	int irq_source_id;
182
183	mutex_lock(&kvm->irq_lock);
184	irq_source_id = find_first_zero_bit(bitmap, BITS_PER_LONG);
185
186	if (irq_source_id >= BITS_PER_LONG) {
187		printk(KERN_WARNING "kvm: exhaust allocatable IRQ sources!\n");
188		irq_source_id = -EFAULT;
189		goto unlock;
190	}
191
192	ASSERT(irq_source_id != KVM_USERSPACE_IRQ_SOURCE_ID);
193	ASSERT(irq_source_id != KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID);
194	set_bit(irq_source_id, bitmap);
195unlock:
196	mutex_unlock(&kvm->irq_lock);
197
198	return irq_source_id;
199}
200
201void kvm_free_irq_source_id(struct kvm *kvm, int irq_source_id)
202{
203	ASSERT(irq_source_id != KVM_USERSPACE_IRQ_SOURCE_ID);
204	ASSERT(irq_source_id != KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID);
205
206	mutex_lock(&kvm->irq_lock);
207	if (irq_source_id < 0 ||
208	    irq_source_id >= BITS_PER_LONG) {
209		printk(KERN_ERR "kvm: IRQ source ID out of range!\n");
210		goto unlock;
211	}
212	clear_bit(irq_source_id, &kvm->arch.irq_sources_bitmap);
213	if (!irqchip_in_kernel(kvm))
214		goto unlock;
215
216	kvm_ioapic_clear_all(kvm->arch.vioapic, irq_source_id);
217	kvm_pic_clear_all(pic_irqchip(kvm), irq_source_id);
218unlock:
219	mutex_unlock(&kvm->irq_lock);
220}
221
222void kvm_register_irq_mask_notifier(struct kvm *kvm, int irq,
223				    struct kvm_irq_mask_notifier *kimn)
224{
225	mutex_lock(&kvm->irq_lock);
226	kimn->irq = irq;
227	hlist_add_head_rcu(&kimn->link, &kvm->arch.mask_notifier_list);
228	mutex_unlock(&kvm->irq_lock);
229}
230
231void kvm_unregister_irq_mask_notifier(struct kvm *kvm, int irq,
232				      struct kvm_irq_mask_notifier *kimn)
233{
234	mutex_lock(&kvm->irq_lock);
235	hlist_del_rcu(&kimn->link);
236	mutex_unlock(&kvm->irq_lock);
237	synchronize_srcu(&kvm->irq_srcu);
238}
239
240void kvm_fire_mask_notifiers(struct kvm *kvm, unsigned irqchip, unsigned pin,
241			     bool mask)
242{
243	struct kvm_irq_mask_notifier *kimn;
244	int idx, gsi;
245
246	idx = srcu_read_lock(&kvm->irq_srcu);
247	gsi = kvm_irq_map_chip_pin(kvm, irqchip, pin);
248	if (gsi != -1)
249		hlist_for_each_entry_rcu(kimn, &kvm->arch.mask_notifier_list, link)
250			if (kimn->irq == gsi)
251				kimn->func(kimn, mask);
252	srcu_read_unlock(&kvm->irq_srcu, idx);
253}
254
255int kvm_set_routing_entry(struct kvm_kernel_irq_routing_entry *e,
256			  const struct kvm_irq_routing_entry *ue)
257{
258	int r = -EINVAL;
259	int delta;
260	unsigned max_pin;
261
262	switch (ue->type) {
263	case KVM_IRQ_ROUTING_IRQCHIP:
264		delta = 0;
265		switch (ue->u.irqchip.irqchip) {
266		case KVM_IRQCHIP_PIC_MASTER:
267			e->set = kvm_set_pic_irq;
268			max_pin = PIC_NUM_PINS;
269			break;
270		case KVM_IRQCHIP_PIC_SLAVE:
271			e->set = kvm_set_pic_irq;
272			max_pin = PIC_NUM_PINS;
273			delta = 8;
274			break;
275		case KVM_IRQCHIP_IOAPIC:
276			max_pin = KVM_IOAPIC_NUM_PINS;
277			e->set = kvm_set_ioapic_irq;
278			break;
279		default:
280			goto out;
281		}
282		e->irqchip.irqchip = ue->u.irqchip.irqchip;
283		e->irqchip.pin = ue->u.irqchip.pin + delta;
284		if (e->irqchip.pin >= max_pin)
285			goto out;
286		break;
287	case KVM_IRQ_ROUTING_MSI:
288		e->set = kvm_set_msi;
289		e->msi.address_lo = ue->u.msi.address_lo;
290		e->msi.address_hi = ue->u.msi.address_hi;
291		e->msi.data = ue->u.msi.data;
292		break;
293	default:
294		goto out;
295	}
296
297	r = 0;
298out:
299	return r;
300}
301
302#define IOAPIC_ROUTING_ENTRY(irq) \
303	{ .gsi = irq, .type = KVM_IRQ_ROUTING_IRQCHIP,	\
304	  .u.irqchip = { .irqchip = KVM_IRQCHIP_IOAPIC, .pin = (irq) } }
305#define ROUTING_ENTRY1(irq) IOAPIC_ROUTING_ENTRY(irq)
306
307#define PIC_ROUTING_ENTRY(irq) \
308	{ .gsi = irq, .type = KVM_IRQ_ROUTING_IRQCHIP,	\
309	  .u.irqchip = { .irqchip = SELECT_PIC(irq), .pin = (irq) % 8 } }
310#define ROUTING_ENTRY2(irq) \
311	IOAPIC_ROUTING_ENTRY(irq), PIC_ROUTING_ENTRY(irq)
312
313static const struct kvm_irq_routing_entry default_routing[] = {
314	ROUTING_ENTRY2(0), ROUTING_ENTRY2(1),
315	ROUTING_ENTRY2(2), ROUTING_ENTRY2(3),
316	ROUTING_ENTRY2(4), ROUTING_ENTRY2(5),
317	ROUTING_ENTRY2(6), ROUTING_ENTRY2(7),
318	ROUTING_ENTRY2(8), ROUTING_ENTRY2(9),
319	ROUTING_ENTRY2(10), ROUTING_ENTRY2(11),
320	ROUTING_ENTRY2(12), ROUTING_ENTRY2(13),
321	ROUTING_ENTRY2(14), ROUTING_ENTRY2(15),
322	ROUTING_ENTRY1(16), ROUTING_ENTRY1(17),
323	ROUTING_ENTRY1(18), ROUTING_ENTRY1(19),
324	ROUTING_ENTRY1(20), ROUTING_ENTRY1(21),
325	ROUTING_ENTRY1(22), ROUTING_ENTRY1(23),
326};
327
328int kvm_setup_default_irq_routing(struct kvm *kvm)
329{
330	return kvm_set_irq_routing(kvm, default_routing,
331				   ARRAY_SIZE(default_routing), 0);
332}
333