1 /* 2 * x86 SMP booting functions 3 * 4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> 5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 6 * Copyright 2001 Andi Kleen, SuSE Labs. 7 * 8 * Much of the core SMP work is based on previous work by Thomas Radke, to 9 * whom a great many thanks are extended. 10 * 11 * Thanks to Intel for making available several different Pentium, 12 * Pentium Pro and Pentium-II/Xeon MP machines. 13 * Original development of Linux SMP code supported by Caldera. 14 * 15 * This code is released under the GNU General Public License version 2 or 16 * later. 17 * 18 * Fixes 19 * Felix Koop : NR_CPUS used properly 20 * Jose Renau : Handle single CPU case. 21 * Alan Cox : By repeated request 8) - Total BogoMIPS report. 22 * Greg Wright : Fix for kernel stacks panic. 23 * Erich Boleyn : MP v1.4 and additional changes. 24 * Matthias Sattler : Changes for 2.1 kernel map. 25 * Michel Lespinasse : Changes for 2.1 kernel map. 26 * Michael Chastain : Change trampoline.S to gnu as. 27 * Alan Cox : Dumb bug: 'B' step PPro's are fine 28 * Ingo Molnar : Added APIC timers, based on code 29 * from Jose Renau 30 * Ingo Molnar : various cleanups and rewrites 31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. 32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs 33 * Andi Kleen : Changed for SMP boot into long mode. 34 * Martin J. Bligh : Added support for multi-quad systems 35 * Dave Jones : Report invalid combinations of Athlon CPUs. 36 * Rusty Russell : Hacked into shape for new "hotplug" boot process. 37 * Andi Kleen : Converted to new state machine. 38 * Ashok Raj : CPU hotplug support 39 * Glauber Costa : i386 and x86_64 integration 40 */ 41 42#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 43 44#include <linux/init.h> 45#include <linux/smp.h> 46#include <linux/module.h> 47#include <linux/sched.h> 48#include <linux/percpu.h> 49#include <linux/bootmem.h> 50#include <linux/err.h> 51#include <linux/nmi.h> 52#include <linux/tboot.h> 53#include <linux/stackprotector.h> 54#include <linux/gfp.h> 55#include <linux/cpuidle.h> 56 57#include <asm/acpi.h> 58#include <asm/desc.h> 59#include <asm/nmi.h> 60#include <asm/irq.h> 61#include <asm/idle.h> 62#include <asm/realmode.h> 63#include <asm/cpu.h> 64#include <asm/numa.h> 65#include <asm/pgtable.h> 66#include <asm/tlbflush.h> 67#include <asm/mtrr.h> 68#include <asm/mwait.h> 69#include <asm/apic.h> 70#include <asm/io_apic.h> 71#include <asm/i387.h> 72#include <asm/fpu-internal.h> 73#include <asm/setup.h> 74#include <asm/uv/uv.h> 75#include <linux/mc146818rtc.h> 76#include <asm/i8259.h> 77#include <asm/realmode.h> 78#include <asm/misc.h> 79 80/* Number of siblings per CPU package */ 81int smp_num_siblings = 1; 82EXPORT_SYMBOL(smp_num_siblings); 83 84/* Last level cache ID of each logical CPU */ 85DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID; 86 87/* representing HT siblings of each logical CPU */ 88DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map); 89EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); 90 91/* representing HT and core siblings of each logical CPU */ 92DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map); 93EXPORT_PER_CPU_SYMBOL(cpu_core_map); 94 95DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map); 96 97/* Per CPU bogomips and other parameters */ 98DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); 99EXPORT_PER_CPU_SYMBOL(cpu_info); 100 101atomic_t init_deasserted; 102 103static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip) 104{ 105 unsigned long flags; 106 107 spin_lock_irqsave(&rtc_lock, flags); 108 CMOS_WRITE(0xa, 0xf); 109 spin_unlock_irqrestore(&rtc_lock, flags); 110 local_flush_tlb(); 111 pr_debug("1.\n"); 112 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) = 113 start_eip >> 4; 114 pr_debug("2.\n"); 115 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 116 start_eip & 0xf; 117 pr_debug("3.\n"); 118} 119 120static inline void smpboot_restore_warm_reset_vector(void) 121{ 122 unsigned long flags; 123 124 /* 125 * Install writable page 0 entry to set BIOS data area. 126 */ 127 local_flush_tlb(); 128 129 /* 130 * Paranoid: Set warm reset code and vector here back 131 * to default values. 132 */ 133 spin_lock_irqsave(&rtc_lock, flags); 134 CMOS_WRITE(0, 0xf); 135 spin_unlock_irqrestore(&rtc_lock, flags); 136 137 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0; 138} 139 140/* 141 * Report back to the Boot Processor during boot time or to the caller processor 142 * during CPU online. 143 */ 144static void smp_callin(void) 145{ 146 int cpuid, phys_id; 147 148 /* 149 * If waken up by an INIT in an 82489DX configuration 150 * we may get here before an INIT-deassert IPI reaches 151 * our local APIC. We have to wait for the IPI or we'll 152 * lock up on an APIC access. 153 * 154 * Since CPU0 is not wakened up by INIT, it doesn't wait for the IPI. 155 */ 156 cpuid = smp_processor_id(); 157 if (apic->wait_for_init_deassert && cpuid) 158 while (!atomic_read(&init_deasserted)) 159 cpu_relax(); 160 161 /* 162 * (This works even if the APIC is not enabled.) 163 */ 164 phys_id = read_apic_id(); 165 166 /* 167 * the boot CPU has finished the init stage and is spinning 168 * on callin_map until we finish. We are free to set up this 169 * CPU, first the APIC. (this is probably redundant on most 170 * boards) 171 */ 172 apic_ap_setup(); 173 174 /* 175 * Need to setup vector mappings before we enable interrupts. 176 */ 177 setup_vector_irq(smp_processor_id()); 178 179 /* 180 * Save our processor parameters. Note: this information 181 * is needed for clock calibration. 182 */ 183 smp_store_cpu_info(cpuid); 184 185 /* 186 * Get our bogomips. 187 * Update loops_per_jiffy in cpu_data. Previous call to 188 * smp_store_cpu_info() stored a value that is close but not as 189 * accurate as the value just calculated. 190 */ 191 calibrate_delay(); 192 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy; 193 pr_debug("Stack at about %p\n", &cpuid); 194 195 /* 196 * This must be done before setting cpu_online_mask 197 * or calling notify_cpu_starting. 198 */ 199 set_cpu_sibling_map(raw_smp_processor_id()); 200 wmb(); 201 202 notify_cpu_starting(cpuid); 203 204 /* 205 * Allow the master to continue. 206 */ 207 cpumask_set_cpu(cpuid, cpu_callin_mask); 208} 209 210static int cpu0_logical_apicid; 211static int enable_start_cpu0; 212/* 213 * Activate a secondary processor. 214 */ 215static void notrace start_secondary(void *unused) 216{ 217 /* 218 * Don't put *anything* before cpu_init(), SMP booting is too 219 * fragile that we want to limit the things done here to the 220 * most necessary things. 221 */ 222 cpu_init(); 223 x86_cpuinit.early_percpu_clock_init(); 224 preempt_disable(); 225 smp_callin(); 226 227 enable_start_cpu0 = 0; 228 229#ifdef CONFIG_X86_32 230 /* switch away from the initial page table */ 231 load_cr3(swapper_pg_dir); 232 __flush_tlb_all(); 233#endif 234 235 /* otherwise gcc will move up smp_processor_id before the cpu_init */ 236 barrier(); 237 /* 238 * Check TSC synchronization with the BP: 239 */ 240 check_tsc_sync_target(); 241 242 /* 243 * Enable the espfix hack for this CPU 244 */ 245#ifdef CONFIG_X86_ESPFIX64 246 init_espfix_ap(); 247#endif 248 249 /* 250 * We need to hold vector_lock so there the set of online cpus 251 * does not change while we are assigning vectors to cpus. Holding 252 * this lock ensures we don't half assign or remove an irq from a cpu. 253 */ 254 lock_vector_lock(); 255 set_cpu_online(smp_processor_id(), true); 256 unlock_vector_lock(); 257 cpu_set_state_online(smp_processor_id()); 258 x86_platform.nmi_init(); 259 260 /* enable local interrupts */ 261 local_irq_enable(); 262 263 /* to prevent fake stack check failure in clock setup */ 264 boot_init_stack_canary(); 265 266 x86_cpuinit.setup_percpu_clockev(); 267 268 wmb(); 269 cpu_startup_entry(CPUHP_ONLINE); 270} 271 272void __init smp_store_boot_cpu_info(void) 273{ 274 int id = 0; /* CPU 0 */ 275 struct cpuinfo_x86 *c = &cpu_data(id); 276 277 *c = boot_cpu_data; 278 c->cpu_index = id; 279} 280 281/* 282 * The bootstrap kernel entry code has set these up. Save them for 283 * a given CPU 284 */ 285void smp_store_cpu_info(int id) 286{ 287 struct cpuinfo_x86 *c = &cpu_data(id); 288 289 *c = boot_cpu_data; 290 c->cpu_index = id; 291 /* 292 * During boot time, CPU0 has this setup already. Save the info when 293 * bringing up AP or offlined CPU0. 294 */ 295 identify_secondary_cpu(c); 296} 297 298static bool 299topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 300{ 301 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 302 303 return (cpu_to_node(cpu1) == cpu_to_node(cpu2)); 304} 305 306static bool 307topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name) 308{ 309 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 310 311 return !WARN_ONCE(!topology_same_node(c, o), 312 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! " 313 "[node: %d != %d]. Ignoring dependency.\n", 314 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2)); 315} 316 317#define link_mask(_m, c1, c2) \ 318do { \ 319 cpumask_set_cpu((c1), cpu_##_m##_mask(c2)); \ 320 cpumask_set_cpu((c2), cpu_##_m##_mask(c1)); \ 321} while (0) 322 323static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 324{ 325 if (cpu_has_topoext) { 326 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 327 328 if (c->phys_proc_id == o->phys_proc_id && 329 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2) && 330 c->compute_unit_id == o->compute_unit_id) 331 return topology_sane(c, o, "smt"); 332 333 } else if (c->phys_proc_id == o->phys_proc_id && 334 c->cpu_core_id == o->cpu_core_id) { 335 return topology_sane(c, o, "smt"); 336 } 337 338 return false; 339} 340 341static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 342{ 343 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 344 345 if (per_cpu(cpu_llc_id, cpu1) != BAD_APICID && 346 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) 347 return topology_sane(c, o, "llc"); 348 349 return false; 350} 351 352/* 353 * Unlike the other levels, we do not enforce keeping a 354 * multicore group inside a NUMA node. If this happens, we will 355 * discard the MC level of the topology later. 356 */ 357static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 358{ 359 if (c->phys_proc_id == o->phys_proc_id) 360 return true; 361 return false; 362} 363 364static struct sched_domain_topology_level numa_inside_package_topology[] = { 365#ifdef CONFIG_SCHED_SMT 366 { cpu_smt_mask, cpu_smt_flags, SD_INIT_NAME(SMT) }, 367#endif 368#ifdef CONFIG_SCHED_MC 369 { cpu_coregroup_mask, cpu_core_flags, SD_INIT_NAME(MC) }, 370#endif 371 { NULL, }, 372}; 373/* 374 * set_sched_topology() sets the topology internal to a CPU. The 375 * NUMA topologies are layered on top of it to build the full 376 * system topology. 377 * 378 * If NUMA nodes are observed to occur within a CPU package, this 379 * function should be called. It forces the sched domain code to 380 * only use the SMT level for the CPU portion of the topology. 381 * This essentially falls back to relying on NUMA information 382 * from the SRAT table to describe the entire system topology 383 * (except for hyperthreads). 384 */ 385static void primarily_use_numa_for_topology(void) 386{ 387 set_sched_topology(numa_inside_package_topology); 388} 389 390void set_cpu_sibling_map(int cpu) 391{ 392 bool has_smt = smp_num_siblings > 1; 393 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1; 394 struct cpuinfo_x86 *c = &cpu_data(cpu); 395 struct cpuinfo_x86 *o; 396 int i; 397 398 cpumask_set_cpu(cpu, cpu_sibling_setup_mask); 399 400 if (!has_mp) { 401 cpumask_set_cpu(cpu, cpu_sibling_mask(cpu)); 402 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu)); 403 cpumask_set_cpu(cpu, cpu_core_mask(cpu)); 404 c->booted_cores = 1; 405 return; 406 } 407 408 for_each_cpu(i, cpu_sibling_setup_mask) { 409 o = &cpu_data(i); 410 411 if ((i == cpu) || (has_smt && match_smt(c, o))) 412 link_mask(sibling, cpu, i); 413 414 if ((i == cpu) || (has_mp && match_llc(c, o))) 415 link_mask(llc_shared, cpu, i); 416 417 } 418 419 /* 420 * This needs a separate iteration over the cpus because we rely on all 421 * cpu_sibling_mask links to be set-up. 422 */ 423 for_each_cpu(i, cpu_sibling_setup_mask) { 424 o = &cpu_data(i); 425 426 if ((i == cpu) || (has_mp && match_die(c, o))) { 427 link_mask(core, cpu, i); 428 429 /* 430 * Does this new cpu bringup a new core? 431 */ 432 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) { 433 /* 434 * for each core in package, increment 435 * the booted_cores for this new cpu 436 */ 437 if (cpumask_first(cpu_sibling_mask(i)) == i) 438 c->booted_cores++; 439 /* 440 * increment the core count for all 441 * the other cpus in this package 442 */ 443 if (i != cpu) 444 cpu_data(i).booted_cores++; 445 } else if (i != cpu && !c->booted_cores) 446 c->booted_cores = cpu_data(i).booted_cores; 447 } 448 if (match_die(c, o) && !topology_same_node(c, o)) 449 primarily_use_numa_for_topology(); 450 } 451} 452 453/* maps the cpu to the sched domain representing multi-core */ 454const struct cpumask *cpu_coregroup_mask(int cpu) 455{ 456 return cpu_llc_shared_mask(cpu); 457} 458 459static void impress_friends(void) 460{ 461 int cpu; 462 unsigned long bogosum = 0; 463 /* 464 * Allow the user to impress friends. 465 */ 466 pr_debug("Before bogomips\n"); 467 for_each_possible_cpu(cpu) 468 if (cpumask_test_cpu(cpu, cpu_callout_mask)) 469 bogosum += cpu_data(cpu).loops_per_jiffy; 470 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n", 471 num_online_cpus(), 472 bogosum/(500000/HZ), 473 (bogosum/(5000/HZ))%100); 474 475 pr_debug("Before bogocount - setting activated=1\n"); 476} 477 478void __inquire_remote_apic(int apicid) 479{ 480 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; 481 const char * const names[] = { "ID", "VERSION", "SPIV" }; 482 int timeout; 483 u32 status; 484 485 pr_info("Inquiring remote APIC 0x%x...\n", apicid); 486 487 for (i = 0; i < ARRAY_SIZE(regs); i++) { 488 pr_info("... APIC 0x%x %s: ", apicid, names[i]); 489 490 /* 491 * Wait for idle. 492 */ 493 status = safe_apic_wait_icr_idle(); 494 if (status) 495 pr_cont("a previous APIC delivery may have failed\n"); 496 497 apic_icr_write(APIC_DM_REMRD | regs[i], apicid); 498 499 timeout = 0; 500 do { 501 udelay(100); 502 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; 503 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); 504 505 switch (status) { 506 case APIC_ICR_RR_VALID: 507 status = apic_read(APIC_RRR); 508 pr_cont("%08x\n", status); 509 break; 510 default: 511 pr_cont("failed\n"); 512 } 513 } 514} 515 516/* 517 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal 518 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this 519 * won't ... remember to clear down the APIC, etc later. 520 */ 521int 522wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip) 523{ 524 unsigned long send_status, accept_status = 0; 525 int maxlvt; 526 527 /* Target chip */ 528 /* Boot on the stack */ 529 /* Kick the second */ 530 apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid); 531 532 pr_debug("Waiting for send to finish...\n"); 533 send_status = safe_apic_wait_icr_idle(); 534 535 /* 536 * Give the other CPU some time to accept the IPI. 537 */ 538 udelay(200); 539 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { 540 maxlvt = lapic_get_maxlvt(); 541 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 542 apic_write(APIC_ESR, 0); 543 accept_status = (apic_read(APIC_ESR) & 0xEF); 544 } 545 pr_debug("NMI sent\n"); 546 547 if (send_status) 548 pr_err("APIC never delivered???\n"); 549 if (accept_status) 550 pr_err("APIC delivery error (%lx)\n", accept_status); 551 552 return (send_status | accept_status); 553} 554 555static int 556wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) 557{ 558 unsigned long send_status, accept_status = 0; 559 int maxlvt, num_starts, j; 560 561 maxlvt = lapic_get_maxlvt(); 562 563 /* 564 * Be paranoid about clearing APIC errors. 565 */ 566 if (APIC_INTEGRATED(apic_version[phys_apicid])) { 567 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 568 apic_write(APIC_ESR, 0); 569 apic_read(APIC_ESR); 570 } 571 572 pr_debug("Asserting INIT\n"); 573 574 /* 575 * Turn INIT on target chip 576 */ 577 /* 578 * Send IPI 579 */ 580 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, 581 phys_apicid); 582 583 pr_debug("Waiting for send to finish...\n"); 584 send_status = safe_apic_wait_icr_idle(); 585 586 mdelay(10); 587 588 pr_debug("Deasserting INIT\n"); 589 590 /* Target chip */ 591 /* Send IPI */ 592 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); 593 594 pr_debug("Waiting for send to finish...\n"); 595 send_status = safe_apic_wait_icr_idle(); 596 597 mb(); 598 atomic_set(&init_deasserted, 1); 599 600 /* 601 * Should we send STARTUP IPIs ? 602 * 603 * Determine this based on the APIC version. 604 * If we don't have an integrated APIC, don't send the STARTUP IPIs. 605 */ 606 if (APIC_INTEGRATED(apic_version[phys_apicid])) 607 num_starts = 2; 608 else 609 num_starts = 0; 610 611 /* 612 * Paravirt / VMI wants a startup IPI hook here to set up the 613 * target processor state. 614 */ 615 startup_ipi_hook(phys_apicid, (unsigned long) start_secondary, 616 stack_start); 617 618 /* 619 * Run STARTUP IPI loop. 620 */ 621 pr_debug("#startup loops: %d\n", num_starts); 622 623 for (j = 1; j <= num_starts; j++) { 624 pr_debug("Sending STARTUP #%d\n", j); 625 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 626 apic_write(APIC_ESR, 0); 627 apic_read(APIC_ESR); 628 pr_debug("After apic_write\n"); 629 630 /* 631 * STARTUP IPI 632 */ 633 634 /* Target chip */ 635 /* Boot on the stack */ 636 /* Kick the second */ 637 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), 638 phys_apicid); 639 640 /* 641 * Give the other CPU some time to accept the IPI. 642 */ 643 udelay(300); 644 645 pr_debug("Startup point 1\n"); 646 647 pr_debug("Waiting for send to finish...\n"); 648 send_status = safe_apic_wait_icr_idle(); 649 650 /* 651 * Give the other CPU some time to accept the IPI. 652 */ 653 udelay(200); 654 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 655 apic_write(APIC_ESR, 0); 656 accept_status = (apic_read(APIC_ESR) & 0xEF); 657 if (send_status || accept_status) 658 break; 659 } 660 pr_debug("After Startup\n"); 661 662 if (send_status) 663 pr_err("APIC never delivered???\n"); 664 if (accept_status) 665 pr_err("APIC delivery error (%lx)\n", accept_status); 666 667 return (send_status | accept_status); 668} 669 670void smp_announce(void) 671{ 672 int num_nodes = num_online_nodes(); 673 674 printk(KERN_INFO "x86: Booted up %d node%s, %d CPUs\n", 675 num_nodes, (num_nodes > 1 ? "s" : ""), num_online_cpus()); 676} 677 678/* reduce the number of lines printed when booting a large cpu count system */ 679static void announce_cpu(int cpu, int apicid) 680{ 681 static int current_node = -1; 682 int node = early_cpu_to_node(cpu); 683 static int width, node_width; 684 685 if (!width) 686 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */ 687 688 if (!node_width) 689 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */ 690 691 if (cpu == 1) 692 printk(KERN_INFO "x86: Booting SMP configuration:\n"); 693 694 if (system_state == SYSTEM_BOOTING) { 695 if (node != current_node) { 696 if (current_node > (-1)) 697 pr_cont("\n"); 698 current_node = node; 699 700 printk(KERN_INFO ".... node %*s#%d, CPUs: ", 701 node_width - num_digits(node), " ", node); 702 } 703 704 /* Add padding for the BSP */ 705 if (cpu == 1) 706 pr_cont("%*s", width + 1, " "); 707 708 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu); 709 710 } else 711 pr_info("Booting Node %d Processor %d APIC 0x%x\n", 712 node, cpu, apicid); 713} 714 715static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs) 716{ 717 int cpu; 718 719 cpu = smp_processor_id(); 720 if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0) 721 return NMI_HANDLED; 722 723 return NMI_DONE; 724} 725 726/* 727 * Wake up AP by INIT, INIT, STARTUP sequence. 728 * 729 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS 730 * boot-strap code which is not a desired behavior for waking up BSP. To 731 * void the boot-strap code, wake up CPU0 by NMI instead. 732 * 733 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined 734 * (i.e. physically hot removed and then hot added), NMI won't wake it up. 735 * We'll change this code in the future to wake up hard offlined CPU0 if 736 * real platform and request are available. 737 */ 738static int 739wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid, 740 int *cpu0_nmi_registered) 741{ 742 int id; 743 int boot_error; 744 745 preempt_disable(); 746 747 /* 748 * Wake up AP by INIT, INIT, STARTUP sequence. 749 */ 750 if (cpu) { 751 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip); 752 goto out; 753 } 754 755 /* 756 * Wake up BSP by nmi. 757 * 758 * Register a NMI handler to help wake up CPU0. 759 */ 760 boot_error = register_nmi_handler(NMI_LOCAL, 761 wakeup_cpu0_nmi, 0, "wake_cpu0"); 762 763 if (!boot_error) { 764 enable_start_cpu0 = 1; 765 *cpu0_nmi_registered = 1; 766 if (apic->dest_logical == APIC_DEST_LOGICAL) 767 id = cpu0_logical_apicid; 768 else 769 id = apicid; 770 boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip); 771 } 772 773out: 774 preempt_enable(); 775 776 return boot_error; 777} 778 779void common_cpu_up(unsigned int cpu, struct task_struct *idle) 780{ 781 /* Just in case we booted with a single CPU. */ 782 alternatives_enable_smp(); 783 784 per_cpu(current_task, cpu) = idle; 785 786#ifdef CONFIG_X86_32 787 /* Stack for startup_32 can be just as for start_secondary onwards */ 788 irq_ctx_init(cpu); 789 per_cpu(cpu_current_top_of_stack, cpu) = 790 (unsigned long)task_stack_page(idle) + THREAD_SIZE; 791#else 792 clear_tsk_thread_flag(idle, TIF_FORK); 793 initial_gs = per_cpu_offset(cpu); 794#endif 795 per_cpu(kernel_stack, cpu) = 796 (unsigned long)task_stack_page(idle) + THREAD_SIZE; 797} 798 799/* 800 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad 801 * (ie clustered apic addressing mode), this is a LOGICAL apic ID. 802 * Returns zero if CPU booted OK, else error code from 803 * ->wakeup_secondary_cpu. 804 */ 805static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle) 806{ 807 volatile u32 *trampoline_status = 808 (volatile u32 *) __va(real_mode_header->trampoline_status); 809 /* start_ip had better be page-aligned! */ 810 unsigned long start_ip = real_mode_header->trampoline_start; 811 812 unsigned long boot_error = 0; 813 int cpu0_nmi_registered = 0; 814 unsigned long timeout; 815 816 idle->thread.sp = (unsigned long) (((struct pt_regs *) 817 (THREAD_SIZE + task_stack_page(idle))) - 1); 818 819 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu); 820 initial_code = (unsigned long)start_secondary; 821 stack_start = idle->thread.sp; 822 823 /* So we see what's up */ 824 announce_cpu(cpu, apicid); 825 826 /* 827 * This grunge runs the startup process for 828 * the targeted processor. 829 */ 830 831 atomic_set(&init_deasserted, 0); 832 833 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { 834 835 pr_debug("Setting warm reset code and vector.\n"); 836 837 smpboot_setup_warm_reset_vector(start_ip); 838 /* 839 * Be paranoid about clearing APIC errors. 840 */ 841 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { 842 apic_write(APIC_ESR, 0); 843 apic_read(APIC_ESR); 844 } 845 } 846 847 /* 848 * AP might wait on cpu_callout_mask in cpu_init() with 849 * cpu_initialized_mask set if previous attempt to online 850 * it timed-out. Clear cpu_initialized_mask so that after 851 * INIT/SIPI it could start with a clean state. 852 */ 853 cpumask_clear_cpu(cpu, cpu_initialized_mask); 854 smp_mb(); 855 856 /* 857 * Wake up a CPU in difference cases: 858 * - Use the method in the APIC driver if it's defined 859 * Otherwise, 860 * - Use an INIT boot APIC message for APs or NMI for BSP. 861 */ 862 if (apic->wakeup_secondary_cpu) 863 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip); 864 else 865 boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid, 866 &cpu0_nmi_registered); 867 868 if (!boot_error) { 869 /* 870 * Wait 10s total for a response from AP 871 */ 872 boot_error = -1; 873 timeout = jiffies + 10*HZ; 874 while (time_before(jiffies, timeout)) { 875 if (cpumask_test_cpu(cpu, cpu_initialized_mask)) { 876 /* 877 * Tell AP to proceed with initialization 878 */ 879 cpumask_set_cpu(cpu, cpu_callout_mask); 880 boot_error = 0; 881 break; 882 } 883 udelay(100); 884 schedule(); 885 } 886 } 887 888 if (!boot_error) { 889 /* 890 * Wait till AP completes initial initialization 891 */ 892 while (!cpumask_test_cpu(cpu, cpu_callin_mask)) { 893 /* 894 * Allow other tasks to run while we wait for the 895 * AP to come online. This also gives a chance 896 * for the MTRR work(triggered by the AP coming online) 897 * to be completed in the stop machine context. 898 */ 899 udelay(100); 900 schedule(); 901 } 902 } 903 904 /* mark "stuck" area as not stuck */ 905 *trampoline_status = 0; 906 907 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { 908 /* 909 * Cleanup possible dangling ends... 910 */ 911 smpboot_restore_warm_reset_vector(); 912 } 913 /* 914 * Clean up the nmi handler. Do this after the callin and callout sync 915 * to avoid impact of possible long unregister time. 916 */ 917 if (cpu0_nmi_registered) 918 unregister_nmi_handler(NMI_LOCAL, "wake_cpu0"); 919 920 return boot_error; 921} 922 923int native_cpu_up(unsigned int cpu, struct task_struct *tidle) 924{ 925 int apicid = apic->cpu_present_to_apicid(cpu); 926 unsigned long flags; 927 int err; 928 929 WARN_ON(irqs_disabled()); 930 931 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); 932 933 if (apicid == BAD_APICID || 934 !physid_isset(apicid, phys_cpu_present_map) || 935 !apic->apic_id_valid(apicid)) { 936 pr_err("%s: bad cpu %d\n", __func__, cpu); 937 return -EINVAL; 938 } 939 940 /* 941 * Already booted CPU? 942 */ 943 if (cpumask_test_cpu(cpu, cpu_callin_mask)) { 944 pr_debug("do_boot_cpu %d Already started\n", cpu); 945 return -ENOSYS; 946 } 947 948 /* 949 * Save current MTRR state in case it was changed since early boot 950 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: 951 */ 952 mtrr_save_state(); 953 954 /* x86 CPUs take themselves offline, so delayed offline is OK. */ 955 err = cpu_check_up_prepare(cpu); 956 if (err && err != -EBUSY) 957 return err; 958 959 /* the FPU context is blank, nobody can own it */ 960 __cpu_disable_lazy_restore(cpu); 961 962 common_cpu_up(cpu, tidle); 963 964 err = do_boot_cpu(apicid, cpu, tidle); 965 if (err) { 966 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu); 967 return -EIO; 968 } 969 970 /* 971 * Check TSC synchronization with the AP (keep irqs disabled 972 * while doing so): 973 */ 974 local_irq_save(flags); 975 check_tsc_sync_source(cpu); 976 local_irq_restore(flags); 977 978 while (!cpu_online(cpu)) { 979 cpu_relax(); 980 touch_nmi_watchdog(); 981 } 982 983 return 0; 984} 985 986/** 987 * arch_disable_smp_support() - disables SMP support for x86 at runtime 988 */ 989void arch_disable_smp_support(void) 990{ 991 disable_ioapic_support(); 992} 993 994/* 995 * Fall back to non SMP mode after errors. 996 * 997 * RED-PEN audit/test this more. I bet there is more state messed up here. 998 */ 999static __init void disable_smp(void) 1000{ 1001 pr_info("SMP disabled\n"); 1002 1003 disable_ioapic_support(); 1004 1005 init_cpu_present(cpumask_of(0)); 1006 init_cpu_possible(cpumask_of(0)); 1007 1008 if (smp_found_config) 1009 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 1010 else 1011 physid_set_mask_of_physid(0, &phys_cpu_present_map); 1012 cpumask_set_cpu(0, cpu_sibling_mask(0)); 1013 cpumask_set_cpu(0, cpu_core_mask(0)); 1014} 1015 1016enum { 1017 SMP_OK, 1018 SMP_NO_CONFIG, 1019 SMP_NO_APIC, 1020 SMP_FORCE_UP, 1021}; 1022 1023/* 1024 * Various sanity checks. 1025 */ 1026static int __init smp_sanity_check(unsigned max_cpus) 1027{ 1028 preempt_disable(); 1029 1030#if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) 1031 if (def_to_bigsmp && nr_cpu_ids > 8) { 1032 unsigned int cpu; 1033 unsigned nr; 1034 1035 pr_warn("More than 8 CPUs detected - skipping them\n" 1036 "Use CONFIG_X86_BIGSMP\n"); 1037 1038 nr = 0; 1039 for_each_present_cpu(cpu) { 1040 if (nr >= 8) 1041 set_cpu_present(cpu, false); 1042 nr++; 1043 } 1044 1045 nr = 0; 1046 for_each_possible_cpu(cpu) { 1047 if (nr >= 8) 1048 set_cpu_possible(cpu, false); 1049 nr++; 1050 } 1051 1052 nr_cpu_ids = 8; 1053 } 1054#endif 1055 1056 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { 1057 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n", 1058 hard_smp_processor_id()); 1059 1060 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1061 } 1062 1063 /* 1064 * If we couldn't find an SMP configuration at boot time, 1065 * get out of here now! 1066 */ 1067 if (!smp_found_config && !acpi_lapic) { 1068 preempt_enable(); 1069 pr_notice("SMP motherboard not detected\n"); 1070 return SMP_NO_CONFIG; 1071 } 1072 1073 /* 1074 * Should not be necessary because the MP table should list the boot 1075 * CPU too, but we do it for the sake of robustness anyway. 1076 */ 1077 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { 1078 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n", 1079 boot_cpu_physical_apicid); 1080 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1081 } 1082 preempt_enable(); 1083 1084 /* 1085 * If we couldn't find a local APIC, then get out of here now! 1086 */ 1087 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && 1088 !cpu_has_apic) { 1089 if (!disable_apic) { 1090 pr_err("BIOS bug, local APIC #%d not detected!...\n", 1091 boot_cpu_physical_apicid); 1092 pr_err("... forcing use of dummy APIC emulation (tell your hw vendor)\n"); 1093 } 1094 return SMP_NO_APIC; 1095 } 1096 1097 /* 1098 * If SMP should be disabled, then really disable it! 1099 */ 1100 if (!max_cpus) { 1101 pr_info("SMP mode deactivated\n"); 1102 return SMP_FORCE_UP; 1103 } 1104 1105 return SMP_OK; 1106} 1107 1108static void __init smp_cpu_index_default(void) 1109{ 1110 int i; 1111 struct cpuinfo_x86 *c; 1112 1113 for_each_possible_cpu(i) { 1114 c = &cpu_data(i); 1115 /* mark all to hotplug */ 1116 c->cpu_index = nr_cpu_ids; 1117 } 1118} 1119 1120/* 1121 * Prepare for SMP bootup. The MP table or ACPI has been read 1122 * earlier. Just do some sanity checking here and enable APIC mode. 1123 */ 1124void __init native_smp_prepare_cpus(unsigned int max_cpus) 1125{ 1126 unsigned int i; 1127 1128 smp_cpu_index_default(); 1129 1130 /* 1131 * Setup boot CPU information 1132 */ 1133 smp_store_boot_cpu_info(); /* Final full version of the data */ 1134 cpumask_copy(cpu_callin_mask, cpumask_of(0)); 1135 mb(); 1136 1137 current_thread_info()->cpu = 0; /* needed? */ 1138 for_each_possible_cpu(i) { 1139 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); 1140 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); 1141 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL); 1142 } 1143 set_cpu_sibling_map(0); 1144 1145 switch (smp_sanity_check(max_cpus)) { 1146 case SMP_NO_CONFIG: 1147 disable_smp(); 1148 if (APIC_init_uniprocessor()) 1149 pr_notice("Local APIC not detected. Using dummy APIC emulation.\n"); 1150 return; 1151 case SMP_NO_APIC: 1152 disable_smp(); 1153 return; 1154 case SMP_FORCE_UP: 1155 disable_smp(); 1156 apic_bsp_setup(false); 1157 return; 1158 case SMP_OK: 1159 break; 1160 } 1161 1162 default_setup_apic_routing(); 1163 1164 if (read_apic_id() != boot_cpu_physical_apicid) { 1165 panic("Boot APIC ID in local APIC unexpected (%d vs %d)", 1166 read_apic_id(), boot_cpu_physical_apicid); 1167 /* Or can we switch back to PIC here? */ 1168 } 1169 1170 cpu0_logical_apicid = apic_bsp_setup(false); 1171 1172 pr_info("CPU%d: ", 0); 1173 print_cpu_info(&cpu_data(0)); 1174 1175 if (is_uv_system()) 1176 uv_system_init(); 1177 1178 set_mtrr_aps_delayed_init(); 1179} 1180 1181void arch_enable_nonboot_cpus_begin(void) 1182{ 1183 set_mtrr_aps_delayed_init(); 1184} 1185 1186void arch_enable_nonboot_cpus_end(void) 1187{ 1188 mtrr_aps_init(); 1189} 1190 1191/* 1192 * Early setup to make printk work. 1193 */ 1194void __init native_smp_prepare_boot_cpu(void) 1195{ 1196 int me = smp_processor_id(); 1197 switch_to_new_gdt(me); 1198 /* already set me in cpu_online_mask in boot_cpu_init() */ 1199 cpumask_set_cpu(me, cpu_callout_mask); 1200 cpu_set_state_online(me); 1201} 1202 1203void __init native_smp_cpus_done(unsigned int max_cpus) 1204{ 1205 pr_debug("Boot done\n"); 1206 1207 nmi_selftest(); 1208 impress_friends(); 1209 setup_ioapic_dest(); 1210 mtrr_aps_init(); 1211} 1212 1213static int __initdata setup_possible_cpus = -1; 1214static int __init _setup_possible_cpus(char *str) 1215{ 1216 get_option(&str, &setup_possible_cpus); 1217 return 0; 1218} 1219early_param("possible_cpus", _setup_possible_cpus); 1220 1221 1222/* 1223 * cpu_possible_mask should be static, it cannot change as cpu's 1224 * are onlined, or offlined. The reason is per-cpu data-structures 1225 * are allocated by some modules at init time, and dont expect to 1226 * do this dynamically on cpu arrival/departure. 1227 * cpu_present_mask on the other hand can change dynamically. 1228 * In case when cpu_hotplug is not compiled, then we resort to current 1229 * behaviour, which is cpu_possible == cpu_present. 1230 * - Ashok Raj 1231 * 1232 * Three ways to find out the number of additional hotplug CPUs: 1233 * - If the BIOS specified disabled CPUs in ACPI/mptables use that. 1234 * - The user can overwrite it with possible_cpus=NUM 1235 * - Otherwise don't reserve additional CPUs. 1236 * We do this because additional CPUs waste a lot of memory. 1237 * -AK 1238 */ 1239__init void prefill_possible_map(void) 1240{ 1241 int i, possible; 1242 1243 /* no processor from mptable or madt */ 1244 if (!num_processors) 1245 num_processors = 1; 1246 1247 i = setup_max_cpus ?: 1; 1248 if (setup_possible_cpus == -1) { 1249 possible = num_processors; 1250#ifdef CONFIG_HOTPLUG_CPU 1251 if (setup_max_cpus) 1252 possible += disabled_cpus; 1253#else 1254 if (possible > i) 1255 possible = i; 1256#endif 1257 } else 1258 possible = setup_possible_cpus; 1259 1260 total_cpus = max_t(int, possible, num_processors + disabled_cpus); 1261 1262 /* nr_cpu_ids could be reduced via nr_cpus= */ 1263 if (possible > nr_cpu_ids) { 1264 pr_warn("%d Processors exceeds NR_CPUS limit of %d\n", 1265 possible, nr_cpu_ids); 1266 possible = nr_cpu_ids; 1267 } 1268 1269#ifdef CONFIG_HOTPLUG_CPU 1270 if (!setup_max_cpus) 1271#endif 1272 if (possible > i) { 1273 pr_warn("%d Processors exceeds max_cpus limit of %u\n", 1274 possible, setup_max_cpus); 1275 possible = i; 1276 } 1277 1278 pr_info("Allowing %d CPUs, %d hotplug CPUs\n", 1279 possible, max_t(int, possible - num_processors, 0)); 1280 1281 for (i = 0; i < possible; i++) 1282 set_cpu_possible(i, true); 1283 for (; i < NR_CPUS; i++) 1284 set_cpu_possible(i, false); 1285 1286 nr_cpu_ids = possible; 1287} 1288 1289#ifdef CONFIG_HOTPLUG_CPU 1290 1291static void remove_siblinginfo(int cpu) 1292{ 1293 int sibling; 1294 struct cpuinfo_x86 *c = &cpu_data(cpu); 1295 1296 for_each_cpu(sibling, cpu_core_mask(cpu)) { 1297 cpumask_clear_cpu(cpu, cpu_core_mask(sibling)); 1298 /*/ 1299 * last thread sibling in this cpu core going down 1300 */ 1301 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) 1302 cpu_data(sibling).booted_cores--; 1303 } 1304 1305 for_each_cpu(sibling, cpu_sibling_mask(cpu)) 1306 cpumask_clear_cpu(cpu, cpu_sibling_mask(sibling)); 1307 for_each_cpu(sibling, cpu_llc_shared_mask(cpu)) 1308 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling)); 1309 cpumask_clear(cpu_llc_shared_mask(cpu)); 1310 cpumask_clear(cpu_sibling_mask(cpu)); 1311 cpumask_clear(cpu_core_mask(cpu)); 1312 c->phys_proc_id = 0; 1313 c->cpu_core_id = 0; 1314 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); 1315} 1316 1317static void __ref remove_cpu_from_maps(int cpu) 1318{ 1319 set_cpu_online(cpu, false); 1320 cpumask_clear_cpu(cpu, cpu_callout_mask); 1321 cpumask_clear_cpu(cpu, cpu_callin_mask); 1322 /* was set by cpu_init() */ 1323 cpumask_clear_cpu(cpu, cpu_initialized_mask); 1324 numa_remove_cpu(cpu); 1325} 1326 1327void cpu_disable_common(void) 1328{ 1329 int cpu = smp_processor_id(); 1330 1331 remove_siblinginfo(cpu); 1332 1333 /* It's now safe to remove this processor from the online map */ 1334 lock_vector_lock(); 1335 remove_cpu_from_maps(cpu); 1336 unlock_vector_lock(); 1337 fixup_irqs(); 1338} 1339 1340int native_cpu_disable(void) 1341{ 1342 int ret; 1343 1344 ret = check_irq_vectors_for_cpu_disable(); 1345 if (ret) 1346 return ret; 1347 1348 clear_local_APIC(); 1349 cpu_disable_common(); 1350 1351 return 0; 1352} 1353 1354int common_cpu_die(unsigned int cpu) 1355{ 1356 int ret = 0; 1357 1358 /* We don't do anything here: idle task is faking death itself. */ 1359 1360 /* They ack this in play_dead() by setting CPU_DEAD */ 1361 if (cpu_wait_death(cpu, 5)) { 1362 if (system_state == SYSTEM_RUNNING) 1363 pr_info("CPU %u is now offline\n", cpu); 1364 } else { 1365 pr_err("CPU %u didn't die...\n", cpu); 1366 ret = -1; 1367 } 1368 1369 return ret; 1370} 1371 1372void native_cpu_die(unsigned int cpu) 1373{ 1374 common_cpu_die(cpu); 1375} 1376 1377void play_dead_common(void) 1378{ 1379 idle_task_exit(); 1380 reset_lazy_tlbstate(); 1381 amd_e400_remove_cpu(raw_smp_processor_id()); 1382 1383 /* Ack it */ 1384 (void)cpu_report_death(); 1385 1386 /* 1387 * With physical CPU hotplug, we should halt the cpu 1388 */ 1389 local_irq_disable(); 1390} 1391 1392static bool wakeup_cpu0(void) 1393{ 1394 if (smp_processor_id() == 0 && enable_start_cpu0) 1395 return true; 1396 1397 return false; 1398} 1399 1400/* 1401 * We need to flush the caches before going to sleep, lest we have 1402 * dirty data in our caches when we come back up. 1403 */ 1404static inline void mwait_play_dead(void) 1405{ 1406 unsigned int eax, ebx, ecx, edx; 1407 unsigned int highest_cstate = 0; 1408 unsigned int highest_subcstate = 0; 1409 void *mwait_ptr; 1410 int i; 1411 1412 if (!this_cpu_has(X86_FEATURE_MWAIT)) 1413 return; 1414 if (!this_cpu_has(X86_FEATURE_CLFLUSH)) 1415 return; 1416 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF) 1417 return; 1418 1419 eax = CPUID_MWAIT_LEAF; 1420 ecx = 0; 1421 native_cpuid(&eax, &ebx, &ecx, &edx); 1422 1423 /* 1424 * eax will be 0 if EDX enumeration is not valid. 1425 * Initialized below to cstate, sub_cstate value when EDX is valid. 1426 */ 1427 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) { 1428 eax = 0; 1429 } else { 1430 edx >>= MWAIT_SUBSTATE_SIZE; 1431 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) { 1432 if (edx & MWAIT_SUBSTATE_MASK) { 1433 highest_cstate = i; 1434 highest_subcstate = edx & MWAIT_SUBSTATE_MASK; 1435 } 1436 } 1437 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) | 1438 (highest_subcstate - 1); 1439 } 1440 1441 /* 1442 * This should be a memory location in a cache line which is 1443 * unlikely to be touched by other processors. The actual 1444 * content is immaterial as it is not actually modified in any way. 1445 */ 1446 mwait_ptr = ¤t_thread_info()->flags; 1447 1448 wbinvd(); 1449 1450 while (1) { 1451 /* 1452 * The CLFLUSH is a workaround for erratum AAI65 for 1453 * the Xeon 7400 series. It's not clear it is actually 1454 * needed, but it should be harmless in either case. 1455 * The WBINVD is insufficient due to the spurious-wakeup 1456 * case where we return around the loop. 1457 */ 1458 mb(); 1459 clflush(mwait_ptr); 1460 mb(); 1461 __monitor(mwait_ptr, 0, 0); 1462 mb(); 1463 __mwait(eax, 0); 1464 /* 1465 * If NMI wants to wake up CPU0, start CPU0. 1466 */ 1467 if (wakeup_cpu0()) 1468 start_cpu0(); 1469 } 1470} 1471 1472static inline void hlt_play_dead(void) 1473{ 1474 if (__this_cpu_read(cpu_info.x86) >= 4) 1475 wbinvd(); 1476 1477 while (1) { 1478 native_halt(); 1479 /* 1480 * If NMI wants to wake up CPU0, start CPU0. 1481 */ 1482 if (wakeup_cpu0()) 1483 start_cpu0(); 1484 } 1485} 1486 1487void native_play_dead(void) 1488{ 1489 play_dead_common(); 1490 tboot_shutdown(TB_SHUTDOWN_WFS); 1491 1492 mwait_play_dead(); /* Only returns on failure */ 1493 if (cpuidle_play_dead()) 1494 hlt_play_dead(); 1495} 1496 1497#else /* ... !CONFIG_HOTPLUG_CPU */ 1498int native_cpu_disable(void) 1499{ 1500 return -ENOSYS; 1501} 1502 1503void native_cpu_die(unsigned int cpu) 1504{ 1505 /* We said "no" in __cpu_disable */ 1506 BUG(); 1507} 1508 1509void native_play_dead(void) 1510{ 1511 BUG(); 1512} 1513 1514#endif 1515