1/*
2 *	Intel CPU Microcode Update Driver for Linux
3 *
4 *	Copyright (C) 2000-2006 Tigran Aivazian <tigran@aivazian.fsnet.co.uk>
5 *		      2006	Shaohua Li <shaohua.li@intel.com>
6 *
7 *	This driver allows to upgrade microcode on Intel processors
8 *	belonging to IA-32 family - PentiumPro, Pentium II,
9 *	Pentium III, Xeon, Pentium 4, etc.
10 *
11 *	Reference: Section 8.11 of Volume 3a, IA-32 Intel? Architecture
12 *	Software Developer's Manual
13 *	Order Number 253668 or free download from:
14 *
15 *	http://developer.intel.com/Assets/PDF/manual/253668.pdf
16 *
17 *	For more information, go to http://www.urbanmyth.org/microcode
18 *
19 *	This program is free software; you can redistribute it and/or
20 *	modify it under the terms of the GNU General Public License
21 *	as published by the Free Software Foundation; either version
22 *	2 of the License, or (at your option) any later version.
23 *
24 *	1.0	16 Feb 2000, Tigran Aivazian <tigran@sco.com>
25 *		Initial release.
26 *	1.01	18 Feb 2000, Tigran Aivazian <tigran@sco.com>
27 *		Added read() support + cleanups.
28 *	1.02	21 Feb 2000, Tigran Aivazian <tigran@sco.com>
29 *		Added 'device trimming' support. open(O_WRONLY) zeroes
30 *		and frees the saved copy of applied microcode.
31 *	1.03	29 Feb 2000, Tigran Aivazian <tigran@sco.com>
32 *		Made to use devfs (/dev/cpu/microcode) + cleanups.
33 *	1.04	06 Jun 2000, Simon Trimmer <simon@veritas.com>
34 *		Added misc device support (now uses both devfs and misc).
35 *		Added MICROCODE_IOCFREE ioctl to clear memory.
36 *	1.05	09 Jun 2000, Simon Trimmer <simon@veritas.com>
37 *		Messages for error cases (non Intel & no suitable microcode).
38 *	1.06	03 Aug 2000, Tigran Aivazian <tigran@veritas.com>
39 *		Removed ->release(). Removed exclusive open and status bitmap.
40 *		Added microcode_rwsem to serialize read()/write()/ioctl().
41 *		Removed global kernel lock usage.
42 *	1.07	07 Sep 2000, Tigran Aivazian <tigran@veritas.com>
43 *		Write 0 to 0x8B msr and then cpuid before reading revision,
44 *		so that it works even if there were no update done by the
45 *		BIOS. Otherwise, reading from 0x8B gives junk (which happened
46 *		to be 0 on my machine which is why it worked even when I
47 *		disabled update by the BIOS)
48 *		Thanks to Eric W. Biederman <ebiederman@lnxi.com> for the fix.
49 *	1.08	11 Dec 2000, Richard Schaal <richard.schaal@intel.com> and
50 *			     Tigran Aivazian <tigran@veritas.com>
51 *		Intel Pentium 4 processor support and bugfixes.
52 *	1.09	30 Oct 2001, Tigran Aivazian <tigran@veritas.com>
53 *		Bugfix for HT (Hyper-Threading) enabled processors
54 *		whereby processor resources are shared by all logical processors
55 *		in a single CPU package.
56 *	1.10	28 Feb 2002 Asit K Mallick <asit.k.mallick@intel.com> and
57 *		Tigran Aivazian <tigran@veritas.com>,
58 *		Serialize updates as required on HT processors due to
59 *		speculative nature of implementation.
60 *	1.11	22 Mar 2002 Tigran Aivazian <tigran@veritas.com>
61 *		Fix the panic when writing zero-length microcode chunk.
62 *	1.12	29 Sep 2003 Nitin Kamble <nitin.a.kamble@intel.com>,
63 *		Jun Nakajima <jun.nakajima@intel.com>
64 *		Support for the microcode updates in the new format.
65 *	1.13	10 Oct 2003 Tigran Aivazian <tigran@veritas.com>
66 *		Removed ->read() method and obsoleted MICROCODE_IOCFREE ioctl
67 *		because we no longer hold a copy of applied microcode
68 *		in kernel memory.
69 *	1.14	25 Jun 2004 Tigran Aivazian <tigran@veritas.com>
70 *		Fix sigmatch() macro to handle old CPUs with pf == 0.
71 *		Thanks to Stuart Swales for pointing out this bug.
72 */
73
74#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
75
76#include <linux/firmware.h>
77#include <linux/uaccess.h>
78#include <linux/kernel.h>
79#include <linux/module.h>
80#include <linux/vmalloc.h>
81
82#include <asm/microcode_intel.h>
83#include <asm/processor.h>
84#include <asm/msr.h>
85
86MODULE_DESCRIPTION("Microcode Update Driver");
87MODULE_AUTHOR("Tigran Aivazian <tigran@aivazian.fsnet.co.uk>");
88MODULE_LICENSE("GPL");
89
90static int collect_cpu_info(int cpu_num, struct cpu_signature *csig)
91{
92	struct cpuinfo_x86 *c = &cpu_data(cpu_num);
93	unsigned int val[2];
94
95	memset(csig, 0, sizeof(*csig));
96
97	csig->sig = cpuid_eax(0x00000001);
98
99	if ((c->x86_model >= 5) || (c->x86 > 6)) {
100		/* get processor flags from MSR 0x17 */
101		rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]);
102		csig->pf = 1 << ((val[1] >> 18) & 7);
103	}
104
105	csig->rev = c->microcode;
106	pr_info("CPU%d sig=0x%x, pf=0x%x, revision=0x%x\n",
107		cpu_num, csig->sig, csig->pf, csig->rev);
108
109	return 0;
110}
111
112/*
113 * return 0 - no update found
114 * return 1 - found update
115 */
116static int get_matching_mc(struct microcode_intel *mc_intel, int cpu)
117{
118	struct cpu_signature cpu_sig;
119	unsigned int csig, cpf, crev;
120
121	collect_cpu_info(cpu, &cpu_sig);
122
123	csig = cpu_sig.sig;
124	cpf = cpu_sig.pf;
125	crev = cpu_sig.rev;
126
127	return get_matching_microcode(csig, cpf, crev, mc_intel);
128}
129
130static int apply_microcode_intel(int cpu)
131{
132	struct microcode_intel *mc_intel;
133	struct ucode_cpu_info *uci;
134	unsigned int val[2];
135	int cpu_num = raw_smp_processor_id();
136	struct cpuinfo_x86 *c = &cpu_data(cpu_num);
137
138	uci = ucode_cpu_info + cpu;
139	mc_intel = uci->mc;
140
141	/* We should bind the task to the CPU */
142	BUG_ON(cpu_num != cpu);
143
144	if (mc_intel == NULL)
145		return 0;
146
147	/*
148	 * Microcode on this CPU could be updated earlier. Only apply the
149	 * microcode patch in mc_intel when it is newer than the one on this
150	 * CPU.
151	 */
152	if (get_matching_mc(mc_intel, cpu) == 0)
153		return 0;
154
155	/* write microcode via MSR 0x79 */
156	wrmsr(MSR_IA32_UCODE_WRITE,
157	      (unsigned long) mc_intel->bits,
158	      (unsigned long) mc_intel->bits >> 16 >> 16);
159	wrmsr(MSR_IA32_UCODE_REV, 0, 0);
160
161	/* As documented in the SDM: Do a CPUID 1 here */
162	sync_core();
163
164	/* get the current revision from MSR 0x8B */
165	rdmsr(MSR_IA32_UCODE_REV, val[0], val[1]);
166
167	if (val[1] != mc_intel->hdr.rev) {
168		pr_err("CPU%d update to revision 0x%x failed\n",
169		       cpu_num, mc_intel->hdr.rev);
170		return -1;
171	}
172	pr_info("CPU%d updated to revision 0x%x, date = %04x-%02x-%02x\n",
173		cpu_num, val[1],
174		mc_intel->hdr.date & 0xffff,
175		mc_intel->hdr.date >> 24,
176		(mc_intel->hdr.date >> 16) & 0xff);
177
178	uci->cpu_sig.rev = val[1];
179	c->microcode = val[1];
180
181	return 0;
182}
183
184static enum ucode_state generic_load_microcode(int cpu, void *data, size_t size,
185				int (*get_ucode_data)(void *, const void *, size_t))
186{
187	struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
188	u8 *ucode_ptr = data, *new_mc = NULL, *mc = NULL;
189	int new_rev = uci->cpu_sig.rev;
190	unsigned int leftover = size;
191	enum ucode_state state = UCODE_OK;
192	unsigned int curr_mc_size = 0;
193	unsigned int csig, cpf;
194
195	while (leftover) {
196		struct microcode_header_intel mc_header;
197		unsigned int mc_size;
198
199		if (leftover < sizeof(mc_header)) {
200			pr_err("error! Truncated header in microcode data file\n");
201			break;
202		}
203
204		if (get_ucode_data(&mc_header, ucode_ptr, sizeof(mc_header)))
205			break;
206
207		mc_size = get_totalsize(&mc_header);
208		if (!mc_size || mc_size > leftover) {
209			pr_err("error! Bad data in microcode data file\n");
210			break;
211		}
212
213		/* For performance reasons, reuse mc area when possible */
214		if (!mc || mc_size > curr_mc_size) {
215			vfree(mc);
216			mc = vmalloc(mc_size);
217			if (!mc)
218				break;
219			curr_mc_size = mc_size;
220		}
221
222		if (get_ucode_data(mc, ucode_ptr, mc_size) ||
223		    microcode_sanity_check(mc, 1) < 0) {
224			break;
225		}
226
227		csig = uci->cpu_sig.sig;
228		cpf = uci->cpu_sig.pf;
229		if (get_matching_microcode(csig, cpf, new_rev, mc)) {
230			vfree(new_mc);
231			new_rev = mc_header.rev;
232			new_mc  = mc;
233			mc = NULL;	/* trigger new vmalloc */
234		}
235
236		ucode_ptr += mc_size;
237		leftover  -= mc_size;
238	}
239
240	vfree(mc);
241
242	if (leftover) {
243		vfree(new_mc);
244		state = UCODE_ERROR;
245		goto out;
246	}
247
248	if (!new_mc) {
249		state = UCODE_NFOUND;
250		goto out;
251	}
252
253	vfree(uci->mc);
254	uci->mc = (struct microcode_intel *)new_mc;
255
256	/*
257	 * If early loading microcode is supported, save this mc into
258	 * permanent memory. So it will be loaded early when a CPU is hot added
259	 * or resumes.
260	 */
261	save_mc_for_early(new_mc);
262
263	pr_debug("CPU%d found a matching microcode update with version 0x%x (current=0x%x)\n",
264		 cpu, new_rev, uci->cpu_sig.rev);
265out:
266	return state;
267}
268
269static int get_ucode_fw(void *to, const void *from, size_t n)
270{
271	memcpy(to, from, n);
272	return 0;
273}
274
275static enum ucode_state request_microcode_fw(int cpu, struct device *device,
276					     bool refresh_fw)
277{
278	char name[30];
279	struct cpuinfo_x86 *c = &cpu_data(cpu);
280	const struct firmware *firmware;
281	enum ucode_state ret;
282
283	sprintf(name, "intel-ucode/%02x-%02x-%02x",
284		c->x86, c->x86_model, c->x86_mask);
285
286	if (request_firmware_direct(&firmware, name, device)) {
287		pr_debug("data file %s load failed\n", name);
288		return UCODE_NFOUND;
289	}
290
291	ret = generic_load_microcode(cpu, (void *)firmware->data,
292				     firmware->size, &get_ucode_fw);
293
294	release_firmware(firmware);
295
296	return ret;
297}
298
299static int get_ucode_user(void *to, const void *from, size_t n)
300{
301	return copy_from_user(to, from, n);
302}
303
304static enum ucode_state
305request_microcode_user(int cpu, const void __user *buf, size_t size)
306{
307	return generic_load_microcode(cpu, (void *)buf, size, &get_ucode_user);
308}
309
310static void microcode_fini_cpu(int cpu)
311{
312	struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
313
314	vfree(uci->mc);
315	uci->mc = NULL;
316}
317
318static struct microcode_ops microcode_intel_ops = {
319	.request_microcode_user		  = request_microcode_user,
320	.request_microcode_fw             = request_microcode_fw,
321	.collect_cpu_info                 = collect_cpu_info,
322	.apply_microcode                  = apply_microcode_intel,
323	.microcode_fini_cpu               = microcode_fini_cpu,
324};
325
326struct microcode_ops * __init init_intel_microcode(void)
327{
328	struct cpuinfo_x86 *c = &cpu_data(0);
329
330	if (c->x86_vendor != X86_VENDOR_INTEL || c->x86 < 6 ||
331	    cpu_has(c, X86_FEATURE_IA64)) {
332		pr_err("Intel CPU family 0x%x not supported\n", c->x86);
333		return NULL;
334	}
335
336	return &microcode_intel_ops;
337}
338
339