1 /*
2 * P5 specific Machine Check Exception Reporting
3 * (C) Copyright 2002 Alan Cox <alan@lxorguk.ukuu.org.uk>
4 */
5 #include <linux/interrupt.h>
6 #include <linux/kernel.h>
7 #include <linux/types.h>
8 #include <linux/smp.h>
9
10 #include <asm/processor.h>
11 #include <asm/traps.h>
12 #include <asm/tlbflush.h>
13 #include <asm/mce.h>
14 #include <asm/msr.h>
15
16 /* By default disabled */
17 int mce_p5_enabled __read_mostly;
18
19 /* Machine check handler for Pentium class Intel CPUs: */
pentium_machine_check(struct pt_regs * regs,long error_code)20 static void pentium_machine_check(struct pt_regs *regs, long error_code)
21 {
22 enum ctx_state prev_state;
23 u32 loaddr, hi, lotype;
24
25 prev_state = ist_enter(regs);
26
27 rdmsr(MSR_IA32_P5_MC_ADDR, loaddr, hi);
28 rdmsr(MSR_IA32_P5_MC_TYPE, lotype, hi);
29
30 printk(KERN_EMERG
31 "CPU#%d: Machine Check Exception: 0x%8X (type 0x%8X).\n",
32 smp_processor_id(), loaddr, lotype);
33
34 if (lotype & (1<<5)) {
35 printk(KERN_EMERG
36 "CPU#%d: Possible thermal failure (CPU on fire ?).\n",
37 smp_processor_id());
38 }
39
40 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
41
42 ist_exit(regs, prev_state);
43 }
44
45 /* Set up machine check reporting for processors with Intel style MCE: */
intel_p5_mcheck_init(struct cpuinfo_x86 * c)46 void intel_p5_mcheck_init(struct cpuinfo_x86 *c)
47 {
48 u32 l, h;
49
50 /* Default P5 to off as its often misconnected: */
51 if (!mce_p5_enabled)
52 return;
53
54 /* Check for MCE support: */
55 if (!cpu_has(c, X86_FEATURE_MCE))
56 return;
57
58 machine_check_vector = pentium_machine_check;
59 /* Make sure the vector pointer is visible before we enable MCEs: */
60 wmb();
61
62 /* Read registers before enabling: */
63 rdmsr(MSR_IA32_P5_MC_ADDR, l, h);
64 rdmsr(MSR_IA32_P5_MC_TYPE, l, h);
65 printk(KERN_INFO
66 "Intel old style machine check architecture supported.\n");
67
68 /* Enable MCE: */
69 cr4_set_bits(X86_CR4_MCE);
70 printk(KERN_INFO
71 "Intel old style machine check reporting enabled on CPU#%d.\n",
72 smp_processor_id());
73 }
74