1#include <linux/device.h> 2#include <asm/mce.h> 3 4enum severity_level { 5 MCE_NO_SEVERITY, 6 MCE_DEFERRED_SEVERITY, 7 MCE_UCNA_SEVERITY = MCE_DEFERRED_SEVERITY, 8 MCE_KEEP_SEVERITY, 9 MCE_SOME_SEVERITY, 10 MCE_AO_SEVERITY, 11 MCE_UC_SEVERITY, 12 MCE_AR_SEVERITY, 13 MCE_PANIC_SEVERITY, 14}; 15 16#define ATTR_LEN 16 17#define INITIAL_CHECK_INTERVAL 5 * 60 /* 5 minutes */ 18 19/* One object for each MCE bank, shared by all CPUs */ 20struct mce_bank { 21 u64 ctl; /* subevents to enable */ 22 unsigned char init; /* initialise bank? */ 23 struct device_attribute attr; /* device attribute */ 24 char attrname[ATTR_LEN]; /* attribute name */ 25}; 26 27extern int (*mce_severity)(struct mce *a, int tolerant, char **msg, bool is_excp); 28struct dentry *mce_get_debugfs_dir(void); 29 30extern struct mce_bank *mce_banks; 31extern mce_banks_t mce_banks_ce_disabled; 32 33#ifdef CONFIG_X86_MCE_INTEL 34unsigned long cmci_intel_adjust_timer(unsigned long interval); 35bool mce_intel_cmci_poll(void); 36void mce_intel_hcpu_update(unsigned long cpu); 37void cmci_disable_bank(int bank); 38#else 39# define cmci_intel_adjust_timer mce_adjust_timer_default 40static inline bool mce_intel_cmci_poll(void) { return false; } 41static inline void mce_intel_hcpu_update(unsigned long cpu) { } 42static inline void cmci_disable_bank(int bank) { } 43#endif 44 45void mce_timer_kick(unsigned long interval); 46 47#ifdef CONFIG_ACPI_APEI 48int apei_write_mce(struct mce *m); 49ssize_t apei_read_mce(struct mce *m, u64 *record_id); 50int apei_check_mce(void); 51int apei_clear_mce(u64 record_id); 52#else 53static inline int apei_write_mce(struct mce *m) 54{ 55 return -EINVAL; 56} 57static inline ssize_t apei_read_mce(struct mce *m, u64 *record_id) 58{ 59 return 0; 60} 61static inline int apei_check_mce(void) 62{ 63 return 0; 64} 65static inline int apei_clear_mce(u64 record_id) 66{ 67 return -EINVAL; 68} 69#endif 70