1#include <linux/bootmem.h> 2#include <linux/linkage.h> 3#include <linux/bitops.h> 4#include <linux/kernel.h> 5#include <linux/module.h> 6#include <linux/percpu.h> 7#include <linux/string.h> 8#include <linux/delay.h> 9#include <linux/sched.h> 10#include <linux/init.h> 11#include <linux/kprobes.h> 12#include <linux/kgdb.h> 13#include <linux/smp.h> 14#include <linux/io.h> 15 16#include <asm/stackprotector.h> 17#include <asm/perf_event.h> 18#include <asm/mmu_context.h> 19#include <asm/archrandom.h> 20#include <asm/hypervisor.h> 21#include <asm/processor.h> 22#include <asm/tlbflush.h> 23#include <asm/debugreg.h> 24#include <asm/sections.h> 25#include <asm/vsyscall.h> 26#include <linux/topology.h> 27#include <linux/cpumask.h> 28#include <asm/pgtable.h> 29#include <linux/atomic.h> 30#include <asm/proto.h> 31#include <asm/setup.h> 32#include <asm/apic.h> 33#include <asm/desc.h> 34#include <asm/i387.h> 35#include <asm/fpu-internal.h> 36#include <asm/mtrr.h> 37#include <linux/numa.h> 38#include <asm/asm.h> 39#include <asm/cpu.h> 40#include <asm/mce.h> 41#include <asm/msr.h> 42#include <asm/pat.h> 43#include <asm/microcode.h> 44#include <asm/microcode_intel.h> 45 46#ifdef CONFIG_X86_LOCAL_APIC 47#include <asm/uv/uv.h> 48#endif 49 50#include "cpu.h" 51 52/* all of these masks are initialized in setup_cpu_local_masks() */ 53cpumask_var_t cpu_initialized_mask; 54cpumask_var_t cpu_callout_mask; 55cpumask_var_t cpu_callin_mask; 56 57/* representing cpus for which sibling maps can be computed */ 58cpumask_var_t cpu_sibling_setup_mask; 59 60/* correctly size the local cpu masks */ 61void __init setup_cpu_local_masks(void) 62{ 63 alloc_bootmem_cpumask_var(&cpu_initialized_mask); 64 alloc_bootmem_cpumask_var(&cpu_callin_mask); 65 alloc_bootmem_cpumask_var(&cpu_callout_mask); 66 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); 67} 68 69static void default_init(struct cpuinfo_x86 *c) 70{ 71#ifdef CONFIG_X86_64 72 cpu_detect_cache_sizes(c); 73#else 74 /* Not much we can do here... */ 75 /* Check if at least it has cpuid */ 76 if (c->cpuid_level == -1) { 77 /* No cpuid. It must be an ancient CPU */ 78 if (c->x86 == 4) 79 strcpy(c->x86_model_id, "486"); 80 else if (c->x86 == 3) 81 strcpy(c->x86_model_id, "386"); 82 } 83#endif 84} 85 86static const struct cpu_dev default_cpu = { 87 .c_init = default_init, 88 .c_vendor = "Unknown", 89 .c_x86_vendor = X86_VENDOR_UNKNOWN, 90}; 91 92static const struct cpu_dev *this_cpu = &default_cpu; 93 94DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { 95#ifdef CONFIG_X86_64 96 /* 97 * We need valid kernel segments for data and code in long mode too 98 * IRET will check the segment types kkeil 2000/10/28 99 * Also sysret mandates a special GDT layout 100 * 101 * TLS descriptors are currently at a different place compared to i386. 102 * Hopefully nobody expects them at a fixed place (Wine?) 103 */ 104 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff), 105 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff), 106 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff), 107 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff), 108 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff), 109 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff), 110#else 111 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff), 112 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 113 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff), 114 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff), 115 /* 116 * Segments used for calling PnP BIOS have byte granularity. 117 * They code segments and data segments have fixed 64k limits, 118 * the transfer segment sizes are set at run time. 119 */ 120 /* 32-bit code */ 121 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 122 /* 16-bit code */ 123 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 124 /* 16-bit data */ 125 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff), 126 /* 16-bit data */ 127 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0), 128 /* 16-bit data */ 129 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0), 130 /* 131 * The APM segments have byte granularity and their bases 132 * are set at run time. All have 64k limits. 133 */ 134 /* 32-bit code */ 135 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 136 /* 16-bit code */ 137 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 138 /* data */ 139 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff), 140 141 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 142 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 143 GDT_STACK_CANARY_INIT 144#endif 145} }; 146EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); 147 148static int __init x86_xsave_setup(char *s) 149{ 150 if (strlen(s)) 151 return 0; 152 setup_clear_cpu_cap(X86_FEATURE_XSAVE); 153 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT); 154 setup_clear_cpu_cap(X86_FEATURE_XSAVES); 155 setup_clear_cpu_cap(X86_FEATURE_AVX); 156 setup_clear_cpu_cap(X86_FEATURE_AVX2); 157 return 1; 158} 159__setup("noxsave", x86_xsave_setup); 160 161static int __init x86_xsaveopt_setup(char *s) 162{ 163 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT); 164 return 1; 165} 166__setup("noxsaveopt", x86_xsaveopt_setup); 167 168static int __init x86_xsaves_setup(char *s) 169{ 170 setup_clear_cpu_cap(X86_FEATURE_XSAVES); 171 return 1; 172} 173__setup("noxsaves", x86_xsaves_setup); 174 175#ifdef CONFIG_X86_32 176static int cachesize_override = -1; 177static int disable_x86_serial_nr = 1; 178 179static int __init cachesize_setup(char *str) 180{ 181 get_option(&str, &cachesize_override); 182 return 1; 183} 184__setup("cachesize=", cachesize_setup); 185 186static int __init x86_fxsr_setup(char *s) 187{ 188 setup_clear_cpu_cap(X86_FEATURE_FXSR); 189 setup_clear_cpu_cap(X86_FEATURE_XMM); 190 return 1; 191} 192__setup("nofxsr", x86_fxsr_setup); 193 194static int __init x86_sep_setup(char *s) 195{ 196 setup_clear_cpu_cap(X86_FEATURE_SEP); 197 return 1; 198} 199__setup("nosep", x86_sep_setup); 200 201/* Standard macro to see if a specific flag is changeable */ 202static inline int flag_is_changeable_p(u32 flag) 203{ 204 u32 f1, f2; 205 206 /* 207 * Cyrix and IDT cpus allow disabling of CPUID 208 * so the code below may return different results 209 * when it is executed before and after enabling 210 * the CPUID. Add "volatile" to not allow gcc to 211 * optimize the subsequent calls to this function. 212 */ 213 asm volatile ("pushfl \n\t" 214 "pushfl \n\t" 215 "popl %0 \n\t" 216 "movl %0, %1 \n\t" 217 "xorl %2, %0 \n\t" 218 "pushl %0 \n\t" 219 "popfl \n\t" 220 "pushfl \n\t" 221 "popl %0 \n\t" 222 "popfl \n\t" 223 224 : "=&r" (f1), "=&r" (f2) 225 : "ir" (flag)); 226 227 return ((f1^f2) & flag) != 0; 228} 229 230/* Probe for the CPUID instruction */ 231int have_cpuid_p(void) 232{ 233 return flag_is_changeable_p(X86_EFLAGS_ID); 234} 235 236static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 237{ 238 unsigned long lo, hi; 239 240 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) 241 return; 242 243 /* Disable processor serial number: */ 244 245 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 246 lo |= 0x200000; 247 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 248 249 printk(KERN_NOTICE "CPU serial number disabled.\n"); 250 clear_cpu_cap(c, X86_FEATURE_PN); 251 252 /* Disabling the serial number may affect the cpuid level */ 253 c->cpuid_level = cpuid_eax(0); 254} 255 256static int __init x86_serial_nr_setup(char *s) 257{ 258 disable_x86_serial_nr = 0; 259 return 1; 260} 261__setup("serialnumber", x86_serial_nr_setup); 262#else 263static inline int flag_is_changeable_p(u32 flag) 264{ 265 return 1; 266} 267static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 268{ 269} 270#endif 271 272static __init int setup_disable_smep(char *arg) 273{ 274 setup_clear_cpu_cap(X86_FEATURE_SMEP); 275 return 1; 276} 277__setup("nosmep", setup_disable_smep); 278 279static __always_inline void setup_smep(struct cpuinfo_x86 *c) 280{ 281 if (cpu_has(c, X86_FEATURE_SMEP)) 282 cr4_set_bits(X86_CR4_SMEP); 283} 284 285static __init int setup_disable_smap(char *arg) 286{ 287 setup_clear_cpu_cap(X86_FEATURE_SMAP); 288 return 1; 289} 290__setup("nosmap", setup_disable_smap); 291 292static __always_inline void setup_smap(struct cpuinfo_x86 *c) 293{ 294 unsigned long eflags = native_save_fl(); 295 296 /* This should have been cleared long ago */ 297 BUG_ON(eflags & X86_EFLAGS_AC); 298 299 if (cpu_has(c, X86_FEATURE_SMAP)) { 300#ifdef CONFIG_X86_SMAP 301 cr4_set_bits(X86_CR4_SMAP); 302#else 303 cr4_clear_bits(X86_CR4_SMAP); 304#endif 305 } 306} 307 308/* 309 * Some CPU features depend on higher CPUID levels, which may not always 310 * be available due to CPUID level capping or broken virtualization 311 * software. Add those features to this table to auto-disable them. 312 */ 313struct cpuid_dependent_feature { 314 u32 feature; 315 u32 level; 316}; 317 318static const struct cpuid_dependent_feature 319cpuid_dependent_features[] = { 320 { X86_FEATURE_MWAIT, 0x00000005 }, 321 { X86_FEATURE_DCA, 0x00000009 }, 322 { X86_FEATURE_XSAVE, 0x0000000d }, 323 { 0, 0 } 324}; 325 326static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) 327{ 328 const struct cpuid_dependent_feature *df; 329 330 for (df = cpuid_dependent_features; df->feature; df++) { 331 332 if (!cpu_has(c, df->feature)) 333 continue; 334 /* 335 * Note: cpuid_level is set to -1 if unavailable, but 336 * extended_extended_level is set to 0 if unavailable 337 * and the legitimate extended levels are all negative 338 * when signed; hence the weird messing around with 339 * signs here... 340 */ 341 if (!((s32)df->level < 0 ? 342 (u32)df->level > (u32)c->extended_cpuid_level : 343 (s32)df->level > (s32)c->cpuid_level)) 344 continue; 345 346 clear_cpu_cap(c, df->feature); 347 if (!warn) 348 continue; 349 350 printk(KERN_WARNING 351 "CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n", 352 x86_cap_flag(df->feature), df->level); 353 } 354} 355 356/* 357 * Naming convention should be: <Name> [(<Codename>)] 358 * This table only is used unless init_<vendor>() below doesn't set it; 359 * in particular, if CPUID levels 0x80000002..4 are supported, this 360 * isn't used 361 */ 362 363/* Look up CPU names by table lookup. */ 364static const char *table_lookup_model(struct cpuinfo_x86 *c) 365{ 366#ifdef CONFIG_X86_32 367 const struct legacy_cpu_model_info *info; 368 369 if (c->x86_model >= 16) 370 return NULL; /* Range check */ 371 372 if (!this_cpu) 373 return NULL; 374 375 info = this_cpu->legacy_models; 376 377 while (info->family) { 378 if (info->family == c->x86) 379 return info->model_names[c->x86_model]; 380 info++; 381 } 382#endif 383 return NULL; /* Not found */ 384} 385 386__u32 cpu_caps_cleared[NCAPINTS]; 387__u32 cpu_caps_set[NCAPINTS]; 388 389void load_percpu_segment(int cpu) 390{ 391#ifdef CONFIG_X86_32 392 loadsegment(fs, __KERNEL_PERCPU); 393#else 394 loadsegment(gs, 0); 395 wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu)); 396#endif 397 load_stack_canary_segment(); 398} 399 400/* 401 * Current gdt points %fs at the "master" per-cpu area: after this, 402 * it's on the real one. 403 */ 404void switch_to_new_gdt(int cpu) 405{ 406 struct desc_ptr gdt_descr; 407 408 gdt_descr.address = (long)get_cpu_gdt_table(cpu); 409 gdt_descr.size = GDT_SIZE - 1; 410 load_gdt(&gdt_descr); 411 /* Reload the per-cpu base */ 412 413 load_percpu_segment(cpu); 414} 415 416static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; 417 418static void get_model_name(struct cpuinfo_x86 *c) 419{ 420 unsigned int *v; 421 char *p, *q; 422 423 if (c->extended_cpuid_level < 0x80000004) 424 return; 425 426 v = (unsigned int *)c->x86_model_id; 427 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); 428 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); 429 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); 430 c->x86_model_id[48] = 0; 431 432 /* 433 * Intel chips right-justify this string for some dumb reason; 434 * undo that brain damage: 435 */ 436 p = q = &c->x86_model_id[0]; 437 while (*p == ' ') 438 p++; 439 if (p != q) { 440 while (*p) 441 *q++ = *p++; 442 while (q <= &c->x86_model_id[48]) 443 *q++ = '\0'; /* Zero-pad the rest */ 444 } 445} 446 447void cpu_detect_cache_sizes(struct cpuinfo_x86 *c) 448{ 449 unsigned int n, dummy, ebx, ecx, edx, l2size; 450 451 n = c->extended_cpuid_level; 452 453 if (n >= 0x80000005) { 454 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); 455 c->x86_cache_size = (ecx>>24) + (edx>>24); 456#ifdef CONFIG_X86_64 457 /* On K8 L1 TLB is inclusive, so don't count it */ 458 c->x86_tlbsize = 0; 459#endif 460 } 461 462 if (n < 0x80000006) /* Some chips just has a large L1. */ 463 return; 464 465 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); 466 l2size = ecx >> 16; 467 468#ifdef CONFIG_X86_64 469 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); 470#else 471 /* do processor-specific cache resizing */ 472 if (this_cpu->legacy_cache_size) 473 l2size = this_cpu->legacy_cache_size(c, l2size); 474 475 /* Allow user to override all this if necessary. */ 476 if (cachesize_override != -1) 477 l2size = cachesize_override; 478 479 if (l2size == 0) 480 return; /* Again, no L2 cache is possible */ 481#endif 482 483 c->x86_cache_size = l2size; 484} 485 486u16 __read_mostly tlb_lli_4k[NR_INFO]; 487u16 __read_mostly tlb_lli_2m[NR_INFO]; 488u16 __read_mostly tlb_lli_4m[NR_INFO]; 489u16 __read_mostly tlb_lld_4k[NR_INFO]; 490u16 __read_mostly tlb_lld_2m[NR_INFO]; 491u16 __read_mostly tlb_lld_4m[NR_INFO]; 492u16 __read_mostly tlb_lld_1g[NR_INFO]; 493 494static void cpu_detect_tlb(struct cpuinfo_x86 *c) 495{ 496 if (this_cpu->c_detect_tlb) 497 this_cpu->c_detect_tlb(c); 498 499 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n", 500 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES], 501 tlb_lli_4m[ENTRIES]); 502 503 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n", 504 tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES], 505 tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]); 506} 507 508void detect_ht(struct cpuinfo_x86 *c) 509{ 510#ifdef CONFIG_X86_HT 511 u32 eax, ebx, ecx, edx; 512 int index_msb, core_bits; 513 static bool printed; 514 515 if (!cpu_has(c, X86_FEATURE_HT)) 516 return; 517 518 if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) 519 goto out; 520 521 if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) 522 return; 523 524 cpuid(1, &eax, &ebx, &ecx, &edx); 525 526 smp_num_siblings = (ebx & 0xff0000) >> 16; 527 528 if (smp_num_siblings == 1) { 529 printk_once(KERN_INFO "CPU0: Hyper-Threading is disabled\n"); 530 goto out; 531 } 532 533 if (smp_num_siblings <= 1) 534 goto out; 535 536 index_msb = get_count_order(smp_num_siblings); 537 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); 538 539 smp_num_siblings = smp_num_siblings / c->x86_max_cores; 540 541 index_msb = get_count_order(smp_num_siblings); 542 543 core_bits = get_count_order(c->x86_max_cores); 544 545 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & 546 ((1 << core_bits) - 1); 547 548out: 549 if (!printed && (c->x86_max_cores * smp_num_siblings) > 1) { 550 printk(KERN_INFO "CPU: Physical Processor ID: %d\n", 551 c->phys_proc_id); 552 printk(KERN_INFO "CPU: Processor Core ID: %d\n", 553 c->cpu_core_id); 554 printed = 1; 555 } 556#endif 557} 558 559static void get_cpu_vendor(struct cpuinfo_x86 *c) 560{ 561 char *v = c->x86_vendor_id; 562 int i; 563 564 for (i = 0; i < X86_VENDOR_NUM; i++) { 565 if (!cpu_devs[i]) 566 break; 567 568 if (!strcmp(v, cpu_devs[i]->c_ident[0]) || 569 (cpu_devs[i]->c_ident[1] && 570 !strcmp(v, cpu_devs[i]->c_ident[1]))) { 571 572 this_cpu = cpu_devs[i]; 573 c->x86_vendor = this_cpu->c_x86_vendor; 574 return; 575 } 576 } 577 578 printk_once(KERN_ERR 579 "CPU: vendor_id '%s' unknown, using generic init.\n" \ 580 "CPU: Your system may be unstable.\n", v); 581 582 c->x86_vendor = X86_VENDOR_UNKNOWN; 583 this_cpu = &default_cpu; 584} 585 586void cpu_detect(struct cpuinfo_x86 *c) 587{ 588 /* Get vendor name */ 589 cpuid(0x00000000, (unsigned int *)&c->cpuid_level, 590 (unsigned int *)&c->x86_vendor_id[0], 591 (unsigned int *)&c->x86_vendor_id[8], 592 (unsigned int *)&c->x86_vendor_id[4]); 593 594 c->x86 = 4; 595 /* Intel-defined flags: level 0x00000001 */ 596 if (c->cpuid_level >= 0x00000001) { 597 u32 junk, tfms, cap0, misc; 598 599 cpuid(0x00000001, &tfms, &misc, &junk, &cap0); 600 c->x86 = (tfms >> 8) & 0xf; 601 c->x86_model = (tfms >> 4) & 0xf; 602 c->x86_mask = tfms & 0xf; 603 604 if (c->x86 == 0xf) 605 c->x86 += (tfms >> 20) & 0xff; 606 if (c->x86 >= 0x6) 607 c->x86_model += ((tfms >> 16) & 0xf) << 4; 608 609 if (cap0 & (1<<19)) { 610 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; 611 c->x86_cache_alignment = c->x86_clflush_size; 612 } 613 } 614} 615 616void get_cpu_cap(struct cpuinfo_x86 *c) 617{ 618 u32 tfms, xlvl; 619 u32 ebx; 620 621 /* Intel-defined flags: level 0x00000001 */ 622 if (c->cpuid_level >= 0x00000001) { 623 u32 capability, excap; 624 625 cpuid(0x00000001, &tfms, &ebx, &excap, &capability); 626 c->x86_capability[0] = capability; 627 c->x86_capability[4] = excap; 628 } 629 630 /* Additional Intel-defined flags: level 0x00000007 */ 631 if (c->cpuid_level >= 0x00000007) { 632 u32 eax, ebx, ecx, edx; 633 634 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); 635 636 c->x86_capability[9] = ebx; 637 } 638 639 /* Extended state features: level 0x0000000d */ 640 if (c->cpuid_level >= 0x0000000d) { 641 u32 eax, ebx, ecx, edx; 642 643 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx); 644 645 c->x86_capability[10] = eax; 646 } 647 648 /* Additional Intel-defined flags: level 0x0000000F */ 649 if (c->cpuid_level >= 0x0000000F) { 650 u32 eax, ebx, ecx, edx; 651 652 /* QoS sub-leaf, EAX=0Fh, ECX=0 */ 653 cpuid_count(0x0000000F, 0, &eax, &ebx, &ecx, &edx); 654 c->x86_capability[11] = edx; 655 if (cpu_has(c, X86_FEATURE_CQM_LLC)) { 656 /* will be overridden if occupancy monitoring exists */ 657 c->x86_cache_max_rmid = ebx; 658 659 /* QoS sub-leaf, EAX=0Fh, ECX=1 */ 660 cpuid_count(0x0000000F, 1, &eax, &ebx, &ecx, &edx); 661 c->x86_capability[12] = edx; 662 if (cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC)) { 663 c->x86_cache_max_rmid = ecx; 664 c->x86_cache_occ_scale = ebx; 665 } 666 } else { 667 c->x86_cache_max_rmid = -1; 668 c->x86_cache_occ_scale = -1; 669 } 670 } 671 672 /* AMD-defined flags: level 0x80000001 */ 673 xlvl = cpuid_eax(0x80000000); 674 c->extended_cpuid_level = xlvl; 675 676 if ((xlvl & 0xffff0000) == 0x80000000) { 677 if (xlvl >= 0x80000001) { 678 c->x86_capability[1] = cpuid_edx(0x80000001); 679 c->x86_capability[6] = cpuid_ecx(0x80000001); 680 } 681 } 682 683 if (c->extended_cpuid_level >= 0x80000008) { 684 u32 eax = cpuid_eax(0x80000008); 685 686 c->x86_virt_bits = (eax >> 8) & 0xff; 687 c->x86_phys_bits = eax & 0xff; 688 } 689#ifdef CONFIG_X86_32 690 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) 691 c->x86_phys_bits = 36; 692#endif 693 694 if (c->extended_cpuid_level >= 0x80000007) 695 c->x86_power = cpuid_edx(0x80000007); 696 697 init_scattered_cpuid_features(c); 698} 699 700static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c) 701{ 702#ifdef CONFIG_X86_32 703 int i; 704 705 /* 706 * First of all, decide if this is a 486 or higher 707 * It's a 486 if we can modify the AC flag 708 */ 709 if (flag_is_changeable_p(X86_EFLAGS_AC)) 710 c->x86 = 4; 711 else 712 c->x86 = 3; 713 714 for (i = 0; i < X86_VENDOR_NUM; i++) 715 if (cpu_devs[i] && cpu_devs[i]->c_identify) { 716 c->x86_vendor_id[0] = 0; 717 cpu_devs[i]->c_identify(c); 718 if (c->x86_vendor_id[0]) { 719 get_cpu_vendor(c); 720 break; 721 } 722 } 723#endif 724} 725 726/* 727 * Do minimum CPU detection early. 728 * Fields really needed: vendor, cpuid_level, family, model, mask, 729 * cache alignment. 730 * The others are not touched to avoid unwanted side effects. 731 * 732 * WARNING: this function is only called on the BP. Don't add code here 733 * that is supposed to run on all CPUs. 734 */ 735static void __init early_identify_cpu(struct cpuinfo_x86 *c) 736{ 737#ifdef CONFIG_X86_64 738 c->x86_clflush_size = 64; 739 c->x86_phys_bits = 36; 740 c->x86_virt_bits = 48; 741#else 742 c->x86_clflush_size = 32; 743 c->x86_phys_bits = 32; 744 c->x86_virt_bits = 32; 745#endif 746 c->x86_cache_alignment = c->x86_clflush_size; 747 748 memset(&c->x86_capability, 0, sizeof c->x86_capability); 749 c->extended_cpuid_level = 0; 750 751 if (!have_cpuid_p()) 752 identify_cpu_without_cpuid(c); 753 754 /* cyrix could have cpuid enabled via c_identify()*/ 755 if (!have_cpuid_p()) 756 return; 757 758 cpu_detect(c); 759 get_cpu_vendor(c); 760 get_cpu_cap(c); 761 fpu_detect(c); 762 763 if (this_cpu->c_early_init) 764 this_cpu->c_early_init(c); 765 766 c->cpu_index = 0; 767 filter_cpuid_features(c, false); 768 769 if (this_cpu->c_bsp_init) 770 this_cpu->c_bsp_init(c); 771 772 setup_force_cpu_cap(X86_FEATURE_ALWAYS); 773} 774 775void __init early_cpu_init(void) 776{ 777 const struct cpu_dev *const *cdev; 778 int count = 0; 779 780#ifdef CONFIG_PROCESSOR_SELECT 781 printk(KERN_INFO "KERNEL supported cpus:\n"); 782#endif 783 784 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { 785 const struct cpu_dev *cpudev = *cdev; 786 787 if (count >= X86_VENDOR_NUM) 788 break; 789 cpu_devs[count] = cpudev; 790 count++; 791 792#ifdef CONFIG_PROCESSOR_SELECT 793 { 794 unsigned int j; 795 796 for (j = 0; j < 2; j++) { 797 if (!cpudev->c_ident[j]) 798 continue; 799 printk(KERN_INFO " %s %s\n", cpudev->c_vendor, 800 cpudev->c_ident[j]); 801 } 802 } 803#endif 804 } 805 early_identify_cpu(&boot_cpu_data); 806} 807 808/* 809 * The NOPL instruction is supposed to exist on all CPUs of family >= 6; 810 * unfortunately, that's not true in practice because of early VIA 811 * chips and (more importantly) broken virtualizers that are not easy 812 * to detect. In the latter case it doesn't even *fail* reliably, so 813 * probing for it doesn't even work. Disable it completely on 32-bit 814 * unless we can find a reliable way to detect all the broken cases. 815 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has(). 816 */ 817static void detect_nopl(struct cpuinfo_x86 *c) 818{ 819#ifdef CONFIG_X86_32 820 clear_cpu_cap(c, X86_FEATURE_NOPL); 821#else 822 set_cpu_cap(c, X86_FEATURE_NOPL); 823#endif 824} 825 826static void generic_identify(struct cpuinfo_x86 *c) 827{ 828 c->extended_cpuid_level = 0; 829 830 if (!have_cpuid_p()) 831 identify_cpu_without_cpuid(c); 832 833 /* cyrix could have cpuid enabled via c_identify()*/ 834 if (!have_cpuid_p()) 835 return; 836 837 cpu_detect(c); 838 839 get_cpu_vendor(c); 840 841 get_cpu_cap(c); 842 843 if (c->cpuid_level >= 0x00000001) { 844 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; 845#ifdef CONFIG_X86_32 846# ifdef CONFIG_X86_HT 847 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 848# else 849 c->apicid = c->initial_apicid; 850# endif 851#endif 852 c->phys_proc_id = c->initial_apicid; 853 } 854 855 get_model_name(c); /* Default name */ 856 857 detect_nopl(c); 858} 859 860static void x86_init_cache_qos(struct cpuinfo_x86 *c) 861{ 862 /* 863 * The heavy lifting of max_rmid and cache_occ_scale are handled 864 * in get_cpu_cap(). Here we just set the max_rmid for the boot_cpu 865 * in case CQM bits really aren't there in this CPU. 866 */ 867 if (c != &boot_cpu_data) { 868 boot_cpu_data.x86_cache_max_rmid = 869 min(boot_cpu_data.x86_cache_max_rmid, 870 c->x86_cache_max_rmid); 871 } 872} 873 874/* 875 * This does the hard work of actually picking apart the CPU stuff... 876 */ 877static void identify_cpu(struct cpuinfo_x86 *c) 878{ 879 int i; 880 881 c->loops_per_jiffy = loops_per_jiffy; 882 c->x86_cache_size = -1; 883 c->x86_vendor = X86_VENDOR_UNKNOWN; 884 c->x86_model = c->x86_mask = 0; /* So far unknown... */ 885 c->x86_vendor_id[0] = '\0'; /* Unset */ 886 c->x86_model_id[0] = '\0'; /* Unset */ 887 c->x86_max_cores = 1; 888 c->x86_coreid_bits = 0; 889#ifdef CONFIG_X86_64 890 c->x86_clflush_size = 64; 891 c->x86_phys_bits = 36; 892 c->x86_virt_bits = 48; 893#else 894 c->cpuid_level = -1; /* CPUID not detected */ 895 c->x86_clflush_size = 32; 896 c->x86_phys_bits = 32; 897 c->x86_virt_bits = 32; 898#endif 899 c->x86_cache_alignment = c->x86_clflush_size; 900 memset(&c->x86_capability, 0, sizeof c->x86_capability); 901 902 generic_identify(c); 903 904 if (this_cpu->c_identify) 905 this_cpu->c_identify(c); 906 907 /* Clear/Set all flags overriden by options, after probe */ 908 for (i = 0; i < NCAPINTS; i++) { 909 c->x86_capability[i] &= ~cpu_caps_cleared[i]; 910 c->x86_capability[i] |= cpu_caps_set[i]; 911 } 912 913#ifdef CONFIG_X86_64 914 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 915#endif 916 917 /* 918 * Vendor-specific initialization. In this section we 919 * canonicalize the feature flags, meaning if there are 920 * features a certain CPU supports which CPUID doesn't 921 * tell us, CPUID claiming incorrect flags, or other bugs, 922 * we handle them here. 923 * 924 * At the end of this section, c->x86_capability better 925 * indicate the features this CPU genuinely supports! 926 */ 927 if (this_cpu->c_init) 928 this_cpu->c_init(c); 929 930 /* Disable the PN if appropriate */ 931 squash_the_stupid_serial_number(c); 932 933 /* Set up SMEP/SMAP */ 934 setup_smep(c); 935 setup_smap(c); 936 937 /* 938 * The vendor-specific functions might have changed features. 939 * Now we do "generic changes." 940 */ 941 942 /* Filter out anything that depends on CPUID levels we don't have */ 943 filter_cpuid_features(c, true); 944 945 /* If the model name is still unset, do table lookup. */ 946 if (!c->x86_model_id[0]) { 947 const char *p; 948 p = table_lookup_model(c); 949 if (p) 950 strcpy(c->x86_model_id, p); 951 else 952 /* Last resort... */ 953 sprintf(c->x86_model_id, "%02x/%02x", 954 c->x86, c->x86_model); 955 } 956 957#ifdef CONFIG_X86_64 958 detect_ht(c); 959#endif 960 961 init_hypervisor(c); 962 x86_init_rdrand(c); 963 x86_init_cache_qos(c); 964 965 /* 966 * Clear/Set all flags overriden by options, need do it 967 * before following smp all cpus cap AND. 968 */ 969 for (i = 0; i < NCAPINTS; i++) { 970 c->x86_capability[i] &= ~cpu_caps_cleared[i]; 971 c->x86_capability[i] |= cpu_caps_set[i]; 972 } 973 974 /* 975 * On SMP, boot_cpu_data holds the common feature set between 976 * all CPUs; so make sure that we indicate which features are 977 * common between the CPUs. The first time this routine gets 978 * executed, c == &boot_cpu_data. 979 */ 980 if (c != &boot_cpu_data) { 981 /* AND the already accumulated flags with these */ 982 for (i = 0; i < NCAPINTS; i++) 983 boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; 984 985 /* OR, i.e. replicate the bug flags */ 986 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++) 987 c->x86_capability[i] |= boot_cpu_data.x86_capability[i]; 988 } 989 990 /* Init Machine Check Exception if available. */ 991 mcheck_cpu_init(c); 992 993 select_idle_routine(c); 994 995#ifdef CONFIG_NUMA 996 numa_add_cpu(smp_processor_id()); 997#endif 998} 999 1000/* 1001 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions 1002 * on 32-bit kernels: 1003 */ 1004#ifdef CONFIG_X86_32 1005void enable_sep_cpu(void) 1006{ 1007 struct tss_struct *tss; 1008 int cpu; 1009 1010 cpu = get_cpu(); 1011 tss = &per_cpu(cpu_tss, cpu); 1012 1013 if (!boot_cpu_has(X86_FEATURE_SEP)) 1014 goto out; 1015 1016 /* 1017 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field -- 1018 * see the big comment in struct x86_hw_tss's definition. 1019 */ 1020 1021 tss->x86_tss.ss1 = __KERNEL_CS; 1022 wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0); 1023 1024 wrmsr(MSR_IA32_SYSENTER_ESP, 1025 (unsigned long)tss + offsetofend(struct tss_struct, SYSENTER_stack), 1026 0); 1027 1028 wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)ia32_sysenter_target, 0); 1029 1030out: 1031 put_cpu(); 1032} 1033#endif 1034 1035void __init identify_boot_cpu(void) 1036{ 1037 identify_cpu(&boot_cpu_data); 1038 init_amd_e400_c1e_mask(); 1039#ifdef CONFIG_X86_32 1040 sysenter_setup(); 1041 enable_sep_cpu(); 1042#endif 1043 cpu_detect_tlb(&boot_cpu_data); 1044} 1045 1046void identify_secondary_cpu(struct cpuinfo_x86 *c) 1047{ 1048 BUG_ON(c == &boot_cpu_data); 1049 identify_cpu(c); 1050#ifdef CONFIG_X86_32 1051 enable_sep_cpu(); 1052#endif 1053 mtrr_ap_init(); 1054} 1055 1056struct msr_range { 1057 unsigned min; 1058 unsigned max; 1059}; 1060 1061static const struct msr_range msr_range_array[] = { 1062 { 0x00000000, 0x00000418}, 1063 { 0xc0000000, 0xc000040b}, 1064 { 0xc0010000, 0xc0010142}, 1065 { 0xc0011000, 0xc001103b}, 1066}; 1067 1068static void __print_cpu_msr(void) 1069{ 1070 unsigned index_min, index_max; 1071 unsigned index; 1072 u64 val; 1073 int i; 1074 1075 for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) { 1076 index_min = msr_range_array[i].min; 1077 index_max = msr_range_array[i].max; 1078 1079 for (index = index_min; index < index_max; index++) { 1080 if (rdmsrl_safe(index, &val)) 1081 continue; 1082 printk(KERN_INFO " MSR%08x: %016llx\n", index, val); 1083 } 1084 } 1085} 1086 1087static int show_msr; 1088 1089static __init int setup_show_msr(char *arg) 1090{ 1091 int num; 1092 1093 get_option(&arg, &num); 1094 1095 if (num > 0) 1096 show_msr = num; 1097 return 1; 1098} 1099__setup("show_msr=", setup_show_msr); 1100 1101static __init int setup_noclflush(char *arg) 1102{ 1103 setup_clear_cpu_cap(X86_FEATURE_CLFLUSH); 1104 setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT); 1105 return 1; 1106} 1107__setup("noclflush", setup_noclflush); 1108 1109void print_cpu_info(struct cpuinfo_x86 *c) 1110{ 1111 const char *vendor = NULL; 1112 1113 if (c->x86_vendor < X86_VENDOR_NUM) { 1114 vendor = this_cpu->c_vendor; 1115 } else { 1116 if (c->cpuid_level >= 0) 1117 vendor = c->x86_vendor_id; 1118 } 1119 1120 if (vendor && !strstr(c->x86_model_id, vendor)) 1121 printk(KERN_CONT "%s ", vendor); 1122 1123 if (c->x86_model_id[0]) 1124 printk(KERN_CONT "%s", strim(c->x86_model_id)); 1125 else 1126 printk(KERN_CONT "%d86", c->x86); 1127 1128 printk(KERN_CONT " (fam: %02x, model: %02x", c->x86, c->x86_model); 1129 1130 if (c->x86_mask || c->cpuid_level >= 0) 1131 printk(KERN_CONT ", stepping: %02x)\n", c->x86_mask); 1132 else 1133 printk(KERN_CONT ")\n"); 1134 1135 print_cpu_msr(c); 1136} 1137 1138void print_cpu_msr(struct cpuinfo_x86 *c) 1139{ 1140 if (c->cpu_index < show_msr) 1141 __print_cpu_msr(); 1142} 1143 1144static __init int setup_disablecpuid(char *arg) 1145{ 1146 int bit; 1147 1148 if (get_option(&arg, &bit) && bit < NCAPINTS*32) 1149 setup_clear_cpu_cap(bit); 1150 else 1151 return 0; 1152 1153 return 1; 1154} 1155__setup("clearcpuid=", setup_disablecpuid); 1156 1157DEFINE_PER_CPU(unsigned long, kernel_stack) = 1158 (unsigned long)&init_thread_union + THREAD_SIZE; 1159EXPORT_PER_CPU_SYMBOL(kernel_stack); 1160 1161#ifdef CONFIG_X86_64 1162struct desc_ptr idt_descr = { NR_VECTORS * 16 - 1, (unsigned long) idt_table }; 1163struct desc_ptr debug_idt_descr = { NR_VECTORS * 16 - 1, 1164 (unsigned long) debug_idt_table }; 1165 1166DEFINE_PER_CPU_FIRST(union irq_stack_union, 1167 irq_stack_union) __aligned(PAGE_SIZE) __visible; 1168 1169/* 1170 * The following percpu variables are hot. Align current_task to 1171 * cacheline size such that they fall in the same cacheline. 1172 */ 1173DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned = 1174 &init_task; 1175EXPORT_PER_CPU_SYMBOL(current_task); 1176 1177DEFINE_PER_CPU(char *, irq_stack_ptr) = 1178 init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64; 1179 1180DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1; 1181 1182DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; 1183EXPORT_PER_CPU_SYMBOL(__preempt_count); 1184 1185DEFINE_PER_CPU(struct task_struct *, fpu_owner_task); 1186 1187/* 1188 * Special IST stacks which the CPU switches to when it calls 1189 * an IST-marked descriptor entry. Up to 7 stacks (hardware 1190 * limit), all of them are 4K, except the debug stack which 1191 * is 8K. 1192 */ 1193static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = { 1194 [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ, 1195 [DEBUG_STACK - 1] = DEBUG_STKSZ 1196}; 1197 1198static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks 1199 [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]); 1200 1201/* May not be marked __init: used by software suspend */ 1202void syscall_init(void) 1203{ 1204 /* 1205 * LSTAR and STAR live in a bit strange symbiosis. 1206 * They both write to the same internal register. STAR allows to 1207 * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip. 1208 */ 1209 wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32); 1210 wrmsrl(MSR_LSTAR, system_call); 1211 1212#ifdef CONFIG_IA32_EMULATION 1213 wrmsrl(MSR_CSTAR, ia32_cstar_target); 1214 /* 1215 * This only works on Intel CPUs. 1216 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP. 1217 * This does not cause SYSENTER to jump to the wrong location, because 1218 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit). 1219 */ 1220 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS); 1221 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); 1222 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)ia32_sysenter_target); 1223#else 1224 wrmsrl(MSR_CSTAR, ignore_sysret); 1225 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG); 1226 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); 1227 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL); 1228#endif 1229 1230 /* Flags to clear on syscall */ 1231 wrmsrl(MSR_SYSCALL_MASK, 1232 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF| 1233 X86_EFLAGS_IOPL|X86_EFLAGS_AC|X86_EFLAGS_NT); 1234} 1235 1236/* 1237 * Copies of the original ist values from the tss are only accessed during 1238 * debugging, no special alignment required. 1239 */ 1240DEFINE_PER_CPU(struct orig_ist, orig_ist); 1241 1242static DEFINE_PER_CPU(unsigned long, debug_stack_addr); 1243DEFINE_PER_CPU(int, debug_stack_usage); 1244 1245int is_debug_stack(unsigned long addr) 1246{ 1247 return __this_cpu_read(debug_stack_usage) || 1248 (addr <= __this_cpu_read(debug_stack_addr) && 1249 addr > (__this_cpu_read(debug_stack_addr) - DEBUG_STKSZ)); 1250} 1251NOKPROBE_SYMBOL(is_debug_stack); 1252 1253DEFINE_PER_CPU(u32, debug_idt_ctr); 1254 1255void debug_stack_set_zero(void) 1256{ 1257 this_cpu_inc(debug_idt_ctr); 1258 load_current_idt(); 1259} 1260NOKPROBE_SYMBOL(debug_stack_set_zero); 1261 1262void debug_stack_reset(void) 1263{ 1264 if (WARN_ON(!this_cpu_read(debug_idt_ctr))) 1265 return; 1266 if (this_cpu_dec_return(debug_idt_ctr) == 0) 1267 load_current_idt(); 1268} 1269NOKPROBE_SYMBOL(debug_stack_reset); 1270 1271#else /* CONFIG_X86_64 */ 1272 1273DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task; 1274EXPORT_PER_CPU_SYMBOL(current_task); 1275DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; 1276EXPORT_PER_CPU_SYMBOL(__preempt_count); 1277DEFINE_PER_CPU(struct task_struct *, fpu_owner_task); 1278 1279/* 1280 * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find 1281 * the top of the kernel stack. Use an extra percpu variable to track the 1282 * top of the kernel stack directly. 1283 */ 1284DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) = 1285 (unsigned long)&init_thread_union + THREAD_SIZE; 1286EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack); 1287 1288#ifdef CONFIG_CC_STACKPROTECTOR 1289DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); 1290#endif 1291 1292#endif /* CONFIG_X86_64 */ 1293 1294/* 1295 * Clear all 6 debug registers: 1296 */ 1297static void clear_all_debug_regs(void) 1298{ 1299 int i; 1300 1301 for (i = 0; i < 8; i++) { 1302 /* Ignore db4, db5 */ 1303 if ((i == 4) || (i == 5)) 1304 continue; 1305 1306 set_debugreg(0, i); 1307 } 1308} 1309 1310#ifdef CONFIG_KGDB 1311/* 1312 * Restore debug regs if using kgdbwait and you have a kernel debugger 1313 * connection established. 1314 */ 1315static void dbg_restore_debug_regs(void) 1316{ 1317 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break)) 1318 arch_kgdb_ops.correct_hw_break(); 1319} 1320#else /* ! CONFIG_KGDB */ 1321#define dbg_restore_debug_regs() 1322#endif /* ! CONFIG_KGDB */ 1323 1324static void wait_for_master_cpu(int cpu) 1325{ 1326#ifdef CONFIG_SMP 1327 /* 1328 * wait for ACK from master CPU before continuing 1329 * with AP initialization 1330 */ 1331 WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)); 1332 while (!cpumask_test_cpu(cpu, cpu_callout_mask)) 1333 cpu_relax(); 1334#endif 1335} 1336 1337/* 1338 * cpu_init() initializes state that is per-CPU. Some data is already 1339 * initialized (naturally) in the bootstrap process, such as the GDT 1340 * and IDT. We reload them nevertheless, this function acts as a 1341 * 'CPU state barrier', nothing should get across. 1342 * A lot of state is already set up in PDA init for 64 bit 1343 */ 1344#ifdef CONFIG_X86_64 1345 1346void cpu_init(void) 1347{ 1348 struct orig_ist *oist; 1349 struct task_struct *me; 1350 struct tss_struct *t; 1351 unsigned long v; 1352 int cpu = stack_smp_processor_id(); 1353 int i; 1354 1355 wait_for_master_cpu(cpu); 1356 1357 /* 1358 * Initialize the CR4 shadow before doing anything that could 1359 * try to read it. 1360 */ 1361 cr4_init_shadow(); 1362 1363 /* 1364 * Load microcode on this cpu if a valid microcode is available. 1365 * This is early microcode loading procedure. 1366 */ 1367 load_ucode_ap(); 1368 1369 t = &per_cpu(cpu_tss, cpu); 1370 oist = &per_cpu(orig_ist, cpu); 1371 1372#ifdef CONFIG_NUMA 1373 if (this_cpu_read(numa_node) == 0 && 1374 early_cpu_to_node(cpu) != NUMA_NO_NODE) 1375 set_numa_node(early_cpu_to_node(cpu)); 1376#endif 1377 1378 me = current; 1379 1380 pr_debug("Initializing CPU#%d\n", cpu); 1381 1382 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 1383 1384 /* 1385 * Initialize the per-CPU GDT with the boot GDT, 1386 * and set up the GDT descriptor: 1387 */ 1388 1389 switch_to_new_gdt(cpu); 1390 loadsegment(fs, 0); 1391 1392 load_current_idt(); 1393 1394 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); 1395 syscall_init(); 1396 1397 wrmsrl(MSR_FS_BASE, 0); 1398 wrmsrl(MSR_KERNEL_GS_BASE, 0); 1399 barrier(); 1400 1401 x86_configure_nx(); 1402 x2apic_setup(); 1403 1404 /* 1405 * set up and load the per-CPU TSS 1406 */ 1407 if (!oist->ist[0]) { 1408 char *estacks = per_cpu(exception_stacks, cpu); 1409 1410 for (v = 0; v < N_EXCEPTION_STACKS; v++) { 1411 estacks += exception_stack_sizes[v]; 1412 oist->ist[v] = t->x86_tss.ist[v] = 1413 (unsigned long)estacks; 1414 if (v == DEBUG_STACK-1) 1415 per_cpu(debug_stack_addr, cpu) = (unsigned long)estacks; 1416 } 1417 } 1418 1419 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); 1420 1421 /* 1422 * <= is required because the CPU will access up to 1423 * 8 bits beyond the end of the IO permission bitmap. 1424 */ 1425 for (i = 0; i <= IO_BITMAP_LONGS; i++) 1426 t->io_bitmap[i] = ~0UL; 1427 1428 atomic_inc(&init_mm.mm_count); 1429 me->active_mm = &init_mm; 1430 BUG_ON(me->mm); 1431 enter_lazy_tlb(&init_mm, me); 1432 1433 load_sp0(t, ¤t->thread); 1434 set_tss_desc(cpu, t); 1435 load_TR_desc(); 1436 load_mm_ldt(&init_mm); 1437 1438 clear_all_debug_regs(); 1439 dbg_restore_debug_regs(); 1440 1441 fpu_init(); 1442 1443 if (is_uv_system()) 1444 uv_cpu_init(); 1445} 1446 1447#else 1448 1449void cpu_init(void) 1450{ 1451 int cpu = smp_processor_id(); 1452 struct task_struct *curr = current; 1453 struct tss_struct *t = &per_cpu(cpu_tss, cpu); 1454 struct thread_struct *thread = &curr->thread; 1455 1456 wait_for_master_cpu(cpu); 1457 1458 /* 1459 * Initialize the CR4 shadow before doing anything that could 1460 * try to read it. 1461 */ 1462 cr4_init_shadow(); 1463 1464 show_ucode_info_early(); 1465 1466 printk(KERN_INFO "Initializing CPU#%d\n", cpu); 1467 1468 if (cpu_feature_enabled(X86_FEATURE_VME) || cpu_has_tsc || cpu_has_de) 1469 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 1470 1471 load_current_idt(); 1472 switch_to_new_gdt(cpu); 1473 1474 /* 1475 * Set up and load the per-CPU TSS and LDT 1476 */ 1477 atomic_inc(&init_mm.mm_count); 1478 curr->active_mm = &init_mm; 1479 BUG_ON(curr->mm); 1480 enter_lazy_tlb(&init_mm, curr); 1481 1482 load_sp0(t, thread); 1483 set_tss_desc(cpu, t); 1484 load_TR_desc(); 1485 load_mm_ldt(&init_mm); 1486 1487 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); 1488 1489#ifdef CONFIG_DOUBLEFAULT 1490 /* Set up doublefault TSS pointer in the GDT */ 1491 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); 1492#endif 1493 1494 clear_all_debug_regs(); 1495 dbg_restore_debug_regs(); 1496 1497 fpu_init(); 1498} 1499#endif 1500 1501#ifdef CONFIG_X86_DEBUG_STATIC_CPU_HAS 1502void warn_pre_alternatives(void) 1503{ 1504 WARN(1, "You're using static_cpu_has before alternatives have run!\n"); 1505} 1506EXPORT_SYMBOL_GPL(warn_pre_alternatives); 1507#endif 1508 1509inline bool __static_cpu_has_safe(u16 bit) 1510{ 1511 return boot_cpu_has(bit); 1512} 1513EXPORT_SYMBOL_GPL(__static_cpu_has_safe); 1514