1#ifndef _ASM_X86_MSR_INDEX_H 2#define _ASM_X86_MSR_INDEX_H 3 4/* CPU model specific register (MSR) numbers */ 5 6/* x86-64 specific MSRs */ 7#define MSR_EFER 0xc0000080 /* extended feature register */ 8#define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */ 9#define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */ 10#define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */ 11#define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */ 12#define MSR_FS_BASE 0xc0000100 /* 64bit FS base */ 13#define MSR_GS_BASE 0xc0000101 /* 64bit GS base */ 14#define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */ 15#define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */ 16 17/* EFER bits: */ 18#define _EFER_SCE 0 /* SYSCALL/SYSRET */ 19#define _EFER_LME 8 /* Long mode enable */ 20#define _EFER_LMA 10 /* Long mode active (read-only) */ 21#define _EFER_NX 11 /* No execute enable */ 22#define _EFER_SVME 12 /* Enable virtualization */ 23#define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */ 24#define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */ 25 26#define EFER_SCE (1<<_EFER_SCE) 27#define EFER_LME (1<<_EFER_LME) 28#define EFER_LMA (1<<_EFER_LMA) 29#define EFER_NX (1<<_EFER_NX) 30#define EFER_SVME (1<<_EFER_SVME) 31#define EFER_LMSLE (1<<_EFER_LMSLE) 32#define EFER_FFXSR (1<<_EFER_FFXSR) 33 34/* Intel MSRs. Some also available on other CPUs */ 35#define MSR_IA32_PERFCTR0 0x000000c1 36#define MSR_IA32_PERFCTR1 0x000000c2 37#define MSR_FSB_FREQ 0x000000cd 38#define MSR_NHM_PLATFORM_INFO 0x000000ce 39 40#define MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2 41#define NHM_C3_AUTO_DEMOTE (1UL << 25) 42#define NHM_C1_AUTO_DEMOTE (1UL << 26) 43#define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25) 44#define SNB_C1_AUTO_UNDEMOTE (1UL << 27) 45#define SNB_C3_AUTO_UNDEMOTE (1UL << 28) 46 47#define MSR_PLATFORM_INFO 0x000000ce 48#define MSR_MTRRcap 0x000000fe 49#define MSR_IA32_BBL_CR_CTL 0x00000119 50#define MSR_IA32_BBL_CR_CTL3 0x0000011e 51 52#define MSR_IA32_SYSENTER_CS 0x00000174 53#define MSR_IA32_SYSENTER_ESP 0x00000175 54#define MSR_IA32_SYSENTER_EIP 0x00000176 55 56#define MSR_IA32_MCG_CAP 0x00000179 57#define MSR_IA32_MCG_STATUS 0x0000017a 58#define MSR_IA32_MCG_CTL 0x0000017b 59 60#define MSR_OFFCORE_RSP_0 0x000001a6 61#define MSR_OFFCORE_RSP_1 0x000001a7 62#define MSR_NHM_TURBO_RATIO_LIMIT 0x000001ad 63#define MSR_IVT_TURBO_RATIO_LIMIT 0x000001ae 64#define MSR_TURBO_RATIO_LIMIT 0x000001ad 65#define MSR_TURBO_RATIO_LIMIT1 0x000001ae 66#define MSR_TURBO_RATIO_LIMIT2 0x000001af 67 68#define MSR_LBR_SELECT 0x000001c8 69#define MSR_LBR_TOS 0x000001c9 70#define MSR_LBR_NHM_FROM 0x00000680 71#define MSR_LBR_NHM_TO 0x000006c0 72#define MSR_LBR_CORE_FROM 0x00000040 73#define MSR_LBR_CORE_TO 0x00000060 74 75#define MSR_LBR_INFO_0 0x00000dc0 /* ... 0xddf for _31 */ 76#define LBR_INFO_MISPRED BIT_ULL(63) 77#define LBR_INFO_IN_TX BIT_ULL(62) 78#define LBR_INFO_ABORT BIT_ULL(61) 79#define LBR_INFO_CYCLES 0xffff 80 81#define MSR_IA32_PEBS_ENABLE 0x000003f1 82#define MSR_IA32_DS_AREA 0x00000600 83#define MSR_IA32_PERF_CAPABILITIES 0x00000345 84#define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6 85 86#define MSR_IA32_RTIT_CTL 0x00000570 87#define RTIT_CTL_TRACEEN BIT(0) 88#define RTIT_CTL_OS BIT(2) 89#define RTIT_CTL_USR BIT(3) 90#define RTIT_CTL_CR3EN BIT(7) 91#define RTIT_CTL_TOPA BIT(8) 92#define RTIT_CTL_TSC_EN BIT(10) 93#define RTIT_CTL_DISRETC BIT(11) 94#define RTIT_CTL_BRANCH_EN BIT(13) 95#define MSR_IA32_RTIT_STATUS 0x00000571 96#define RTIT_STATUS_CONTEXTEN BIT(1) 97#define RTIT_STATUS_TRIGGEREN BIT(2) 98#define RTIT_STATUS_ERROR BIT(4) 99#define RTIT_STATUS_STOPPED BIT(5) 100#define MSR_IA32_RTIT_CR3_MATCH 0x00000572 101#define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560 102#define MSR_IA32_RTIT_OUTPUT_MASK 0x00000561 103 104#define MSR_MTRRfix64K_00000 0x00000250 105#define MSR_MTRRfix16K_80000 0x00000258 106#define MSR_MTRRfix16K_A0000 0x00000259 107#define MSR_MTRRfix4K_C0000 0x00000268 108#define MSR_MTRRfix4K_C8000 0x00000269 109#define MSR_MTRRfix4K_D0000 0x0000026a 110#define MSR_MTRRfix4K_D8000 0x0000026b 111#define MSR_MTRRfix4K_E0000 0x0000026c 112#define MSR_MTRRfix4K_E8000 0x0000026d 113#define MSR_MTRRfix4K_F0000 0x0000026e 114#define MSR_MTRRfix4K_F8000 0x0000026f 115#define MSR_MTRRdefType 0x000002ff 116 117#define MSR_IA32_CR_PAT 0x00000277 118 119#define MSR_IA32_DEBUGCTLMSR 0x000001d9 120#define MSR_IA32_LASTBRANCHFROMIP 0x000001db 121#define MSR_IA32_LASTBRANCHTOIP 0x000001dc 122#define MSR_IA32_LASTINTFROMIP 0x000001dd 123#define MSR_IA32_LASTINTTOIP 0x000001de 124 125/* DEBUGCTLMSR bits (others vary by model): */ 126#define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */ 127#define DEBUGCTLMSR_BTF (1UL << 1) /* single-step on branches */ 128#define DEBUGCTLMSR_TR (1UL << 6) 129#define DEBUGCTLMSR_BTS (1UL << 7) 130#define DEBUGCTLMSR_BTINT (1UL << 8) 131#define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9) 132#define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10) 133#define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11) 134 135#define MSR_IA32_POWER_CTL 0x000001fc 136 137#define MSR_IA32_MC0_CTL 0x00000400 138#define MSR_IA32_MC0_STATUS 0x00000401 139#define MSR_IA32_MC0_ADDR 0x00000402 140#define MSR_IA32_MC0_MISC 0x00000403 141 142/* C-state Residency Counters */ 143#define MSR_PKG_C3_RESIDENCY 0x000003f8 144#define MSR_PKG_C6_RESIDENCY 0x000003f9 145#define MSR_PKG_C7_RESIDENCY 0x000003fa 146#define MSR_CORE_C3_RESIDENCY 0x000003fc 147#define MSR_CORE_C6_RESIDENCY 0x000003fd 148#define MSR_CORE_C7_RESIDENCY 0x000003fe 149#define MSR_KNL_CORE_C6_RESIDENCY 0x000003ff 150#define MSR_PKG_C2_RESIDENCY 0x0000060d 151#define MSR_PKG_C8_RESIDENCY 0x00000630 152#define MSR_PKG_C9_RESIDENCY 0x00000631 153#define MSR_PKG_C10_RESIDENCY 0x00000632 154 155/* Run Time Average Power Limiting (RAPL) Interface */ 156 157#define MSR_RAPL_POWER_UNIT 0x00000606 158 159#define MSR_PKG_POWER_LIMIT 0x00000610 160#define MSR_PKG_ENERGY_STATUS 0x00000611 161#define MSR_PKG_PERF_STATUS 0x00000613 162#define MSR_PKG_POWER_INFO 0x00000614 163 164#define MSR_DRAM_POWER_LIMIT 0x00000618 165#define MSR_DRAM_ENERGY_STATUS 0x00000619 166#define MSR_DRAM_PERF_STATUS 0x0000061b 167#define MSR_DRAM_POWER_INFO 0x0000061c 168 169#define MSR_PP0_POWER_LIMIT 0x00000638 170#define MSR_PP0_ENERGY_STATUS 0x00000639 171#define MSR_PP0_POLICY 0x0000063a 172#define MSR_PP0_PERF_STATUS 0x0000063b 173 174#define MSR_PP1_POWER_LIMIT 0x00000640 175#define MSR_PP1_ENERGY_STATUS 0x00000641 176#define MSR_PP1_POLICY 0x00000642 177 178#define MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658 179#define MSR_PKG_ANY_CORE_C0_RES 0x00000659 180#define MSR_PKG_ANY_GFXE_C0_RES 0x0000065A 181#define MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B 182 183#define MSR_CORE_C1_RES 0x00000660 184 185#define MSR_CC6_DEMOTION_POLICY_CONFIG 0x00000668 186#define MSR_MC6_DEMOTION_POLICY_CONFIG 0x00000669 187 188#define MSR_CORE_PERF_LIMIT_REASONS 0x00000690 189#define MSR_GFX_PERF_LIMIT_REASONS 0x000006B0 190#define MSR_RING_PERF_LIMIT_REASONS 0x000006B1 191 192/* Hardware P state interface */ 193#define MSR_PPERF 0x0000064e 194#define MSR_PERF_LIMIT_REASONS 0x0000064f 195#define MSR_PM_ENABLE 0x00000770 196#define MSR_HWP_CAPABILITIES 0x00000771 197#define MSR_HWP_REQUEST_PKG 0x00000772 198#define MSR_HWP_INTERRUPT 0x00000773 199#define MSR_HWP_REQUEST 0x00000774 200#define MSR_HWP_STATUS 0x00000777 201 202/* CPUID.6.EAX */ 203#define HWP_BASE_BIT (1<<7) 204#define HWP_NOTIFICATIONS_BIT (1<<8) 205#define HWP_ACTIVITY_WINDOW_BIT (1<<9) 206#define HWP_ENERGY_PERF_PREFERENCE_BIT (1<<10) 207#define HWP_PACKAGE_LEVEL_REQUEST_BIT (1<<11) 208 209/* IA32_HWP_CAPABILITIES */ 210#define HWP_HIGHEST_PERF(x) (x & 0xff) 211#define HWP_GUARANTEED_PERF(x) ((x & (0xff << 8)) >>8) 212#define HWP_MOSTEFFICIENT_PERF(x) ((x & (0xff << 16)) >>16) 213#define HWP_LOWEST_PERF(x) ((x & (0xff << 24)) >>24) 214 215/* IA32_HWP_REQUEST */ 216#define HWP_MIN_PERF(x) (x & 0xff) 217#define HWP_MAX_PERF(x) ((x & 0xff) << 8) 218#define HWP_DESIRED_PERF(x) ((x & 0xff) << 16) 219#define HWP_ENERGY_PERF_PREFERENCE(x) ((x & 0xff) << 24) 220#define HWP_ACTIVITY_WINDOW(x) ((x & 0xff3) << 32) 221#define HWP_PACKAGE_CONTROL(x) ((x & 0x1) << 42) 222 223/* IA32_HWP_STATUS */ 224#define HWP_GUARANTEED_CHANGE(x) (x & 0x1) 225#define HWP_EXCURSION_TO_MINIMUM(x) (x & 0x4) 226 227/* IA32_HWP_INTERRUPT */ 228#define HWP_CHANGE_TO_GUARANTEED_INT(x) (x & 0x1) 229#define HWP_EXCURSION_TO_MINIMUM_INT(x) (x & 0x2) 230 231#define MSR_AMD64_MC0_MASK 0xc0010044 232 233#define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) 234#define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x)) 235#define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x)) 236#define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x)) 237 238#define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x)) 239 240/* These are consecutive and not in the normal 4er MCE bank block */ 241#define MSR_IA32_MC0_CTL2 0x00000280 242#define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x)) 243 244#define MSR_P6_PERFCTR0 0x000000c1 245#define MSR_P6_PERFCTR1 0x000000c2 246#define MSR_P6_EVNTSEL0 0x00000186 247#define MSR_P6_EVNTSEL1 0x00000187 248 249#define MSR_KNC_PERFCTR0 0x00000020 250#define MSR_KNC_PERFCTR1 0x00000021 251#define MSR_KNC_EVNTSEL0 0x00000028 252#define MSR_KNC_EVNTSEL1 0x00000029 253 254/* Alternative perfctr range with full access. */ 255#define MSR_IA32_PMC0 0x000004c1 256 257/* AMD64 MSRs. Not complete. See the architecture manual for a more 258 complete list. */ 259 260#define MSR_AMD64_PATCH_LEVEL 0x0000008b 261#define MSR_AMD64_TSC_RATIO 0xc0000104 262#define MSR_AMD64_NB_CFG 0xc001001f 263#define MSR_AMD64_PATCH_LOADER 0xc0010020 264#define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 265#define MSR_AMD64_OSVW_STATUS 0xc0010141 266#define MSR_AMD64_LS_CFG 0xc0011020 267#define MSR_AMD64_DC_CFG 0xc0011022 268#define MSR_AMD64_BU_CFG2 0xc001102a 269#define MSR_AMD64_IBSFETCHCTL 0xc0011030 270#define MSR_AMD64_IBSFETCHLINAD 0xc0011031 271#define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032 272#define MSR_AMD64_IBSFETCH_REG_COUNT 3 273#define MSR_AMD64_IBSFETCH_REG_MASK ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1) 274#define MSR_AMD64_IBSOPCTL 0xc0011033 275#define MSR_AMD64_IBSOPRIP 0xc0011034 276#define MSR_AMD64_IBSOPDATA 0xc0011035 277#define MSR_AMD64_IBSOPDATA2 0xc0011036 278#define MSR_AMD64_IBSOPDATA3 0xc0011037 279#define MSR_AMD64_IBSDCLINAD 0xc0011038 280#define MSR_AMD64_IBSDCPHYSAD 0xc0011039 281#define MSR_AMD64_IBSOP_REG_COUNT 7 282#define MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1) 283#define MSR_AMD64_IBSCTL 0xc001103a 284#define MSR_AMD64_IBSBRTARGET 0xc001103b 285#define MSR_AMD64_IBSOPDATA4 0xc001103d 286#define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */ 287 288/* Fam 16h MSRs */ 289#define MSR_F16H_L2I_PERF_CTL 0xc0010230 290#define MSR_F16H_L2I_PERF_CTR 0xc0010231 291#define MSR_F16H_DR1_ADDR_MASK 0xc0011019 292#define MSR_F16H_DR2_ADDR_MASK 0xc001101a 293#define MSR_F16H_DR3_ADDR_MASK 0xc001101b 294#define MSR_F16H_DR0_ADDR_MASK 0xc0011027 295 296/* Fam 15h MSRs */ 297#define MSR_F15H_PERF_CTL 0xc0010200 298#define MSR_F15H_PERF_CTR 0xc0010201 299#define MSR_F15H_NB_PERF_CTL 0xc0010240 300#define MSR_F15H_NB_PERF_CTR 0xc0010241 301 302/* Fam 10h MSRs */ 303#define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058 304#define FAM10H_MMIO_CONF_ENABLE (1<<0) 305#define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf 306#define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2 307#define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL 308#define FAM10H_MMIO_CONF_BASE_SHIFT 20 309#define MSR_FAM10H_NODE_ID 0xc001100c 310 311/* K8 MSRs */ 312#define MSR_K8_TOP_MEM1 0xc001001a 313#define MSR_K8_TOP_MEM2 0xc001001d 314#define MSR_K8_SYSCFG 0xc0010010 315#define MSR_K8_INT_PENDING_MSG 0xc0010055 316/* C1E active bits in int pending message */ 317#define K8_INTP_C1E_ACTIVE_MASK 0x18000000 318#define MSR_K8_TSEG_ADDR 0xc0010112 319#define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */ 320#define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */ 321#define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */ 322 323/* K7 MSRs */ 324#define MSR_K7_EVNTSEL0 0xc0010000 325#define MSR_K7_PERFCTR0 0xc0010004 326#define MSR_K7_EVNTSEL1 0xc0010001 327#define MSR_K7_PERFCTR1 0xc0010005 328#define MSR_K7_EVNTSEL2 0xc0010002 329#define MSR_K7_PERFCTR2 0xc0010006 330#define MSR_K7_EVNTSEL3 0xc0010003 331#define MSR_K7_PERFCTR3 0xc0010007 332#define MSR_K7_CLK_CTL 0xc001001b 333#define MSR_K7_HWCR 0xc0010015 334#define MSR_K7_FID_VID_CTL 0xc0010041 335#define MSR_K7_FID_VID_STATUS 0xc0010042 336 337/* K6 MSRs */ 338#define MSR_K6_WHCR 0xc0000082 339#define MSR_K6_UWCCR 0xc0000085 340#define MSR_K6_EPMR 0xc0000086 341#define MSR_K6_PSOR 0xc0000087 342#define MSR_K6_PFIR 0xc0000088 343 344/* Centaur-Hauls/IDT defined MSRs. */ 345#define MSR_IDT_FCR1 0x00000107 346#define MSR_IDT_FCR2 0x00000108 347#define MSR_IDT_FCR3 0x00000109 348#define MSR_IDT_FCR4 0x0000010a 349 350#define MSR_IDT_MCR0 0x00000110 351#define MSR_IDT_MCR1 0x00000111 352#define MSR_IDT_MCR2 0x00000112 353#define MSR_IDT_MCR3 0x00000113 354#define MSR_IDT_MCR4 0x00000114 355#define MSR_IDT_MCR5 0x00000115 356#define MSR_IDT_MCR6 0x00000116 357#define MSR_IDT_MCR7 0x00000117 358#define MSR_IDT_MCR_CTRL 0x00000120 359 360/* VIA Cyrix defined MSRs*/ 361#define MSR_VIA_FCR 0x00001107 362#define MSR_VIA_LONGHAUL 0x0000110a 363#define MSR_VIA_RNG 0x0000110b 364#define MSR_VIA_BCR2 0x00001147 365 366/* Transmeta defined MSRs */ 367#define MSR_TMTA_LONGRUN_CTRL 0x80868010 368#define MSR_TMTA_LONGRUN_FLAGS 0x80868011 369#define MSR_TMTA_LRTI_READOUT 0x80868018 370#define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a 371 372/* Intel defined MSRs. */ 373#define MSR_IA32_P5_MC_ADDR 0x00000000 374#define MSR_IA32_P5_MC_TYPE 0x00000001 375#define MSR_IA32_TSC 0x00000010 376#define MSR_IA32_PLATFORM_ID 0x00000017 377#define MSR_IA32_EBL_CR_POWERON 0x0000002a 378#define MSR_EBC_FREQUENCY_ID 0x0000002c 379#define MSR_SMI_COUNT 0x00000034 380#define MSR_IA32_FEATURE_CONTROL 0x0000003a 381#define MSR_IA32_TSC_ADJUST 0x0000003b 382#define MSR_IA32_BNDCFGS 0x00000d90 383 384#define MSR_IA32_XSS 0x00000da0 385 386#define FEATURE_CONTROL_LOCKED (1<<0) 387#define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1) 388#define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2) 389 390#define MSR_IA32_APICBASE 0x0000001b 391#define MSR_IA32_APICBASE_BSP (1<<8) 392#define MSR_IA32_APICBASE_ENABLE (1<<11) 393#define MSR_IA32_APICBASE_BASE (0xfffff<<12) 394 395#define MSR_IA32_TSCDEADLINE 0x000006e0 396 397#define MSR_IA32_UCODE_WRITE 0x00000079 398#define MSR_IA32_UCODE_REV 0x0000008b 399 400#define MSR_IA32_SMM_MONITOR_CTL 0x0000009b 401#define MSR_IA32_SMBASE 0x0000009e 402 403#define MSR_IA32_PERF_STATUS 0x00000198 404#define MSR_IA32_PERF_CTL 0x00000199 405#define INTEL_PERF_CTL_MASK 0xffff 406#define MSR_AMD_PSTATE_DEF_BASE 0xc0010064 407#define MSR_AMD_PERF_STATUS 0xc0010063 408#define MSR_AMD_PERF_CTL 0xc0010062 409 410#define MSR_IA32_MPERF 0x000000e7 411#define MSR_IA32_APERF 0x000000e8 412 413#define MSR_IA32_THERM_CONTROL 0x0000019a 414#define MSR_IA32_THERM_INTERRUPT 0x0000019b 415 416#define THERM_INT_HIGH_ENABLE (1 << 0) 417#define THERM_INT_LOW_ENABLE (1 << 1) 418#define THERM_INT_PLN_ENABLE (1 << 24) 419 420#define MSR_IA32_THERM_STATUS 0x0000019c 421 422#define THERM_STATUS_PROCHOT (1 << 0) 423#define THERM_STATUS_POWER_LIMIT (1 << 10) 424 425#define MSR_THERM2_CTL 0x0000019d 426 427#define MSR_THERM2_CTL_TM_SELECT (1ULL << 16) 428 429#define MSR_IA32_MISC_ENABLE 0x000001a0 430 431#define MSR_IA32_TEMPERATURE_TARGET 0x000001a2 432 433#define MSR_MISC_PWR_MGMT 0x000001aa 434 435#define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0 436#define ENERGY_PERF_BIAS_PERFORMANCE 0 437#define ENERGY_PERF_BIAS_NORMAL 6 438#define ENERGY_PERF_BIAS_POWERSAVE 15 439 440#define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1 441 442#define PACKAGE_THERM_STATUS_PROCHOT (1 << 0) 443#define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10) 444 445#define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2 446 447#define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0) 448#define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1) 449#define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24) 450 451/* Thermal Thresholds Support */ 452#define THERM_INT_THRESHOLD0_ENABLE (1 << 15) 453#define THERM_SHIFT_THRESHOLD0 8 454#define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0) 455#define THERM_INT_THRESHOLD1_ENABLE (1 << 23) 456#define THERM_SHIFT_THRESHOLD1 16 457#define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1) 458#define THERM_STATUS_THRESHOLD0 (1 << 6) 459#define THERM_LOG_THRESHOLD0 (1 << 7) 460#define THERM_STATUS_THRESHOLD1 (1 << 8) 461#define THERM_LOG_THRESHOLD1 (1 << 9) 462 463/* MISC_ENABLE bits: architectural */ 464#define MSR_IA32_MISC_ENABLE_FAST_STRING_BIT 0 465#define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << MSR_IA32_MISC_ENABLE_FAST_STRING_BIT) 466#define MSR_IA32_MISC_ENABLE_TCC_BIT 1 467#define MSR_IA32_MISC_ENABLE_TCC (1ULL << MSR_IA32_MISC_ENABLE_TCC_BIT) 468#define MSR_IA32_MISC_ENABLE_EMON_BIT 7 469#define MSR_IA32_MISC_ENABLE_EMON (1ULL << MSR_IA32_MISC_ENABLE_EMON_BIT) 470#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT 11 471#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT) 472#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT 12 473#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT) 474#define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT 16 475#define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT) 476#define MSR_IA32_MISC_ENABLE_MWAIT_BIT 18 477#define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << MSR_IA32_MISC_ENABLE_MWAIT_BIT) 478#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT 22 479#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) 480#define MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT 23 481#define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT) 482#define MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT 34 483#define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT) 484 485/* MISC_ENABLE bits: model-specific, meaning may vary from core to core */ 486#define MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT 2 487#define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT) 488#define MSR_IA32_MISC_ENABLE_TM1_BIT 3 489#define MSR_IA32_MISC_ENABLE_TM1 (1ULL << MSR_IA32_MISC_ENABLE_TM1_BIT) 490#define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT 4 491#define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT) 492#define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT 6 493#define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT) 494#define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT 8 495#define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT) 496#define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT 9 497#define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) 498#define MSR_IA32_MISC_ENABLE_FERR_BIT 10 499#define MSR_IA32_MISC_ENABLE_FERR (1ULL << MSR_IA32_MISC_ENABLE_FERR_BIT) 500#define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT 10 501#define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT) 502#define MSR_IA32_MISC_ENABLE_TM2_BIT 13 503#define MSR_IA32_MISC_ENABLE_TM2 (1ULL << MSR_IA32_MISC_ENABLE_TM2_BIT) 504#define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT 19 505#define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT) 506#define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT 20 507#define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT) 508#define MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT 24 509#define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT) 510#define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT 37 511#define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT) 512#define MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT 38 513#define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT) 514#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT 39 515#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT) 516 517#define MSR_IA32_TSC_DEADLINE 0x000006E0 518 519/* P4/Xeon+ specific */ 520#define MSR_IA32_MCG_EAX 0x00000180 521#define MSR_IA32_MCG_EBX 0x00000181 522#define MSR_IA32_MCG_ECX 0x00000182 523#define MSR_IA32_MCG_EDX 0x00000183 524#define MSR_IA32_MCG_ESI 0x00000184 525#define MSR_IA32_MCG_EDI 0x00000185 526#define MSR_IA32_MCG_EBP 0x00000186 527#define MSR_IA32_MCG_ESP 0x00000187 528#define MSR_IA32_MCG_EFLAGS 0x00000188 529#define MSR_IA32_MCG_EIP 0x00000189 530#define MSR_IA32_MCG_RESERVED 0x0000018a 531 532/* Pentium IV performance counter MSRs */ 533#define MSR_P4_BPU_PERFCTR0 0x00000300 534#define MSR_P4_BPU_PERFCTR1 0x00000301 535#define MSR_P4_BPU_PERFCTR2 0x00000302 536#define MSR_P4_BPU_PERFCTR3 0x00000303 537#define MSR_P4_MS_PERFCTR0 0x00000304 538#define MSR_P4_MS_PERFCTR1 0x00000305 539#define MSR_P4_MS_PERFCTR2 0x00000306 540#define MSR_P4_MS_PERFCTR3 0x00000307 541#define MSR_P4_FLAME_PERFCTR0 0x00000308 542#define MSR_P4_FLAME_PERFCTR1 0x00000309 543#define MSR_P4_FLAME_PERFCTR2 0x0000030a 544#define MSR_P4_FLAME_PERFCTR3 0x0000030b 545#define MSR_P4_IQ_PERFCTR0 0x0000030c 546#define MSR_P4_IQ_PERFCTR1 0x0000030d 547#define MSR_P4_IQ_PERFCTR2 0x0000030e 548#define MSR_P4_IQ_PERFCTR3 0x0000030f 549#define MSR_P4_IQ_PERFCTR4 0x00000310 550#define MSR_P4_IQ_PERFCTR5 0x00000311 551#define MSR_P4_BPU_CCCR0 0x00000360 552#define MSR_P4_BPU_CCCR1 0x00000361 553#define MSR_P4_BPU_CCCR2 0x00000362 554#define MSR_P4_BPU_CCCR3 0x00000363 555#define MSR_P4_MS_CCCR0 0x00000364 556#define MSR_P4_MS_CCCR1 0x00000365 557#define MSR_P4_MS_CCCR2 0x00000366 558#define MSR_P4_MS_CCCR3 0x00000367 559#define MSR_P4_FLAME_CCCR0 0x00000368 560#define MSR_P4_FLAME_CCCR1 0x00000369 561#define MSR_P4_FLAME_CCCR2 0x0000036a 562#define MSR_P4_FLAME_CCCR3 0x0000036b 563#define MSR_P4_IQ_CCCR0 0x0000036c 564#define MSR_P4_IQ_CCCR1 0x0000036d 565#define MSR_P4_IQ_CCCR2 0x0000036e 566#define MSR_P4_IQ_CCCR3 0x0000036f 567#define MSR_P4_IQ_CCCR4 0x00000370 568#define MSR_P4_IQ_CCCR5 0x00000371 569#define MSR_P4_ALF_ESCR0 0x000003ca 570#define MSR_P4_ALF_ESCR1 0x000003cb 571#define MSR_P4_BPU_ESCR0 0x000003b2 572#define MSR_P4_BPU_ESCR1 0x000003b3 573#define MSR_P4_BSU_ESCR0 0x000003a0 574#define MSR_P4_BSU_ESCR1 0x000003a1 575#define MSR_P4_CRU_ESCR0 0x000003b8 576#define MSR_P4_CRU_ESCR1 0x000003b9 577#define MSR_P4_CRU_ESCR2 0x000003cc 578#define MSR_P4_CRU_ESCR3 0x000003cd 579#define MSR_P4_CRU_ESCR4 0x000003e0 580#define MSR_P4_CRU_ESCR5 0x000003e1 581#define MSR_P4_DAC_ESCR0 0x000003a8 582#define MSR_P4_DAC_ESCR1 0x000003a9 583#define MSR_P4_FIRM_ESCR0 0x000003a4 584#define MSR_P4_FIRM_ESCR1 0x000003a5 585#define MSR_P4_FLAME_ESCR0 0x000003a6 586#define MSR_P4_FLAME_ESCR1 0x000003a7 587#define MSR_P4_FSB_ESCR0 0x000003a2 588#define MSR_P4_FSB_ESCR1 0x000003a3 589#define MSR_P4_IQ_ESCR0 0x000003ba 590#define MSR_P4_IQ_ESCR1 0x000003bb 591#define MSR_P4_IS_ESCR0 0x000003b4 592#define MSR_P4_IS_ESCR1 0x000003b5 593#define MSR_P4_ITLB_ESCR0 0x000003b6 594#define MSR_P4_ITLB_ESCR1 0x000003b7 595#define MSR_P4_IX_ESCR0 0x000003c8 596#define MSR_P4_IX_ESCR1 0x000003c9 597#define MSR_P4_MOB_ESCR0 0x000003aa 598#define MSR_P4_MOB_ESCR1 0x000003ab 599#define MSR_P4_MS_ESCR0 0x000003c0 600#define MSR_P4_MS_ESCR1 0x000003c1 601#define MSR_P4_PMH_ESCR0 0x000003ac 602#define MSR_P4_PMH_ESCR1 0x000003ad 603#define MSR_P4_RAT_ESCR0 0x000003bc 604#define MSR_P4_RAT_ESCR1 0x000003bd 605#define MSR_P4_SAAT_ESCR0 0x000003ae 606#define MSR_P4_SAAT_ESCR1 0x000003af 607#define MSR_P4_SSU_ESCR0 0x000003be 608#define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */ 609 610#define MSR_P4_TBPU_ESCR0 0x000003c2 611#define MSR_P4_TBPU_ESCR1 0x000003c3 612#define MSR_P4_TC_ESCR0 0x000003c4 613#define MSR_P4_TC_ESCR1 0x000003c5 614#define MSR_P4_U2L_ESCR0 0x000003b0 615#define MSR_P4_U2L_ESCR1 0x000003b1 616 617#define MSR_P4_PEBS_MATRIX_VERT 0x000003f2 618 619/* Intel Core-based CPU performance counters */ 620#define MSR_CORE_PERF_FIXED_CTR0 0x00000309 621#define MSR_CORE_PERF_FIXED_CTR1 0x0000030a 622#define MSR_CORE_PERF_FIXED_CTR2 0x0000030b 623#define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d 624#define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e 625#define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f 626#define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390 627 628/* Geode defined MSRs */ 629#define MSR_GEODE_BUSCONT_CONF0 0x00001900 630 631/* Intel VT MSRs */ 632#define MSR_IA32_VMX_BASIC 0x00000480 633#define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 634#define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 635#define MSR_IA32_VMX_EXIT_CTLS 0x00000483 636#define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 637#define MSR_IA32_VMX_MISC 0x00000485 638#define MSR_IA32_VMX_CR0_FIXED0 0x00000486 639#define MSR_IA32_VMX_CR0_FIXED1 0x00000487 640#define MSR_IA32_VMX_CR4_FIXED0 0x00000488 641#define MSR_IA32_VMX_CR4_FIXED1 0x00000489 642#define MSR_IA32_VMX_VMCS_ENUM 0x0000048a 643#define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b 644#define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c 645#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d 646#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e 647#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f 648#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 649#define MSR_IA32_VMX_VMFUNC 0x00000491 650 651/* VMX_BASIC bits and bitmasks */ 652#define VMX_BASIC_VMCS_SIZE_SHIFT 32 653#define VMX_BASIC_TRUE_CTLS (1ULL << 55) 654#define VMX_BASIC_64 0x0001000000000000LLU 655#define VMX_BASIC_MEM_TYPE_SHIFT 50 656#define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU 657#define VMX_BASIC_MEM_TYPE_WB 6LLU 658#define VMX_BASIC_INOUT 0x0040000000000000LLU 659 660/* MSR_IA32_VMX_MISC bits */ 661#define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29) 662#define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F 663/* AMD-V MSRs */ 664 665#define MSR_VM_CR 0xc0010114 666#define MSR_VM_IGNNE 0xc0010115 667#define MSR_VM_HSAVE_PA 0xc0010117 668 669#endif /* _ASM_X86_MSR_INDEX_H */ 670