1/*
2 * x86 TSC related functions
3 */
4#ifndef _ASM_X86_TSC_H
5#define _ASM_X86_TSC_H
6
7#include <asm/processor.h>
8
9#define NS_SCALE	10 /* 2^10, carefully chosen */
10#define US_SCALE	32 /* 2^32, arbitralrily chosen */
11
12/*
13 * Standard way to access the cycle counter.
14 */
15typedef unsigned long long cycles_t;
16
17extern unsigned int cpu_khz;
18extern unsigned int tsc_khz;
19
20extern void disable_TSC(void);
21
22static inline cycles_t get_cycles(void)
23{
24	unsigned long long ret = 0;
25
26#ifndef CONFIG_X86_TSC
27	if (!cpu_has_tsc)
28		return 0;
29#endif
30	rdtscll(ret);
31
32	return ret;
33}
34
35static __always_inline cycles_t vget_cycles(void)
36{
37	/*
38	 * We only do VDSOs on TSC capable CPUs, so this shouldn't
39	 * access boot_cpu_data (which is not VDSO-safe):
40	 */
41#ifndef CONFIG_X86_TSC
42	if (!cpu_has_tsc)
43		return 0;
44#endif
45	return (cycles_t)__native_read_tsc();
46}
47
48extern void tsc_init(void);
49extern void mark_tsc_unstable(char *reason);
50extern int unsynchronized_tsc(void);
51extern int check_tsc_unstable(void);
52extern int check_tsc_disabled(void);
53extern unsigned long native_calibrate_tsc(void);
54
55extern int tsc_clocksource_reliable;
56
57/*
58 * Boot-time check whether the TSCs are synchronized across
59 * all CPUs/cores:
60 */
61extern void check_tsc_sync_source(int cpu);
62extern void check_tsc_sync_target(void);
63
64extern int notsc_setup(char *);
65extern void tsc_save_sched_clock_state(void);
66extern void tsc_restore_sched_clock_state(void);
67
68/* MSR based TSC calibration for Intel Atom SoC platforms */
69unsigned long try_msr_calibrate_tsc(void);
70
71#endif /* _ASM_X86_TSC_H */
72