1/*
2 * linux/arch/unicore32/include/asm/cacheflush.h
3 *
4 * Code specific to PKUnity SoC and UniCore ISA
5 *
6 * Copyright (C) 2001-2010 GUAN Xue-tao
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12#ifndef __UNICORE_CACHEFLUSH_H__
13#define __UNICORE_CACHEFLUSH_H__
14
15#include <linux/mm.h>
16
17#include <asm/shmparam.h>
18
19#define CACHE_COLOUR(vaddr)	((vaddr & (SHMLBA - 1)) >> PAGE_SHIFT)
20
21/*
22 * This flag is used to indicate that the page pointed to by a pte is clean
23 * and does not require cleaning before returning it to the user.
24 */
25#define PG_dcache_clean PG_arch_1
26
27/*
28 *	MM Cache Management
29 *	===================
30 *
31 *	The arch/unicore32/mm/cache.S files implement these methods.
32 *
33 *	Start addresses are inclusive and end addresses are exclusive;
34 *	start addresses should be rounded down, end addresses up.
35 *
36 *	See Documentation/cachetlb.txt for more information.
37 *	Please note that the implementation of these, and the required
38 *	effects are cache-type (VIVT/VIPT/PIPT) specific.
39 *
40 *	flush_icache_all()
41 *
42 *		Unconditionally clean and invalidate the entire icache.
43 *		Currently only needed for cache-v6.S and cache-v7.S, see
44 *		__flush_icache_all for the generic implementation.
45 *
46 *	flush_kern_all()
47 *
48 *		Unconditionally clean and invalidate the entire cache.
49 *
50 *	flush_user_all()
51 *
52 *		Clean and invalidate all user space cache entries
53 *		before a change of page tables.
54 *
55 *	flush_user_range(start, end, flags)
56 *
57 *		Clean and invalidate a range of cache entries in the
58 *		specified address space before a change of page tables.
59 *		- start - user start address (inclusive, page aligned)
60 *		- end   - user end address   (exclusive, page aligned)
61 *		- flags - vma->vm_flags field
62 *
63 *	coherent_kern_range(start, end)
64 *
65 *		Ensure coherency between the Icache and the Dcache in the
66 *		region described by start, end.  If you have non-snooping
67 *		Harvard caches, you need to implement this function.
68 *		- start  - virtual start address
69 *		- end    - virtual end address
70 *
71 *	coherent_user_range(start, end)
72 *
73 *		Ensure coherency between the Icache and the Dcache in the
74 *		region described by start, end.  If you have non-snooping
75 *		Harvard caches, you need to implement this function.
76 *		- start  - virtual start address
77 *		- end    - virtual end address
78 *
79 *	flush_kern_dcache_area(kaddr, size)
80 *
81 *		Ensure that the data held in page is written back.
82 *		- kaddr  - page address
83 *		- size   - region size
84 *
85 *	DMA Cache Coherency
86 *	===================
87 *
88 *	dma_flush_range(start, end)
89 *
90 *		Clean and invalidate the specified virtual address range.
91 *		- start  - virtual start address
92 *		- end    - virtual end address
93 */
94
95extern void __cpuc_flush_icache_all(void);
96extern void __cpuc_flush_kern_all(void);
97extern void __cpuc_flush_user_all(void);
98extern void __cpuc_flush_user_range(unsigned long, unsigned long, unsigned int);
99extern void __cpuc_coherent_kern_range(unsigned long, unsigned long);
100extern void __cpuc_coherent_user_range(unsigned long, unsigned long);
101extern void __cpuc_flush_dcache_area(void *, size_t);
102extern void __cpuc_flush_kern_dcache_area(void *addr, size_t size);
103
104/*
105 * These are private to the dma-mapping API.  Do not use directly.
106 * Their sole purpose is to ensure that data held in the cache
107 * is visible to DMA, or data written by DMA to system memory is
108 * visible to the CPU.
109 */
110extern void __cpuc_dma_clean_range(unsigned long, unsigned long);
111extern void __cpuc_dma_flush_range(unsigned long, unsigned long);
112
113/*
114 * Copy user data from/to a page which is mapped into a different
115 * processes address space.  Really, we want to allow our "user
116 * space" model to handle this.
117 */
118extern void copy_to_user_page(struct vm_area_struct *, struct page *,
119	unsigned long, void *, const void *, unsigned long);
120#define copy_from_user_page(vma, page, vaddr, dst, src, len)	\
121	do {							\
122		memcpy(dst, src, len);				\
123	} while (0)
124
125/*
126 * Convert calls to our calling convention.
127 */
128/* Invalidate I-cache */
129static inline void __flush_icache_all(void)
130{
131	asm("movc	p0.c5, %0, #20;\n"
132	    "nop; nop; nop; nop; nop; nop; nop; nop\n"
133	    :
134	    : "r" (0));
135}
136
137#define flush_cache_all()		__cpuc_flush_kern_all()
138
139extern void flush_cache_mm(struct mm_struct *mm);
140extern void flush_cache_range(struct vm_area_struct *vma,
141		unsigned long start, unsigned long end);
142extern void flush_cache_page(struct vm_area_struct *vma,
143		unsigned long user_addr, unsigned long pfn);
144
145#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
146
147/*
148 * flush_cache_user_range is used when we want to ensure that the
149 * Harvard caches are synchronised for the user space address range.
150 * This is used for the UniCore private sys_cacheflush system call.
151 */
152#define flush_cache_user_range(vma, start, end) \
153	__cpuc_coherent_user_range((start) & PAGE_MASK, PAGE_ALIGN(end))
154
155/*
156 * Perform necessary cache operations to ensure that data previously
157 * stored within this range of addresses can be executed by the CPU.
158 */
159#define flush_icache_range(s, e)	__cpuc_coherent_kern_range(s, e)
160
161/*
162 * Perform necessary cache operations to ensure that the TLB will
163 * see data written in the specified area.
164 */
165#define clean_dcache_area(start, size)	cpu_dcache_clean_area(start, size)
166
167/*
168 * flush_dcache_page is used when the kernel has written to the page
169 * cache page at virtual address page->virtual.
170 *
171 * If this page isn't mapped (ie, page_mapping == NULL), or it might
172 * have userspace mappings, then we _must_ always clean + invalidate
173 * the dcache entries associated with the kernel mapping.
174 *
175 * Otherwise we can defer the operation, and clean the cache when we are
176 * about to change to user space.  This is the same method as used on SPARC64.
177 * See update_mmu_cache for the user space part.
178 */
179#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
180extern void flush_dcache_page(struct page *);
181
182#define flush_dcache_mmap_lock(mapping)			\
183	spin_lock_irq(&(mapping)->tree_lock)
184#define flush_dcache_mmap_unlock(mapping)		\
185	spin_unlock_irq(&(mapping)->tree_lock)
186
187#define flush_icache_user_range(vma, page, addr, len)	\
188	flush_dcache_page(page)
189
190/*
191 * We don't appear to need to do anything here.  In fact, if we did, we'd
192 * duplicate cache flushing elsewhere performed by flush_dcache_page().
193 */
194#define flush_icache_page(vma, page)	do { } while (0)
195
196/*
197 * flush_cache_vmap() is used when creating mappings (eg, via vmap,
198 * vmalloc, ioremap etc) in kernel space for pages.  On non-VIPT
199 * caches, since the direct-mappings of these pages may contain cached
200 * data, we need to do a full cache flush to ensure that writebacks
201 * don't corrupt data placed into these pages via the new mappings.
202 */
203static inline void flush_cache_vmap(unsigned long start, unsigned long end)
204{
205}
206
207static inline void flush_cache_vunmap(unsigned long start, unsigned long end)
208{
209}
210
211#endif
212